opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2020 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40 #include "safe-ctype.h"
  41
  42 #include <setjmp.h>
  43
  44 static int print_insn (bfd_vma, disassemble_info *);
  45 static void dofloat (int);
  46 static void OP_ST (int, int);
  47 static void OP_STi (int, int);
  48 static int putop (const char *, int);
  49 static void oappend (const char *);
  50 static void append_seg (void);
  51 static void OP_indirE (int, int);
  52 static void print_operand_value (char *, int, bfd_vma);
  53 static void OP_E_register (int, int);
  54 static void OP_E_memory (int, int);
  55 static void print_displacement (char *, bfd_vma);
  56 static void OP_E (int, int);
  57 static void OP_G (int, int);
  58 static bfd_vma get64 (void);
  59 static bfd_signed_vma get32 (void);
  60 static bfd_signed_vma get32s (void);
  61 static int get16 (void);
  62 static void set_op (bfd_vma, int);
  63 static void OP_Skip_MODRM (int, int);
  64 static void OP_REG (int, int);
  65 static void OP_IMREG (int, int);
  66 static void OP_I (int, int);
  67 static void OP_I64 (int, int);
  68 static void OP_sI (int, int);
  69 static void OP_J (int, int);
  70 static void OP_SEG (int, int);
  71 static void OP_DIR (int, int);
  72 static void OP_OFF (int, int);
  73 static void OP_OFF64 (int, int);
  74 static void ptr_reg (int, int);
  75 static void OP_ESreg (int, int);
  76 static void OP_DSreg (int, int);
  77 static void OP_C (int, int);
  78 static void OP_D (int, int);
  79 static void OP_T (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_VexR (int, int);
  91 static void OP_VexW (int, int);
  92 static void OP_Rounding (int, int);
  93 static void OP_REG_VexI4 (int, int);
  94 static void OP_VexI4 (int, int);
  95 static void PCLMUL_Fixup (int, int);
  96 static void VPCMP_Fixup (int, int);
  97 static void VPCOM_Fixup (int, int);
  98 static void OP_0f07 (int, int);
  99 static void OP_Monitor (int, int);
 100 static void OP_Mwait (int, int);
 101 static void NOP_Fixup1 (int, int);
 102 static void NOP_Fixup2 (int, int);
 103 static void OP_3DNowSuffix (int, int);
 104 static void CMP_Fixup (int, int);
 105 static void BadOp (void);
 106 static void REP_Fixup (int, int);
 107 static void SEP_Fixup (int, int);
 108 static void BND_Fixup (int, int);
 109 static void NOTRACK_Fixup (int, int);
 110 static void HLE_Fixup1 (int, int);
 111 static void HLE_Fixup2 (int, int);
 112 static void HLE_Fixup3 (int, int);
 113 static void CMPXCHG8B_Fixup (int, int);
 114 static void XMM_Fixup (int, int);
 115 static void FXSAVE_Fixup (int, int);
 116
 117 static void MOVSXD_Fixup (int, int);
 118
 119 static void OP_Mask (int, int);
 120
 121 struct dis_private {
 122   /* Points to first byte not fetched.  */
 123   bfd_byte *max_fetched;
 124   bfd_byte the_buffer[MAX_MNEM_SIZE];
 125   bfd_vma insn_start;
 126   int orig_sizeflag;
 127   OPCODES_SIGJMP_BUF bailout;
 128 };
 129
 130 enum address_mode
 131 {
 132   mode_16bit,
 133   mode_32bit,
 134   mode_64bit
 135 };
 136
 137 enum address_mode address_mode;
 138
 139 /* Flags for the prefixes for the current instruction.  See below.  */
 140 static int prefixes;
 141
 142 /* REX prefix the current instruction.  See below.  */
 143 static int rex;
 144 /* Bits of REX we've already used.  */
 145 static int rex_used;
 146 /* Mark parts used in the REX prefix.  When we are testing for
 147    empty prefix (for 8bit register REX extension), just mask it
 148    out.  Otherwise test for REX bit is excuse for existence of REX
 149    only in case value is nonzero.  */
 150 #define USED_REX(value)                                 \
 151   {                                                     \
 152     if (value)                                          \
 153       {                                                 \
 154         if ((rex & value))                              \
 155           rex_used |= (value) | REX_OPCODE;             \
 156       }                                                 \
 157     else                                                \
 158       rex_used |= REX_OPCODE;                           \
 159   }
 160
 161 /* Flags for prefixes which we somehow handled when printing the
 162    current instruction.  */
 163 static int used_prefixes;
 164
 165 /* Flags stored in PREFIXES.  */
 166 #define PREFIX_REPZ 1
 167 #define PREFIX_REPNZ 2
 168 #define PREFIX_LOCK 4
 169 #define PREFIX_CS 8
 170 #define PREFIX_SS 0x10
 171 #define PREFIX_DS 0x20
 172 #define PREFIX_ES 0x40
 173 #define PREFIX_FS 0x80
 174 #define PREFIX_GS 0x100
 175 #define PREFIX_DATA 0x200
 176 #define PREFIX_ADDR 0x400
 177 #define PREFIX_FWAIT 0x800
 178
 179 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 180    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 181    on error.  */
 182 #define FETCH_DATA(info, addr) \
 183   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 184    ? 1 : fetch_data ((info), (addr)))
 185
 186 static int
 187 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 188 {
 189   int status;
 190   struct dis_private *priv = (struct dis_private *) info->private_data;
 191   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 192
 193   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 194     status = (*info->read_memory_func) (start,
 195                                         priv->max_fetched,
 196                                         addr - priv->max_fetched,
 197                                         info);
 198   else
 199     status = -1;
 200   if (status != 0)
 201     {
 202       /* If we did manage to read at least one byte, then
 203          print_insn_i386 will do something sensible.  Otherwise, print
 204          an error.  We do that here because this is where we know
 205          STATUS.  */
 206       if (priv->max_fetched == priv->the_buffer)
 207         (*info->memory_error_func) (status, start, info);
 208       OPCODES_SIGLONGJMP (priv->bailout, 1);
 209     }
 210   else
 211     priv->max_fetched = addr;
 212   return 1;
 213 }
 214
 215 /* Possible values for prefix requirement.  */
 216 #define PREFIX_IGNORED_SHIFT    16
 217 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 218 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 219 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 220 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 221 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 222
 223 /* Opcode prefixes.  */
 224 #define PREFIX_OPCODE           (PREFIX_REPZ \
 225                                  | PREFIX_REPNZ \
 226                                  | PREFIX_DATA)
 227
 228 /* Prefixes ignored.  */
 229 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 230                                  | PREFIX_IGNORED_REPNZ \
 231                                  | PREFIX_IGNORED_DATA)
 232
 233 #define XX { NULL, 0 }
 234 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 235
 236 #define Eb { OP_E, b_mode }
 237 #define Ebnd { OP_E, bnd_mode }
 238 #define EbS { OP_E, b_swap_mode }
 239 #define EbndS { OP_E, bnd_swap_mode }
 240 #define Ev { OP_E, v_mode }
 241 #define Eva { OP_E, va_mode }
 242 #define Ev_bnd { OP_E, v_bnd_mode }
 243 #define EvS { OP_E, v_swap_mode }
 244 #define Ed { OP_E, d_mode }
 245 #define Edq { OP_E, dq_mode }
 246 #define Edqw { OP_E, dqw_mode }
 247 #define Edqb { OP_E, dqb_mode }
 248 #define Edb { OP_E, db_mode }
 249 #define Edw { OP_E, dw_mode }
 250 #define Edqd { OP_E, dqd_mode }
 251 #define Eq { OP_E, q_mode }
 252 #define indirEv { OP_indirE, indir_v_mode }
 253 #define indirEp { OP_indirE, f_mode }
 254 #define stackEv { OP_E, stack_v_mode }
 255 #define Em { OP_E, m_mode }
 256 #define Ew { OP_E, w_mode }
 257 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 258 #define Ma { OP_M, a_mode }
 259 #define Mb { OP_M, b_mode }
 260 #define Md { OP_M, d_mode }
 261 #define Mo { OP_M, o_mode }
 262 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 263 #define Mq { OP_M, q_mode }
 264 #define Mv { OP_M, v_mode }
 265 #define Mv_bnd { OP_M, v_bndmk_mode }
 266 #define Mx { OP_M, x_mode }
 267 #define Mxmm { OP_M, xmm_mode }
 268 #define Gb { OP_G, b_mode }
 269 #define Gbnd { OP_G, bnd_mode }
 270 #define Gv { OP_G, v_mode }
 271 #define Gd { OP_G, d_mode }
 272 #define Gdq { OP_G, dq_mode }
 273 #define Gm { OP_G, m_mode }
 274 #define Gva { OP_G, va_mode }
 275 #define Gw { OP_G, w_mode }
 276 #define Ib { OP_I, b_mode }
 277 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 278 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 279 #define Iv { OP_I, v_mode }
 280 #define sIv { OP_sI, v_mode }
 281 #define Iv64 { OP_I64, v_mode }
 282 #define Id { OP_I, d_mode }
 283 #define Iw { OP_I, w_mode }
 284 #define I1 { OP_I, const_1_mode }
 285 #define Jb { OP_J, b_mode }
 286 #define Jv { OP_J, v_mode }
 287 #define Jdqw { OP_J, dqw_mode }
 288 #define Cm { OP_C, m_mode }
 289 #define Dm { OP_D, m_mode }
 290 #define Td { OP_T, d_mode }
 291 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 292
 293 #define RMeAX { OP_REG, eAX_reg }
 294 #define RMeBX { OP_REG, eBX_reg }
 295 #define RMeCX { OP_REG, eCX_reg }
 296 #define RMeDX { OP_REG, eDX_reg }
 297 #define RMeSP { OP_REG, eSP_reg }
 298 #define RMeBP { OP_REG, eBP_reg }
 299 #define RMeSI { OP_REG, eSI_reg }
 300 #define RMeDI { OP_REG, eDI_reg }
 301 #define RMrAX { OP_REG, rAX_reg }
 302 #define RMrBX { OP_REG, rBX_reg }
 303 #define RMrCX { OP_REG, rCX_reg }
 304 #define RMrDX { OP_REG, rDX_reg }
 305 #define RMrSP { OP_REG, rSP_reg }
 306 #define RMrBP { OP_REG, rBP_reg }
 307 #define RMrSI { OP_REG, rSI_reg }
 308 #define RMrDI { OP_REG, rDI_reg }
 309 #define RMAL { OP_REG, al_reg }
 310 #define RMCL { OP_REG, cl_reg }
 311 #define RMDL { OP_REG, dl_reg }
 312 #define RMBL { OP_REG, bl_reg }
 313 #define RMAH { OP_REG, ah_reg }
 314 #define RMCH { OP_REG, ch_reg }
 315 #define RMDH { OP_REG, dh_reg }
 316 #define RMBH { OP_REG, bh_reg }
 317 #define RMAX { OP_REG, ax_reg }
 318 #define RMDX { OP_REG, dx_reg }
 319
 320 #define eAX { OP_IMREG, eAX_reg }
 321 #define AL { OP_IMREG, al_reg }
 322 #define CL { OP_IMREG, cl_reg }
 323 #define zAX { OP_IMREG, z_mode_ax_reg }
 324 #define indirDX { OP_IMREG, indir_dx_reg }
 325
 326 #define Sw { OP_SEG, w_mode }
 327 #define Sv { OP_SEG, v_mode }
 328 #define Ap { OP_DIR, 0 }
 329 #define Ob { OP_OFF64, b_mode }
 330 #define Ov { OP_OFF64, v_mode }
 331 #define Xb { OP_DSreg, eSI_reg }
 332 #define Xv { OP_DSreg, eSI_reg }
 333 #define Xz { OP_DSreg, eSI_reg }
 334 #define Yb { OP_ESreg, eDI_reg }
 335 #define Yv { OP_ESreg, eDI_reg }
 336 #define DSBX { OP_DSreg, eBX_reg }
 337
 338 #define es { OP_REG, es_reg }
 339 #define ss { OP_REG, ss_reg }
 340 #define cs { OP_REG, cs_reg }
 341 #define ds { OP_REG, ds_reg }
 342 #define fs { OP_REG, fs_reg }
 343 #define gs { OP_REG, gs_reg }
 344
 345 #define MX { OP_MMX, 0 }
 346 #define XM { OP_XMM, 0 }
 347 #define XMScalar { OP_XMM, scalar_mode }
 348 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 349 #define XMM { OP_XMM, xmm_mode }
 350 #define TMM { OP_XMM, tmm_mode }
 351 #define XMxmmq { OP_XMM, xmmq_mode }
 352 #define EM { OP_EM, v_mode }
 353 #define EMS { OP_EM, v_swap_mode }
 354 #define EMd { OP_EM, d_mode }
 355 #define EMx { OP_EM, x_mode }
 356 #define EXbwUnit { OP_EX, bw_unit_mode }
 357 #define EXw { OP_EX, w_mode }
 358 #define EXd { OP_EX, d_mode }
 359 #define EXdS { OP_EX, d_swap_mode }
 360 #define EXq { OP_EX, q_mode }
 361 #define EXqS { OP_EX, q_swap_mode }
 362 #define EXx { OP_EX, x_mode }
 363 #define EXxS { OP_EX, x_swap_mode }
 364 #define EXxmm { OP_EX, xmm_mode }
 365 #define EXymm { OP_EX, ymm_mode }
 366 #define EXtmm { OP_EX, tmm_mode }
 367 #define EXxmmq { OP_EX, xmmq_mode }
 368 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 369 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 370 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 371 #define EXxmm_md { OP_EX, xmm_md_mode }
 372 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 373 #define EXxmmdw { OP_EX, xmmdw_mode }
 374 #define EXxmmqd { OP_EX, xmmqd_mode }
 375 #define EXymmq { OP_EX, ymmq_mode }
 376 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 377 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 378 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 379 #define MS { OP_MS, v_mode }
 380 #define XS { OP_XS, v_mode }
 381 #define EMCq { OP_EMC, q_mode }
 382 #define MXC { OP_MXC, 0 }
 383 #define OPSUF { OP_3DNowSuffix, 0 }
 384 #define SEP { SEP_Fixup, 0 }
 385 #define CMP { CMP_Fixup, 0 }
 386 #define XMM0 { XMM_Fixup, 0 }
 387 #define FXSAVE { FXSAVE_Fixup, 0 }
 388
 389 #define Vex { OP_VEX, vex_mode }
 390 #define VexW { OP_VexW, vex_mode }
 391 #define VexScalar { OP_VEX, vex_scalar_mode }
 392 #define VexScalarR { OP_VexR, vex_scalar_mode }
 393 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 394 #define VexGdq { OP_VEX, dq_mode }
 395 #define VexTmm { OP_VEX, tmm_mode }
 396 #define XMVexI4 { OP_REG_VexI4, x_mode }
 397 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
 398 #define VexI4 { OP_VexI4, 0 }
 399 #define PCLMUL { PCLMUL_Fixup, 0 }
 400 #define VPCMP { VPCMP_Fixup, 0 }
 401 #define VPCOM { VPCOM_Fixup, 0 }
 402
 403 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 404 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 405 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 406
 407 #define XMask { OP_Mask, mask_mode }
 408 #define MaskG { OP_G, mask_mode }
 409 #define MaskE { OP_E, mask_mode }
 410 #define MaskBDE { OP_E, mask_bd_mode }
 411 #define MaskVex { OP_VEX, mask_mode }
 412
 413 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 414 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 415 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 416 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 417
 418 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
 419
 420 /* Used handle "rep" prefix for string instructions.  */
 421 #define Xbr { REP_Fixup, eSI_reg }
 422 #define Xvr { REP_Fixup, eSI_reg }
 423 #define Ybr { REP_Fixup, eDI_reg }
 424 #define Yvr { REP_Fixup, eDI_reg }
 425 #define Yzr { REP_Fixup, eDI_reg }
 426 #define indirDXr { REP_Fixup, indir_dx_reg }
 427 #define ALr { REP_Fixup, al_reg }
 428 #define eAXr { REP_Fixup, eAX_reg }
 429
 430 /* Used handle HLE prefix for lockable instructions.  */
 431 #define Ebh1 { HLE_Fixup1, b_mode }
 432 #define Evh1 { HLE_Fixup1, v_mode }
 433 #define Ebh2 { HLE_Fixup2, b_mode }
 434 #define Evh2 { HLE_Fixup2, v_mode }
 435 #define Ebh3 { HLE_Fixup3, b_mode }
 436 #define Evh3 { HLE_Fixup3, v_mode }
 437
 438 #define BND { BND_Fixup, 0 }
 439 #define NOTRACK { NOTRACK_Fixup, 0 }
 440
 441 #define cond_jump_flag { NULL, cond_jump_mode }
 442 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 443
 444 /* bits in sizeflag */
 445 #define SUFFIX_ALWAYS 4
 446 #define AFLAG 2
 447 #define DFLAG 1
 448
 449 enum
 450 {
 451   /* byte operand */
 452   b_mode = 1,
 453   /* byte operand with operand swapped */
 454   b_swap_mode,
 455   /* byte operand, sign extend like 'T' suffix */
 456   b_T_mode,
 457   /* operand size depends on prefixes */
 458   v_mode,
 459   /* operand size depends on prefixes with operand swapped */
 460   v_swap_mode,
 461   /* operand size depends on address prefix */
 462   va_mode,
 463   /* word operand */
 464   w_mode,
 465   /* double word operand  */
 466   d_mode,
 467   /* double word operand with operand swapped */
 468   d_swap_mode,
 469   /* quad word operand */
 470   q_mode,
 471   /* quad word operand with operand swapped */
 472   q_swap_mode,
 473   /* ten-byte operand */
 474   t_mode,
 475   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 476      broadcast enabled.  */
 477   x_mode,
 478   /* Similar to x_mode, but with different EVEX mem shifts.  */
 479   evex_x_gscat_mode,
 480   /* Similar to x_mode, but with yet different EVEX mem shifts.  */
 481   bw_unit_mode,
 482   /* Similar to x_mode, but with disabled broadcast.  */
 483   evex_x_nobcst_mode,
 484   /* Similar to x_mode, but with operands swapped and disabled broadcast
 485      in EVEX.  */
 486   x_swap_mode,
 487   /* 16-byte XMM operand */
 488   xmm_mode,
 489   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 490      memory operand (depending on vector length).  Broadcast isn't
 491      allowed.  */
 492   xmmq_mode,
 493   /* Same as xmmq_mode, but broadcast is allowed.  */
 494   evex_half_bcst_xmmq_mode,
 495   /* XMM register or byte memory operand */
 496   xmm_mb_mode,
 497   /* XMM register or word memory operand */
 498   xmm_mw_mode,
 499   /* XMM register or double word memory operand */
 500   xmm_md_mode,
 501   /* XMM register or quad word memory operand */
 502   xmm_mq_mode,
 503   /* 16-byte XMM, word, double word or quad word operand.  */
 504   xmmdw_mode,
 505   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 506   xmmqd_mode,
 507   /* 32-byte YMM operand */
 508   ymm_mode,
 509   /* quad word, ymmword or zmmword memory operand.  */
 510   ymmq_mode,
 511   /* 32-byte YMM or 16-byte word operand */
 512   ymmxmm_mode,
 513   /* TMM operand */
 514   tmm_mode,
 515   /* d_mode in 32bit, q_mode in 64bit mode.  */
 516   m_mode,
 517   /* pair of v_mode operands */
 518   a_mode,
 519   cond_jump_mode,
 520   loop_jcxz_mode,
 521   movsxd_mode,
 522   v_bnd_mode,
 523   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 524   v_bndmk_mode,
 525   /* operand size depends on REX prefixes.  */
 526   dq_mode,
 527   /* registers like dq_mode, memory like w_mode, displacements like
 528      v_mode without considering Intel64 ISA.  */
 529   dqw_mode,
 530   /* bounds operand */
 531   bnd_mode,
 532   /* bounds operand with operand swapped */
 533   bnd_swap_mode,
 534   /* 4- or 6-byte pointer operand */
 535   f_mode,
 536   const_1_mode,
 537   /* v_mode for indirect branch opcodes.  */
 538   indir_v_mode,
 539   /* v_mode for stack-related opcodes.  */
 540   stack_v_mode,
 541   /* non-quad operand size depends on prefixes */
 542   z_mode,
 543   /* 16-byte operand */
 544   o_mode,
 545   /* registers like dq_mode, memory like b_mode.  */
 546   dqb_mode,
 547   /* registers like d_mode, memory like b_mode.  */
 548   db_mode,
 549   /* registers like d_mode, memory like w_mode.  */
 550   dw_mode,
 551   /* registers like dq_mode, memory like d_mode.  */
 552   dqd_mode,
 553   /* normal vex mode */
 554   vex_mode,
 555
 556   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 557   vex_vsib_d_w_dq_mode,
 558   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 559   vex_vsib_d_w_d_mode,
 560   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 561   vex_vsib_q_w_dq_mode,
 562   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 563   vex_vsib_q_w_d_mode,
 564   /* mandatory non-vector SIB.  */
 565   vex_sibmem_mode,
 566
 567   /* scalar, ignore vector length.  */
 568   scalar_mode,
 569   /* like vex_mode, ignore vector length.  */
 570   vex_scalar_mode,
 571   /* Operand size depends on the VEX.W bit, ignore vector length.  */
 572   vex_scalar_w_dq_mode,
 573
 574   /* Static rounding.  */
 575   evex_rounding_mode,
 576   /* Static rounding, 64-bit mode only.  */
 577   evex_rounding_64_mode,
 578   /* Supress all exceptions.  */
 579   evex_sae_mode,
 580
 581   /* Mask register operand.  */
 582   mask_mode,
 583   /* Mask register operand.  */
 584   mask_bd_mode,
 585
 586   es_reg,
 587   cs_reg,
 588   ss_reg,
 589   ds_reg,
 590   fs_reg,
 591   gs_reg,
 592
 593   eAX_reg,
 594   eCX_reg,
 595   eDX_reg,
 596   eBX_reg,
 597   eSP_reg,
 598   eBP_reg,
 599   eSI_reg,
 600   eDI_reg,
 601
 602   al_reg,
 603   cl_reg,
 604   dl_reg,
 605   bl_reg,
 606   ah_reg,
 607   ch_reg,
 608   dh_reg,
 609   bh_reg,
 610
 611   ax_reg,
 612   cx_reg,
 613   dx_reg,
 614   bx_reg,
 615   sp_reg,
 616   bp_reg,
 617   si_reg,
 618   di_reg,
 619
 620   rAX_reg,
 621   rCX_reg,
 622   rDX_reg,
 623   rBX_reg,
 624   rSP_reg,
 625   rBP_reg,
 626   rSI_reg,
 627   rDI_reg,
 628
 629   z_mode_ax_reg,
 630   indir_dx_reg
 631 };
 632
 633 enum
 634 {
 635   FLOATCODE = 1,
 636   USE_REG_TABLE,
 637   USE_MOD_TABLE,
 638   USE_RM_TABLE,
 639   USE_PREFIX_TABLE,
 640   USE_X86_64_TABLE,
 641   USE_3BYTE_TABLE,
 642   USE_XOP_8F_TABLE,
 643   USE_VEX_C4_TABLE,
 644   USE_VEX_C5_TABLE,
 645   USE_VEX_LEN_TABLE,
 646   USE_VEX_W_TABLE,
 647   USE_EVEX_TABLE,
 648   USE_EVEX_LEN_TABLE
 649 };
 650
 651 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 652
 653 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 654 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 655 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 656 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 657 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 658 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 659 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 660 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 661 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 662 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 663 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 664 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 665 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 666 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 667 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 668 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 669
 670 enum
 671 {
 672   REG_80 = 0,
 673   REG_81,
 674   REG_83,
 675   REG_8F,
 676   REG_C0,
 677   REG_C1,
 678   REG_C6,
 679   REG_C7,
 680   REG_D0,
 681   REG_D1,
 682   REG_D2,
 683   REG_D3,
 684   REG_F6,
 685   REG_F7,
 686   REG_FE,
 687   REG_FF,
 688   REG_0F00,
 689   REG_0F01,
 690   REG_0F0D,
 691   REG_0F18,
 692   REG_0F1C_P_0_MOD_0,
 693   REG_0F1E_P_1_MOD_3,
 694   REG_0F38D8_PREFIX_1,
 695   REG_0F71,
 696   REG_0F72,
 697   REG_0F73,
 698   REG_0FA6,
 699   REG_0FA7,
 700   REG_0FAE,
 701   REG_0FBA,
 702   REG_0FC7,
 703   REG_VEX_0F71,
 704   REG_VEX_0F72,
 705   REG_VEX_0F73,
 706   REG_VEX_0FAE,
 707   REG_VEX_0F3849_X86_64_P_0_W_0_M_1,
 708   REG_VEX_0F38F3,
 709
 710   REG_0FXOP_09_01_L_0,
 711   REG_0FXOP_09_02_L_0,
 712   REG_0FXOP_09_12_M_1_L_0,
 713   REG_0FXOP_0A_12_L_0,
 714
 715   REG_EVEX_0F71,
 716   REG_EVEX_0F72,
 717   REG_EVEX_0F73,
 718   REG_EVEX_0F38C6,
 719   REG_EVEX_0F38C7
 720 };
 721
 722 enum
 723 {
 724   MOD_8D = 0,
 725   MOD_C6_REG_7,
 726   MOD_C7_REG_7,
 727   MOD_FF_REG_3,
 728   MOD_FF_REG_5,
 729   MOD_0F01_REG_0,
 730   MOD_0F01_REG_1,
 731   MOD_0F01_REG_2,
 732   MOD_0F01_REG_3,
 733   MOD_0F01_REG_5,
 734   MOD_0F01_REG_7,
 735   MOD_0F12_PREFIX_0,
 736   MOD_0F12_PREFIX_2,
 737   MOD_0F13,
 738   MOD_0F16_PREFIX_0,
 739   MOD_0F16_PREFIX_2,
 740   MOD_0F17,
 741   MOD_0F18_REG_0,
 742   MOD_0F18_REG_1,
 743   MOD_0F18_REG_2,
 744   MOD_0F18_REG_3,
 745   MOD_0F18_REG_4,
 746   MOD_0F18_REG_5,
 747   MOD_0F18_REG_6,
 748   MOD_0F18_REG_7,
 749   MOD_0F1A_PREFIX_0,
 750   MOD_0F1B_PREFIX_0,
 751   MOD_0F1B_PREFIX_1,
 752   MOD_0F1C_PREFIX_0,
 753   MOD_0F1E_PREFIX_1,
 754   MOD_0F2B_PREFIX_0,
 755   MOD_0F2B_PREFIX_1,
 756   MOD_0F2B_PREFIX_2,
 757   MOD_0F2B_PREFIX_3,
 758   MOD_0F50,
 759   MOD_0F71_REG_2,
 760   MOD_0F71_REG_4,
 761   MOD_0F71_REG_6,
 762   MOD_0F72_REG_2,
 763   MOD_0F72_REG_4,
 764   MOD_0F72_REG_6,
 765   MOD_0F73_REG_2,
 766   MOD_0F73_REG_3,
 767   MOD_0F73_REG_6,
 768   MOD_0F73_REG_7,
 769   MOD_0FAE_REG_0,
 770   MOD_0FAE_REG_1,
 771   MOD_0FAE_REG_2,
 772   MOD_0FAE_REG_3,
 773   MOD_0FAE_REG_4,
 774   MOD_0FAE_REG_5,
 775   MOD_0FAE_REG_6,
 776   MOD_0FAE_REG_7,
 777   MOD_0FB2,
 778   MOD_0FB4,
 779   MOD_0FB5,
 780   MOD_0FC3,
 781   MOD_0FC7_REG_3,
 782   MOD_0FC7_REG_4,
 783   MOD_0FC7_REG_5,
 784   MOD_0FC7_REG_6,
 785   MOD_0FC7_REG_7,
 786   MOD_0FD7,
 787   MOD_0FE7_PREFIX_2,
 788   MOD_0FF0_PREFIX_3,
 789   MOD_0F382A,
 790   MOD_0F38DC_PREFIX_1,
 791   MOD_0F38DD_PREFIX_1,
 792   MOD_0F38DE_PREFIX_1,
 793   MOD_0F38DF_PREFIX_1,
 794   MOD_0F38F5,
 795   MOD_0F38F6_PREFIX_0,
 796   MOD_0F38F8_PREFIX_1,
 797   MOD_0F38F8_PREFIX_2,
 798   MOD_0F38F8_PREFIX_3,
 799   MOD_0F38F9,
 800   MOD_0F38FA_PREFIX_1,
 801   MOD_0F38FB_PREFIX_1,
 802   MOD_62_32BIT,
 803   MOD_C4_32BIT,
 804   MOD_C5_32BIT,
 805   MOD_VEX_0F12_PREFIX_0,
 806   MOD_VEX_0F12_PREFIX_2,
 807   MOD_VEX_0F13,
 808   MOD_VEX_0F16_PREFIX_0,
 809   MOD_VEX_0F16_PREFIX_2,
 810   MOD_VEX_0F17,
 811   MOD_VEX_0F2B,
 812   MOD_VEX_W_0_0F41_P_0_LEN_1,
 813   MOD_VEX_W_1_0F41_P_0_LEN_1,
 814   MOD_VEX_W_0_0F41_P_2_LEN_1,
 815   MOD_VEX_W_1_0F41_P_2_LEN_1,
 816   MOD_VEX_W_0_0F42_P_0_LEN_1,
 817   MOD_VEX_W_1_0F42_P_0_LEN_1,
 818   MOD_VEX_W_0_0F42_P_2_LEN_1,
 819   MOD_VEX_W_1_0F42_P_2_LEN_1,
 820   MOD_VEX_W_0_0F44_P_0_LEN_1,
 821   MOD_VEX_W_1_0F44_P_0_LEN_1,
 822   MOD_VEX_W_0_0F44_P_2_LEN_1,
 823   MOD_VEX_W_1_0F44_P_2_LEN_1,
 824   MOD_VEX_W_0_0F45_P_0_LEN_1,
 825   MOD_VEX_W_1_0F45_P_0_LEN_1,
 826   MOD_VEX_W_0_0F45_P_2_LEN_1,
 827   MOD_VEX_W_1_0F45_P_2_LEN_1,
 828   MOD_VEX_W_0_0F46_P_0_LEN_1,
 829   MOD_VEX_W_1_0F46_P_0_LEN_1,
 830   MOD_VEX_W_0_0F46_P_2_LEN_1,
 831   MOD_VEX_W_1_0F46_P_2_LEN_1,
 832   MOD_VEX_W_0_0F47_P_0_LEN_1,
 833   MOD_VEX_W_1_0F47_P_0_LEN_1,
 834   MOD_VEX_W_0_0F47_P_2_LEN_1,
 835   MOD_VEX_W_1_0F47_P_2_LEN_1,
 836   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 837   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 838   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 839   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 840   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 841   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 842   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 843   MOD_VEX_0F50,
 844   MOD_VEX_0F71_REG_2,
 845   MOD_VEX_0F71_REG_4,
 846   MOD_VEX_0F71_REG_6,
 847   MOD_VEX_0F72_REG_2,
 848   MOD_VEX_0F72_REG_4,
 849   MOD_VEX_0F72_REG_6,
 850   MOD_VEX_0F73_REG_2,
 851   MOD_VEX_0F73_REG_3,
 852   MOD_VEX_0F73_REG_6,
 853   MOD_VEX_0F73_REG_7,
 854   MOD_VEX_W_0_0F91_P_0_LEN_0,
 855   MOD_VEX_W_1_0F91_P_0_LEN_0,
 856   MOD_VEX_W_0_0F91_P_2_LEN_0,
 857   MOD_VEX_W_1_0F91_P_2_LEN_0,
 858   MOD_VEX_W_0_0F92_P_0_LEN_0,
 859   MOD_VEX_W_0_0F92_P_2_LEN_0,
 860   MOD_VEX_0F92_P_3_LEN_0,
 861   MOD_VEX_W_0_0F93_P_0_LEN_0,
 862   MOD_VEX_W_0_0F93_P_2_LEN_0,
 863   MOD_VEX_0F93_P_3_LEN_0,
 864   MOD_VEX_W_0_0F98_P_0_LEN_0,
 865   MOD_VEX_W_1_0F98_P_0_LEN_0,
 866   MOD_VEX_W_0_0F98_P_2_LEN_0,
 867   MOD_VEX_W_1_0F98_P_2_LEN_0,
 868   MOD_VEX_W_0_0F99_P_0_LEN_0,
 869   MOD_VEX_W_1_0F99_P_0_LEN_0,
 870   MOD_VEX_W_0_0F99_P_2_LEN_0,
 871   MOD_VEX_W_1_0F99_P_2_LEN_0,
 872   MOD_VEX_0FAE_REG_2,
 873   MOD_VEX_0FAE_REG_3,
 874   MOD_VEX_0FD7,
 875   MOD_VEX_0FE7,
 876   MOD_VEX_0FF0_PREFIX_3,
 877   MOD_VEX_0F381A,
 878   MOD_VEX_0F382A,
 879   MOD_VEX_0F382C,
 880   MOD_VEX_0F382D,
 881   MOD_VEX_0F382E,
 882   MOD_VEX_0F382F,
 883   MOD_VEX_0F3849_X86_64_P_0_W_0,
 884   MOD_VEX_0F3849_X86_64_P_2_W_0,
 885   MOD_VEX_0F3849_X86_64_P_3_W_0,
 886   MOD_VEX_0F384B_X86_64_P_1_W_0,
 887   MOD_VEX_0F384B_X86_64_P_2_W_0,
 888   MOD_VEX_0F384B_X86_64_P_3_W_0,
 889   MOD_VEX_0F385A,
 890   MOD_VEX_0F385C_X86_64_P_1_W_0,
 891   MOD_VEX_0F385E_X86_64_P_0_W_0,
 892   MOD_VEX_0F385E_X86_64_P_1_W_0,
 893   MOD_VEX_0F385E_X86_64_P_2_W_0,
 894   MOD_VEX_0F385E_X86_64_P_3_W_0,
 895   MOD_VEX_0F388C,
 896   MOD_VEX_0F388E,
 897   MOD_VEX_0F3A30_L_0,
 898   MOD_VEX_0F3A31_L_0,
 899   MOD_VEX_0F3A32_L_0,
 900   MOD_VEX_0F3A33_L_0,
 901
 902   MOD_VEX_0FXOP_09_12,
 903
 904   MOD_EVEX_0F12_PREFIX_0,
 905   MOD_EVEX_0F12_PREFIX_2,
 906   MOD_EVEX_0F13,
 907   MOD_EVEX_0F16_PREFIX_0,
 908   MOD_EVEX_0F16_PREFIX_2,
 909   MOD_EVEX_0F17,
 910   MOD_EVEX_0F2B,
 911   MOD_EVEX_0F381A_W_0,
 912   MOD_EVEX_0F381A_W_1,
 913   MOD_EVEX_0F381B_W_0,
 914   MOD_EVEX_0F381B_W_1,
 915   MOD_EVEX_0F3828_P_1,
 916   MOD_EVEX_0F382A_P_1_W_1,
 917   MOD_EVEX_0F3838_P_1,
 918   MOD_EVEX_0F383A_P_1_W_0,
 919   MOD_EVEX_0F385A_W_0,
 920   MOD_EVEX_0F385A_W_1,
 921   MOD_EVEX_0F385B_W_0,
 922   MOD_EVEX_0F385B_W_1,
 923   MOD_EVEX_0F387A_W_0,
 924   MOD_EVEX_0F387B_W_0,
 925   MOD_EVEX_0F387C,
 926   MOD_EVEX_0F38C6_REG_1,
 927   MOD_EVEX_0F38C6_REG_2,
 928   MOD_EVEX_0F38C6_REG_5,
 929   MOD_EVEX_0F38C6_REG_6,
 930   MOD_EVEX_0F38C7_REG_1,
 931   MOD_EVEX_0F38C7_REG_2,
 932   MOD_EVEX_0F38C7_REG_5,
 933   MOD_EVEX_0F38C7_REG_6
 934 };
 935
 936 enum
 937 {
 938   RM_C6_REG_7 = 0,
 939   RM_C7_REG_7,
 940   RM_0F01_REG_0,
 941   RM_0F01_REG_1,
 942   RM_0F01_REG_2,
 943   RM_0F01_REG_3,
 944   RM_0F01_REG_5_MOD_3,
 945   RM_0F01_REG_7_MOD_3,
 946   RM_0F1E_P_1_MOD_3_REG_7,
 947   RM_0FAE_REG_6_MOD_3_P_0,
 948   RM_0FAE_REG_7_MOD_3,
 949   RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
 950 };
 951
 952 enum
 953 {
 954   PREFIX_90 = 0,
 955   PREFIX_0F01_REG_1_RM_4,
 956   PREFIX_0F01_REG_1_RM_5,
 957   PREFIX_0F01_REG_1_RM_6,
 958   PREFIX_0F01_REG_1_RM_7,
 959   PREFIX_0F01_REG_3_RM_1,
 960   PREFIX_0F01_REG_5_MOD_0,
 961   PREFIX_0F01_REG_5_MOD_3_RM_0,
 962   PREFIX_0F01_REG_5_MOD_3_RM_1,
 963   PREFIX_0F01_REG_5_MOD_3_RM_2,
 964   PREFIX_0F01_REG_5_MOD_3_RM_4,
 965   PREFIX_0F01_REG_5_MOD_3_RM_5,
 966   PREFIX_0F01_REG_5_MOD_3_RM_6,
 967   PREFIX_0F01_REG_5_MOD_3_RM_7,
 968   PREFIX_0F01_REG_7_MOD_3_RM_2,
 969   PREFIX_0F09,
 970   PREFIX_0F10,
 971   PREFIX_0F11,
 972   PREFIX_0F12,
 973   PREFIX_0F16,
 974   PREFIX_0F1A,
 975   PREFIX_0F1B,
 976   PREFIX_0F1C,
 977   PREFIX_0F1E,
 978   PREFIX_0F2A,
 979   PREFIX_0F2B,
 980   PREFIX_0F2C,
 981   PREFIX_0F2D,
 982   PREFIX_0F2E,
 983   PREFIX_0F2F,
 984   PREFIX_0F51,
 985   PREFIX_0F52,
 986   PREFIX_0F53,
 987   PREFIX_0F58,
 988   PREFIX_0F59,
 989   PREFIX_0F5A,
 990   PREFIX_0F5B,
 991   PREFIX_0F5C,
 992   PREFIX_0F5D,
 993   PREFIX_0F5E,
 994   PREFIX_0F5F,
 995   PREFIX_0F60,
 996   PREFIX_0F61,
 997   PREFIX_0F62,
 998   PREFIX_0F6F,
 999   PREFIX_0F70,
1000   PREFIX_0F78,
1001   PREFIX_0F79,
1002   PREFIX_0F7C,
1003   PREFIX_0F7D,
1004   PREFIX_0F7E,
1005   PREFIX_0F7F,
1006   PREFIX_0FAE_REG_0_MOD_3,
1007   PREFIX_0FAE_REG_1_MOD_3,
1008   PREFIX_0FAE_REG_2_MOD_3,
1009   PREFIX_0FAE_REG_3_MOD_3,
1010   PREFIX_0FAE_REG_4_MOD_0,
1011   PREFIX_0FAE_REG_4_MOD_3,
1012   PREFIX_0FAE_REG_5_MOD_3,
1013   PREFIX_0FAE_REG_6_MOD_0,
1014   PREFIX_0FAE_REG_6_MOD_3,
1015   PREFIX_0FAE_REG_7_MOD_0,
1016   PREFIX_0FB8,
1017   PREFIX_0FBC,
1018   PREFIX_0FBD,
1019   PREFIX_0FC2,
1020   PREFIX_0FC7_REG_6_MOD_0,
1021   PREFIX_0FC7_REG_6_MOD_3,
1022   PREFIX_0FC7_REG_7_MOD_3,
1023   PREFIX_0FD0,
1024   PREFIX_0FD6,
1025   PREFIX_0FE6,
1026   PREFIX_0FE7,
1027   PREFIX_0FF0,
1028   PREFIX_0FF7,
1029   PREFIX_0F38D8,
1030   PREFIX_0F38DC,
1031   PREFIX_0F38DD,
1032   PREFIX_0F38DE,
1033   PREFIX_0F38DF,
1034   PREFIX_0F38F0,
1035   PREFIX_0F38F1,
1036   PREFIX_0F38F6,
1037   PREFIX_0F38F8,
1038   PREFIX_0F38FA,
1039   PREFIX_0F38FB,
1040   PREFIX_VEX_0F10,
1041   PREFIX_VEX_0F11,
1042   PREFIX_VEX_0F12,
1043   PREFIX_VEX_0F16,
1044   PREFIX_VEX_0F2A,
1045   PREFIX_VEX_0F2C,
1046   PREFIX_VEX_0F2D,
1047   PREFIX_VEX_0F2E,
1048   PREFIX_VEX_0F2F,
1049   PREFIX_VEX_0F41,
1050   PREFIX_VEX_0F42,
1051   PREFIX_VEX_0F44,
1052   PREFIX_VEX_0F45,
1053   PREFIX_VEX_0F46,
1054   PREFIX_VEX_0F47,
1055   PREFIX_VEX_0F4A,
1056   PREFIX_VEX_0F4B,
1057   PREFIX_VEX_0F51,
1058   PREFIX_VEX_0F52,
1059   PREFIX_VEX_0F53,
1060   PREFIX_VEX_0F58,
1061   PREFIX_VEX_0F59,
1062   PREFIX_VEX_0F5A,
1063   PREFIX_VEX_0F5B,
1064   PREFIX_VEX_0F5C,
1065   PREFIX_VEX_0F5D,
1066   PREFIX_VEX_0F5E,
1067   PREFIX_VEX_0F5F,
1068   PREFIX_VEX_0F6F,
1069   PREFIX_VEX_0F70,
1070   PREFIX_VEX_0F7C,
1071   PREFIX_VEX_0F7D,
1072   PREFIX_VEX_0F7E,
1073   PREFIX_VEX_0F7F,
1074   PREFIX_VEX_0F90,
1075   PREFIX_VEX_0F91,
1076   PREFIX_VEX_0F92,
1077   PREFIX_VEX_0F93,
1078   PREFIX_VEX_0F98,
1079   PREFIX_VEX_0F99,
1080   PREFIX_VEX_0FC2,
1081   PREFIX_VEX_0FD0,
1082   PREFIX_VEX_0FE6,
1083   PREFIX_VEX_0FF0,
1084   PREFIX_VEX_0F3849_X86_64,
1085   PREFIX_VEX_0F384B_X86_64,
1086   PREFIX_VEX_0F385C_X86_64,
1087   PREFIX_VEX_0F385E_X86_64,
1088   PREFIX_VEX_0F38F5,
1089   PREFIX_VEX_0F38F6,
1090   PREFIX_VEX_0F38F7,
1091   PREFIX_VEX_0F3AF0,
1092
1093   PREFIX_EVEX_0F10,
1094   PREFIX_EVEX_0F11,
1095   PREFIX_EVEX_0F12,
1096   PREFIX_EVEX_0F16,
1097   PREFIX_EVEX_0F2A,
1098   PREFIX_EVEX_0F51,
1099   PREFIX_EVEX_0F58,
1100   PREFIX_EVEX_0F59,
1101   PREFIX_EVEX_0F5A,
1102   PREFIX_EVEX_0F5B,
1103   PREFIX_EVEX_0F5C,
1104   PREFIX_EVEX_0F5D,
1105   PREFIX_EVEX_0F5E,
1106   PREFIX_EVEX_0F5F,
1107   PREFIX_EVEX_0F6F,
1108   PREFIX_EVEX_0F70,
1109   PREFIX_EVEX_0F78,
1110   PREFIX_EVEX_0F79,
1111   PREFIX_EVEX_0F7A,
1112   PREFIX_EVEX_0F7B,
1113   PREFIX_EVEX_0F7E,
1114   PREFIX_EVEX_0F7F,
1115   PREFIX_EVEX_0FC2,
1116   PREFIX_EVEX_0FE6,
1117   PREFIX_EVEX_0F3810,
1118   PREFIX_EVEX_0F3811,
1119   PREFIX_EVEX_0F3812,
1120   PREFIX_EVEX_0F3813,
1121   PREFIX_EVEX_0F3814,
1122   PREFIX_EVEX_0F3815,
1123   PREFIX_EVEX_0F3820,
1124   PREFIX_EVEX_0F3821,
1125   PREFIX_EVEX_0F3822,
1126   PREFIX_EVEX_0F3823,
1127   PREFIX_EVEX_0F3824,
1128   PREFIX_EVEX_0F3825,
1129   PREFIX_EVEX_0F3826,
1130   PREFIX_EVEX_0F3827,
1131   PREFIX_EVEX_0F3828,
1132   PREFIX_EVEX_0F3829,
1133   PREFIX_EVEX_0F382A,
1134   PREFIX_EVEX_0F3830,
1135   PREFIX_EVEX_0F3831,
1136   PREFIX_EVEX_0F3832,
1137   PREFIX_EVEX_0F3833,
1138   PREFIX_EVEX_0F3834,
1139   PREFIX_EVEX_0F3835,
1140   PREFIX_EVEX_0F3838,
1141   PREFIX_EVEX_0F3839,
1142   PREFIX_EVEX_0F383A,
1143   PREFIX_EVEX_0F3852,
1144   PREFIX_EVEX_0F3853,
1145   PREFIX_EVEX_0F3868,
1146   PREFIX_EVEX_0F3872,
1147   PREFIX_EVEX_0F389A,
1148   PREFIX_EVEX_0F389B,
1149   PREFIX_EVEX_0F38AA,
1150   PREFIX_EVEX_0F38AB,
1151 };
1152
1153 enum
1154 {
1155   X86_64_06 = 0,
1156   X86_64_07,
1157   X86_64_0E,
1158   X86_64_16,
1159   X86_64_17,
1160   X86_64_1E,
1161   X86_64_1F,
1162   X86_64_27,
1163   X86_64_2F,
1164   X86_64_37,
1165   X86_64_3F,
1166   X86_64_60,
1167   X86_64_61,
1168   X86_64_62,
1169   X86_64_63,
1170   X86_64_6D,
1171   X86_64_6F,
1172   X86_64_82,
1173   X86_64_9A,
1174   X86_64_C2,
1175   X86_64_C3,
1176   X86_64_C4,
1177   X86_64_C5,
1178   X86_64_CE,
1179   X86_64_D4,
1180   X86_64_D5,
1181   X86_64_E8,
1182   X86_64_E9,
1183   X86_64_EA,
1184   X86_64_0F01_REG_0,
1185   X86_64_0F01_REG_1,
1186   X86_64_0F01_REG_1_RM_5_PREFIX_2,
1187   X86_64_0F01_REG_1_RM_6_PREFIX_2,
1188   X86_64_0F01_REG_1_RM_7_PREFIX_2,
1189   X86_64_0F01_REG_2,
1190   X86_64_0F01_REG_3,
1191   X86_64_0F24,
1192   X86_64_0F26,
1193   X86_64_VEX_0F3849,
1194   X86_64_VEX_0F384B,
1195   X86_64_VEX_0F385C,
1196   X86_64_VEX_0F385E,
1197   X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
1198   X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
1199   X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
1200   X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
1201   X86_64_0FC7_REG_6_MOD_3_PREFIX_1
1202 };
1203
1204 enum
1205 {
1206   THREE_BYTE_0F38 = 0,
1207   THREE_BYTE_0F3A
1208 };
1209
1210 enum
1211 {
1212   XOP_08 = 0,
1213   XOP_09,
1214   XOP_0A
1215 };
1216
1217 enum
1218 {
1219   VEX_0F = 0,
1220   VEX_0F38,
1221   VEX_0F3A
1222 };
1223
1224 enum
1225 {
1226   EVEX_0F = 0,
1227   EVEX_0F38,
1228   EVEX_0F3A
1229 };
1230
1231 enum
1232 {
1233   VEX_LEN_0F12_P_0_M_0 = 0,
1234   VEX_LEN_0F12_P_0_M_1,
1235 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1236   VEX_LEN_0F13_M_0,
1237   VEX_LEN_0F16_P_0_M_0,
1238   VEX_LEN_0F16_P_0_M_1,
1239 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1240   VEX_LEN_0F17_M_0,
1241   VEX_LEN_0F41_P_0,
1242   VEX_LEN_0F41_P_2,
1243   VEX_LEN_0F42_P_0,
1244   VEX_LEN_0F42_P_2,
1245   VEX_LEN_0F44_P_0,
1246   VEX_LEN_0F44_P_2,
1247   VEX_LEN_0F45_P_0,
1248   VEX_LEN_0F45_P_2,
1249   VEX_LEN_0F46_P_0,
1250   VEX_LEN_0F46_P_2,
1251   VEX_LEN_0F47_P_0,
1252   VEX_LEN_0F47_P_2,
1253   VEX_LEN_0F4A_P_0,
1254   VEX_LEN_0F4A_P_2,
1255   VEX_LEN_0F4B_P_0,
1256   VEX_LEN_0F4B_P_2,
1257   VEX_LEN_0F6E,
1258   VEX_LEN_0F77,
1259   VEX_LEN_0F7E_P_1,
1260   VEX_LEN_0F7E_P_2,
1261   VEX_LEN_0F90_P_0,
1262   VEX_LEN_0F90_P_2,
1263   VEX_LEN_0F91_P_0,
1264   VEX_LEN_0F91_P_2,
1265   VEX_LEN_0F92_P_0,
1266   VEX_LEN_0F92_P_2,
1267   VEX_LEN_0F92_P_3,
1268   VEX_LEN_0F93_P_0,
1269   VEX_LEN_0F93_P_2,
1270   VEX_LEN_0F93_P_3,
1271   VEX_LEN_0F98_P_0,
1272   VEX_LEN_0F98_P_2,
1273   VEX_LEN_0F99_P_0,
1274   VEX_LEN_0F99_P_2,
1275   VEX_LEN_0FAE_R_2_M_0,
1276   VEX_LEN_0FAE_R_3_M_0,
1277   VEX_LEN_0FC4,
1278   VEX_LEN_0FC5,
1279   VEX_LEN_0FD6,
1280   VEX_LEN_0FF7,
1281   VEX_LEN_0F3816,
1282   VEX_LEN_0F3819,
1283   VEX_LEN_0F381A_M_0,
1284   VEX_LEN_0F3836,
1285   VEX_LEN_0F3841,
1286   VEX_LEN_0F3849_X86_64_P_0_W_0_M_0,
1287   VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0,
1288   VEX_LEN_0F3849_X86_64_P_2_W_0_M_0,
1289   VEX_LEN_0F3849_X86_64_P_3_W_0_M_0,
1290   VEX_LEN_0F384B_X86_64_P_1_W_0_M_0,
1291   VEX_LEN_0F384B_X86_64_P_2_W_0_M_0,
1292   VEX_LEN_0F384B_X86_64_P_3_W_0_M_0,
1293   VEX_LEN_0F385A_M_0,
1294   VEX_LEN_0F385C_X86_64_P_1_W_0_M_0,
1295   VEX_LEN_0F385E_X86_64_P_0_W_0_M_0,
1296   VEX_LEN_0F385E_X86_64_P_1_W_0_M_0,
1297   VEX_LEN_0F385E_X86_64_P_2_W_0_M_0,
1298   VEX_LEN_0F385E_X86_64_P_3_W_0_M_0,
1299   VEX_LEN_0F38DB,
1300   VEX_LEN_0F38F2,
1301   VEX_LEN_0F38F3_R_1,
1302   VEX_LEN_0F38F3_R_2,
1303   VEX_LEN_0F38F3_R_3,
1304   VEX_LEN_0F38F5_P_0,
1305   VEX_LEN_0F38F5_P_1,
1306   VEX_LEN_0F38F5_P_3,
1307   VEX_LEN_0F38F6_P_3,
1308   VEX_LEN_0F38F7_P_0,
1309   VEX_LEN_0F38F7_P_1,
1310   VEX_LEN_0F38F7_P_2,
1311   VEX_LEN_0F38F7_P_3,
1312   VEX_LEN_0F3A00,
1313   VEX_LEN_0F3A01,
1314   VEX_LEN_0F3A06,
1315   VEX_LEN_0F3A14,
1316   VEX_LEN_0F3A15,
1317   VEX_LEN_0F3A16,
1318   VEX_LEN_0F3A17,
1319   VEX_LEN_0F3A18,
1320   VEX_LEN_0F3A19,
1321   VEX_LEN_0F3A20,
1322   VEX_LEN_0F3A21,
1323   VEX_LEN_0F3A22,
1324   VEX_LEN_0F3A30,
1325   VEX_LEN_0F3A31,
1326   VEX_LEN_0F3A32,
1327   VEX_LEN_0F3A33,
1328   VEX_LEN_0F3A38,
1329   VEX_LEN_0F3A39,
1330   VEX_LEN_0F3A41,
1331   VEX_LEN_0F3A46,
1332   VEX_LEN_0F3A60,
1333   VEX_LEN_0F3A61,
1334   VEX_LEN_0F3A62,
1335   VEX_LEN_0F3A63,
1336   VEX_LEN_0F3ADF,
1337   VEX_LEN_0F3AF0_P_3,
1338   VEX_LEN_0FXOP_08_85,
1339   VEX_LEN_0FXOP_08_86,
1340   VEX_LEN_0FXOP_08_87,
1341   VEX_LEN_0FXOP_08_8E,
1342   VEX_LEN_0FXOP_08_8F,
1343   VEX_LEN_0FXOP_08_95,
1344   VEX_LEN_0FXOP_08_96,
1345   VEX_LEN_0FXOP_08_97,
1346   VEX_LEN_0FXOP_08_9E,
1347   VEX_LEN_0FXOP_08_9F,
1348   VEX_LEN_0FXOP_08_A3,
1349   VEX_LEN_0FXOP_08_A6,
1350   VEX_LEN_0FXOP_08_B6,
1351   VEX_LEN_0FXOP_08_C0,
1352   VEX_LEN_0FXOP_08_C1,
1353   VEX_LEN_0FXOP_08_C2,
1354   VEX_LEN_0FXOP_08_C3,
1355   VEX_LEN_0FXOP_08_CC,
1356   VEX_LEN_0FXOP_08_CD,
1357   VEX_LEN_0FXOP_08_CE,
1358   VEX_LEN_0FXOP_08_CF,
1359   VEX_LEN_0FXOP_08_EC,
1360   VEX_LEN_0FXOP_08_ED,
1361   VEX_LEN_0FXOP_08_EE,
1362   VEX_LEN_0FXOP_08_EF,
1363   VEX_LEN_0FXOP_09_01,
1364   VEX_LEN_0FXOP_09_02,
1365   VEX_LEN_0FXOP_09_12_M_1,
1366   VEX_LEN_0FXOP_09_82_W_0,
1367   VEX_LEN_0FXOP_09_83_W_0,
1368   VEX_LEN_0FXOP_09_90,
1369   VEX_LEN_0FXOP_09_91,
1370   VEX_LEN_0FXOP_09_92,
1371   VEX_LEN_0FXOP_09_93,
1372   VEX_LEN_0FXOP_09_94,
1373   VEX_LEN_0FXOP_09_95,
1374   VEX_LEN_0FXOP_09_96,
1375   VEX_LEN_0FXOP_09_97,
1376   VEX_LEN_0FXOP_09_98,
1377   VEX_LEN_0FXOP_09_99,
1378   VEX_LEN_0FXOP_09_9A,
1379   VEX_LEN_0FXOP_09_9B,
1380   VEX_LEN_0FXOP_09_C1,
1381   VEX_LEN_0FXOP_09_C2,
1382   VEX_LEN_0FXOP_09_C3,
1383   VEX_LEN_0FXOP_09_C6,
1384   VEX_LEN_0FXOP_09_C7,
1385   VEX_LEN_0FXOP_09_CB,
1386   VEX_LEN_0FXOP_09_D1,
1387   VEX_LEN_0FXOP_09_D2,
1388   VEX_LEN_0FXOP_09_D3,
1389   VEX_LEN_0FXOP_09_D6,
1390   VEX_LEN_0FXOP_09_D7,
1391   VEX_LEN_0FXOP_09_DB,
1392   VEX_LEN_0FXOP_09_E1,
1393   VEX_LEN_0FXOP_09_E2,
1394   VEX_LEN_0FXOP_09_E3,
1395   VEX_LEN_0FXOP_0A_12,
1396 };
1397
1398 enum
1399 {
1400   EVEX_LEN_0F6E = 0,
1401   EVEX_LEN_0F7E_P_1,
1402   EVEX_LEN_0F7E_P_2,
1403   EVEX_LEN_0FC4,
1404   EVEX_LEN_0FC5,
1405   EVEX_LEN_0FD6,
1406   EVEX_LEN_0F3816,
1407   EVEX_LEN_0F3819_W_0,
1408   EVEX_LEN_0F3819_W_1,
1409   EVEX_LEN_0F381A_W_0_M_0,
1410   EVEX_LEN_0F381A_W_1_M_0,
1411   EVEX_LEN_0F381B_W_0_M_0,
1412   EVEX_LEN_0F381B_W_1_M_0,
1413   EVEX_LEN_0F3836,
1414   EVEX_LEN_0F385A_W_0_M_0,
1415   EVEX_LEN_0F385A_W_1_M_0,
1416   EVEX_LEN_0F385B_W_0_M_0,
1417   EVEX_LEN_0F385B_W_1_M_0,
1418   EVEX_LEN_0F38C6_R_1_M_0,
1419   EVEX_LEN_0F38C6_R_2_M_0,
1420   EVEX_LEN_0F38C6_R_5_M_0,
1421   EVEX_LEN_0F38C6_R_6_M_0,
1422   EVEX_LEN_0F38C7_R_1_M_0_W_0,
1423   EVEX_LEN_0F38C7_R_1_M_0_W_1,
1424   EVEX_LEN_0F38C7_R_2_M_0_W_0,
1425   EVEX_LEN_0F38C7_R_2_M_0_W_1,
1426   EVEX_LEN_0F38C7_R_5_M_0_W_0,
1427   EVEX_LEN_0F38C7_R_5_M_0_W_1,
1428   EVEX_LEN_0F38C7_R_6_M_0_W_0,
1429   EVEX_LEN_0F38C7_R_6_M_0_W_1,
1430   EVEX_LEN_0F3A00_W_1,
1431   EVEX_LEN_0F3A01_W_1,
1432   EVEX_LEN_0F3A14,
1433   EVEX_LEN_0F3A15,
1434   EVEX_LEN_0F3A16,
1435   EVEX_LEN_0F3A17,
1436   EVEX_LEN_0F3A18_W_0,
1437   EVEX_LEN_0F3A18_W_1,
1438   EVEX_LEN_0F3A19_W_0,
1439   EVEX_LEN_0F3A19_W_1,
1440   EVEX_LEN_0F3A1A_W_0,
1441   EVEX_LEN_0F3A1A_W_1,
1442   EVEX_LEN_0F3A1B_W_0,
1443   EVEX_LEN_0F3A1B_W_1,
1444   EVEX_LEN_0F3A20,
1445   EVEX_LEN_0F3A21_W_0,
1446   EVEX_LEN_0F3A22,
1447   EVEX_LEN_0F3A23_W_0,
1448   EVEX_LEN_0F3A23_W_1,
1449   EVEX_LEN_0F3A38_W_0,
1450   EVEX_LEN_0F3A38_W_1,
1451   EVEX_LEN_0F3A39_W_0,
1452   EVEX_LEN_0F3A39_W_1,
1453   EVEX_LEN_0F3A3A_W_0,
1454   EVEX_LEN_0F3A3A_W_1,
1455   EVEX_LEN_0F3A3B_W_0,
1456   EVEX_LEN_0F3A3B_W_1,
1457   EVEX_LEN_0F3A43_W_0,
1458   EVEX_LEN_0F3A43_W_1
1459 };
1460
1461 enum
1462 {
1463   VEX_W_0F41_P_0_LEN_1 = 0,
1464   VEX_W_0F41_P_2_LEN_1,
1465   VEX_W_0F42_P_0_LEN_1,
1466   VEX_W_0F42_P_2_LEN_1,
1467   VEX_W_0F44_P_0_LEN_0,
1468   VEX_W_0F44_P_2_LEN_0,
1469   VEX_W_0F45_P_0_LEN_1,
1470   VEX_W_0F45_P_2_LEN_1,
1471   VEX_W_0F46_P_0_LEN_1,
1472   VEX_W_0F46_P_2_LEN_1,
1473   VEX_W_0F47_P_0_LEN_1,
1474   VEX_W_0F47_P_2_LEN_1,
1475   VEX_W_0F4A_P_0_LEN_1,
1476   VEX_W_0F4A_P_2_LEN_1,
1477   VEX_W_0F4B_P_0_LEN_1,
1478   VEX_W_0F4B_P_2_LEN_1,
1479   VEX_W_0F90_P_0_LEN_0,
1480   VEX_W_0F90_P_2_LEN_0,
1481   VEX_W_0F91_P_0_LEN_0,
1482   VEX_W_0F91_P_2_LEN_0,
1483   VEX_W_0F92_P_0_LEN_0,
1484   VEX_W_0F92_P_2_LEN_0,
1485   VEX_W_0F93_P_0_LEN_0,
1486   VEX_W_0F93_P_2_LEN_0,
1487   VEX_W_0F98_P_0_LEN_0,
1488   VEX_W_0F98_P_2_LEN_0,
1489   VEX_W_0F99_P_0_LEN_0,
1490   VEX_W_0F99_P_2_LEN_0,
1491   VEX_W_0F380C,
1492   VEX_W_0F380D,
1493   VEX_W_0F380E,
1494   VEX_W_0F380F,
1495   VEX_W_0F3813,
1496   VEX_W_0F3816_L_1,
1497   VEX_W_0F3818,
1498   VEX_W_0F3819_L_1,
1499   VEX_W_0F381A_M_0_L_1,
1500   VEX_W_0F382C_M_0,
1501   VEX_W_0F382D_M_0,
1502   VEX_W_0F382E_M_0,
1503   VEX_W_0F382F_M_0,
1504   VEX_W_0F3836,
1505   VEX_W_0F3846,
1506   VEX_W_0F3849_X86_64_P_0,
1507   VEX_W_0F3849_X86_64_P_2,
1508   VEX_W_0F3849_X86_64_P_3,
1509   VEX_W_0F384B_X86_64_P_1,
1510   VEX_W_0F384B_X86_64_P_2,
1511   VEX_W_0F384B_X86_64_P_3,
1512   VEX_W_0F3858,
1513   VEX_W_0F3859,
1514   VEX_W_0F385A_M_0_L_0,
1515   VEX_W_0F385C_X86_64_P_1,
1516   VEX_W_0F385E_X86_64_P_0,
1517   VEX_W_0F385E_X86_64_P_1,
1518   VEX_W_0F385E_X86_64_P_2,
1519   VEX_W_0F385E_X86_64_P_3,
1520   VEX_W_0F3878,
1521   VEX_W_0F3879,
1522   VEX_W_0F38CF,
1523   VEX_W_0F3A00_L_1,
1524   VEX_W_0F3A01_L_1,
1525   VEX_W_0F3A02,
1526   VEX_W_0F3A04,
1527   VEX_W_0F3A05,
1528   VEX_W_0F3A06_L_1,
1529   VEX_W_0F3A18_L_1,
1530   VEX_W_0F3A19_L_1,
1531   VEX_W_0F3A1D,
1532   VEX_W_0F3A38_L_1,
1533   VEX_W_0F3A39_L_1,
1534   VEX_W_0F3A46_L_1,
1535   VEX_W_0F3A4A,
1536   VEX_W_0F3A4B,
1537   VEX_W_0F3A4C,
1538   VEX_W_0F3ACE,
1539   VEX_W_0F3ACF,
1540
1541   VEX_W_0FXOP_08_85_L_0,
1542   VEX_W_0FXOP_08_86_L_0,
1543   VEX_W_0FXOP_08_87_L_0,
1544   VEX_W_0FXOP_08_8E_L_0,
1545   VEX_W_0FXOP_08_8F_L_0,
1546   VEX_W_0FXOP_08_95_L_0,
1547   VEX_W_0FXOP_08_96_L_0,
1548   VEX_W_0FXOP_08_97_L_0,
1549   VEX_W_0FXOP_08_9E_L_0,
1550   VEX_W_0FXOP_08_9F_L_0,
1551   VEX_W_0FXOP_08_A6_L_0,
1552   VEX_W_0FXOP_08_B6_L_0,
1553   VEX_W_0FXOP_08_C0_L_0,
1554   VEX_W_0FXOP_08_C1_L_0,
1555   VEX_W_0FXOP_08_C2_L_0,
1556   VEX_W_0FXOP_08_C3_L_0,
1557   VEX_W_0FXOP_08_CC_L_0,
1558   VEX_W_0FXOP_08_CD_L_0,
1559   VEX_W_0FXOP_08_CE_L_0,
1560   VEX_W_0FXOP_08_CF_L_0,
1561   VEX_W_0FXOP_08_EC_L_0,
1562   VEX_W_0FXOP_08_ED_L_0,
1563   VEX_W_0FXOP_08_EE_L_0,
1564   VEX_W_0FXOP_08_EF_L_0,
1565
1566   VEX_W_0FXOP_09_80,
1567   VEX_W_0FXOP_09_81,
1568   VEX_W_0FXOP_09_82,
1569   VEX_W_0FXOP_09_83,
1570   VEX_W_0FXOP_09_C1_L_0,
1571   VEX_W_0FXOP_09_C2_L_0,
1572   VEX_W_0FXOP_09_C3_L_0,
1573   VEX_W_0FXOP_09_C6_L_0,
1574   VEX_W_0FXOP_09_C7_L_0,
1575   VEX_W_0FXOP_09_CB_L_0,
1576   VEX_W_0FXOP_09_D1_L_0,
1577   VEX_W_0FXOP_09_D2_L_0,
1578   VEX_W_0FXOP_09_D3_L_0,
1579   VEX_W_0FXOP_09_D6_L_0,
1580   VEX_W_0FXOP_09_D7_L_0,
1581   VEX_W_0FXOP_09_DB_L_0,
1582   VEX_W_0FXOP_09_E1_L_0,
1583   VEX_W_0FXOP_09_E2_L_0,
1584   VEX_W_0FXOP_09_E3_L_0,
1585
1586   EVEX_W_0F10_P_1,
1587   EVEX_W_0F10_P_3,
1588   EVEX_W_0F11_P_1,
1589   EVEX_W_0F11_P_3,
1590   EVEX_W_0F12_P_0_M_1,
1591   EVEX_W_0F12_P_1,
1592   EVEX_W_0F12_P_3,
1593   EVEX_W_0F16_P_0_M_1,
1594   EVEX_W_0F16_P_1,
1595   EVEX_W_0F2A_P_3,
1596   EVEX_W_0F51_P_1,
1597   EVEX_W_0F51_P_3,
1598   EVEX_W_0F58_P_1,
1599   EVEX_W_0F58_P_3,
1600   EVEX_W_0F59_P_1,
1601   EVEX_W_0F59_P_3,
1602   EVEX_W_0F5A_P_0,
1603   EVEX_W_0F5A_P_1,
1604   EVEX_W_0F5A_P_2,
1605   EVEX_W_0F5A_P_3,
1606   EVEX_W_0F5B_P_0,
1607   EVEX_W_0F5B_P_1,
1608   EVEX_W_0F5B_P_2,
1609   EVEX_W_0F5C_P_1,
1610   EVEX_W_0F5C_P_3,
1611   EVEX_W_0F5D_P_1,
1612   EVEX_W_0F5D_P_3,
1613   EVEX_W_0F5E_P_1,
1614   EVEX_W_0F5E_P_3,
1615   EVEX_W_0F5F_P_1,
1616   EVEX_W_0F5F_P_3,
1617   EVEX_W_0F62,
1618   EVEX_W_0F66,
1619   EVEX_W_0F6A,
1620   EVEX_W_0F6B,
1621   EVEX_W_0F6C,
1622   EVEX_W_0F6D,
1623   EVEX_W_0F6F_P_1,
1624   EVEX_W_0F6F_P_2,
1625   EVEX_W_0F6F_P_3,
1626   EVEX_W_0F70_P_2,
1627   EVEX_W_0F72_R_2,
1628   EVEX_W_0F72_R_6,
1629   EVEX_W_0F73_R_2,
1630   EVEX_W_0F73_R_6,
1631   EVEX_W_0F76,
1632   EVEX_W_0F78_P_0,
1633   EVEX_W_0F78_P_2,
1634   EVEX_W_0F79_P_0,
1635   EVEX_W_0F79_P_2,
1636   EVEX_W_0F7A_P_1,
1637   EVEX_W_0F7A_P_2,
1638   EVEX_W_0F7A_P_3,
1639   EVEX_W_0F7B_P_2,
1640   EVEX_W_0F7B_P_3,
1641   EVEX_W_0F7E_P_1,
1642   EVEX_W_0F7F_P_1,
1643   EVEX_W_0F7F_P_2,
1644   EVEX_W_0F7F_P_3,
1645   EVEX_W_0FC2_P_1,
1646   EVEX_W_0FC2_P_3,
1647   EVEX_W_0FD2,
1648   EVEX_W_0FD3,
1649   EVEX_W_0FD4,
1650   EVEX_W_0FD6_L_0,
1651   EVEX_W_0FE6_P_1,
1652   EVEX_W_0FE6_P_2,
1653   EVEX_W_0FE6_P_3,
1654   EVEX_W_0FE7,
1655   EVEX_W_0FF2,
1656   EVEX_W_0FF3,
1657   EVEX_W_0FF4,
1658   EVEX_W_0FFA,
1659   EVEX_W_0FFB,
1660   EVEX_W_0FFE,
1661   EVEX_W_0F380D,
1662   EVEX_W_0F3810_P_1,
1663   EVEX_W_0F3810_P_2,
1664   EVEX_W_0F3811_P_1,
1665   EVEX_W_0F3811_P_2,
1666   EVEX_W_0F3812_P_1,
1667   EVEX_W_0F3812_P_2,
1668   EVEX_W_0F3813_P_1,
1669   EVEX_W_0F3813_P_2,
1670   EVEX_W_0F3814_P_1,
1671   EVEX_W_0F3815_P_1,
1672   EVEX_W_0F3819,
1673   EVEX_W_0F381A,
1674   EVEX_W_0F381B,
1675   EVEX_W_0F381E,
1676   EVEX_W_0F381F,
1677   EVEX_W_0F3820_P_1,
1678   EVEX_W_0F3821_P_1,
1679   EVEX_W_0F3822_P_1,
1680   EVEX_W_0F3823_P_1,
1681   EVEX_W_0F3824_P_1,
1682   EVEX_W_0F3825_P_1,
1683   EVEX_W_0F3825_P_2,
1684   EVEX_W_0F3828_P_2,
1685   EVEX_W_0F3829_P_2,
1686   EVEX_W_0F382A_P_1,
1687   EVEX_W_0F382A_P_2,
1688   EVEX_W_0F382B,
1689   EVEX_W_0F3830_P_1,
1690   EVEX_W_0F3831_P_1,
1691   EVEX_W_0F3832_P_1,
1692   EVEX_W_0F3833_P_1,
1693   EVEX_W_0F3834_P_1,
1694   EVEX_W_0F3835_P_1,
1695   EVEX_W_0F3835_P_2,
1696   EVEX_W_0F3837,
1697   EVEX_W_0F383A_P_1,
1698   EVEX_W_0F3852_P_1,
1699   EVEX_W_0F3859,
1700   EVEX_W_0F385A,
1701   EVEX_W_0F385B,
1702   EVEX_W_0F3870,
1703   EVEX_W_0F3872_P_1,
1704   EVEX_W_0F3872_P_2,
1705   EVEX_W_0F3872_P_3,
1706   EVEX_W_0F387A,
1707   EVEX_W_0F387B,
1708   EVEX_W_0F3883,
1709   EVEX_W_0F3891,
1710   EVEX_W_0F3893,
1711   EVEX_W_0F38A1,
1712   EVEX_W_0F38A3,
1713   EVEX_W_0F38C7_R_1_M_0,
1714   EVEX_W_0F38C7_R_2_M_0,
1715   EVEX_W_0F38C7_R_5_M_0,
1716   EVEX_W_0F38C7_R_6_M_0,
1717
1718   EVEX_W_0F3A00,
1719   EVEX_W_0F3A01,
1720   EVEX_W_0F3A05,
1721   EVEX_W_0F3A08,
1722   EVEX_W_0F3A09,
1723   EVEX_W_0F3A0A,
1724   EVEX_W_0F3A0B,
1725   EVEX_W_0F3A18,
1726   EVEX_W_0F3A19,
1727   EVEX_W_0F3A1A,
1728   EVEX_W_0F3A1B,
1729   EVEX_W_0F3A21,
1730   EVEX_W_0F3A23,
1731   EVEX_W_0F3A38,
1732   EVEX_W_0F3A39,
1733   EVEX_W_0F3A3A,
1734   EVEX_W_0F3A3B,
1735   EVEX_W_0F3A42,
1736   EVEX_W_0F3A43,
1737   EVEX_W_0F3A70,
1738   EVEX_W_0F3A72,
1739 };
1740
1741 typedef void (*op_rtn) (int bytemode, int sizeflag);
1742
1743 struct dis386 {
1744   const char *name;
1745   struct
1746     {
1747       op_rtn rtn;
1748       int bytemode;
1749     } op[MAX_OPERANDS];
1750   unsigned int prefix_requirement;
1751 };
1752
1753 /* Upper case letters in the instruction names here are macros.
1754    'A' => print 'b' if no register operands or suffix_always is true
1755    'B' => print 'b' if suffix_always is true
1756    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1757           size prefix
1758    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1759           suffix_always is true
1760    'E' => print 'e' if 32-bit form of jcxz
1761    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1762    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1763    'H' => print ",pt" or ",pn" branch hint
1764    'I' unused.
1765    'J' unused.
1766    'K' => print 'd' or 'q' if rex prefix is present.
1767    'L' unused.
1768    'M' => print 'r' if intel_mnemonic is false.
1769    'N' => print 'n' if instruction has no wait "prefix"
1770    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1771    'P' => behave as 'T' except with register operand outside of suffix_always
1772           mode
1773    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1774           is true
1775    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1776    'S' => print 'w', 'l' or 'q' if suffix_always is true
1777    'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1778           prefix or if suffix_always is true.
1779    'U' unused.
1780    'V' unused.
1781    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1782    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1783    'Y' unused.
1784    'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1785    '!' => change condition from true to false or from false to true.
1786    '%' => add 1 upper case letter to the macro.
1787    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1788           prefix or suffix_always is true (lcall/ljmp).
1789    '@' => in 64bit mode for Intel64 ISA or if instruction
1790           has no operand sizing prefix, print 'q' if suffix_always is true or
1791           nothing otherwise; behave as 'P' in all other cases
1792
1793    2 upper case letter macros:
1794    "XY" => print 'x' or 'y' if suffix_always is true or no register
1795            operands and no broadcast.
1796    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1797            register operands and no broadcast.
1798    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1799    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1800            being false, or no operand at all in 64bit mode, or if suffix_always
1801            is true.
1802    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1803    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1804    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1805    "DQ" => print 'd' or 'q' depending on the VEX.W bit
1806    "BW" => print 'b' or 'w' depending on the VEX.W bit
1807    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1808            an operand size prefix, or suffix_always is true.  print
1809            'q' if rex prefix is present.
1810
1811    Many of the above letters print nothing in Intel mode.  See "putop"
1812    for the details.
1813
1814    Braces '{' and '}', and vertical bars '|', indicate alternative
1815    mnemonic strings for AT&T and Intel.  */
1816
1817 static const struct dis386 dis386[] = {
1818   /* 00 */
1819   { "addB",             { Ebh1, Gb }, 0 },
1820   { "addS",             { Evh1, Gv }, 0 },
1821   { "addB",             { Gb, EbS }, 0 },
1822   { "addS",             { Gv, EvS }, 0 },
1823   { "addB",             { AL, Ib }, 0 },
1824   { "addS",             { eAX, Iv }, 0 },
1825   { X86_64_TABLE (X86_64_06) },
1826   { X86_64_TABLE (X86_64_07) },
1827   /* 08 */
1828   { "orB",              { Ebh1, Gb }, 0 },
1829   { "orS",              { Evh1, Gv }, 0 },
1830   { "orB",              { Gb, EbS }, 0 },
1831   { "orS",              { Gv, EvS }, 0 },
1832   { "orB",              { AL, Ib }, 0 },
1833   { "orS",              { eAX, Iv }, 0 },
1834   { X86_64_TABLE (X86_64_0E) },
1835   { Bad_Opcode },       /* 0x0f extended opcode escape */
1836   /* 10 */
1837   { "adcB",             { Ebh1, Gb }, 0 },
1838   { "adcS",             { Evh1, Gv }, 0 },
1839   { "adcB",             { Gb, EbS }, 0 },
1840   { "adcS",             { Gv, EvS }, 0 },
1841   { "adcB",             { AL, Ib }, 0 },
1842   { "adcS",             { eAX, Iv }, 0 },
1843   { X86_64_TABLE (X86_64_16) },
1844   { X86_64_TABLE (X86_64_17) },
1845   /* 18 */
1846   { "sbbB",             { Ebh1, Gb }, 0 },
1847   { "sbbS",             { Evh1, Gv }, 0 },
1848   { "sbbB",             { Gb, EbS }, 0 },
1849   { "sbbS",             { Gv, EvS }, 0 },
1850   { "sbbB",             { AL, Ib }, 0 },
1851   { "sbbS",             { eAX, Iv }, 0 },
1852   { X86_64_TABLE (X86_64_1E) },
1853   { X86_64_TABLE (X86_64_1F) },
1854   /* 20 */
1855   { "andB",             { Ebh1, Gb }, 0 },
1856   { "andS",             { Evh1, Gv }, 0 },
1857   { "andB",             { Gb, EbS }, 0 },
1858   { "andS",             { Gv, EvS }, 0 },
1859   { "andB",             { AL, Ib }, 0 },
1860   { "andS",             { eAX, Iv }, 0 },
1861   { Bad_Opcode },       /* SEG ES prefix */
1862   { X86_64_TABLE (X86_64_27) },
1863   /* 28 */
1864   { "subB",             { Ebh1, Gb }, 0 },
1865   { "subS",             { Evh1, Gv }, 0 },
1866   { "subB",             { Gb, EbS }, 0 },
1867   { "subS",             { Gv, EvS }, 0 },
1868   { "subB",             { AL, Ib }, 0 },
1869   { "subS",             { eAX, Iv }, 0 },
1870   { Bad_Opcode },       /* SEG CS prefix */
1871   { X86_64_TABLE (X86_64_2F) },
1872   /* 30 */
1873   { "xorB",             { Ebh1, Gb }, 0 },
1874   { "xorS",             { Evh1, Gv }, 0 },
1875   { "xorB",             { Gb, EbS }, 0 },
1876   { "xorS",             { Gv, EvS }, 0 },
1877   { "xorB",             { AL, Ib }, 0 },
1878   { "xorS",             { eAX, Iv }, 0 },
1879   { Bad_Opcode },       /* SEG SS prefix */
1880   { X86_64_TABLE (X86_64_37) },
1881   /* 38 */
1882   { "cmpB",             { Eb, Gb }, 0 },
1883   { "cmpS",             { Ev, Gv }, 0 },
1884   { "cmpB",             { Gb, EbS }, 0 },
1885   { "cmpS",             { Gv, EvS }, 0 },
1886   { "cmpB",             { AL, Ib }, 0 },
1887   { "cmpS",             { eAX, Iv }, 0 },
1888   { Bad_Opcode },       /* SEG DS prefix */
1889   { X86_64_TABLE (X86_64_3F) },
1890   /* 40 */
1891   { "inc{S|}",          { RMeAX }, 0 },
1892   { "inc{S|}",          { RMeCX }, 0 },
1893   { "inc{S|}",          { RMeDX }, 0 },
1894   { "inc{S|}",          { RMeBX }, 0 },
1895   { "inc{S|}",          { RMeSP }, 0 },
1896   { "inc{S|}",          { RMeBP }, 0 },
1897   { "inc{S|}",          { RMeSI }, 0 },
1898   { "inc{S|}",          { RMeDI }, 0 },
1899   /* 48 */
1900   { "dec{S|}",          { RMeAX }, 0 },
1901   { "dec{S|}",          { RMeCX }, 0 },
1902   { "dec{S|}",          { RMeDX }, 0 },
1903   { "dec{S|}",          { RMeBX }, 0 },
1904   { "dec{S|}",          { RMeSP }, 0 },
1905   { "dec{S|}",          { RMeBP }, 0 },
1906   { "dec{S|}",          { RMeSI }, 0 },
1907   { "dec{S|}",          { RMeDI }, 0 },
1908   /* 50 */
1909   { "push{!P|}",                { RMrAX }, 0 },
1910   { "push{!P|}",                { RMrCX }, 0 },
1911   { "push{!P|}",                { RMrDX }, 0 },
1912   { "push{!P|}",                { RMrBX }, 0 },
1913   { "push{!P|}",                { RMrSP }, 0 },
1914   { "push{!P|}",                { RMrBP }, 0 },
1915   { "push{!P|}",                { RMrSI }, 0 },
1916   { "push{!P|}",                { RMrDI }, 0 },
1917   /* 58 */
1918   { "pop{!P|}",         { RMrAX }, 0 },
1919   { "pop{!P|}",         { RMrCX }, 0 },
1920   { "pop{!P|}",         { RMrDX }, 0 },
1921   { "pop{!P|}",         { RMrBX }, 0 },
1922   { "pop{!P|}",         { RMrSP }, 0 },
1923   { "pop{!P|}",         { RMrBP }, 0 },
1924   { "pop{!P|}",         { RMrSI }, 0 },
1925   { "pop{!P|}",         { RMrDI }, 0 },
1926   /* 60 */
1927   { X86_64_TABLE (X86_64_60) },
1928   { X86_64_TABLE (X86_64_61) },
1929   { X86_64_TABLE (X86_64_62) },
1930   { X86_64_TABLE (X86_64_63) },
1931   { Bad_Opcode },       /* seg fs */
1932   { Bad_Opcode },       /* seg gs */
1933   { Bad_Opcode },       /* op size prefix */
1934   { Bad_Opcode },       /* adr size prefix */
1935   /* 68 */
1936   { "pushP",            { sIv }, 0 },
1937   { "imulS",            { Gv, Ev, Iv }, 0 },
1938   { "pushP",            { sIbT }, 0 },
1939   { "imulS",            { Gv, Ev, sIb }, 0 },
1940   { "ins{b|}",          { Ybr, indirDX }, 0 },
1941   { X86_64_TABLE (X86_64_6D) },
1942   { "outs{b|}",         { indirDXr, Xb }, 0 },
1943   { X86_64_TABLE (X86_64_6F) },
1944   /* 70 */
1945   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
1946   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
1947   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
1948   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
1949   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
1950   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
1951   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
1952   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
1953   /* 78 */
1954   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
1955   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
1956   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
1957   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
1958   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
1959   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
1960   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
1961   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
1962   /* 80 */
1963   { REG_TABLE (REG_80) },
1964   { REG_TABLE (REG_81) },
1965   { X86_64_TABLE (X86_64_82) },
1966   { REG_TABLE (REG_83) },
1967   { "testB",            { Eb, Gb }, 0 },
1968   { "testS",            { Ev, Gv }, 0 },
1969   { "xchgB",            { Ebh2, Gb }, 0 },
1970   { "xchgS",            { Evh2, Gv }, 0 },
1971   /* 88 */
1972   { "movB",             { Ebh3, Gb }, 0 },
1973   { "movS",             { Evh3, Gv }, 0 },
1974   { "movB",             { Gb, EbS }, 0 },
1975   { "movS",             { Gv, EvS }, 0 },
1976   { "movD",             { Sv, Sw }, 0 },
1977   { MOD_TABLE (MOD_8D) },
1978   { "movD",             { Sw, Sv }, 0 },
1979   { REG_TABLE (REG_8F) },
1980   /* 90 */
1981   { PREFIX_TABLE (PREFIX_90) },
1982   { "xchgS",            { RMeCX, eAX }, 0 },
1983   { "xchgS",            { RMeDX, eAX }, 0 },
1984   { "xchgS",            { RMeBX, eAX }, 0 },
1985   { "xchgS",            { RMeSP, eAX }, 0 },
1986   { "xchgS",            { RMeBP, eAX }, 0 },
1987   { "xchgS",            { RMeSI, eAX }, 0 },
1988   { "xchgS",            { RMeDI, eAX }, 0 },
1989   /* 98 */
1990   { "cW{t|}R",          { XX }, 0 },
1991   { "cR{t|}O",          { XX }, 0 },
1992   { X86_64_TABLE (X86_64_9A) },
1993   { Bad_Opcode },       /* fwait */
1994   { "pushfP",           { XX }, 0 },
1995   { "popfP",            { XX }, 0 },
1996   { "sahf",             { XX }, 0 },
1997   { "lahf",             { XX }, 0 },
1998   /* a0 */
1999   { "mov%LB",           { AL, Ob }, 0 },
2000   { "mov%LS",           { eAX, Ov }, 0 },
2001   { "mov%LB",           { Ob, AL }, 0 },
2002   { "mov%LS",           { Ov, eAX }, 0 },
2003   { "movs{b|}",         { Ybr, Xb }, 0 },
2004   { "movs{R|}",         { Yvr, Xv }, 0 },
2005   { "cmps{b|}",         { Xb, Yb }, 0 },
2006   { "cmps{R|}",         { Xv, Yv }, 0 },
2007   /* a8 */
2008   { "testB",            { AL, Ib }, 0 },
2009   { "testS",            { eAX, Iv }, 0 },
2010   { "stosB",            { Ybr, AL }, 0 },
2011   { "stosS",            { Yvr, eAX }, 0 },
2012   { "lodsB",            { ALr, Xb }, 0 },
2013   { "lodsS",            { eAXr, Xv }, 0 },
2014   { "scasB",            { AL, Yb }, 0 },
2015   { "scasS",            { eAX, Yv }, 0 },
2016   /* b0 */
2017   { "movB",             { RMAL, Ib }, 0 },
2018   { "movB",             { RMCL, Ib }, 0 },
2019   { "movB",             { RMDL, Ib }, 0 },
2020   { "movB",             { RMBL, Ib }, 0 },
2021   { "movB",             { RMAH, Ib }, 0 },
2022   { "movB",             { RMCH, Ib }, 0 },
2023   { "movB",             { RMDH, Ib }, 0 },
2024   { "movB",             { RMBH, Ib }, 0 },
2025   /* b8 */
2026   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2027   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2028   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2029   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2030   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2031   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2032   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2033   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2034   /* c0 */
2035   { REG_TABLE (REG_C0) },
2036   { REG_TABLE (REG_C1) },
2037   { X86_64_TABLE (X86_64_C2) },
2038   { X86_64_TABLE (X86_64_C3) },
2039   { X86_64_TABLE (X86_64_C4) },
2040   { X86_64_TABLE (X86_64_C5) },
2041   { REG_TABLE (REG_C6) },
2042   { REG_TABLE (REG_C7) },
2043   /* c8 */
2044   { "enterP",           { Iw, Ib }, 0 },
2045   { "leaveP",           { XX }, 0 },
2046   { "{l|}ret{|f}%LP",   { Iw }, 0 },
2047   { "{l|}ret{|f}%LP",   { XX }, 0 },
2048   { "int3",             { XX }, 0 },
2049   { "int",              { Ib }, 0 },
2050   { X86_64_TABLE (X86_64_CE) },
2051   { "iret%LP",          { XX }, 0 },
2052   /* d0 */
2053   { REG_TABLE (REG_D0) },
2054   { REG_TABLE (REG_D1) },
2055   { REG_TABLE (REG_D2) },
2056   { REG_TABLE (REG_D3) },
2057   { X86_64_TABLE (X86_64_D4) },
2058   { X86_64_TABLE (X86_64_D5) },
2059   { Bad_Opcode },
2060   { "xlat",             { DSBX }, 0 },
2061   /* d8 */
2062   { FLOAT },
2063   { FLOAT },
2064   { FLOAT },
2065   { FLOAT },
2066   { FLOAT },
2067   { FLOAT },
2068   { FLOAT },
2069   { FLOAT },
2070   /* e0 */
2071   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2072   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2073   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2074   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2075   { "inB",              { AL, Ib }, 0 },
2076   { "inG",              { zAX, Ib }, 0 },
2077   { "outB",             { Ib, AL }, 0 },
2078   { "outG",             { Ib, zAX }, 0 },
2079   /* e8 */
2080   { X86_64_TABLE (X86_64_E8) },
2081   { X86_64_TABLE (X86_64_E9) },
2082   { X86_64_TABLE (X86_64_EA) },
2083   { "jmp",              { Jb, BND }, 0 },
2084   { "inB",              { AL, indirDX }, 0 },
2085   { "inG",              { zAX, indirDX }, 0 },
2086   { "outB",             { indirDX, AL }, 0 },
2087   { "outG",             { indirDX, zAX }, 0 },
2088   /* f0 */
2089   { Bad_Opcode },       /* lock prefix */
2090   { "icebp",            { XX }, 0 },
2091   { Bad_Opcode },       /* repne */
2092   { Bad_Opcode },       /* repz */
2093   { "hlt",              { XX }, 0 },
2094   { "cmc",              { XX }, 0 },
2095   { REG_TABLE (REG_F6) },
2096   { REG_TABLE (REG_F7) },
2097   /* f8 */
2098   { "clc",              { XX }, 0 },
2099   { "stc",              { XX }, 0 },
2100   { "cli",              { XX }, 0 },
2101   { "sti",              { XX }, 0 },
2102   { "cld",              { XX }, 0 },
2103   { "std",              { XX }, 0 },
2104   { REG_TABLE (REG_FE) },
2105   { REG_TABLE (REG_FF) },
2106 };
2107
2108 static const struct dis386 dis386_twobyte[] = {
2109   /* 00 */
2110   { REG_TABLE (REG_0F00 ) },
2111   { REG_TABLE (REG_0F01 ) },
2112   { "larS",             { Gv, Ew }, 0 },
2113   { "lslS",             { Gv, Ew }, 0 },
2114   { Bad_Opcode },
2115   { "syscall",          { XX }, 0 },
2116   { "clts",             { XX }, 0 },
2117   { "sysret%LQ",                { XX }, 0 },
2118   /* 08 */
2119   { "invd",             { XX }, 0 },
2120   { PREFIX_TABLE (PREFIX_0F09) },
2121   { Bad_Opcode },
2122   { "ud2",              { XX }, 0 },
2123   { Bad_Opcode },
2124   { REG_TABLE (REG_0F0D) },
2125   { "femms",            { XX }, 0 },
2126   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2127   /* 10 */
2128   { PREFIX_TABLE (PREFIX_0F10) },
2129   { PREFIX_TABLE (PREFIX_0F11) },
2130   { PREFIX_TABLE (PREFIX_0F12) },
2131   { MOD_TABLE (MOD_0F13) },
2132   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2133   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2134   { PREFIX_TABLE (PREFIX_0F16) },
2135   { MOD_TABLE (MOD_0F17) },
2136   /* 18 */
2137   { REG_TABLE (REG_0F18) },
2138   { "nopQ",             { Ev }, 0 },
2139   { PREFIX_TABLE (PREFIX_0F1A) },
2140   { PREFIX_TABLE (PREFIX_0F1B) },
2141   { PREFIX_TABLE (PREFIX_0F1C) },
2142   { "nopQ",             { Ev }, 0 },
2143   { PREFIX_TABLE (PREFIX_0F1E) },
2144   { "nopQ",             { Ev }, 0 },
2145   /* 20 */
2146   { "movZ",             { Em, Cm }, 0 },
2147   { "movZ",             { Em, Dm }, 0 },
2148   { "movZ",             { Cm, Em }, 0 },
2149   { "movZ",             { Dm, Em }, 0 },
2150   { X86_64_TABLE (X86_64_0F24) },
2151   { Bad_Opcode },
2152   { X86_64_TABLE (X86_64_0F26) },
2153   { Bad_Opcode },
2154   /* 28 */
2155   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2156   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2157   { PREFIX_TABLE (PREFIX_0F2A) },
2158   { PREFIX_TABLE (PREFIX_0F2B) },
2159   { PREFIX_TABLE (PREFIX_0F2C) },
2160   { PREFIX_TABLE (PREFIX_0F2D) },
2161   { PREFIX_TABLE (PREFIX_0F2E) },
2162   { PREFIX_TABLE (PREFIX_0F2F) },
2163   /* 30 */
2164   { "wrmsr",            { XX }, 0 },
2165   { "rdtsc",            { XX }, 0 },
2166   { "rdmsr",            { XX }, 0 },
2167   { "rdpmc",            { XX }, 0 },
2168   { "sysenter",         { SEP }, 0 },
2169   { "sysexit",          { SEP }, 0 },
2170   { Bad_Opcode },
2171   { "getsec",           { XX }, 0 },
2172   /* 38 */
2173   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2174   { Bad_Opcode },
2175   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2176   { Bad_Opcode },
2177   { Bad_Opcode },
2178   { Bad_Opcode },
2179   { Bad_Opcode },
2180   { Bad_Opcode },
2181   /* 40 */
2182   { "cmovoS",           { Gv, Ev }, 0 },
2183   { "cmovnoS",          { Gv, Ev }, 0 },
2184   { "cmovbS",           { Gv, Ev }, 0 },
2185   { "cmovaeS",          { Gv, Ev }, 0 },
2186   { "cmoveS",           { Gv, Ev }, 0 },
2187   { "cmovneS",          { Gv, Ev }, 0 },
2188   { "cmovbeS",          { Gv, Ev }, 0 },
2189   { "cmovaS",           { Gv, Ev }, 0 },
2190   /* 48 */
2191   { "cmovsS",           { Gv, Ev }, 0 },
2192   { "cmovnsS",          { Gv, Ev }, 0 },
2193   { "cmovpS",           { Gv, Ev }, 0 },
2194   { "cmovnpS",          { Gv, Ev }, 0 },
2195   { "cmovlS",           { Gv, Ev }, 0 },
2196   { "cmovgeS",          { Gv, Ev }, 0 },
2197   { "cmovleS",          { Gv, Ev }, 0 },
2198   { "cmovgS",           { Gv, Ev }, 0 },
2199   /* 50 */
2200   { MOD_TABLE (MOD_0F50) },
2201   { PREFIX_TABLE (PREFIX_0F51) },
2202   { PREFIX_TABLE (PREFIX_0F52) },
2203   { PREFIX_TABLE (PREFIX_0F53) },
2204   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2205   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2206   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2207   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2208   /* 58 */
2209   { PREFIX_TABLE (PREFIX_0F58) },
2210   { PREFIX_TABLE (PREFIX_0F59) },
2211   { PREFIX_TABLE (PREFIX_0F5A) },
2212   { PREFIX_TABLE (PREFIX_0F5B) },
2213   { PREFIX_TABLE (PREFIX_0F5C) },
2214   { PREFIX_TABLE (PREFIX_0F5D) },
2215   { PREFIX_TABLE (PREFIX_0F5E) },
2216   { PREFIX_TABLE (PREFIX_0F5F) },
2217   /* 60 */
2218   { PREFIX_TABLE (PREFIX_0F60) },
2219   { PREFIX_TABLE (PREFIX_0F61) },
2220   { PREFIX_TABLE (PREFIX_0F62) },
2221   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2222   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2223   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2224   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2225   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2226   /* 68 */
2227   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2228   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2229   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2230   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2231   { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2232   { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2233   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2234   { PREFIX_TABLE (PREFIX_0F6F) },
2235   /* 70 */
2236   { PREFIX_TABLE (PREFIX_0F70) },
2237   { REG_TABLE (REG_0F71) },
2238   { REG_TABLE (REG_0F72) },
2239   { REG_TABLE (REG_0F73) },
2240   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2241   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2242   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2243   { "emms",             { XX }, PREFIX_OPCODE },
2244   /* 78 */
2245   { PREFIX_TABLE (PREFIX_0F78) },
2246   { PREFIX_TABLE (PREFIX_0F79) },
2247   { Bad_Opcode },
2248   { Bad_Opcode },
2249   { PREFIX_TABLE (PREFIX_0F7C) },
2250   { PREFIX_TABLE (PREFIX_0F7D) },
2251   { PREFIX_TABLE (PREFIX_0F7E) },
2252   { PREFIX_TABLE (PREFIX_0F7F) },
2253   /* 80 */
2254   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2255   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2256   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2257   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2258   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2259   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2260   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2261   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2262   /* 88 */
2263   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2264   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2265   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2266   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2267   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2268   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2269   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2270   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2271   /* 90 */
2272   { "seto",             { Eb }, 0 },
2273   { "setno",            { Eb }, 0 },
2274   { "setb",             { Eb }, 0 },
2275   { "setae",            { Eb }, 0 },
2276   { "sete",             { Eb }, 0 },
2277   { "setne",            { Eb }, 0 },
2278   { "setbe",            { Eb }, 0 },
2279   { "seta",             { Eb }, 0 },
2280   /* 98 */
2281   { "sets",             { Eb }, 0 },
2282   { "setns",            { Eb }, 0 },
2283   { "setp",             { Eb }, 0 },
2284   { "setnp",            { Eb }, 0 },
2285   { "setl",             { Eb }, 0 },
2286   { "setge",            { Eb }, 0 },
2287   { "setle",            { Eb }, 0 },
2288   { "setg",             { Eb }, 0 },
2289   /* a0 */
2290   { "pushP",            { fs }, 0 },
2291   { "popP",             { fs }, 0 },
2292   { "cpuid",            { XX }, 0 },
2293   { "btS",              { Ev, Gv }, 0 },
2294   { "shldS",            { Ev, Gv, Ib }, 0 },
2295   { "shldS",            { Ev, Gv, CL }, 0 },
2296   { REG_TABLE (REG_0FA6) },
2297   { REG_TABLE (REG_0FA7) },
2298   /* a8 */
2299   { "pushP",            { gs }, 0 },
2300   { "popP",             { gs }, 0 },
2301   { "rsm",              { XX }, 0 },
2302   { "btsS",             { Evh1, Gv }, 0 },
2303   { "shrdS",            { Ev, Gv, Ib }, 0 },
2304   { "shrdS",            { Ev, Gv, CL }, 0 },
2305   { REG_TABLE (REG_0FAE) },
2306   { "imulS",            { Gv, Ev }, 0 },
2307   /* b0 */
2308   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2309   { "cmpxchgS",         { Evh1, Gv }, 0 },
2310   { MOD_TABLE (MOD_0FB2) },
2311   { "btrS",             { Evh1, Gv }, 0 },
2312   { MOD_TABLE (MOD_0FB4) },
2313   { MOD_TABLE (MOD_0FB5) },
2314   { "movz{bR|x}",       { Gv, Eb }, 0 },
2315   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2316   /* b8 */
2317   { PREFIX_TABLE (PREFIX_0FB8) },
2318   { "ud1S",             { Gv, Ev }, 0 },
2319   { REG_TABLE (REG_0FBA) },
2320   { "btcS",             { Evh1, Gv }, 0 },
2321   { PREFIX_TABLE (PREFIX_0FBC) },
2322   { PREFIX_TABLE (PREFIX_0FBD) },
2323   { "movs{bR|x}",       { Gv, Eb }, 0 },
2324   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2325   /* c0 */
2326   { "xaddB",            { Ebh1, Gb }, 0 },
2327   { "xaddS",            { Evh1, Gv }, 0 },
2328   { PREFIX_TABLE (PREFIX_0FC2) },
2329   { MOD_TABLE (MOD_0FC3) },
2330   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2331   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2332   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2333   { REG_TABLE (REG_0FC7) },
2334   /* c8 */
2335   { "bswap",            { RMeAX }, 0 },
2336   { "bswap",            { RMeCX }, 0 },
2337   { "bswap",            { RMeDX }, 0 },
2338   { "bswap",            { RMeBX }, 0 },
2339   { "bswap",            { RMeSP }, 0 },
2340   { "bswap",            { RMeBP }, 0 },
2341   { "bswap",            { RMeSI }, 0 },
2342   { "bswap",            { RMeDI }, 0 },
2343   /* d0 */
2344   { PREFIX_TABLE (PREFIX_0FD0) },
2345   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2346   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2347   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2348   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2349   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2350   { PREFIX_TABLE (PREFIX_0FD6) },
2351   { MOD_TABLE (MOD_0FD7) },
2352   /* d8 */
2353   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2354   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2355   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2356   { "pand",             { MX, EM }, PREFIX_OPCODE },
2357   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2358   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2359   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2360   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2361   /* e0 */
2362   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2363   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2364   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2365   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2366   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2367   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2368   { PREFIX_TABLE (PREFIX_0FE6) },
2369   { PREFIX_TABLE (PREFIX_0FE7) },
2370   /* e8 */
2371   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2372   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2373   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2374   { "por",              { MX, EM }, PREFIX_OPCODE },
2375   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2376   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2377   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2378   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2379   /* f0 */
2380   { PREFIX_TABLE (PREFIX_0FF0) },
2381   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2382   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2383   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2384   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2385   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2386   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2387   { PREFIX_TABLE (PREFIX_0FF7) },
2388   /* f8 */
2389   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2390   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2391   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2392   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2393   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2394   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2395   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2396   { "ud0S",             { Gv, Ev }, 0 },
2397 };
2398
2399 static const unsigned char onebyte_has_modrm[256] = {
2400   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2401   /*       -------------------------------        */
2402   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2403   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2404   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2405   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2406   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2407   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2408   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2409   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2410   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2411   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2412   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2413   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2414   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2415   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2416   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2417   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2418   /*       -------------------------------        */
2419   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2420 };
2421
2422 static const unsigned char twobyte_has_modrm[256] = {
2423   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2424   /*       -------------------------------        */
2425   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2426   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2427   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2428   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2429   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2430   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2431   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2432   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2433   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2434   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2435   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2436   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2437   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2438   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2439   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2440   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2441   /*       -------------------------------        */
2442   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2443 };
2444
2445 static char obuf[100];
2446 static char *obufp;
2447 static char *mnemonicendp;
2448 static char scratchbuf[100];
2449 static unsigned char *start_codep;
2450 static unsigned char *insn_codep;
2451 static unsigned char *codep;
2452 static unsigned char *end_codep;
2453 static int last_lock_prefix;
2454 static int last_repz_prefix;
2455 static int last_repnz_prefix;
2456 static int last_data_prefix;
2457 static int last_addr_prefix;
2458 static int last_rex_prefix;
2459 static int last_seg_prefix;
2460 static int fwait_prefix;
2461 /* The active segment register prefix.  */
2462 static int active_seg_prefix;
2463 #define MAX_CODE_LENGTH 15
2464 /* We can up to 14 prefixes since the maximum instruction length is
2465    15bytes.  */
2466 static int all_prefixes[MAX_CODE_LENGTH - 1];
2467 static disassemble_info *the_info;
2468 static struct
2469   {
2470     int mod;
2471     int reg;
2472     int rm;
2473   }
2474 modrm;
2475 static unsigned char need_modrm;
2476 static struct
2477   {
2478     int scale;
2479     int index;
2480     int base;
2481   }
2482 sib;
2483 static struct
2484   {
2485     int register_specifier;
2486     int length;
2487     int prefix;
2488     int w;
2489     int evex;
2490     int r;
2491     int v;
2492     int mask_register_specifier;
2493     int zeroing;
2494     int ll;
2495     int b;
2496   }
2497 vex;
2498 static unsigned char need_vex;
2499
2500 struct op
2501   {
2502     const char *name;
2503     unsigned int len;
2504   };
2505
2506 /* If we are accessing mod/rm/reg without need_modrm set, then the
2507    values are stale.  Hitting this abort likely indicates that you
2508    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2509 #define MODRM_CHECK  if (!need_modrm) abort ()
2510
2511 static const char **names64;
2512 static const char **names32;
2513 static const char **names16;
2514 static const char **names8;
2515 static const char **names8rex;
2516 static const char **names_seg;
2517 static const char *index64;
2518 static const char *index32;
2519 static const char **index16;
2520 static const char **names_bnd;
2521
2522 static const char *intel_names64[] = {
2523   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2524   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2525 };
2526 static const char *intel_names32[] = {
2527   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2528   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2529 };
2530 static const char *intel_names16[] = {
2531   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2532   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2533 };
2534 static const char *intel_names8[] = {
2535   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2536 };
2537 static const char *intel_names8rex[] = {
2538   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2539   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2540 };
2541 static const char *intel_names_seg[] = {
2542   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2543 };
2544 static const char *intel_index64 = "riz";
2545 static const char *intel_index32 = "eiz";
2546 static const char *intel_index16[] = {
2547   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2548 };
2549
2550 static const char *att_names64[] = {
2551   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2552   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2553 };
2554 static const char *att_names32[] = {
2555   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2556   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2557 };
2558 static const char *att_names16[] = {
2559   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2560   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2561 };
2562 static const char *att_names8[] = {
2563   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2564 };
2565 static const char *att_names8rex[] = {
2566   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2567   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2568 };
2569 static const char *att_names_seg[] = {
2570   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2571 };
2572 static const char *att_index64 = "%riz";
2573 static const char *att_index32 = "%eiz";
2574 static const char *att_index16[] = {
2575   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2576 };
2577
2578 static const char **names_mm;
2579 static const char *intel_names_mm[] = {
2580   "mm0", "mm1", "mm2", "mm3",
2581   "mm4", "mm5", "mm6", "mm7"
2582 };
2583 static const char *att_names_mm[] = {
2584   "%mm0", "%mm1", "%mm2", "%mm3",
2585   "%mm4", "%mm5", "%mm6", "%mm7"
2586 };
2587
2588 static const char *intel_names_bnd[] = {
2589   "bnd0", "bnd1", "bnd2", "bnd3"
2590 };
2591
2592 static const char *att_names_bnd[] = {
2593   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2594 };
2595
2596 static const char **names_xmm;
2597 static const char *intel_names_xmm[] = {
2598   "xmm0", "xmm1", "xmm2", "xmm3",
2599   "xmm4", "xmm5", "xmm6", "xmm7",
2600   "xmm8", "xmm9", "xmm10", "xmm11",
2601   "xmm12", "xmm13", "xmm14", "xmm15",
2602   "xmm16", "xmm17", "xmm18", "xmm19",
2603   "xmm20", "xmm21", "xmm22", "xmm23",
2604   "xmm24", "xmm25", "xmm26", "xmm27",
2605   "xmm28", "xmm29", "xmm30", "xmm31"
2606 };
2607 static const char *att_names_xmm[] = {
2608   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2609   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2610   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2611   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2612   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2613   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2614   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2615   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2616 };
2617
2618 static const char **names_ymm;
2619 static const char *intel_names_ymm[] = {
2620   "ymm0", "ymm1", "ymm2", "ymm3",
2621   "ymm4", "ymm5", "ymm6", "ymm7",
2622   "ymm8", "ymm9", "ymm10", "ymm11",
2623   "ymm12", "ymm13", "ymm14", "ymm15",
2624   "ymm16", "ymm17", "ymm18", "ymm19",
2625   "ymm20", "ymm21", "ymm22", "ymm23",
2626   "ymm24", "ymm25", "ymm26", "ymm27",
2627   "ymm28", "ymm29", "ymm30", "ymm31"
2628 };
2629 static const char *att_names_ymm[] = {
2630   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2631   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2632   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2633   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2634   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2635   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2636   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2637   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2638 };
2639
2640 static const char **names_zmm;
2641 static const char *intel_names_zmm[] = {
2642   "zmm0", "zmm1", "zmm2", "zmm3",
2643   "zmm4", "zmm5", "zmm6", "zmm7",
2644   "zmm8", "zmm9", "zmm10", "zmm11",
2645   "zmm12", "zmm13", "zmm14", "zmm15",
2646   "zmm16", "zmm17", "zmm18", "zmm19",
2647   "zmm20", "zmm21", "zmm22", "zmm23",
2648   "zmm24", "zmm25", "zmm26", "zmm27",
2649   "zmm28", "zmm29", "zmm30", "zmm31"
2650 };
2651 static const char *att_names_zmm[] = {
2652   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2653   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2654   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2655   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2656   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2657   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2658   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2659   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2660 };
2661
2662 static const char **names_tmm;
2663 static const char *intel_names_tmm[] = {
2664   "tmm0", "tmm1", "tmm2", "tmm3",
2665   "tmm4", "tmm5", "tmm6", "tmm7"
2666 };
2667 static const char *att_names_tmm[] = {
2668   "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2669   "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2670 };
2671
2672 static const char **names_mask;
2673 static const char *intel_names_mask[] = {
2674   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
2675 };
2676 static const char *att_names_mask[] = {
2677   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2678 };
2679
2680 static const char *names_rounding[] =
2681 {
2682   "{rn-sae}",
2683   "{rd-sae}",
2684   "{ru-sae}",
2685   "{rz-sae}"
2686 };
2687
2688 static const struct dis386 reg_table[][8] = {
2689   /* REG_80 */
2690   {
2691     { "addA",   { Ebh1, Ib }, 0 },
2692     { "orA",    { Ebh1, Ib }, 0 },
2693     { "adcA",   { Ebh1, Ib }, 0 },
2694     { "sbbA",   { Ebh1, Ib }, 0 },
2695     { "andA",   { Ebh1, Ib }, 0 },
2696     { "subA",   { Ebh1, Ib }, 0 },
2697     { "xorA",   { Ebh1, Ib }, 0 },
2698     { "cmpA",   { Eb, Ib }, 0 },
2699   },
2700   /* REG_81 */
2701   {
2702     { "addQ",   { Evh1, Iv }, 0 },
2703     { "orQ",    { Evh1, Iv }, 0 },
2704     { "adcQ",   { Evh1, Iv }, 0 },
2705     { "sbbQ",   { Evh1, Iv }, 0 },
2706     { "andQ",   { Evh1, Iv }, 0 },
2707     { "subQ",   { Evh1, Iv }, 0 },
2708     { "xorQ",   { Evh1, Iv }, 0 },
2709     { "cmpQ",   { Ev, Iv }, 0 },
2710   },
2711   /* REG_83 */
2712   {
2713     { "addQ",   { Evh1, sIb }, 0 },
2714     { "orQ",    { Evh1, sIb }, 0 },
2715     { "adcQ",   { Evh1, sIb }, 0 },
2716     { "sbbQ",   { Evh1, sIb }, 0 },
2717     { "andQ",   { Evh1, sIb }, 0 },
2718     { "subQ",   { Evh1, sIb }, 0 },
2719     { "xorQ",   { Evh1, sIb }, 0 },
2720     { "cmpQ",   { Ev, sIb }, 0 },
2721   },
2722   /* REG_8F */
2723   {
2724     { "pop{P|}", { stackEv }, 0 },
2725     { XOP_8F_TABLE (XOP_09) },
2726     { Bad_Opcode },
2727     { Bad_Opcode },
2728     { Bad_Opcode },
2729     { XOP_8F_TABLE (XOP_09) },
2730   },
2731   /* REG_C0 */
2732   {
2733     { "rolA",   { Eb, Ib }, 0 },
2734     { "rorA",   { Eb, Ib }, 0 },
2735     { "rclA",   { Eb, Ib }, 0 },
2736     { "rcrA",   { Eb, Ib }, 0 },
2737     { "shlA",   { Eb, Ib }, 0 },
2738     { "shrA",   { Eb, Ib }, 0 },
2739     { "shlA",   { Eb, Ib }, 0 },
2740     { "sarA",   { Eb, Ib }, 0 },
2741   },
2742   /* REG_C1 */
2743   {
2744     { "rolQ",   { Ev, Ib }, 0 },
2745     { "rorQ",   { Ev, Ib }, 0 },
2746     { "rclQ",   { Ev, Ib }, 0 },
2747     { "rcrQ",   { Ev, Ib }, 0 },
2748     { "shlQ",   { Ev, Ib }, 0 },
2749     { "shrQ",   { Ev, Ib }, 0 },
2750     { "shlQ",   { Ev, Ib }, 0 },
2751     { "sarQ",   { Ev, Ib }, 0 },
2752   },
2753   /* REG_C6 */
2754   {
2755     { "movA",   { Ebh3, Ib }, 0 },
2756     { Bad_Opcode },
2757     { Bad_Opcode },
2758     { Bad_Opcode },
2759     { Bad_Opcode },
2760     { Bad_Opcode },
2761     { Bad_Opcode },
2762     { MOD_TABLE (MOD_C6_REG_7) },
2763   },
2764   /* REG_C7 */
2765   {
2766     { "movQ",   { Evh3, Iv }, 0 },
2767     { Bad_Opcode },
2768     { Bad_Opcode },
2769     { Bad_Opcode },
2770     { Bad_Opcode },
2771     { Bad_Opcode },
2772     { Bad_Opcode },
2773     { MOD_TABLE (MOD_C7_REG_7) },
2774   },
2775   /* REG_D0 */
2776   {
2777     { "rolA",   { Eb, I1 }, 0 },
2778     { "rorA",   { Eb, I1 }, 0 },
2779     { "rclA",   { Eb, I1 }, 0 },
2780     { "rcrA",   { Eb, I1 }, 0 },
2781     { "shlA",   { Eb, I1 }, 0 },
2782     { "shrA",   { Eb, I1 }, 0 },
2783     { "shlA",   { Eb, I1 }, 0 },
2784     { "sarA",   { Eb, I1 }, 0 },
2785   },
2786   /* REG_D1 */
2787   {
2788     { "rolQ",   { Ev, I1 }, 0 },
2789     { "rorQ",   { Ev, I1 }, 0 },
2790     { "rclQ",   { Ev, I1 }, 0 },
2791     { "rcrQ",   { Ev, I1 }, 0 },
2792     { "shlQ",   { Ev, I1 }, 0 },
2793     { "shrQ",   { Ev, I1 }, 0 },
2794     { "shlQ",   { Ev, I1 }, 0 },
2795     { "sarQ",   { Ev, I1 }, 0 },
2796   },
2797   /* REG_D2 */
2798   {
2799     { "rolA",   { Eb, CL }, 0 },
2800     { "rorA",   { Eb, CL }, 0 },
2801     { "rclA",   { Eb, CL }, 0 },
2802     { "rcrA",   { Eb, CL }, 0 },
2803     { "shlA",   { Eb, CL }, 0 },
2804     { "shrA",   { Eb, CL }, 0 },
2805     { "shlA",   { Eb, CL }, 0 },
2806     { "sarA",   { Eb, CL }, 0 },
2807   },
2808   /* REG_D3 */
2809   {
2810     { "rolQ",   { Ev, CL }, 0 },
2811     { "rorQ",   { Ev, CL }, 0 },
2812     { "rclQ",   { Ev, CL }, 0 },
2813     { "rcrQ",   { Ev, CL }, 0 },
2814     { "shlQ",   { Ev, CL }, 0 },
2815     { "shrQ",   { Ev, CL }, 0 },
2816     { "shlQ",   { Ev, CL }, 0 },
2817     { "sarQ",   { Ev, CL }, 0 },
2818   },
2819   /* REG_F6 */
2820   {
2821     { "testA",  { Eb, Ib }, 0 },
2822     { "testA",  { Eb, Ib }, 0 },
2823     { "notA",   { Ebh1 }, 0 },
2824     { "negA",   { Ebh1 }, 0 },
2825     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
2826     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
2827     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
2828     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
2829   },
2830   /* REG_F7 */
2831   {
2832     { "testQ",  { Ev, Iv }, 0 },
2833     { "testQ",  { Ev, Iv }, 0 },
2834     { "notQ",   { Evh1 }, 0 },
2835     { "negQ",   { Evh1 }, 0 },
2836     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
2837     { "imulQ",  { Ev }, 0 },
2838     { "divQ",   { Ev }, 0 },
2839     { "idivQ",  { Ev }, 0 },
2840   },
2841   /* REG_FE */
2842   {
2843     { "incA",   { Ebh1 }, 0 },
2844     { "decA",   { Ebh1 }, 0 },
2845   },
2846   /* REG_FF */
2847   {
2848     { "incQ",   { Evh1 }, 0 },
2849     { "decQ",   { Evh1 }, 0 },
2850     { "call{@|}", { NOTRACK, indirEv, BND }, 0 },
2851     { MOD_TABLE (MOD_FF_REG_3) },
2852     { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 },
2853     { MOD_TABLE (MOD_FF_REG_5) },
2854     { "push{P|}", { stackEv }, 0 },
2855     { Bad_Opcode },
2856   },
2857   /* REG_0F00 */
2858   {
2859     { "sldtD",  { Sv }, 0 },
2860     { "strD",   { Sv }, 0 },
2861     { "lldt",   { Ew }, 0 },
2862     { "ltr",    { Ew }, 0 },
2863     { "verr",   { Ew }, 0 },
2864     { "verw",   { Ew }, 0 },
2865     { Bad_Opcode },
2866     { Bad_Opcode },
2867   },
2868   /* REG_0F01 */
2869   {
2870     { MOD_TABLE (MOD_0F01_REG_0) },
2871     { MOD_TABLE (MOD_0F01_REG_1) },
2872     { MOD_TABLE (MOD_0F01_REG_2) },
2873     { MOD_TABLE (MOD_0F01_REG_3) },
2874     { "smswD",  { Sv }, 0 },
2875     { MOD_TABLE (MOD_0F01_REG_5) },
2876     { "lmsw",   { Ew }, 0 },
2877     { MOD_TABLE (MOD_0F01_REG_7) },
2878   },
2879   /* REG_0F0D */
2880   {
2881     { "prefetch",       { Mb }, 0 },
2882     { "prefetchw",      { Mb }, 0 },
2883     { "prefetchwt1",    { Mb }, 0 },
2884     { "prefetch",       { Mb }, 0 },
2885     { "prefetch",       { Mb }, 0 },
2886     { "prefetch",       { Mb }, 0 },
2887     { "prefetch",       { Mb }, 0 },
2888     { "prefetch",       { Mb }, 0 },
2889   },
2890   /* REG_0F18 */
2891   {
2892     { MOD_TABLE (MOD_0F18_REG_0) },
2893     { MOD_TABLE (MOD_0F18_REG_1) },
2894     { MOD_TABLE (MOD_0F18_REG_2) },
2895     { MOD_TABLE (MOD_0F18_REG_3) },
2896     { MOD_TABLE (MOD_0F18_REG_4) },
2897     { MOD_TABLE (MOD_0F18_REG_5) },
2898     { MOD_TABLE (MOD_0F18_REG_6) },
2899     { MOD_TABLE (MOD_0F18_REG_7) },
2900   },
2901   /* REG_0F1C_P_0_MOD_0 */
2902   {
2903     { "cldemote",       { Mb }, 0 },
2904     { "nopQ",           { Ev }, 0 },
2905     { "nopQ",           { Ev }, 0 },
2906     { "nopQ",           { Ev }, 0 },
2907     { "nopQ",           { Ev }, 0 },
2908     { "nopQ",           { Ev }, 0 },
2909     { "nopQ",           { Ev }, 0 },
2910     { "nopQ",           { Ev }, 0 },
2911   },
2912   /* REG_0F1E_P_1_MOD_3 */
2913   {
2914     { "nopQ",           { Ev }, 0 },
2915     { "rdsspK",         { Edq }, PREFIX_OPCODE },
2916     { "nopQ",           { Ev }, 0 },
2917     { "nopQ",           { Ev }, 0 },
2918     { "nopQ",           { Ev }, 0 },
2919     { "nopQ",           { Ev }, 0 },
2920     { "nopQ",           { Ev }, 0 },
2921     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2922   },
2923   /* REG_0F38D8_PREFIX_1 */
2924   {
2925     { "aesencwide128kl",        { M }, 0 },
2926     { "aesdecwide128kl",        { M }, 0 },
2927     { "aesencwide256kl",        { M }, 0 },
2928     { "aesdecwide256kl",        { M }, 0 },
2929   },
2930   /* REG_0F71 */
2931   {
2932     { Bad_Opcode },
2933     { Bad_Opcode },
2934     { MOD_TABLE (MOD_0F71_REG_2) },
2935     { Bad_Opcode },
2936     { MOD_TABLE (MOD_0F71_REG_4) },
2937     { Bad_Opcode },
2938     { MOD_TABLE (MOD_0F71_REG_6) },
2939   },
2940   /* REG_0F72 */
2941   {
2942     { Bad_Opcode },
2943     { Bad_Opcode },
2944     { MOD_TABLE (MOD_0F72_REG_2) },
2945     { Bad_Opcode },
2946     { MOD_TABLE (MOD_0F72_REG_4) },
2947     { Bad_Opcode },
2948     { MOD_TABLE (MOD_0F72_REG_6) },
2949   },
2950   /* REG_0F73 */
2951   {
2952     { Bad_Opcode },
2953     { Bad_Opcode },
2954     { MOD_TABLE (MOD_0F73_REG_2) },
2955     { MOD_TABLE (MOD_0F73_REG_3) },
2956     { Bad_Opcode },
2957     { Bad_Opcode },
2958     { MOD_TABLE (MOD_0F73_REG_6) },
2959     { MOD_TABLE (MOD_0F73_REG_7) },
2960   },
2961   /* REG_0FA6 */
2962   {
2963     { "montmul",        { { OP_0f07, 0 } }, 0 },
2964     { "xsha1",          { { OP_0f07, 0 } }, 0 },
2965     { "xsha256",        { { OP_0f07, 0 } }, 0 },
2966   },
2967   /* REG_0FA7 */
2968   {
2969     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
2970     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
2971     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
2972     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
2973     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
2974     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
2975   },
2976   /* REG_0FAE */
2977   {
2978     { MOD_TABLE (MOD_0FAE_REG_0) },
2979     { MOD_TABLE (MOD_0FAE_REG_1) },
2980     { MOD_TABLE (MOD_0FAE_REG_2) },
2981     { MOD_TABLE (MOD_0FAE_REG_3) },
2982     { MOD_TABLE (MOD_0FAE_REG_4) },
2983     { MOD_TABLE (MOD_0FAE_REG_5) },
2984     { MOD_TABLE (MOD_0FAE_REG_6) },
2985     { MOD_TABLE (MOD_0FAE_REG_7) },
2986   },
2987   /* REG_0FBA */
2988   {
2989     { Bad_Opcode },
2990     { Bad_Opcode },
2991     { Bad_Opcode },
2992     { Bad_Opcode },
2993     { "btQ",    { Ev, Ib }, 0 },
2994     { "btsQ",   { Evh1, Ib }, 0 },
2995     { "btrQ",   { Evh1, Ib }, 0 },
2996     { "btcQ",   { Evh1, Ib }, 0 },
2997   },
2998   /* REG_0FC7 */
2999   {
3000     { Bad_Opcode },
3001     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3002     { Bad_Opcode },
3003     { MOD_TABLE (MOD_0FC7_REG_3) },
3004     { MOD_TABLE (MOD_0FC7_REG_4) },
3005     { MOD_TABLE (MOD_0FC7_REG_5) },
3006     { MOD_TABLE (MOD_0FC7_REG_6) },
3007     { MOD_TABLE (MOD_0FC7_REG_7) },
3008   },
3009   /* REG_VEX_0F71 */
3010   {
3011     { Bad_Opcode },
3012     { Bad_Opcode },
3013     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3014     { Bad_Opcode },
3015     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3016     { Bad_Opcode },
3017     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3018   },
3019   /* REG_VEX_0F72 */
3020   {
3021     { Bad_Opcode },
3022     { Bad_Opcode },
3023     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3024     { Bad_Opcode },
3025     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3026     { Bad_Opcode },
3027     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3028   },
3029   /* REG_VEX_0F73 */
3030   {
3031     { Bad_Opcode },
3032     { Bad_Opcode },
3033     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3034     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3035     { Bad_Opcode },
3036     { Bad_Opcode },
3037     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3038     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3039   },
3040   /* REG_VEX_0FAE */
3041   {
3042     { Bad_Opcode },
3043     { Bad_Opcode },
3044     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3045     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3046   },
3047   /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
3048   {
3049     { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) },
3050   },
3051   /* REG_VEX_0F38F3 */
3052   {
3053     { Bad_Opcode },
3054     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1) },
3055     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2) },
3056     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3) },
3057   },
3058   /* REG_0FXOP_09_01_L_0 */
3059   {
3060     { Bad_Opcode },
3061     { "blcfill",        { VexGdq, Edq }, 0 },
3062     { "blsfill",        { VexGdq, Edq }, 0 },
3063     { "blcs",   { VexGdq, Edq }, 0 },
3064     { "tzmsk",  { VexGdq, Edq }, 0 },
3065     { "blcic",  { VexGdq, Edq }, 0 },
3066     { "blsic",  { VexGdq, Edq }, 0 },
3067     { "t1mskc", { VexGdq, Edq }, 0 },
3068   },
3069   /* REG_0FXOP_09_02_L_0 */
3070   {
3071     { Bad_Opcode },
3072     { "blcmsk", { VexGdq, Edq }, 0 },
3073     { Bad_Opcode },
3074     { Bad_Opcode },
3075     { Bad_Opcode },
3076     { Bad_Opcode },
3077     { "blci",   { VexGdq, Edq }, 0 },
3078   },
3079   /* REG_0FXOP_09_12_M_1_L_0 */
3080   {
3081     { "llwpcb", { Edq }, 0 },
3082     { "slwpcb", { Edq }, 0 },
3083   },
3084   /* REG_0FXOP_0A_12_L_0 */
3085   {
3086     { "lwpins", { VexGdq, Ed, Id }, 0 },
3087     { "lwpval", { VexGdq, Ed, Id }, 0 },
3088   },
3089
3090 #include "i386-dis-evex-reg.h"
3091 };
3092
3093 static const struct dis386 prefix_table[][4] = {
3094   /* PREFIX_90 */
3095   {
3096     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3097     { "pause", { XX }, 0 },
3098     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3099     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3100   },
3101
3102   /* PREFIX_0F01_REG_1_RM_4 */
3103   {
3104     { Bad_Opcode },
3105     { Bad_Opcode },
3106     { "tdcall",         { Skip_MODRM }, 0 },
3107     { Bad_Opcode },
3108   },
3109
3110   /* PREFIX_0F01_REG_1_RM_5 */
3111   {
3112     { Bad_Opcode },
3113     { Bad_Opcode },
3114     { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) },
3115     { Bad_Opcode },
3116   },
3117
3118   /* PREFIX_0F01_REG_1_RM_6 */
3119   {
3120     { Bad_Opcode },
3121     { Bad_Opcode },
3122     { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) },
3123     { Bad_Opcode },
3124   },
3125
3126   /* PREFIX_0F01_REG_1_RM_7 */
3127   {
3128     { "encls",          { Skip_MODRM }, 0 },
3129     { Bad_Opcode },
3130     { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) },
3131     { Bad_Opcode },
3132   },
3133
3134   /* PREFIX_0F01_REG_3_RM_1 */
3135   {
3136     { "vmmcall",        { Skip_MODRM }, 0 },
3137     { "vmgexit",        { Skip_MODRM }, 0 },
3138     { Bad_Opcode },
3139     { "vmgexit",        { Skip_MODRM }, 0 },
3140   },
3141
3142   /* PREFIX_0F01_REG_5_MOD_0 */
3143   {
3144     { Bad_Opcode },
3145     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3146   },
3147
3148   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3149   {
3150     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
3151     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3152     { Bad_Opcode },
3153     { "xsusldtrk",      { Skip_MODRM }, PREFIX_OPCODE },
3154   },
3155
3156   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3157   {
3158     { Bad_Opcode },
3159     { Bad_Opcode },
3160     { Bad_Opcode },
3161     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3162   },
3163
3164   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3165   {
3166     { Bad_Opcode },
3167     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3168   },
3169
3170   /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
3171   {
3172     { Bad_Opcode },
3173     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1) },
3174   },
3175
3176   /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
3177   {
3178     { Bad_Opcode },
3179     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1) },
3180   },
3181
3182   /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3183   {
3184     { "rdpkru", { Skip_MODRM }, 0 },
3185     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1) },
3186   },
3187
3188   /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3189   {
3190     { "wrpkru", { Skip_MODRM }, 0 },
3191     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1) },
3192   },
3193
3194   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3195   {
3196     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3197     { "mcommit",        { Skip_MODRM }, 0 },
3198   },
3199
3200   /* PREFIX_0F09 */
3201   {
3202     { "wbinvd",   { XX }, 0 },
3203     { "wbnoinvd", { XX }, 0 },
3204   },
3205
3206   /* PREFIX_0F10 */
3207   {
3208     { "movups", { XM, EXx }, PREFIX_OPCODE },
3209     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3210     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3211     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3212   },
3213
3214   /* PREFIX_0F11 */
3215   {
3216     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3217     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3218     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3219     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3220   },
3221
3222   /* PREFIX_0F12 */
3223   {
3224     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3225     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3226     { MOD_TABLE (MOD_0F12_PREFIX_2) },
3227     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3228   },
3229
3230   /* PREFIX_0F16 */
3231   {
3232     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3233     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3234     { MOD_TABLE (MOD_0F16_PREFIX_2) },
3235   },
3236
3237   /* PREFIX_0F1A */
3238   {
3239     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3240     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3241     { "bndmov", { Gbnd, Ebnd }, 0 },
3242     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3243   },
3244
3245   /* PREFIX_0F1B */
3246   {
3247     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3248     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3249     { "bndmov", { EbndS, Gbnd }, 0 },
3250     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3251   },
3252
3253   /* PREFIX_0F1C */
3254   {
3255     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3256     { "nopQ",   { Ev }, PREFIX_OPCODE },
3257     { "nopQ",   { Ev }, PREFIX_OPCODE },
3258     { "nopQ",   { Ev }, PREFIX_OPCODE },
3259   },
3260
3261   /* PREFIX_0F1E */
3262   {
3263     { "nopQ",   { Ev }, PREFIX_OPCODE },
3264     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3265     { "nopQ",   { Ev }, PREFIX_OPCODE },
3266     { "nopQ",   { Ev }, PREFIX_OPCODE },
3267   },
3268
3269   /* PREFIX_0F2A */
3270   {
3271     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3272     { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3273     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3274     { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3275   },
3276
3277   /* PREFIX_0F2B */
3278   {
3279     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3280     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3281     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3282     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3283   },
3284
3285   /* PREFIX_0F2C */
3286   {
3287     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3288     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3289     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3290     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3291   },
3292
3293   /* PREFIX_0F2D */
3294   {
3295     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3296     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3297     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3298     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3299   },
3300
3301   /* PREFIX_0F2E */
3302   {
3303     { "ucomiss",{ XM, EXd }, 0 },
3304     { Bad_Opcode },
3305     { "ucomisd",{ XM, EXq }, 0 },
3306   },
3307
3308   /* PREFIX_0F2F */
3309   {
3310     { "comiss", { XM, EXd }, 0 },
3311     { Bad_Opcode },
3312     { "comisd", { XM, EXq }, 0 },
3313   },
3314
3315   /* PREFIX_0F51 */
3316   {
3317     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3318     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3319     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3320     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3321   },
3322
3323   /* PREFIX_0F52 */
3324   {
3325     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3326     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3327   },
3328
3329   /* PREFIX_0F53 */
3330   {
3331     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3332     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3333   },
3334
3335   /* PREFIX_0F58 */
3336   {
3337     { "addps", { XM, EXx }, PREFIX_OPCODE },
3338     { "addss", { XM, EXd }, PREFIX_OPCODE },
3339     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3340     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3341   },
3342
3343   /* PREFIX_0F59 */
3344   {
3345     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3346     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3347     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3348     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3349   },
3350
3351   /* PREFIX_0F5A */
3352   {
3353     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3354     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3355     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3356     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3357   },
3358
3359   /* PREFIX_0F5B */
3360   {
3361     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3362     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3363     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3364   },
3365
3366   /* PREFIX_0F5C */
3367   {
3368     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3369     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3370     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3371     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3372   },
3373
3374   /* PREFIX_0F5D */
3375   {
3376     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3377     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3378     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3379     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3380   },
3381
3382   /* PREFIX_0F5E */
3383   {
3384     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3385     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3386     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3387     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3388   },
3389
3390   /* PREFIX_0F5F */
3391   {
3392     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3393     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3394     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3395     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3396   },
3397
3398   /* PREFIX_0F60 */
3399   {
3400     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3401     { Bad_Opcode },
3402     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3403   },
3404
3405   /* PREFIX_0F61 */
3406   {
3407     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3408     { Bad_Opcode },
3409     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3410   },
3411
3412   /* PREFIX_0F62 */
3413   {
3414     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3415     { Bad_Opcode },
3416     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3417   },
3418
3419   /* PREFIX_0F6F */
3420   {
3421     { "movq",   { MX, EM }, PREFIX_OPCODE },
3422     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3423     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3424   },
3425
3426   /* PREFIX_0F70 */
3427   {
3428     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3429     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3430     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3431     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3432   },
3433
3434   /* PREFIX_0F78 */
3435   {
3436     {"vmread",  { Em, Gm }, 0 },
3437     { Bad_Opcode },
3438     {"extrq",   { XS, Ib, Ib }, 0 },
3439     {"insertq", { XM, XS, Ib, Ib }, 0 },
3440   },
3441
3442   /* PREFIX_0F79 */
3443   {
3444     {"vmwrite", { Gm, Em }, 0 },
3445     { Bad_Opcode },
3446     {"extrq",   { XM, XS }, 0 },
3447     {"insertq", { XM, XS }, 0 },
3448   },
3449
3450   /* PREFIX_0F7C */
3451   {
3452     { Bad_Opcode },
3453     { Bad_Opcode },
3454     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3455     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3456   },
3457
3458   /* PREFIX_0F7D */
3459   {
3460     { Bad_Opcode },
3461     { Bad_Opcode },
3462     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3463     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3464   },
3465
3466   /* PREFIX_0F7E */
3467   {
3468     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3469     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3470     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3471   },
3472
3473   /* PREFIX_0F7F */
3474   {
3475     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3476     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3477     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3478   },
3479
3480   /* PREFIX_0FAE_REG_0_MOD_3 */
3481   {
3482     { Bad_Opcode },
3483     { "rdfsbase", { Ev }, 0 },
3484   },
3485
3486   /* PREFIX_0FAE_REG_1_MOD_3 */
3487   {
3488     { Bad_Opcode },
3489     { "rdgsbase", { Ev }, 0 },
3490   },
3491
3492   /* PREFIX_0FAE_REG_2_MOD_3 */
3493   {
3494     { Bad_Opcode },
3495     { "wrfsbase", { Ev }, 0 },
3496   },
3497
3498   /* PREFIX_0FAE_REG_3_MOD_3 */
3499   {
3500     { Bad_Opcode },
3501     { "wrgsbase", { Ev }, 0 },
3502   },
3503
3504   /* PREFIX_0FAE_REG_4_MOD_0 */
3505   {
3506     { "xsave",  { FXSAVE }, 0 },
3507     { "ptwrite{%LQ|}", { Edq }, 0 },
3508   },
3509
3510   /* PREFIX_0FAE_REG_4_MOD_3 */
3511   {
3512     { Bad_Opcode },
3513     { "ptwrite{%LQ|}", { Edq }, 0 },
3514   },
3515
3516   /* PREFIX_0FAE_REG_5_MOD_3 */
3517   {
3518     { "lfence",         { Skip_MODRM }, 0 },
3519     { "incsspK",        { Edq }, PREFIX_OPCODE },
3520   },
3521
3522   /* PREFIX_0FAE_REG_6_MOD_0 */
3523   {
3524     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3525     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3526     { "clwb",   { Mb }, PREFIX_OPCODE },
3527   },
3528
3529   /* PREFIX_0FAE_REG_6_MOD_3 */
3530   {
3531     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3532     { "umonitor",       { Eva }, PREFIX_OPCODE },
3533     { "tpause", { Edq }, PREFIX_OPCODE },
3534     { "umwait", { Edq }, PREFIX_OPCODE },
3535   },
3536
3537   /* PREFIX_0FAE_REG_7_MOD_0 */
3538   {
3539     { "clflush",        { Mb }, 0 },
3540     { Bad_Opcode },
3541     { "clflushopt",     { Mb }, 0 },
3542   },
3543
3544   /* PREFIX_0FB8 */
3545   {
3546     { Bad_Opcode },
3547     { "popcntS", { Gv, Ev }, 0 },
3548   },
3549
3550   /* PREFIX_0FBC */
3551   {
3552     { "bsfS",   { Gv, Ev }, 0 },
3553     { "tzcntS", { Gv, Ev }, 0 },
3554     { "bsfS",   { Gv, Ev }, 0 },
3555   },
3556
3557   /* PREFIX_0FBD */
3558   {
3559     { "bsrS",   { Gv, Ev }, 0 },
3560     { "lzcntS", { Gv, Ev }, 0 },
3561     { "bsrS",   { Gv, Ev }, 0 },
3562   },
3563
3564   /* PREFIX_0FC2 */
3565   {
3566     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
3567     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
3568     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
3569     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
3570   },
3571
3572   /* PREFIX_0FC7_REG_6_MOD_0 */
3573   {
3574     { "vmptrld",{ Mq }, 0 },
3575     { "vmxon",  { Mq }, 0 },
3576     { "vmclear",{ Mq }, 0 },
3577   },
3578
3579   /* PREFIX_0FC7_REG_6_MOD_3 */
3580   {
3581     { "rdrand", { Ev }, 0 },
3582     { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1) },
3583     { "rdrand", { Ev }, 0 }
3584   },
3585
3586   /* PREFIX_0FC7_REG_7_MOD_3 */
3587   {
3588     { "rdseed", { Ev }, 0 },
3589     { "rdpid",  { Em }, 0 },
3590     { "rdseed", { Ev }, 0 },
3591   },
3592
3593   /* PREFIX_0FD0 */
3594   {
3595     { Bad_Opcode },
3596     { Bad_Opcode },
3597     { "addsubpd", { XM, EXx }, 0 },
3598     { "addsubps", { XM, EXx }, 0 },
3599   },
3600
3601   /* PREFIX_0FD6 */
3602   {
3603     { Bad_Opcode },
3604     { "movq2dq",{ XM, MS }, 0 },
3605     { "movq",   { EXqS, XM }, 0 },
3606     { "movdq2q",{ MX, XS }, 0 },
3607   },
3608
3609   /* PREFIX_0FE6 */
3610   {
3611     { Bad_Opcode },
3612     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
3613     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
3614     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
3615   },
3616
3617   /* PREFIX_0FE7 */
3618   {
3619     { "movntq", { Mq, MX }, PREFIX_OPCODE },
3620     { Bad_Opcode },
3621     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3622   },
3623
3624   /* PREFIX_0FF0 */
3625   {
3626     { Bad_Opcode },
3627     { Bad_Opcode },
3628     { Bad_Opcode },
3629     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3630   },
3631
3632   /* PREFIX_0FF7 */
3633   {
3634     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
3635     { Bad_Opcode },
3636     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
3637   },
3638
3639   /* PREFIX_0F38D8 */
3640   {
3641     { Bad_Opcode },
3642     { REG_TABLE (REG_0F38D8_PREFIX_1) },
3643   },
3644
3645   /* PREFIX_0F38DC */
3646   {
3647     { Bad_Opcode },
3648     { MOD_TABLE (MOD_0F38DC_PREFIX_1) },
3649     { "aesenc", { XM, EXx }, 0 },
3650   },
3651
3652   /* PREFIX_0F38DD */
3653   {
3654     { Bad_Opcode },
3655     { MOD_TABLE (MOD_0F38DD_PREFIX_1) },
3656     { "aesenclast", { XM, EXx }, 0 },
3657   },
3658
3659   /* PREFIX_0F38DE */
3660   {
3661     { Bad_Opcode },
3662     { MOD_TABLE (MOD_0F38DE_PREFIX_1) },
3663     { "aesdec", { XM, EXx }, 0 },
3664   },
3665
3666   /* PREFIX_0F38DF */
3667   {
3668     { Bad_Opcode },
3669     { MOD_TABLE (MOD_0F38DF_PREFIX_1) },
3670     { "aesdeclast", { XM, EXx }, 0 },
3671   },
3672
3673   /* PREFIX_0F38F0 */
3674   {
3675     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3676     { Bad_Opcode },
3677     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3678     { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
3679   },
3680
3681   /* PREFIX_0F38F1 */
3682   {
3683     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3684     { Bad_Opcode },
3685     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3686     { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
3687   },
3688
3689   /* PREFIX_0F38F6 */
3690   {
3691     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
3692     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
3693     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
3694     { Bad_Opcode },
3695   },
3696
3697   /* PREFIX_0F38F8 */
3698   {
3699     { Bad_Opcode },
3700     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
3701     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
3702     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
3703   },
3704   /* PREFIX_0F38FA */
3705   {
3706     { Bad_Opcode },
3707     { MOD_TABLE (MOD_0F38FA_PREFIX_1) },
3708   },
3709
3710   /* PREFIX_0F38FB */
3711   {
3712     { Bad_Opcode },
3713     { MOD_TABLE (MOD_0F38FB_PREFIX_1) },
3714   },
3715
3716   /* PREFIX_VEX_0F10 */
3717   {
3718     { "vmovups",        { XM, EXx }, 0 },
3719     { "vmovss",         { XMScalar, VexScalarR, EXxmm_md }, 0 },
3720     { "vmovupd",        { XM, EXx }, 0 },
3721     { "vmovsd",         { XMScalar, VexScalarR, EXxmm_mq }, 0 },
3722   },
3723
3724   /* PREFIX_VEX_0F11 */
3725   {
3726     { "vmovups",        { EXxS, XM }, 0 },
3727     { "vmovss",         { EXdS, VexScalarR, XMScalar }, 0 },
3728     { "vmovupd",        { EXxS, XM }, 0 },
3729     { "vmovsd",         { EXqS, VexScalarR, XMScalar }, 0 },
3730   },
3731
3732   /* PREFIX_VEX_0F12 */
3733   {
3734     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3735     { "vmovsldup",      { XM, EXx }, 0 },
3736     { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
3737     { "vmovddup",       { XM, EXymmq }, 0 },
3738   },
3739
3740   /* PREFIX_VEX_0F16 */
3741   {
3742     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3743     { "vmovshdup",      { XM, EXx }, 0 },
3744     { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
3745   },
3746
3747   /* PREFIX_VEX_0F2A */
3748   {
3749     { Bad_Opcode },
3750     { "vcvtsi2ss{%LQ|}",        { XMScalar, VexScalar, Edq }, 0 },
3751     { Bad_Opcode },
3752     { "vcvtsi2sd{%LQ|}",        { XMScalar, VexScalar, Edq }, 0 },
3753   },
3754
3755   /* PREFIX_VEX_0F2C */
3756   {
3757     { Bad_Opcode },
3758     { "vcvttss2si",     { Gdq, EXxmm_md, EXxEVexS }, 0 },
3759     { Bad_Opcode },
3760     { "vcvttsd2si",     { Gdq, EXxmm_mq, EXxEVexS }, 0 },
3761   },
3762
3763   /* PREFIX_VEX_0F2D */
3764   {
3765     { Bad_Opcode },
3766     { "vcvtss2si",      { Gdq, EXxmm_md, EXxEVexR }, 0 },
3767     { Bad_Opcode },
3768     { "vcvtsd2si",      { Gdq, EXxmm_mq, EXxEVexR }, 0 },
3769   },
3770
3771   /* PREFIX_VEX_0F2E */
3772   {
3773     { "vucomisX",       { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
3774     { Bad_Opcode },
3775     { "vucomisX",       { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
3776   },
3777
3778   /* PREFIX_VEX_0F2F */
3779   {
3780     { "vcomisX",        { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
3781     { Bad_Opcode },
3782     { "vcomisX",        { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
3783   },
3784
3785   /* PREFIX_VEX_0F41 */
3786   {
3787     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
3788     { Bad_Opcode },
3789     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
3790   },
3791
3792   /* PREFIX_VEX_0F42 */
3793   {
3794     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
3795     { Bad_Opcode },
3796     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
3797   },
3798
3799   /* PREFIX_VEX_0F44 */
3800   {
3801     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
3802     { Bad_Opcode },
3803     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
3804   },
3805
3806   /* PREFIX_VEX_0F45 */
3807   {
3808     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
3809     { Bad_Opcode },
3810     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
3811   },
3812
3813   /* PREFIX_VEX_0F46 */
3814   {
3815     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
3816     { Bad_Opcode },
3817     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
3818   },
3819
3820   /* PREFIX_VEX_0F47 */
3821   {
3822     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
3823     { Bad_Opcode },
3824     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
3825   },
3826
3827   /* PREFIX_VEX_0F4A */
3828   {
3829     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
3830     { Bad_Opcode },
3831     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
3832   },
3833
3834   /* PREFIX_VEX_0F4B */
3835   {
3836     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
3837     { Bad_Opcode },
3838     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
3839   },
3840
3841   /* PREFIX_VEX_0F51 */
3842   {
3843     { "vsqrtps",        { XM, EXx }, 0 },
3844     { "vsqrtss",        { XMScalar, VexScalar, EXxmm_md }, 0 },
3845     { "vsqrtpd",        { XM, EXx }, 0 },
3846     { "vsqrtsd",        { XMScalar, VexScalar, EXxmm_mq }, 0 },
3847   },
3848
3849   /* PREFIX_VEX_0F52 */
3850   {
3851     { "vrsqrtps",       { XM, EXx }, 0 },
3852     { "vrsqrtss",       { XMScalar, VexScalar, EXxmm_md }, 0 },
3853   },
3854
3855   /* PREFIX_VEX_0F53 */
3856   {
3857     { "vrcpps",         { XM, EXx }, 0 },
3858     { "vrcpss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3859   },
3860
3861   /* PREFIX_VEX_0F58 */
3862   {
3863     { "vaddps",         { XM, Vex, EXx }, 0 },
3864     { "vaddss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3865     { "vaddpd",         { XM, Vex, EXx }, 0 },
3866     { "vaddsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3867   },
3868
3869   /* PREFIX_VEX_0F59 */
3870   {
3871     { "vmulps",         { XM, Vex, EXx }, 0 },
3872     { "vmulss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3873     { "vmulpd",         { XM, Vex, EXx }, 0 },
3874     { "vmulsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3875   },
3876
3877   /* PREFIX_VEX_0F5A */
3878   {
3879     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
3880     { "vcvtss2sd",      { XMScalar, VexScalar, EXxmm_md }, 0 },
3881     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
3882     { "vcvtsd2ss",      { XMScalar, VexScalar, EXxmm_mq }, 0 },
3883   },
3884
3885   /* PREFIX_VEX_0F5B */
3886   {
3887     { "vcvtdq2ps",      { XM, EXx }, 0 },
3888     { "vcvttps2dq",     { XM, EXx }, 0 },
3889     { "vcvtps2dq",      { XM, EXx }, 0 },
3890   },
3891
3892   /* PREFIX_VEX_0F5C */
3893   {
3894     { "vsubps",         { XM, Vex, EXx }, 0 },
3895     { "vsubss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3896     { "vsubpd",         { XM, Vex, EXx }, 0 },
3897     { "vsubsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3898   },
3899
3900   /* PREFIX_VEX_0F5D */
3901   {
3902     { "vminps",         { XM, Vex, EXx }, 0 },
3903     { "vminss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3904     { "vminpd",         { XM, Vex, EXx }, 0 },
3905     { "vminsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3906   },
3907
3908   /* PREFIX_VEX_0F5E */
3909   {
3910     { "vdivps",         { XM, Vex, EXx }, 0 },
3911     { "vdivss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3912     { "vdivpd",         { XM, Vex, EXx }, 0 },
3913     { "vdivsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3914   },
3915
3916   /* PREFIX_VEX_0F5F */
3917   {
3918     { "vmaxps",         { XM, Vex, EXx }, 0 },
3919     { "vmaxss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3920     { "vmaxpd",         { XM, Vex, EXx }, 0 },
3921     { "vmaxsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3922   },
3923
3924   /* PREFIX_VEX_0F6F */
3925   {
3926     { Bad_Opcode },
3927     { "vmovdqu",        { XM, EXx }, 0 },
3928     { "vmovdqa",        { XM, EXx }, 0 },
3929   },
3930
3931   /* PREFIX_VEX_0F70 */
3932   {
3933     { Bad_Opcode },
3934     { "vpshufhw",       { XM, EXx, Ib }, 0 },
3935     { "vpshufd",        { XM, EXx, Ib }, 0 },
3936     { "vpshuflw",       { XM, EXx, Ib }, 0 },
3937   },
3938
3939   /* PREFIX_VEX_0F7C */
3940   {
3941     { Bad_Opcode },
3942     { Bad_Opcode },
3943     { "vhaddpd",        { XM, Vex, EXx }, 0 },
3944     { "vhaddps",        { XM, Vex, EXx }, 0 },
3945   },
3946
3947   /* PREFIX_VEX_0F7D */
3948   {
3949     { Bad_Opcode },
3950     { Bad_Opcode },
3951     { "vhsubpd",        { XM, Vex, EXx }, 0 },
3952     { "vhsubps",        { XM, Vex, EXx }, 0 },
3953   },
3954
3955   /* PREFIX_VEX_0F7E */
3956   {
3957     { Bad_Opcode },
3958     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
3959     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
3960   },
3961
3962   /* PREFIX_VEX_0F7F */
3963   {
3964     { Bad_Opcode },
3965     { "vmovdqu",        { EXxS, XM }, 0 },
3966     { "vmovdqa",        { EXxS, XM }, 0 },
3967   },
3968
3969   /* PREFIX_VEX_0F90 */
3970   {
3971     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
3972     { Bad_Opcode },
3973     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
3974   },
3975
3976   /* PREFIX_VEX_0F91 */
3977   {
3978     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
3979     { Bad_Opcode },
3980     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
3981   },
3982
3983   /* PREFIX_VEX_0F92 */
3984   {
3985     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
3986     { Bad_Opcode },
3987     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
3988     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
3989   },
3990
3991   /* PREFIX_VEX_0F93 */
3992   {
3993     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
3994     { Bad_Opcode },
3995     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
3996     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
3997   },
3998
3999   /* PREFIX_VEX_0F98 */
4000   {
4001     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
4002     { Bad_Opcode },
4003     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
4004   },
4005
4006   /* PREFIX_VEX_0F99 */
4007   {
4008     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
4009     { Bad_Opcode },
4010     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
4011   },
4012
4013   /* PREFIX_VEX_0FC2 */
4014   {
4015     { "vcmpps",         { XM, Vex, EXx, CMP }, 0 },
4016     { "vcmpss",         { XMScalar, VexScalar, EXxmm_md, CMP }, 0 },
4017     { "vcmppd",         { XM, Vex, EXx, CMP }, 0 },
4018     { "vcmpsd",         { XMScalar, VexScalar, EXxmm_mq, CMP }, 0 },
4019   },
4020
4021   /* PREFIX_VEX_0FD0 */
4022   {
4023     { Bad_Opcode },
4024     { Bad_Opcode },
4025     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
4026     { "vaddsubps",      { XM, Vex, EXx }, 0 },
4027   },
4028
4029   /* PREFIX_VEX_0FE6 */
4030   {
4031     { Bad_Opcode },
4032     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
4033     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
4034     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
4035   },
4036
4037   /* PREFIX_VEX_0FF0 */
4038   {
4039     { Bad_Opcode },
4040     { Bad_Opcode },
4041     { Bad_Opcode },
4042     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
4043   },
4044
4045   /* PREFIX_VEX_0F3849_X86_64 */
4046   {
4047     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) },
4048     { Bad_Opcode },
4049     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) },
4050     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) },
4051   },
4052
4053   /* PREFIX_VEX_0F384B_X86_64 */
4054   {
4055     { Bad_Opcode },
4056     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) },
4057     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) },
4058     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) },
4059   },
4060
4061   /* PREFIX_VEX_0F385C_X86_64 */
4062   {
4063     { Bad_Opcode },
4064     { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) },
4065     { Bad_Opcode },
4066   },
4067
4068   /* PREFIX_VEX_0F385E_X86_64 */
4069   {
4070     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) },
4071     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) },
4072     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) },
4073     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) },
4074   },
4075
4076   /* PREFIX_VEX_0F38F5 */
4077   {
4078     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
4079     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
4080     { Bad_Opcode },
4081     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
4082   },
4083
4084   /* PREFIX_VEX_0F38F6 */
4085   {
4086     { Bad_Opcode },
4087     { Bad_Opcode },
4088     { Bad_Opcode },
4089     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
4090   },
4091
4092   /* PREFIX_VEX_0F38F7 */
4093   {
4094     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
4095     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
4096     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
4097     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
4098   },
4099
4100   /* PREFIX_VEX_0F3AF0 */
4101   {
4102     { Bad_Opcode },
4103     { Bad_Opcode },
4104     { Bad_Opcode },
4105     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
4106   },
4107
4108 #include "i386-dis-evex-prefix.h"
4109 };
4110
4111 static const struct dis386 x86_64_table[][2] = {
4112   /* X86_64_06 */
4113   {
4114     { "pushP", { es }, 0 },
4115   },
4116
4117   /* X86_64_07 */
4118   {
4119     { "popP", { es }, 0 },
4120   },
4121
4122   /* X86_64_0E */
4123   {
4124     { "pushP", { cs }, 0 },
4125   },
4126
4127   /* X86_64_16 */
4128   {
4129     { "pushP", { ss }, 0 },
4130   },
4131
4132   /* X86_64_17 */
4133   {
4134     { "popP", { ss }, 0 },
4135   },
4136
4137   /* X86_64_1E */
4138   {
4139     { "pushP", { ds }, 0 },
4140   },
4141
4142   /* X86_64_1F */
4143   {
4144     { "popP", { ds }, 0 },
4145   },
4146
4147   /* X86_64_27 */
4148   {
4149     { "daa", { XX }, 0 },
4150   },
4151
4152   /* X86_64_2F */
4153   {
4154     { "das", { XX }, 0 },
4155   },
4156
4157   /* X86_64_37 */
4158   {
4159     { "aaa", { XX }, 0 },
4160   },
4161
4162   /* X86_64_3F */
4163   {
4164     { "aas", { XX }, 0 },
4165   },
4166
4167   /* X86_64_60 */
4168   {
4169     { "pushaP", { XX }, 0 },
4170   },
4171
4172   /* X86_64_61 */
4173   {
4174     { "popaP", { XX }, 0 },
4175   },
4176
4177   /* X86_64_62 */
4178   {
4179     { MOD_TABLE (MOD_62_32BIT) },
4180     { EVEX_TABLE (EVEX_0F) },
4181   },
4182
4183   /* X86_64_63 */
4184   {
4185     { "arpl", { Ew, Gw }, 0 },
4186     { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4187   },
4188
4189   /* X86_64_6D */
4190   {
4191     { "ins{R|}", { Yzr, indirDX }, 0 },
4192     { "ins{G|}", { Yzr, indirDX }, 0 },
4193   },
4194
4195   /* X86_64_6F */
4196   {
4197     { "outs{R|}", { indirDXr, Xz }, 0 },
4198     { "outs{G|}", { indirDXr, Xz }, 0 },
4199   },
4200
4201   /* X86_64_82 */
4202   {
4203     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
4204     { REG_TABLE (REG_80) },
4205   },
4206
4207   /* X86_64_9A */
4208   {
4209     { "{l|}call{P|}", { Ap }, 0 },
4210   },
4211
4212   /* X86_64_C2 */
4213   {
4214     { "retP",           { Iw, BND }, 0 },
4215     { "ret@",           { Iw, BND }, 0 },
4216   },
4217
4218   /* X86_64_C3 */
4219   {
4220     { "retP",           { BND }, 0 },
4221     { "ret@",           { BND }, 0 },
4222   },
4223
4224   /* X86_64_C4 */
4225   {
4226     { MOD_TABLE (MOD_C4_32BIT) },
4227     { VEX_C4_TABLE (VEX_0F) },
4228   },
4229
4230   /* X86_64_C5 */
4231   {
4232     { MOD_TABLE (MOD_C5_32BIT) },
4233     { VEX_C5_TABLE (VEX_0F) },
4234   },
4235
4236   /* X86_64_CE */
4237   {
4238     { "into", { XX }, 0 },
4239   },
4240
4241   /* X86_64_D4 */
4242   {
4243     { "aam", { Ib }, 0 },
4244   },
4245
4246   /* X86_64_D5 */
4247   {
4248     { "aad", { Ib }, 0 },
4249   },
4250
4251   /* X86_64_E8 */
4252   {
4253     { "callP",          { Jv, BND }, 0 },
4254     { "call@",          { Jv, BND }, 0 }
4255   },
4256
4257   /* X86_64_E9 */
4258   {
4259     { "jmpP",           { Jv, BND }, 0 },
4260     { "jmp@",           { Jv, BND }, 0 }
4261   },
4262
4263   /* X86_64_EA */
4264   {
4265     { "{l|}jmp{P|}", { Ap }, 0 },
4266   },
4267
4268   /* X86_64_0F01_REG_0 */
4269   {
4270     { "sgdt{Q|Q}", { M }, 0 },
4271     { "sgdt", { M }, 0 },
4272   },
4273
4274   /* X86_64_0F01_REG_1 */
4275   {
4276     { "sidt{Q|Q}", { M }, 0 },
4277     { "sidt", { M }, 0 },
4278   },
4279
4280   /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4281   {
4282     { Bad_Opcode },
4283     { "seamret",        { Skip_MODRM }, 0 },
4284   },
4285
4286   /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4287   {
4288     { Bad_Opcode },
4289     { "seamops",        { Skip_MODRM }, 0 },
4290   },
4291
4292   /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4293   {
4294     { Bad_Opcode },
4295     { "seamcall",       { Skip_MODRM }, 0 },
4296   },
4297
4298   /* X86_64_0F01_REG_2 */
4299   {
4300     { "lgdt{Q|Q}", { M }, 0 },
4301     { "lgdt", { M }, 0 },
4302   },
4303
4304   /* X86_64_0F01_REG_3 */
4305   {
4306     { "lidt{Q|Q}", { M }, 0 },
4307     { "lidt", { M }, 0 },
4308   },
4309
4310   {
4311     /* X86_64_0F24 */
4312     { "movZ",           { Em, Td }, 0 },
4313   },
4314
4315   {
4316     /* X86_64_0F26 */
4317     { "movZ",           { Td, Em }, 0 },
4318   },
4319
4320   /* X86_64_VEX_0F3849 */
4321   {
4322     { Bad_Opcode },
4323     { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) },
4324   },
4325
4326   /* X86_64_VEX_0F384B */
4327   {
4328     { Bad_Opcode },
4329     { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) },
4330   },
4331
4332   /* X86_64_VEX_0F385C */
4333   {
4334     { Bad_Opcode },
4335     { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) },
4336   },
4337
4338   /* X86_64_VEX_0F385E */
4339   {
4340     { Bad_Opcode },
4341     { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
4342   },
4343
4344   /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4345   {
4346     { Bad_Opcode },
4347     { "uiret",  { Skip_MODRM }, 0 },
4348   },
4349
4350   /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4351   {
4352     { Bad_Opcode },
4353     { "testui", { Skip_MODRM }, 0 },
4354   },
4355
4356   /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4357   {
4358     { Bad_Opcode },
4359     { "clui",   { Skip_MODRM }, 0 },
4360   },
4361
4362   /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4363   {
4364     { Bad_Opcode },
4365     { "stui",   { Skip_MODRM }, 0 },
4366   },
4367
4368   /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4369   {
4370     { Bad_Opcode },
4371     { "senduipi",       { Eq }, 0 },
4372   },
4373 };
4374
4375 static const struct dis386 three_byte_table[][256] = {
4376
4377   /* THREE_BYTE_0F38 */
4378   {
4379     /* 00 */
4380     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
4381     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
4382     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
4383     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
4384     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
4385     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
4386     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
4387     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
4388     /* 08 */
4389     { "psignb",         { MX, EM }, PREFIX_OPCODE },
4390     { "psignw",         { MX, EM }, PREFIX_OPCODE },
4391     { "psignd",         { MX, EM }, PREFIX_OPCODE },
4392     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
4393     { Bad_Opcode },
4394     { Bad_Opcode },
4395     { Bad_Opcode },
4396     { Bad_Opcode },
4397     /* 10 */
4398     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4399     { Bad_Opcode },
4400     { Bad_Opcode },
4401     { Bad_Opcode },
4402     { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4403     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4404     { Bad_Opcode },
4405     { "ptest",  { XM, EXx }, PREFIX_DATA },
4406     /* 18 */
4407     { Bad_Opcode },
4408     { Bad_Opcode },
4409     { Bad_Opcode },
4410     { Bad_Opcode },
4411     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
4412     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
4413     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
4414     { Bad_Opcode },
4415     /* 20 */
4416     { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4417     { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4418     { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4419     { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4420     { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4421     { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4422     { Bad_Opcode },
4423     { Bad_Opcode },
4424     /* 28 */
4425     { "pmuldq", { XM, EXx }, PREFIX_DATA },
4426     { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4427     { MOD_TABLE (MOD_0F382A) },
4428     { "packusdw", { XM, EXx }, PREFIX_DATA },
4429     { Bad_Opcode },
4430     { Bad_Opcode },
4431     { Bad_Opcode },
4432     { Bad_Opcode },
4433     /* 30 */
4434     { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4435     { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4436     { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4437     { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4438     { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4439     { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4440     { Bad_Opcode },
4441     { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4442     /* 38 */
4443     { "pminsb", { XM, EXx }, PREFIX_DATA },
4444     { "pminsd", { XM, EXx }, PREFIX_DATA },
4445     { "pminuw", { XM, EXx }, PREFIX_DATA },
4446     { "pminud", { XM, EXx }, PREFIX_DATA },
4447     { "pmaxsb", { XM, EXx }, PREFIX_DATA },
4448     { "pmaxsd", { XM, EXx }, PREFIX_DATA },
4449     { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4450     { "pmaxud", { XM, EXx }, PREFIX_DATA },
4451     /* 40 */
4452     { "pmulld", { XM, EXx }, PREFIX_DATA },
4453     { "phminposuw", { XM, EXx }, PREFIX_DATA },
4454     { Bad_Opcode },
4455     { Bad_Opcode },
4456     { Bad_Opcode },
4457     { Bad_Opcode },
4458     { Bad_Opcode },
4459     { Bad_Opcode },
4460     /* 48 */
4461     { Bad_Opcode },
4462     { Bad_Opcode },
4463     { Bad_Opcode },
4464     { Bad_Opcode },
4465     { Bad_Opcode },
4466     { Bad_Opcode },
4467     { Bad_Opcode },
4468     { Bad_Opcode },
4469     /* 50 */
4470     { Bad_Opcode },
4471     { Bad_Opcode },
4472     { Bad_Opcode },
4473     { Bad_Opcode },
4474     { Bad_Opcode },
4475     { Bad_Opcode },
4476     { Bad_Opcode },
4477     { Bad_Opcode },
4478     /* 58 */
4479     { Bad_Opcode },
4480     { Bad_Opcode },
4481     { Bad_Opcode },
4482     { Bad_Opcode },
4483     { Bad_Opcode },
4484     { Bad_Opcode },
4485     { Bad_Opcode },
4486     { Bad_Opcode },
4487     /* 60 */
4488     { Bad_Opcode },
4489     { Bad_Opcode },
4490     { Bad_Opcode },
4491     { Bad_Opcode },
4492     { Bad_Opcode },
4493     { Bad_Opcode },
4494     { Bad_Opcode },
4495     { Bad_Opcode },
4496     /* 68 */
4497     { Bad_Opcode },
4498     { Bad_Opcode },
4499     { Bad_Opcode },
4500     { Bad_Opcode },
4501     { Bad_Opcode },
4502     { Bad_Opcode },
4503     { Bad_Opcode },
4504     { Bad_Opcode },
4505     /* 70 */
4506     { Bad_Opcode },
4507     { Bad_Opcode },
4508     { Bad_Opcode },
4509     { Bad_Opcode },
4510     { Bad_Opcode },
4511     { Bad_Opcode },
4512     { Bad_Opcode },
4513     { Bad_Opcode },
4514     /* 78 */
4515     { Bad_Opcode },
4516     { Bad_Opcode },
4517     { Bad_Opcode },
4518     { Bad_Opcode },
4519     { Bad_Opcode },
4520     { Bad_Opcode },
4521     { Bad_Opcode },
4522     { Bad_Opcode },
4523     /* 80 */
4524     { "invept", { Gm, Mo }, PREFIX_DATA },
4525     { "invvpid", { Gm, Mo }, PREFIX_DATA },
4526     { "invpcid", { Gm, M }, PREFIX_DATA },
4527     { Bad_Opcode },
4528     { Bad_Opcode },
4529     { Bad_Opcode },
4530     { Bad_Opcode },
4531     { Bad_Opcode },
4532     /* 88 */
4533     { Bad_Opcode },
4534     { Bad_Opcode },
4535     { Bad_Opcode },
4536     { Bad_Opcode },
4537     { Bad_Opcode },
4538     { Bad_Opcode },
4539     { Bad_Opcode },
4540     { Bad_Opcode },
4541     /* 90 */
4542     { Bad_Opcode },
4543     { Bad_Opcode },
4544     { Bad_Opcode },
4545     { Bad_Opcode },
4546     { Bad_Opcode },
4547     { Bad_Opcode },
4548     { Bad_Opcode },
4549     { Bad_Opcode },
4550     /* 98 */
4551     { Bad_Opcode },
4552     { Bad_Opcode },
4553     { Bad_Opcode },
4554     { Bad_Opcode },
4555     { Bad_Opcode },
4556     { Bad_Opcode },
4557     { Bad_Opcode },
4558     { Bad_Opcode },
4559     /* a0 */
4560     { Bad_Opcode },
4561     { Bad_Opcode },
4562     { Bad_Opcode },
4563     { Bad_Opcode },
4564     { Bad_Opcode },
4565     { Bad_Opcode },
4566     { Bad_Opcode },
4567     { Bad_Opcode },
4568     /* a8 */
4569     { Bad_Opcode },
4570     { Bad_Opcode },
4571     { Bad_Opcode },
4572     { Bad_Opcode },
4573     { Bad_Opcode },
4574     { Bad_Opcode },
4575     { Bad_Opcode },
4576     { Bad_Opcode },
4577     /* b0 */
4578     { Bad_Opcode },
4579     { Bad_Opcode },
4580     { Bad_Opcode },
4581     { Bad_Opcode },
4582     { Bad_Opcode },
4583     { Bad_Opcode },
4584     { Bad_Opcode },
4585     { Bad_Opcode },
4586     /* b8 */
4587     { Bad_Opcode },
4588     { Bad_Opcode },
4589     { Bad_Opcode },
4590     { Bad_Opcode },
4591     { Bad_Opcode },
4592     { Bad_Opcode },
4593     { Bad_Opcode },
4594     { Bad_Opcode },
4595     /* c0 */
4596     { Bad_Opcode },
4597     { Bad_Opcode },
4598     { Bad_Opcode },
4599     { Bad_Opcode },
4600     { Bad_Opcode },
4601     { Bad_Opcode },
4602     { Bad_Opcode },
4603     { Bad_Opcode },
4604     /* c8 */
4605     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4606     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4607     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4608     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4609     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4610     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4611     { Bad_Opcode },
4612     { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
4613     /* d0 */
4614     { Bad_Opcode },
4615     { Bad_Opcode },
4616     { Bad_Opcode },
4617     { Bad_Opcode },
4618     { Bad_Opcode },
4619     { Bad_Opcode },
4620     { Bad_Opcode },
4621     { Bad_Opcode },
4622     /* d8 */
4623     { PREFIX_TABLE (PREFIX_0F38D8) },
4624     { Bad_Opcode },
4625     { Bad_Opcode },
4626     { "aesimc", { XM, EXx }, PREFIX_DATA },
4627     { PREFIX_TABLE (PREFIX_0F38DC) },
4628     { PREFIX_TABLE (PREFIX_0F38DD) },
4629     { PREFIX_TABLE (PREFIX_0F38DE) },
4630     { PREFIX_TABLE (PREFIX_0F38DF) },
4631     /* e0 */
4632     { Bad_Opcode },
4633     { Bad_Opcode },
4634     { Bad_Opcode },
4635     { Bad_Opcode },
4636     { Bad_Opcode },
4637     { Bad_Opcode },
4638     { Bad_Opcode },
4639     { Bad_Opcode },
4640     /* e8 */
4641     { Bad_Opcode },
4642     { Bad_Opcode },
4643     { Bad_Opcode },
4644     { Bad_Opcode },
4645     { Bad_Opcode },
4646     { Bad_Opcode },
4647     { Bad_Opcode },
4648     { Bad_Opcode },
4649     /* f0 */
4650     { PREFIX_TABLE (PREFIX_0F38F0) },
4651     { PREFIX_TABLE (PREFIX_0F38F1) },
4652     { Bad_Opcode },
4653     { Bad_Opcode },
4654     { Bad_Opcode },
4655     { MOD_TABLE (MOD_0F38F5) },
4656     { PREFIX_TABLE (PREFIX_0F38F6) },
4657     { Bad_Opcode },
4658     /* f8 */
4659     { PREFIX_TABLE (PREFIX_0F38F8) },
4660     { MOD_TABLE (MOD_0F38F9) },
4661     { PREFIX_TABLE (PREFIX_0F38FA) },
4662     { PREFIX_TABLE (PREFIX_0F38FB) },
4663     { Bad_Opcode },
4664     { Bad_Opcode },
4665     { Bad_Opcode },
4666     { Bad_Opcode },
4667   },
4668   /* THREE_BYTE_0F3A */
4669   {
4670     /* 00 */
4671     { Bad_Opcode },
4672     { Bad_Opcode },
4673     { Bad_Opcode },
4674     { Bad_Opcode },
4675     { Bad_Opcode },
4676     { Bad_Opcode },
4677     { Bad_Opcode },
4678     { Bad_Opcode },
4679     /* 08 */
4680     { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
4681     { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
4682     { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
4683     { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
4684     { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
4685     { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
4686     { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
4687     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
4688     /* 10 */
4689     { Bad_Opcode },
4690     { Bad_Opcode },
4691     { Bad_Opcode },
4692     { Bad_Opcode },
4693     { "pextrb", { Edqb, XM, Ib }, PREFIX_DATA },
4694     { "pextrw", { Edqw, XM, Ib }, PREFIX_DATA },
4695     { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
4696     { "extractps", { Edqd, XM, Ib }, PREFIX_DATA },
4697     /* 18 */
4698     { Bad_Opcode },
4699     { Bad_Opcode },
4700     { Bad_Opcode },
4701     { Bad_Opcode },
4702     { Bad_Opcode },
4703     { Bad_Opcode },
4704     { Bad_Opcode },
4705     { Bad_Opcode },
4706     /* 20 */
4707     { "pinsrb", { XM, Edqb, Ib }, PREFIX_DATA },
4708     { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
4709     { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
4710     { Bad_Opcode },
4711     { Bad_Opcode },
4712     { Bad_Opcode },
4713     { Bad_Opcode },
4714     { Bad_Opcode },
4715     /* 28 */
4716     { Bad_Opcode },
4717     { Bad_Opcode },
4718     { Bad_Opcode },
4719     { Bad_Opcode },
4720     { Bad_Opcode },
4721     { Bad_Opcode },
4722     { Bad_Opcode },
4723     { Bad_Opcode },
4724     /* 30 */
4725     { Bad_Opcode },
4726     { Bad_Opcode },
4727     { Bad_Opcode },
4728     { Bad_Opcode },
4729     { Bad_Opcode },
4730     { Bad_Opcode },
4731     { Bad_Opcode },
4732     { Bad_Opcode },
4733     /* 38 */
4734     { Bad_Opcode },
4735     { Bad_Opcode },
4736     { Bad_Opcode },
4737     { Bad_Opcode },
4738     { Bad_Opcode },
4739     { Bad_Opcode },
4740     { Bad_Opcode },
4741     { Bad_Opcode },
4742     /* 40 */
4743     { "dpps",   { XM, EXx, Ib }, PREFIX_DATA },
4744     { "dppd",   { XM, EXx, Ib }, PREFIX_DATA },
4745     { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
4746     { Bad_Opcode },
4747     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
4748     { Bad_Opcode },
4749     { Bad_Opcode },
4750     { Bad_Opcode },
4751     /* 48 */
4752     { Bad_Opcode },
4753     { Bad_Opcode },
4754     { Bad_Opcode },
4755     { Bad_Opcode },
4756     { Bad_Opcode },
4757     { Bad_Opcode },
4758     { Bad_Opcode },
4759     { Bad_Opcode },
4760     /* 50 */
4761     { Bad_Opcode },
4762     { Bad_Opcode },
4763     { Bad_Opcode },
4764     { Bad_Opcode },
4765     { Bad_Opcode },
4766     { Bad_Opcode },
4767     { Bad_Opcode },
4768     { Bad_Opcode },
4769     /* 58 */
4770     { Bad_Opcode },
4771     { Bad_Opcode },
4772     { Bad_Opcode },
4773     { Bad_Opcode },
4774     { Bad_Opcode },
4775     { Bad_Opcode },
4776     { Bad_Opcode },
4777     { Bad_Opcode },
4778     /* 60 */
4779     { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4780     { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4781     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
4782     { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
4783     { Bad_Opcode },
4784     { Bad_Opcode },
4785     { Bad_Opcode },
4786     { Bad_Opcode },
4787     /* 68 */
4788     { Bad_Opcode },
4789     { Bad_Opcode },
4790     { Bad_Opcode },
4791     { Bad_Opcode },
4792     { Bad_Opcode },
4793     { Bad_Opcode },
4794     { Bad_Opcode },
4795     { Bad_Opcode },
4796     /* 70 */
4797     { Bad_Opcode },
4798     { Bad_Opcode },
4799     { Bad_Opcode },
4800     { Bad_Opcode },
4801     { Bad_Opcode },
4802     { Bad_Opcode },
4803     { Bad_Opcode },
4804     { Bad_Opcode },
4805     /* 78 */
4806     { Bad_Opcode },
4807     { Bad_Opcode },
4808     { Bad_Opcode },
4809     { Bad_Opcode },
4810     { Bad_Opcode },
4811     { Bad_Opcode },
4812     { Bad_Opcode },
4813     { Bad_Opcode },
4814     /* 80 */
4815     { Bad_Opcode },
4816     { Bad_Opcode },
4817     { Bad_Opcode },
4818     { Bad_Opcode },
4819     { Bad_Opcode },
4820     { Bad_Opcode },
4821     { Bad_Opcode },
4822     { Bad_Opcode },
4823     /* 88 */
4824     { Bad_Opcode },
4825     { Bad_Opcode },
4826     { Bad_Opcode },
4827     { Bad_Opcode },
4828     { Bad_Opcode },
4829     { Bad_Opcode },
4830     { Bad_Opcode },
4831     { Bad_Opcode },
4832     /* 90 */
4833     { Bad_Opcode },
4834     { Bad_Opcode },
4835     { Bad_Opcode },
4836     { Bad_Opcode },
4837     { Bad_Opcode },
4838     { Bad_Opcode },
4839     { Bad_Opcode },
4840     { Bad_Opcode },
4841     /* 98 */
4842     { Bad_Opcode },
4843     { Bad_Opcode },
4844     { Bad_Opcode },
4845     { Bad_Opcode },
4846     { Bad_Opcode },
4847     { Bad_Opcode },
4848     { Bad_Opcode },
4849     { Bad_Opcode },
4850     /* a0 */
4851     { Bad_Opcode },
4852     { Bad_Opcode },
4853     { Bad_Opcode },
4854     { Bad_Opcode },
4855     { Bad_Opcode },
4856     { Bad_Opcode },
4857     { Bad_Opcode },
4858     { Bad_Opcode },
4859     /* a8 */
4860     { Bad_Opcode },
4861     { Bad_Opcode },
4862     { Bad_Opcode },
4863     { Bad_Opcode },
4864     { Bad_Opcode },
4865     { Bad_Opcode },
4866     { Bad_Opcode },
4867     { Bad_Opcode },
4868     /* b0 */
4869     { Bad_Opcode },
4870     { Bad_Opcode },
4871     { Bad_Opcode },
4872     { Bad_Opcode },
4873     { Bad_Opcode },
4874     { Bad_Opcode },
4875     { Bad_Opcode },
4876     { Bad_Opcode },
4877     /* b8 */
4878     { Bad_Opcode },
4879     { Bad_Opcode },
4880     { Bad_Opcode },
4881     { Bad_Opcode },
4882     { Bad_Opcode },
4883     { Bad_Opcode },
4884     { Bad_Opcode },
4885     { Bad_Opcode },
4886     /* c0 */
4887     { Bad_Opcode },
4888     { Bad_Opcode },
4889     { Bad_Opcode },
4890     { Bad_Opcode },
4891     { Bad_Opcode },
4892     { Bad_Opcode },
4893     { Bad_Opcode },
4894     { Bad_Opcode },
4895     /* c8 */
4896     { Bad_Opcode },
4897     { Bad_Opcode },
4898     { Bad_Opcode },
4899     { Bad_Opcode },
4900     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4901     { Bad_Opcode },
4902     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4903     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4904     /* d0 */
4905     { Bad_Opcode },
4906     { Bad_Opcode },
4907     { Bad_Opcode },
4908     { Bad_Opcode },
4909     { Bad_Opcode },
4910     { Bad_Opcode },
4911     { Bad_Opcode },
4912     { Bad_Opcode },
4913     /* d8 */
4914     { Bad_Opcode },
4915     { Bad_Opcode },
4916     { Bad_Opcode },
4917     { Bad_Opcode },
4918     { Bad_Opcode },
4919     { Bad_Opcode },
4920     { Bad_Opcode },
4921     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
4922     /* e0 */
4923     { Bad_Opcode },
4924     { Bad_Opcode },
4925     { Bad_Opcode },
4926     { Bad_Opcode },
4927     { Bad_Opcode },
4928     { Bad_Opcode },
4929     { Bad_Opcode },
4930     { Bad_Opcode },
4931     /* e8 */
4932     { Bad_Opcode },
4933     { Bad_Opcode },
4934     { Bad_Opcode },
4935     { Bad_Opcode },
4936     { Bad_Opcode },
4937     { Bad_Opcode },
4938     { Bad_Opcode },
4939     { Bad_Opcode },
4940     /* f0 */
4941     { Bad_Opcode },
4942     { Bad_Opcode },
4943     { Bad_Opcode },
4944     { Bad_Opcode },
4945     { Bad_Opcode },
4946     { Bad_Opcode },
4947     { Bad_Opcode },
4948     { Bad_Opcode },
4949     /* f8 */
4950     { Bad_Opcode },
4951     { Bad_Opcode },
4952     { Bad_Opcode },
4953     { Bad_Opcode },
4954     { Bad_Opcode },
4955     { Bad_Opcode },
4956     { Bad_Opcode },
4957     { Bad_Opcode },
4958   },
4959 };
4960
4961 static const struct dis386 xop_table[][256] = {
4962   /* XOP_08 */
4963   {
4964     /* 00 */
4965     { Bad_Opcode },
4966     { Bad_Opcode },
4967     { Bad_Opcode },
4968     { Bad_Opcode },
4969     { Bad_Opcode },
4970     { Bad_Opcode },
4971     { Bad_Opcode },
4972     { Bad_Opcode },
4973     /* 08 */
4974     { Bad_Opcode },
4975     { Bad_Opcode },
4976     { Bad_Opcode },
4977     { Bad_Opcode },
4978     { Bad_Opcode },
4979     { Bad_Opcode },
4980     { Bad_Opcode },
4981     { Bad_Opcode },
4982     /* 10 */
4983     { Bad_Opcode },
4984     { Bad_Opcode },
4985     { Bad_Opcode },
4986     { Bad_Opcode },
4987     { Bad_Opcode },
4988     { Bad_Opcode },
4989     { Bad_Opcode },
4990     { Bad_Opcode },
4991     /* 18 */
4992     { Bad_Opcode },
4993     { Bad_Opcode },
4994     { Bad_Opcode },
4995     { Bad_Opcode },
4996     { Bad_Opcode },
4997     { Bad_Opcode },
4998     { Bad_Opcode },
4999     { Bad_Opcode },
5000     /* 20 */
5001     { Bad_Opcode },
5002     { Bad_Opcode },
5003     { Bad_Opcode },
5004     { Bad_Opcode },
5005     { Bad_Opcode },
5006     { Bad_Opcode },
5007     { Bad_Opcode },
5008     { Bad_Opcode },
5009     /* 28 */
5010     { Bad_Opcode },
5011     { Bad_Opcode },
5012     { Bad_Opcode },
5013     { Bad_Opcode },
5014     { Bad_Opcode },
5015     { Bad_Opcode },
5016     { Bad_Opcode },
5017     { Bad_Opcode },
5018     /* 30 */
5019     { Bad_Opcode },
5020     { Bad_Opcode },
5021     { Bad_Opcode },
5022     { Bad_Opcode },
5023     { Bad_Opcode },
5024     { Bad_Opcode },
5025     { Bad_Opcode },
5026     { Bad_Opcode },
5027     /* 38 */
5028     { Bad_Opcode },
5029     { Bad_Opcode },
5030     { Bad_Opcode },
5031     { Bad_Opcode },
5032     { Bad_Opcode },
5033     { Bad_Opcode },
5034     { Bad_Opcode },
5035     { Bad_Opcode },
5036     /* 40 */
5037     { Bad_Opcode },
5038     { Bad_Opcode },
5039     { Bad_Opcode },
5040     { Bad_Opcode },
5041     { Bad_Opcode },
5042     { Bad_Opcode },
5043     { Bad_Opcode },
5044     { Bad_Opcode },
5045     /* 48 */
5046     { Bad_Opcode },
5047     { Bad_Opcode },
5048     { Bad_Opcode },
5049     { Bad_Opcode },
5050     { Bad_Opcode },
5051     { Bad_Opcode },
5052     { Bad_Opcode },
5053     { Bad_Opcode },
5054     /* 50 */
5055     { Bad_Opcode },
5056     { Bad_Opcode },
5057     { Bad_Opcode },
5058     { Bad_Opcode },
5059     { Bad_Opcode },
5060     { Bad_Opcode },
5061     { Bad_Opcode },
5062     { Bad_Opcode },
5063     /* 58 */
5064     { Bad_Opcode },
5065     { Bad_Opcode },
5066     { Bad_Opcode },
5067     { Bad_Opcode },
5068     { Bad_Opcode },
5069     { Bad_Opcode },
5070     { Bad_Opcode },
5071     { Bad_Opcode },
5072     /* 60 */
5073     { Bad_Opcode },
5074     { Bad_Opcode },
5075     { Bad_Opcode },
5076     { Bad_Opcode },
5077     { Bad_Opcode },
5078     { Bad_Opcode },
5079     { Bad_Opcode },
5080     { Bad_Opcode },
5081     /* 68 */
5082     { Bad_Opcode },
5083     { Bad_Opcode },
5084     { Bad_Opcode },
5085     { Bad_Opcode },
5086     { Bad_Opcode },
5087     { Bad_Opcode },
5088     { Bad_Opcode },
5089     { Bad_Opcode },
5090     /* 70 */
5091     { Bad_Opcode },
5092     { Bad_Opcode },
5093     { Bad_Opcode },
5094     { Bad_Opcode },
5095     { Bad_Opcode },
5096     { Bad_Opcode },
5097     { Bad_Opcode },
5098     { Bad_Opcode },
5099     /* 78 */
5100     { Bad_Opcode },
5101     { Bad_Opcode },
5102     { Bad_Opcode },
5103     { Bad_Opcode },
5104     { Bad_Opcode },
5105     { Bad_Opcode },
5106     { Bad_Opcode },
5107     { Bad_Opcode },
5108     /* 80 */
5109     { Bad_Opcode },
5110     { Bad_Opcode },
5111     { Bad_Opcode },
5112     { Bad_Opcode },
5113     { Bad_Opcode },
5114     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
5115     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
5116     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
5117     /* 88 */
5118     { Bad_Opcode },
5119     { Bad_Opcode },
5120     { Bad_Opcode },
5121     { Bad_Opcode },
5122     { Bad_Opcode },
5123     { Bad_Opcode },
5124     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
5125     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
5126     /* 90 */
5127     { Bad_Opcode },
5128     { Bad_Opcode },
5129     { Bad_Opcode },
5130     { Bad_Opcode },
5131     { Bad_Opcode },
5132     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
5133     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
5134     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
5135     /* 98 */
5136     { Bad_Opcode },
5137     { Bad_Opcode },
5138     { Bad_Opcode },
5139     { Bad_Opcode },
5140     { Bad_Opcode },
5141     { Bad_Opcode },
5142     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
5143     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
5144     /* a0 */
5145     { Bad_Opcode },
5146     { Bad_Opcode },
5147     { "vpcmov",         { XM, Vex, EXx, XMVexI4 }, 0 },
5148     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
5149     { Bad_Opcode },
5150     { Bad_Opcode },
5151     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
5152     { Bad_Opcode },
5153     /* a8 */
5154     { Bad_Opcode },
5155     { Bad_Opcode },
5156     { Bad_Opcode },
5157     { Bad_Opcode },
5158     { Bad_Opcode },
5159     { Bad_Opcode },
5160     { Bad_Opcode },
5161     { Bad_Opcode },
5162     /* b0 */
5163     { Bad_Opcode },
5164     { Bad_Opcode },
5165     { Bad_Opcode },
5166     { Bad_Opcode },
5167     { Bad_Opcode },
5168     { Bad_Opcode },
5169     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
5170     { Bad_Opcode },
5171     /* b8 */
5172     { Bad_Opcode },
5173     { Bad_Opcode },
5174     { Bad_Opcode },
5175     { Bad_Opcode },
5176     { Bad_Opcode },
5177     { Bad_Opcode },
5178     { Bad_Opcode },
5179     { Bad_Opcode },
5180     /* c0 */
5181     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
5182     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
5183     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
5184     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
5185     { Bad_Opcode },
5186     { Bad_Opcode },
5187     { Bad_Opcode },
5188     { Bad_Opcode },
5189     /* c8 */
5190     { Bad_Opcode },
5191     { Bad_Opcode },
5192     { Bad_Opcode },
5193     { Bad_Opcode },
5194     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
5195     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
5196     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
5197     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
5198     /* d0 */
5199     { Bad_Opcode },
5200     { Bad_Opcode },
5201     { Bad_Opcode },
5202     { Bad_Opcode },
5203     { Bad_Opcode },
5204     { Bad_Opcode },
5205     { Bad_Opcode },
5206     { Bad_Opcode },
5207     /* d8 */
5208     { Bad_Opcode },
5209     { Bad_Opcode },
5210     { Bad_Opcode },
5211     { Bad_Opcode },
5212     { Bad_Opcode },
5213     { Bad_Opcode },
5214     { Bad_Opcode },
5215     { Bad_Opcode },
5216     /* e0 */
5217     { Bad_Opcode },
5218     { Bad_Opcode },
5219     { Bad_Opcode },
5220     { Bad_Opcode },
5221     { Bad_Opcode },
5222     { Bad_Opcode },
5223     { Bad_Opcode },
5224     { Bad_Opcode },
5225     /* e8 */
5226     { Bad_Opcode },
5227     { Bad_Opcode },
5228     { Bad_Opcode },
5229     { Bad_Opcode },
5230     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
5231     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
5232     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
5233     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
5234     /* f0 */
5235     { Bad_Opcode },
5236     { Bad_Opcode },
5237     { Bad_Opcode },
5238     { Bad_Opcode },
5239     { Bad_Opcode },
5240     { Bad_Opcode },
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     /* f8 */
5244     { Bad_Opcode },
5245     { Bad_Opcode },
5246     { Bad_Opcode },
5247     { Bad_Opcode },
5248     { Bad_Opcode },
5249     { Bad_Opcode },
5250     { Bad_Opcode },
5251     { Bad_Opcode },
5252   },
5253   /* XOP_09 */
5254   {
5255     /* 00 */
5256     { Bad_Opcode },
5257     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
5258     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
5259     { Bad_Opcode },
5260     { Bad_Opcode },
5261     { Bad_Opcode },
5262     { Bad_Opcode },
5263     { Bad_Opcode },
5264     /* 08 */
5265     { Bad_Opcode },
5266     { Bad_Opcode },
5267     { Bad_Opcode },
5268     { Bad_Opcode },
5269     { Bad_Opcode },
5270     { Bad_Opcode },
5271     { Bad_Opcode },
5272     { Bad_Opcode },
5273     /* 10 */
5274     { Bad_Opcode },
5275     { Bad_Opcode },
5276     { MOD_TABLE (MOD_VEX_0FXOP_09_12) },
5277     { Bad_Opcode },
5278     { Bad_Opcode },
5279     { Bad_Opcode },
5280     { Bad_Opcode },
5281     { Bad_Opcode },
5282     /* 18 */
5283     { Bad_Opcode },
5284     { Bad_Opcode },
5285     { Bad_Opcode },
5286     { Bad_Opcode },
5287     { Bad_Opcode },
5288     { Bad_Opcode },
5289     { Bad_Opcode },
5290     { Bad_Opcode },
5291     /* 20 */
5292     { Bad_Opcode },
5293     { Bad_Opcode },
5294     { Bad_Opcode },
5295     { Bad_Opcode },
5296     { Bad_Opcode },
5297     { Bad_Opcode },
5298     { Bad_Opcode },
5299     { Bad_Opcode },
5300     /* 28 */
5301     { Bad_Opcode },
5302     { Bad_Opcode },
5303     { Bad_Opcode },
5304     { Bad_Opcode },
5305     { Bad_Opcode },
5306     { Bad_Opcode },
5307     { Bad_Opcode },
5308     { Bad_Opcode },
5309     /* 30 */
5310     { Bad_Opcode },
5311     { Bad_Opcode },
5312     { Bad_Opcode },
5313     { Bad_Opcode },
5314     { Bad_Opcode },
5315     { Bad_Opcode },
5316     { Bad_Opcode },
5317     { Bad_Opcode },
5318     /* 38 */
5319     { Bad_Opcode },
5320     { Bad_Opcode },
5321     { Bad_Opcode },
5322     { Bad_Opcode },
5323     { Bad_Opcode },
5324     { Bad_Opcode },
5325     { Bad_Opcode },
5326     { Bad_Opcode },
5327     /* 40 */
5328     { Bad_Opcode },
5329     { Bad_Opcode },
5330     { Bad_Opcode },
5331     { Bad_Opcode },
5332     { Bad_Opcode },
5333     { Bad_Opcode },
5334     { Bad_Opcode },
5335     { Bad_Opcode },
5336     /* 48 */
5337     { Bad_Opcode },
5338     { Bad_Opcode },
5339     { Bad_Opcode },
5340     { Bad_Opcode },
5341     { Bad_Opcode },
5342     { Bad_Opcode },
5343     { Bad_Opcode },
5344     { Bad_Opcode },
5345     /* 50 */
5346     { Bad_Opcode },
5347     { Bad_Opcode },
5348     { Bad_Opcode },
5349     { Bad_Opcode },
5350     { Bad_Opcode },
5351     { Bad_Opcode },
5352     { Bad_Opcode },
5353     { Bad_Opcode },
5354     /* 58 */
5355     { Bad_Opcode },
5356     { Bad_Opcode },
5357     { Bad_Opcode },
5358     { Bad_Opcode },
5359     { Bad_Opcode },
5360     { Bad_Opcode },
5361     { Bad_Opcode },
5362     { Bad_Opcode },
5363     /* 60 */
5364     { Bad_Opcode },
5365     { Bad_Opcode },
5366     { Bad_Opcode },
5367     { Bad_Opcode },
5368     { Bad_Opcode },
5369     { Bad_Opcode },
5370     { Bad_Opcode },
5371     { Bad_Opcode },
5372     /* 68 */
5373     { Bad_Opcode },
5374     { Bad_Opcode },
5375     { Bad_Opcode },
5376     { Bad_Opcode },
5377     { Bad_Opcode },
5378     { Bad_Opcode },
5379     { Bad_Opcode },
5380     { Bad_Opcode },
5381     /* 70 */
5382     { Bad_Opcode },
5383     { Bad_Opcode },
5384     { Bad_Opcode },
5385     { Bad_Opcode },
5386     { Bad_Opcode },
5387     { Bad_Opcode },
5388     { Bad_Opcode },
5389     { Bad_Opcode },
5390     /* 78 */
5391     { Bad_Opcode },
5392     { Bad_Opcode },
5393     { Bad_Opcode },
5394     { Bad_Opcode },
5395     { Bad_Opcode },
5396     { Bad_Opcode },
5397     { Bad_Opcode },
5398     { Bad_Opcode },
5399     /* 80 */
5400     { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
5401     { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
5402     { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
5403     { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
5404     { Bad_Opcode },
5405     { Bad_Opcode },
5406     { Bad_Opcode },
5407     { Bad_Opcode },
5408     /* 88 */
5409     { Bad_Opcode },
5410     { Bad_Opcode },
5411     { Bad_Opcode },
5412     { Bad_Opcode },
5413     { Bad_Opcode },
5414     { Bad_Opcode },
5415     { Bad_Opcode },
5416     { Bad_Opcode },
5417     /* 90 */
5418     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
5419     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
5420     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
5421     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
5422     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
5423     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
5424     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
5425     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
5426     /* 98 */
5427     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
5428     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
5429     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
5430     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
5431     { Bad_Opcode },
5432     { Bad_Opcode },
5433     { Bad_Opcode },
5434     { Bad_Opcode },
5435     /* a0 */
5436     { Bad_Opcode },
5437     { Bad_Opcode },
5438     { Bad_Opcode },
5439     { Bad_Opcode },
5440     { Bad_Opcode },
5441     { Bad_Opcode },
5442     { Bad_Opcode },
5443     { Bad_Opcode },
5444     /* a8 */
5445     { Bad_Opcode },
5446     { Bad_Opcode },
5447     { Bad_Opcode },
5448     { Bad_Opcode },
5449     { Bad_Opcode },
5450     { Bad_Opcode },
5451     { Bad_Opcode },
5452     { Bad_Opcode },
5453     /* b0 */
5454     { Bad_Opcode },
5455     { Bad_Opcode },
5456     { Bad_Opcode },
5457     { Bad_Opcode },
5458     { Bad_Opcode },
5459     { Bad_Opcode },
5460     { Bad_Opcode },
5461     { Bad_Opcode },
5462     /* b8 */
5463     { Bad_Opcode },
5464     { Bad_Opcode },
5465     { Bad_Opcode },
5466     { Bad_Opcode },
5467     { Bad_Opcode },
5468     { Bad_Opcode },
5469     { Bad_Opcode },
5470     { Bad_Opcode },
5471     /* c0 */
5472     { Bad_Opcode },
5473     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
5474     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
5475     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
5476     { Bad_Opcode },
5477     { Bad_Opcode },
5478     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
5479     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
5480     /* c8 */
5481     { Bad_Opcode },
5482     { Bad_Opcode },
5483     { Bad_Opcode },
5484     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
5485     { Bad_Opcode },
5486     { Bad_Opcode },
5487     { Bad_Opcode },
5488     { Bad_Opcode },
5489     /* d0 */
5490     { Bad_Opcode },
5491     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
5492     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
5493     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
5494     { Bad_Opcode },
5495     { Bad_Opcode },
5496     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
5497     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
5498     /* d8 */
5499     { Bad_Opcode },
5500     { Bad_Opcode },
5501     { Bad_Opcode },
5502     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
5503     { Bad_Opcode },
5504     { Bad_Opcode },
5505     { Bad_Opcode },
5506     { Bad_Opcode },
5507     /* e0 */
5508     { Bad_Opcode },
5509     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
5510     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
5511     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
5512     { Bad_Opcode },
5513     { Bad_Opcode },
5514     { Bad_Opcode },
5515     { Bad_Opcode },
5516     /* e8 */
5517     { Bad_Opcode },
5518     { Bad_Opcode },
5519     { Bad_Opcode },
5520     { Bad_Opcode },
5521     { Bad_Opcode },
5522     { Bad_Opcode },
5523     { Bad_Opcode },
5524     { Bad_Opcode },
5525     /* f0 */
5526     { Bad_Opcode },
5527     { Bad_Opcode },
5528     { Bad_Opcode },
5529     { Bad_Opcode },
5530     { Bad_Opcode },
5531     { Bad_Opcode },
5532     { Bad_Opcode },
5533     { Bad_Opcode },
5534     /* f8 */
5535     { Bad_Opcode },
5536     { Bad_Opcode },
5537     { Bad_Opcode },
5538     { Bad_Opcode },
5539     { Bad_Opcode },
5540     { Bad_Opcode },
5541     { Bad_Opcode },
5542     { Bad_Opcode },
5543   },
5544   /* XOP_0A */
5545   {
5546     /* 00 */
5547     { Bad_Opcode },
5548     { Bad_Opcode },
5549     { Bad_Opcode },
5550     { Bad_Opcode },
5551     { Bad_Opcode },
5552     { Bad_Opcode },
5553     { Bad_Opcode },
5554     { Bad_Opcode },
5555     /* 08 */
5556     { Bad_Opcode },
5557     { Bad_Opcode },
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     { Bad_Opcode },
5561     { Bad_Opcode },
5562     { Bad_Opcode },
5563     { Bad_Opcode },
5564     /* 10 */
5565     { "bextrS", { Gdq, Edq, Id }, 0 },
5566     { Bad_Opcode },
5567     { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
5568     { Bad_Opcode },
5569     { Bad_Opcode },
5570     { Bad_Opcode },
5571     { Bad_Opcode },
5572     { Bad_Opcode },
5573     /* 18 */
5574     { Bad_Opcode },
5575     { Bad_Opcode },
5576     { Bad_Opcode },
5577     { Bad_Opcode },
5578     { Bad_Opcode },
5579     { Bad_Opcode },
5580     { Bad_Opcode },
5581     { Bad_Opcode },
5582     /* 20 */
5583     { Bad_Opcode },
5584     { Bad_Opcode },
5585     { Bad_Opcode },
5586     { Bad_Opcode },
5587     { Bad_Opcode },
5588     { Bad_Opcode },
5589     { Bad_Opcode },
5590     { Bad_Opcode },
5591     /* 28 */
5592     { Bad_Opcode },
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     { Bad_Opcode },
5596     { Bad_Opcode },
5597     { Bad_Opcode },
5598     { Bad_Opcode },
5599     { Bad_Opcode },
5600     /* 30 */
5601     { Bad_Opcode },
5602     { Bad_Opcode },
5603     { Bad_Opcode },
5604     { Bad_Opcode },
5605     { Bad_Opcode },
5606     { Bad_Opcode },
5607     { Bad_Opcode },
5608     { Bad_Opcode },
5609     /* 38 */
5610     { Bad_Opcode },
5611     { Bad_Opcode },
5612     { Bad_Opcode },
5613     { Bad_Opcode },
5614     { Bad_Opcode },
5615     { Bad_Opcode },
5616     { Bad_Opcode },
5617     { Bad_Opcode },
5618     /* 40 */
5619     { Bad_Opcode },
5620     { Bad_Opcode },
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     { Bad_Opcode },
5624     { Bad_Opcode },
5625     { Bad_Opcode },
5626     { Bad_Opcode },
5627     /* 48 */
5628     { Bad_Opcode },
5629     { Bad_Opcode },
5630     { Bad_Opcode },
5631     { Bad_Opcode },
5632     { Bad_Opcode },
5633     { Bad_Opcode },
5634     { Bad_Opcode },
5635     { Bad_Opcode },
5636     /* 50 */
5637     { Bad_Opcode },
5638     { Bad_Opcode },
5639     { Bad_Opcode },
5640     { Bad_Opcode },
5641     { Bad_Opcode },
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     { Bad_Opcode },
5645     /* 58 */
5646     { Bad_Opcode },
5647     { Bad_Opcode },
5648     { Bad_Opcode },
5649     { Bad_Opcode },
5650     { Bad_Opcode },
5651     { Bad_Opcode },
5652     { Bad_Opcode },
5653     { Bad_Opcode },
5654     /* 60 */
5655     { Bad_Opcode },
5656     { Bad_Opcode },
5657     { Bad_Opcode },
5658     { Bad_Opcode },
5659     { Bad_Opcode },
5660     { Bad_Opcode },
5661     { Bad_Opcode },
5662     { Bad_Opcode },
5663     /* 68 */
5664     { Bad_Opcode },
5665     { Bad_Opcode },
5666     { Bad_Opcode },
5667     { Bad_Opcode },
5668     { Bad_Opcode },
5669     { Bad_Opcode },
5670     { Bad_Opcode },
5671     { Bad_Opcode },
5672     /* 70 */
5673     { Bad_Opcode },
5674     { Bad_Opcode },
5675     { Bad_Opcode },
5676     { Bad_Opcode },
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     { Bad_Opcode },
5680     { Bad_Opcode },
5681     /* 78 */
5682     { Bad_Opcode },
5683     { Bad_Opcode },
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686     { Bad_Opcode },
5687     { Bad_Opcode },
5688     { Bad_Opcode },
5689     { Bad_Opcode },
5690     /* 80 */
5691     { Bad_Opcode },
5692     { Bad_Opcode },
5693     { Bad_Opcode },
5694     { Bad_Opcode },
5695     { Bad_Opcode },
5696     { Bad_Opcode },
5697     { Bad_Opcode },
5698     { Bad_Opcode },
5699     /* 88 */
5700     { Bad_Opcode },
5701     { Bad_Opcode },
5702     { Bad_Opcode },
5703     { Bad_Opcode },
5704     { Bad_Opcode },
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     { Bad_Opcode },
5708     /* 90 */
5709     { Bad_Opcode },
5710     { Bad_Opcode },
5711     { Bad_Opcode },
5712     { Bad_Opcode },
5713     { Bad_Opcode },
5714     { Bad_Opcode },
5715     { Bad_Opcode },
5716     { Bad_Opcode },
5717     /* 98 */
5718     { Bad_Opcode },
5719     { Bad_Opcode },
5720     { Bad_Opcode },
5721     { Bad_Opcode },
5722     { Bad_Opcode },
5723     { Bad_Opcode },
5724     { Bad_Opcode },
5725     { Bad_Opcode },
5726     /* a0 */
5727     { Bad_Opcode },
5728     { Bad_Opcode },
5729     { Bad_Opcode },
5730     { Bad_Opcode },
5731     { Bad_Opcode },
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735     /* a8 */
5736     { Bad_Opcode },
5737     { Bad_Opcode },
5738     { Bad_Opcode },
5739     { Bad_Opcode },
5740     { Bad_Opcode },
5741     { Bad_Opcode },
5742     { Bad_Opcode },
5743     { Bad_Opcode },
5744     /* b0 */
5745     { Bad_Opcode },
5746     { Bad_Opcode },
5747     { Bad_Opcode },
5748     { Bad_Opcode },
5749     { Bad_Opcode },
5750     { Bad_Opcode },
5751     { Bad_Opcode },
5752     { Bad_Opcode },
5753     /* b8 */
5754     { Bad_Opcode },
5755     { Bad_Opcode },
5756     { Bad_Opcode },
5757     { Bad_Opcode },
5758     { Bad_Opcode },
5759     { Bad_Opcode },
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     /* c0 */
5763     { Bad_Opcode },
5764     { Bad_Opcode },
5765     { Bad_Opcode },
5766     { Bad_Opcode },
5767     { Bad_Opcode },
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770     { Bad_Opcode },
5771     /* c8 */
5772     { Bad_Opcode },
5773     { Bad_Opcode },
5774     { Bad_Opcode },
5775     { Bad_Opcode },
5776     { Bad_Opcode },
5777     { Bad_Opcode },
5778     { Bad_Opcode },
5779     { Bad_Opcode },
5780     /* d0 */
5781     { Bad_Opcode },
5782     { Bad_Opcode },
5783     { Bad_Opcode },
5784     { Bad_Opcode },
5785     { Bad_Opcode },
5786     { Bad_Opcode },
5787     { Bad_Opcode },
5788     { Bad_Opcode },
5789     /* d8 */
5790     { Bad_Opcode },
5791     { Bad_Opcode },
5792     { Bad_Opcode },
5793     { Bad_Opcode },
5794     { Bad_Opcode },
5795     { Bad_Opcode },
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798     /* e0 */
5799     { Bad_Opcode },
5800     { Bad_Opcode },
5801     { Bad_Opcode },
5802     { Bad_Opcode },
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     { Bad_Opcode },
5807     /* e8 */
5808     { Bad_Opcode },
5809     { Bad_Opcode },
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812     { Bad_Opcode },
5813     { Bad_Opcode },
5814     { Bad_Opcode },
5815     { Bad_Opcode },
5816     /* f0 */
5817     { Bad_Opcode },
5818     { Bad_Opcode },
5819     { Bad_Opcode },
5820     { Bad_Opcode },
5821     { Bad_Opcode },
5822     { Bad_Opcode },
5823     { Bad_Opcode },
5824     { Bad_Opcode },
5825     /* f8 */
5826     { Bad_Opcode },
5827     { Bad_Opcode },
5828     { Bad_Opcode },
5829     { Bad_Opcode },
5830     { Bad_Opcode },
5831     { Bad_Opcode },
5832     { Bad_Opcode },
5833     { Bad_Opcode },
5834   },
5835 };
5836
5837 static const struct dis386 vex_table[][256] = {
5838   /* VEX_0F */
5839   {
5840     /* 00 */
5841     { Bad_Opcode },
5842     { Bad_Opcode },
5843     { Bad_Opcode },
5844     { Bad_Opcode },
5845     { Bad_Opcode },
5846     { Bad_Opcode },
5847     { Bad_Opcode },
5848     { Bad_Opcode },
5849     /* 08 */
5850     { Bad_Opcode },
5851     { Bad_Opcode },
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854     { Bad_Opcode },
5855     { Bad_Opcode },
5856     { Bad_Opcode },
5857     { Bad_Opcode },
5858     /* 10 */
5859     { PREFIX_TABLE (PREFIX_VEX_0F10) },
5860     { PREFIX_TABLE (PREFIX_VEX_0F11) },
5861     { PREFIX_TABLE (PREFIX_VEX_0F12) },
5862     { MOD_TABLE (MOD_VEX_0F13) },
5863     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
5864     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
5865     { PREFIX_TABLE (PREFIX_VEX_0F16) },
5866     { MOD_TABLE (MOD_VEX_0F17) },
5867     /* 18 */
5868     { Bad_Opcode },
5869     { Bad_Opcode },
5870     { Bad_Opcode },
5871     { Bad_Opcode },
5872     { Bad_Opcode },
5873     { Bad_Opcode },
5874     { Bad_Opcode },
5875     { Bad_Opcode },
5876     /* 20 */
5877     { Bad_Opcode },
5878     { Bad_Opcode },
5879     { Bad_Opcode },
5880     { Bad_Opcode },
5881     { Bad_Opcode },
5882     { Bad_Opcode },
5883     { Bad_Opcode },
5884     { Bad_Opcode },
5885     /* 28 */
5886     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
5887     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
5888     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
5889     { MOD_TABLE (MOD_VEX_0F2B) },
5890     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
5891     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
5892     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
5893     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
5894     /* 30 */
5895     { Bad_Opcode },
5896     { Bad_Opcode },
5897     { Bad_Opcode },
5898     { Bad_Opcode },
5899     { Bad_Opcode },
5900     { Bad_Opcode },
5901     { Bad_Opcode },
5902     { Bad_Opcode },
5903     /* 38 */
5904     { Bad_Opcode },
5905     { Bad_Opcode },
5906     { Bad_Opcode },
5907     { Bad_Opcode },
5908     { Bad_Opcode },
5909     { Bad_Opcode },
5910     { Bad_Opcode },
5911     { Bad_Opcode },
5912     /* 40 */
5913     { Bad_Opcode },
5914     { PREFIX_TABLE (PREFIX_VEX_0F41) },
5915     { PREFIX_TABLE (PREFIX_VEX_0F42) },
5916     { Bad_Opcode },
5917     { PREFIX_TABLE (PREFIX_VEX_0F44) },
5918     { PREFIX_TABLE (PREFIX_VEX_0F45) },
5919     { PREFIX_TABLE (PREFIX_VEX_0F46) },
5920     { PREFIX_TABLE (PREFIX_VEX_0F47) },
5921     /* 48 */
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
5925     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
5926     { Bad_Opcode },
5927     { Bad_Opcode },
5928     { Bad_Opcode },
5929     { Bad_Opcode },
5930     /* 50 */
5931     { MOD_TABLE (MOD_VEX_0F50) },
5932     { PREFIX_TABLE (PREFIX_VEX_0F51) },
5933     { PREFIX_TABLE (PREFIX_VEX_0F52) },
5934     { PREFIX_TABLE (PREFIX_VEX_0F53) },
5935     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
5936     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
5937     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
5938     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
5939     /* 58 */
5940     { PREFIX_TABLE (PREFIX_VEX_0F58) },
5941     { PREFIX_TABLE (PREFIX_VEX_0F59) },
5942     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
5943     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
5944     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
5945     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
5946     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
5947     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
5948     /* 60 */
5949     { "vpunpcklbw",     { XM, Vex, EXx }, PREFIX_DATA },
5950     { "vpunpcklwd",     { XM, Vex, EXx }, PREFIX_DATA },
5951     { "vpunpckldq",     { XM, Vex, EXx }, PREFIX_DATA },
5952     { "vpacksswb",      { XM, Vex, EXx }, PREFIX_DATA },
5953     { "vpcmpgtb",       { XM, Vex, EXx }, PREFIX_DATA },
5954     { "vpcmpgtw",       { XM, Vex, EXx }, PREFIX_DATA },
5955     { "vpcmpgtd",       { XM, Vex, EXx }, PREFIX_DATA },
5956     { "vpackuswb",      { XM, Vex, EXx }, PREFIX_DATA },
5957     /* 68 */
5958     { "vpunpckhbw",     { XM, Vex, EXx }, PREFIX_DATA },
5959     { "vpunpckhwd",     { XM, Vex, EXx }, PREFIX_DATA },
5960     { "vpunpckhdq",     { XM, Vex, EXx }, PREFIX_DATA },
5961     { "vpackssdw",      { XM, Vex, EXx }, PREFIX_DATA },
5962     { "vpunpcklqdq",    { XM, Vex, EXx }, PREFIX_DATA },
5963     { "vpunpckhqdq",    { XM, Vex, EXx }, PREFIX_DATA },
5964     { VEX_LEN_TABLE (VEX_LEN_0F6E) },
5965     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
5966     /* 70 */
5967     { PREFIX_TABLE (PREFIX_VEX_0F70) },
5968     { REG_TABLE (REG_VEX_0F71) },
5969     { REG_TABLE (REG_VEX_0F72) },
5970     { REG_TABLE (REG_VEX_0F73) },
5971     { "vpcmpeqb",       { XM, Vex, EXx }, PREFIX_DATA },
5972     { "vpcmpeqw",       { XM, Vex, EXx }, PREFIX_DATA },
5973     { "vpcmpeqd",       { XM, Vex, EXx }, PREFIX_DATA },
5974     { VEX_LEN_TABLE (VEX_LEN_0F77) },
5975     /* 78 */
5976     { Bad_Opcode },
5977     { Bad_Opcode },
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
5981     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
5982     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
5983     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
5984     /* 80 */
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987     { Bad_Opcode },
5988     { Bad_Opcode },
5989     { Bad_Opcode },
5990     { Bad_Opcode },
5991     { Bad_Opcode },
5992     { Bad_Opcode },
5993     /* 88 */
5994     { Bad_Opcode },
5995     { Bad_Opcode },
5996     { Bad_Opcode },
5997     { Bad_Opcode },
5998     { Bad_Opcode },
5999     { Bad_Opcode },
6000     { Bad_Opcode },
6001     { Bad_Opcode },
6002     /* 90 */
6003     { PREFIX_TABLE (PREFIX_VEX_0F90) },
6004     { PREFIX_TABLE (PREFIX_VEX_0F91) },
6005     { PREFIX_TABLE (PREFIX_VEX_0F92) },
6006     { PREFIX_TABLE (PREFIX_VEX_0F93) },
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { Bad_Opcode },
6011     /* 98 */
6012     { PREFIX_TABLE (PREFIX_VEX_0F98) },
6013     { PREFIX_TABLE (PREFIX_VEX_0F99) },
6014     { Bad_Opcode },
6015     { Bad_Opcode },
6016     { Bad_Opcode },
6017     { Bad_Opcode },
6018     { Bad_Opcode },
6019     { Bad_Opcode },
6020     /* a0 */
6021     { Bad_Opcode },
6022     { Bad_Opcode },
6023     { Bad_Opcode },
6024     { Bad_Opcode },
6025     { Bad_Opcode },
6026     { Bad_Opcode },
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     /* a8 */
6030     { Bad_Opcode },
6031     { Bad_Opcode },
6032     { Bad_Opcode },
6033     { Bad_Opcode },
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { REG_TABLE (REG_VEX_0FAE) },
6037     { Bad_Opcode },
6038     /* b0 */
6039     { Bad_Opcode },
6040     { Bad_Opcode },
6041     { Bad_Opcode },
6042     { Bad_Opcode },
6043     { Bad_Opcode },
6044     { Bad_Opcode },
6045     { Bad_Opcode },
6046     { Bad_Opcode },
6047     /* b8 */
6048     { Bad_Opcode },
6049     { Bad_Opcode },
6050     { Bad_Opcode },
6051     { Bad_Opcode },
6052     { Bad_Opcode },
6053     { Bad_Opcode },
6054     { Bad_Opcode },
6055     { Bad_Opcode },
6056     /* c0 */
6057     { Bad_Opcode },
6058     { Bad_Opcode },
6059     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
6060     { Bad_Opcode },
6061     { VEX_LEN_TABLE (VEX_LEN_0FC4) },
6062     { VEX_LEN_TABLE (VEX_LEN_0FC5) },
6063     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
6064     { Bad_Opcode },
6065     /* c8 */
6066     { Bad_Opcode },
6067     { Bad_Opcode },
6068     { Bad_Opcode },
6069     { Bad_Opcode },
6070     { Bad_Opcode },
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     { Bad_Opcode },
6074     /* d0 */
6075     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
6076     { "vpsrlw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6077     { "vpsrld",         { XM, Vex, EXxmm }, PREFIX_DATA },
6078     { "vpsrlq",         { XM, Vex, EXxmm }, PREFIX_DATA },
6079     { "vpaddq",         { XM, Vex, EXx }, PREFIX_DATA },
6080     { "vpmullw",        { XM, Vex, EXx }, PREFIX_DATA },
6081     { VEX_LEN_TABLE (VEX_LEN_0FD6) },
6082     { MOD_TABLE (MOD_VEX_0FD7) },
6083     /* d8 */
6084     { "vpsubusb",       { XM, Vex, EXx }, PREFIX_DATA },
6085     { "vpsubusw",       { XM, Vex, EXx }, PREFIX_DATA },
6086     { "vpminub",        { XM, Vex, EXx }, PREFIX_DATA },
6087     { "vpand",          { XM, Vex, EXx }, PREFIX_DATA },
6088     { "vpaddusb",       { XM, Vex, EXx }, PREFIX_DATA },
6089     { "vpaddusw",       { XM, Vex, EXx }, PREFIX_DATA },
6090     { "vpmaxub",        { XM, Vex, EXx }, PREFIX_DATA },
6091     { "vpandn",         { XM, Vex, EXx }, PREFIX_DATA },
6092     /* e0 */
6093     { "vpavgb",         { XM, Vex, EXx }, PREFIX_DATA },
6094     { "vpsraw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6095     { "vpsrad",         { XM, Vex, EXxmm }, PREFIX_DATA },
6096     { "vpavgw",         { XM, Vex, EXx }, PREFIX_DATA },
6097     { "vpmulhuw",       { XM, Vex, EXx }, PREFIX_DATA },
6098     { "vpmulhw",        { XM, Vex, EXx }, PREFIX_DATA },
6099     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
6100     { MOD_TABLE (MOD_VEX_0FE7) },
6101     /* e8 */
6102     { "vpsubsb",        { XM, Vex, EXx }, PREFIX_DATA },
6103     { "vpsubsw",        { XM, Vex, EXx }, PREFIX_DATA },
6104     { "vpminsw",        { XM, Vex, EXx }, PREFIX_DATA },
6105     { "vpor",           { XM, Vex, EXx }, PREFIX_DATA },
6106     { "vpaddsb",        { XM, Vex, EXx }, PREFIX_DATA },
6107     { "vpaddsw",        { XM, Vex, EXx }, PREFIX_DATA },
6108     { "vpmaxsw",        { XM, Vex, EXx }, PREFIX_DATA },
6109     { "vpxor",          { XM, Vex, EXx }, PREFIX_DATA },
6110     /* f0 */
6111     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
6112     { "vpsllw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6113     { "vpslld",         { XM, Vex, EXxmm }, PREFIX_DATA },
6114     { "vpsllq",         { XM, Vex, EXxmm }, PREFIX_DATA },
6115     { "vpmuludq",       { XM, Vex, EXx }, PREFIX_DATA },
6116     { "vpmaddwd",       { XM, Vex, EXx }, PREFIX_DATA },
6117     { "vpsadbw",        { XM, Vex, EXx }, PREFIX_DATA },
6118     { VEX_LEN_TABLE (VEX_LEN_0FF7) },
6119     /* f8 */
6120     { "vpsubb",         { XM, Vex, EXx }, PREFIX_DATA },
6121     { "vpsubw",         { XM, Vex, EXx }, PREFIX_DATA },
6122     { "vpsubd",         { XM, Vex, EXx }, PREFIX_DATA },
6123     { "vpsubq",         { XM, Vex, EXx }, PREFIX_DATA },
6124     { "vpaddb",         { XM, Vex, EXx }, PREFIX_DATA },
6125     { "vpaddw",         { XM, Vex, EXx }, PREFIX_DATA },
6126     { "vpaddd",         { XM, Vex, EXx }, PREFIX_DATA },
6127     { Bad_Opcode },
6128   },
6129   /* VEX_0F38 */
6130   {
6131     /* 00 */
6132     { "vpshufb",        { XM, Vex, EXx }, PREFIX_DATA },
6133     { "vphaddw",        { XM, Vex, EXx }, PREFIX_DATA },
6134     { "vphaddd",        { XM, Vex, EXx }, PREFIX_DATA },
6135     { "vphaddsw",       { XM, Vex, EXx }, PREFIX_DATA },
6136     { "vpmaddubsw",     { XM, Vex, EXx }, PREFIX_DATA },
6137     { "vphsubw",        { XM, Vex, EXx }, PREFIX_DATA },
6138     { "vphsubd",        { XM, Vex, EXx }, PREFIX_DATA },
6139     { "vphsubsw",       { XM, Vex, EXx }, PREFIX_DATA },
6140     /* 08 */
6141     { "vpsignb",        { XM, Vex, EXx }, PREFIX_DATA },
6142     { "vpsignw",        { XM, Vex, EXx }, PREFIX_DATA },
6143     { "vpsignd",        { XM, Vex, EXx }, PREFIX_DATA },
6144     { "vpmulhrsw",      { XM, Vex, EXx }, PREFIX_DATA },
6145     { VEX_W_TABLE (VEX_W_0F380C) },
6146     { VEX_W_TABLE (VEX_W_0F380D) },
6147     { VEX_W_TABLE (VEX_W_0F380E) },
6148     { VEX_W_TABLE (VEX_W_0F380F) },
6149     /* 10 */
6150     { Bad_Opcode },
6151     { Bad_Opcode },
6152     { Bad_Opcode },
6153     { VEX_W_TABLE (VEX_W_0F3813) },
6154     { Bad_Opcode },
6155     { Bad_Opcode },
6156     { VEX_LEN_TABLE (VEX_LEN_0F3816) },
6157     { "vptest",         { XM, EXx }, PREFIX_DATA },
6158     /* 18 */
6159     { VEX_W_TABLE (VEX_W_0F3818) },
6160     { VEX_LEN_TABLE (VEX_LEN_0F3819) },
6161     { MOD_TABLE (MOD_VEX_0F381A) },
6162     { Bad_Opcode },
6163     { "vpabsb",         { XM, EXx }, PREFIX_DATA },
6164     { "vpabsw",         { XM, EXx }, PREFIX_DATA },
6165     { "vpabsd",         { XM, EXx }, PREFIX_DATA },
6166     { Bad_Opcode },
6167     /* 20 */
6168     { "vpmovsxbw",      { XM, EXxmmq }, PREFIX_DATA },
6169     { "vpmovsxbd",      { XM, EXxmmqd }, PREFIX_DATA },
6170     { "vpmovsxbq",      { XM, EXxmmdw }, PREFIX_DATA },
6171     { "vpmovsxwd",      { XM, EXxmmq }, PREFIX_DATA },
6172     { "vpmovsxwq",      { XM, EXxmmqd }, PREFIX_DATA },
6173     { "vpmovsxdq",      { XM, EXxmmq }, PREFIX_DATA },
6174     { Bad_Opcode },
6175     { Bad_Opcode },
6176     /* 28 */
6177     { "vpmuldq",        { XM, Vex, EXx }, PREFIX_DATA },
6178     { "vpcmpeqq",       { XM, Vex, EXx }, PREFIX_DATA },
6179     { MOD_TABLE (MOD_VEX_0F382A) },
6180     { "vpackusdw",      { XM, Vex, EXx }, PREFIX_DATA },
6181     { MOD_TABLE (MOD_VEX_0F382C) },
6182     { MOD_TABLE (MOD_VEX_0F382D) },
6183     { MOD_TABLE (MOD_VEX_0F382E) },
6184     { MOD_TABLE (MOD_VEX_0F382F) },
6185     /* 30 */
6186     { "vpmovzxbw",      { XM, EXxmmq }, PREFIX_DATA },
6187     { "vpmovzxbd",      { XM, EXxmmqd }, PREFIX_DATA },
6188     { "vpmovzxbq",      { XM, EXxmmdw }, PREFIX_DATA },
6189     { "vpmovzxwd",      { XM, EXxmmq }, PREFIX_DATA },
6190     { "vpmovzxwq",      { XM, EXxmmqd }, PREFIX_DATA },
6191     { "vpmovzxdq",      { XM, EXxmmq }, PREFIX_DATA },
6192     { VEX_LEN_TABLE (VEX_LEN_0F3836) },
6193     { "vpcmpgtq",       { XM, Vex, EXx }, PREFIX_DATA },
6194     /* 38 */
6195     { "vpminsb",        { XM, Vex, EXx }, PREFIX_DATA },
6196     { "vpminsd",        { XM, Vex, EXx }, PREFIX_DATA },
6197     { "vpminuw",        { XM, Vex, EXx }, PREFIX_DATA },
6198     { "vpminud",        { XM, Vex, EXx }, PREFIX_DATA },
6199     { "vpmaxsb",        { XM, Vex, EXx }, PREFIX_DATA },
6200     { "vpmaxsd",        { XM, Vex, EXx }, PREFIX_DATA },
6201     { "vpmaxuw",        { XM, Vex, EXx }, PREFIX_DATA },
6202     { "vpmaxud",        { XM, Vex, EXx }, PREFIX_DATA },
6203     /* 40 */
6204     { "vpmulld",        { XM, Vex, EXx }, PREFIX_DATA },
6205     { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6206     { Bad_Opcode },
6207     { Bad_Opcode },
6208     { Bad_Opcode },
6209     { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6210     { VEX_W_TABLE (VEX_W_0F3846) },
6211     { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6212     /* 48 */
6213     { Bad_Opcode },
6214     { X86_64_TABLE (X86_64_VEX_0F3849) },
6215     { Bad_Opcode },
6216     { X86_64_TABLE (X86_64_VEX_0F384B) },
6217     { Bad_Opcode },
6218     { Bad_Opcode },
6219     { Bad_Opcode },
6220     { Bad_Opcode },
6221     /* 50 */
6222     { Bad_Opcode },
6223     { Bad_Opcode },
6224     { Bad_Opcode },
6225     { Bad_Opcode },
6226     { Bad_Opcode },
6227     { Bad_Opcode },
6228     { Bad_Opcode },
6229     { Bad_Opcode },
6230     /* 58 */
6231     { VEX_W_TABLE (VEX_W_0F3858) },
6232     { VEX_W_TABLE (VEX_W_0F3859) },
6233     { MOD_TABLE (MOD_VEX_0F385A) },
6234     { Bad_Opcode },
6235     { X86_64_TABLE (X86_64_VEX_0F385C) },
6236     { Bad_Opcode },
6237     { X86_64_TABLE (X86_64_VEX_0F385E) },
6238     { Bad_Opcode },
6239     /* 60 */
6240     { Bad_Opcode },
6241     { Bad_Opcode },
6242     { Bad_Opcode },
6243     { Bad_Opcode },
6244     { Bad_Opcode },
6245     { Bad_Opcode },
6246     { Bad_Opcode },
6247     { Bad_Opcode },
6248     /* 68 */
6249     { Bad_Opcode },
6250     { Bad_Opcode },
6251     { Bad_Opcode },
6252     { Bad_Opcode },
6253     { Bad_Opcode },
6254     { Bad_Opcode },
6255     { Bad_Opcode },
6256     { Bad_Opcode },
6257     /* 70 */
6258     { Bad_Opcode },
6259     { Bad_Opcode },
6260     { Bad_Opcode },
6261     { Bad_Opcode },
6262     { Bad_Opcode },
6263     { Bad_Opcode },
6264     { Bad_Opcode },
6265     { Bad_Opcode },
6266     /* 78 */
6267     { VEX_W_TABLE (VEX_W_0F3878) },
6268     { VEX_W_TABLE (VEX_W_0F3879) },
6269     { Bad_Opcode },
6270     { Bad_Opcode },
6271     { Bad_Opcode },
6272     { Bad_Opcode },
6273     { Bad_Opcode },
6274     { Bad_Opcode },
6275     /* 80 */
6276     { Bad_Opcode },
6277     { Bad_Opcode },
6278     { Bad_Opcode },
6279     { Bad_Opcode },
6280     { Bad_Opcode },
6281     { Bad_Opcode },
6282     { Bad_Opcode },
6283     { Bad_Opcode },
6284     /* 88 */
6285     { Bad_Opcode },
6286     { Bad_Opcode },
6287     { Bad_Opcode },
6288     { Bad_Opcode },
6289     { MOD_TABLE (MOD_VEX_0F388C) },
6290     { Bad_Opcode },
6291     { MOD_TABLE (MOD_VEX_0F388E) },
6292     { Bad_Opcode },
6293     /* 90 */
6294     { "vpgatherd%DQ", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA },
6295     { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6296     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA },
6297     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6298     { Bad_Opcode },
6299     { Bad_Opcode },
6300     { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6301     { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6302     /* 98 */
6303     { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6304     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6305     { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6306     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6307     { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6308     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6309     { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6310     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6311     /* a0 */
6312     { Bad_Opcode },
6313     { Bad_Opcode },
6314     { Bad_Opcode },
6315     { Bad_Opcode },
6316     { Bad_Opcode },
6317     { Bad_Opcode },
6318     { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6319     { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6320     /* a8 */
6321     { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6322     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6323     { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6324     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6325     { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6326     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6327     { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6328     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6329     /* b0 */
6330     { Bad_Opcode },
6331     { Bad_Opcode },
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     { Bad_Opcode },
6335     { Bad_Opcode },
6336     { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6337     { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6338     /* b8 */
6339     { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6340     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6341     { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6342     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6343     { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6344     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6345     { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6346     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6347     /* c0 */
6348     { Bad_Opcode },
6349     { Bad_Opcode },
6350     { Bad_Opcode },
6351     { Bad_Opcode },
6352     { Bad_Opcode },
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { Bad_Opcode },
6356     /* c8 */
6357     { Bad_Opcode },
6358     { Bad_Opcode },
6359     { Bad_Opcode },
6360     { Bad_Opcode },
6361     { Bad_Opcode },
6362     { Bad_Opcode },
6363     { Bad_Opcode },
6364     { VEX_W_TABLE (VEX_W_0F38CF) },
6365     /* d0 */
6366     { Bad_Opcode },
6367     { Bad_Opcode },
6368     { Bad_Opcode },
6369     { Bad_Opcode },
6370     { Bad_Opcode },
6371     { Bad_Opcode },
6372     { Bad_Opcode },
6373     { Bad_Opcode },
6374     /* d8 */
6375     { Bad_Opcode },
6376     { Bad_Opcode },
6377     { Bad_Opcode },
6378     { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6379     { "vaesenc",        { XM, Vex, EXx }, PREFIX_DATA },
6380     { "vaesenclast",    { XM, Vex, EXx }, PREFIX_DATA },
6381     { "vaesdec",        { XM, Vex, EXx }, PREFIX_DATA },
6382     { "vaesdeclast",    { XM, Vex, EXx }, PREFIX_DATA },
6383     /* e0 */
6384     { Bad_Opcode },
6385     { Bad_Opcode },
6386     { Bad_Opcode },
6387     { Bad_Opcode },
6388     { Bad_Opcode },
6389     { Bad_Opcode },
6390     { Bad_Opcode },
6391     { Bad_Opcode },
6392     /* e8 */
6393     { Bad_Opcode },
6394     { Bad_Opcode },
6395     { Bad_Opcode },
6396     { Bad_Opcode },
6397     { Bad_Opcode },
6398     { Bad_Opcode },
6399     { Bad_Opcode },
6400     { Bad_Opcode },
6401     /* f0 */
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
6405     { REG_TABLE (REG_VEX_0F38F3) },
6406     { Bad_Opcode },
6407     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
6408     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
6409     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
6410     /* f8 */
6411     { Bad_Opcode },
6412     { Bad_Opcode },
6413     { Bad_Opcode },
6414     { Bad_Opcode },
6415     { Bad_Opcode },
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { Bad_Opcode },
6419   },
6420   /* VEX_0F3A */
6421   {
6422     /* 00 */
6423     { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6424     { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6425     { VEX_W_TABLE (VEX_W_0F3A02) },
6426     { Bad_Opcode },
6427     { VEX_W_TABLE (VEX_W_0F3A04) },
6428     { VEX_W_TABLE (VEX_W_0F3A05) },
6429     { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6430     { Bad_Opcode },
6431     /* 08 */
6432     { "vroundps",       { XM, EXx, Ib }, PREFIX_DATA },
6433     { "vroundpd",       { XM, EXx, Ib }, PREFIX_DATA },
6434     { "vroundss",       { XMScalar, VexScalar, EXxmm_md, Ib }, PREFIX_DATA },
6435     { "vroundsd",       { XMScalar, VexScalar, EXxmm_mq, Ib }, PREFIX_DATA },
6436     { "vblendps",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6437     { "vblendpd",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6438     { "vpblendw",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6439     { "vpalignr",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6440     /* 10 */
6441     { Bad_Opcode },
6442     { Bad_Opcode },
6443     { Bad_Opcode },
6444     { Bad_Opcode },
6445     { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6446     { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6447     { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6448     { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6449     /* 18 */
6450     { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6451     { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6452     { Bad_Opcode },
6453     { Bad_Opcode },
6454     { Bad_Opcode },
6455     { VEX_W_TABLE (VEX_W_0F3A1D) },
6456     { Bad_Opcode },
6457     { Bad_Opcode },
6458     /* 20 */
6459     { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6460     { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6461     { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6462     { Bad_Opcode },
6463     { Bad_Opcode },
6464     { Bad_Opcode },
6465     { Bad_Opcode },
6466     { Bad_Opcode },
6467     /* 28 */
6468     { Bad_Opcode },
6469     { Bad_Opcode },
6470     { Bad_Opcode },
6471     { Bad_Opcode },
6472     { Bad_Opcode },
6473     { Bad_Opcode },
6474     { Bad_Opcode },
6475     { Bad_Opcode },
6476     /* 30 */
6477     { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6478     { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6479     { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6480     { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6481     { Bad_Opcode },
6482     { Bad_Opcode },
6483     { Bad_Opcode },
6484     { Bad_Opcode },
6485     /* 38 */
6486     { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6487     { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6488     { Bad_Opcode },
6489     { Bad_Opcode },
6490     { Bad_Opcode },
6491     { Bad_Opcode },
6492     { Bad_Opcode },
6493     { Bad_Opcode },
6494     /* 40 */
6495     { "vdpps",          { XM, Vex, EXx, Ib }, PREFIX_DATA },
6496     { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6497     { "vmpsadbw",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6498     { Bad_Opcode },
6499     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6500     { Bad_Opcode },
6501     { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6502     { Bad_Opcode },
6503     /* 48 */
6504     { "vpermil2ps",     { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6505     { "vpermil2pd",     { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6506     { VEX_W_TABLE (VEX_W_0F3A4A) },
6507     { VEX_W_TABLE (VEX_W_0F3A4B) },
6508     { VEX_W_TABLE (VEX_W_0F3A4C) },
6509     { Bad_Opcode },
6510     { Bad_Opcode },
6511     { Bad_Opcode },
6512     /* 50 */
6513     { Bad_Opcode },
6514     { Bad_Opcode },
6515     { Bad_Opcode },
6516     { Bad_Opcode },
6517     { Bad_Opcode },
6518     { Bad_Opcode },
6519     { Bad_Opcode },
6520     { Bad_Opcode },
6521     /* 58 */
6522     { Bad_Opcode },
6523     { Bad_Opcode },
6524     { Bad_Opcode },
6525     { Bad_Opcode },
6526     { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6527     { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6528     { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6529     { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6530     /* 60 */
6531     { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6532     { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6533     { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6534     { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6535     { Bad_Opcode },
6536     { Bad_Opcode },
6537     { Bad_Opcode },
6538     { Bad_Opcode },
6539     /* 68 */
6540     { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6541     { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6542     { "vfmaddss",       { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6543     { "vfmaddsd",       { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6544     { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6545     { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6546     { "vfmsubss",       { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6547     { "vfmsubsd",       { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6548     /* 70 */
6549     { Bad_Opcode },
6550     { Bad_Opcode },
6551     { Bad_Opcode },
6552     { Bad_Opcode },
6553     { Bad_Opcode },
6554     { Bad_Opcode },
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     /* 78 */
6558     { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6559     { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6560     { "vfnmaddss",      { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6561     { "vfnmaddsd",      { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6562     { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6563     { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6564     { "vfnmsubss",      { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6565     { "vfnmsubsd",      { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6566     /* 80 */
6567     { Bad_Opcode },
6568     { Bad_Opcode },
6569     { Bad_Opcode },
6570     { Bad_Opcode },
6571     { Bad_Opcode },
6572     { Bad_Opcode },
6573     { Bad_Opcode },
6574     { Bad_Opcode },
6575     /* 88 */
6576     { Bad_Opcode },
6577     { Bad_Opcode },
6578     { Bad_Opcode },
6579     { Bad_Opcode },
6580     { Bad_Opcode },
6581     { Bad_Opcode },
6582     { Bad_Opcode },
6583     { Bad_Opcode },
6584     /* 90 */
6585     { Bad_Opcode },
6586     { Bad_Opcode },
6587     { Bad_Opcode },
6588     { Bad_Opcode },
6589     { Bad_Opcode },
6590     { Bad_Opcode },
6591     { Bad_Opcode },
6592     { Bad_Opcode },
6593     /* 98 */
6594     { Bad_Opcode },
6595     { Bad_Opcode },
6596     { Bad_Opcode },
6597     { Bad_Opcode },
6598     { Bad_Opcode },
6599     { Bad_Opcode },
6600     { Bad_Opcode },
6601     { Bad_Opcode },
6602     /* a0 */
6603     { Bad_Opcode },
6604     { Bad_Opcode },
6605     { Bad_Opcode },
6606     { Bad_Opcode },
6607     { Bad_Opcode },
6608     { Bad_Opcode },
6609     { Bad_Opcode },
6610     { Bad_Opcode },
6611     /* a8 */
6612     { Bad_Opcode },
6613     { Bad_Opcode },
6614     { Bad_Opcode },
6615     { Bad_Opcode },
6616     { Bad_Opcode },
6617     { Bad_Opcode },
6618     { Bad_Opcode },
6619     { Bad_Opcode },
6620     /* b0 */
6621     { Bad_Opcode },
6622     { Bad_Opcode },
6623     { Bad_Opcode },
6624     { Bad_Opcode },
6625     { Bad_Opcode },
6626     { Bad_Opcode },
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629     /* b8 */
6630     { Bad_Opcode },
6631     { Bad_Opcode },
6632     { Bad_Opcode },
6633     { Bad_Opcode },
6634     { Bad_Opcode },
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { Bad_Opcode },
6638     /* c0 */
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     { Bad_Opcode },
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     { Bad_Opcode },
6645     { Bad_Opcode },
6646     { Bad_Opcode },
6647     /* c8 */
6648     { Bad_Opcode },
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     { Bad_Opcode },
6652     { Bad_Opcode },
6653     { Bad_Opcode },
6654     { VEX_W_TABLE (VEX_W_0F3ACE) },
6655     { VEX_W_TABLE (VEX_W_0F3ACF) },
6656     /* d0 */
6657     { Bad_Opcode },
6658     { Bad_Opcode },
6659     { Bad_Opcode },
6660     { Bad_Opcode },
6661     { Bad_Opcode },
6662     { Bad_Opcode },
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     /* d8 */
6666     { Bad_Opcode },
6667     { Bad_Opcode },
6668     { Bad_Opcode },
6669     { Bad_Opcode },
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672     { Bad_Opcode },
6673     { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
6674     /* e0 */
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     { Bad_Opcode },
6680     { Bad_Opcode },
6681     { Bad_Opcode },
6682     { Bad_Opcode },
6683     /* e8 */
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     { Bad_Opcode },
6687     { Bad_Opcode },
6688     { Bad_Opcode },
6689     { Bad_Opcode },
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     /* f0 */
6693     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
6694     { Bad_Opcode },
6695     { Bad_Opcode },
6696     { Bad_Opcode },
6697     { Bad_Opcode },
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     { Bad_Opcode },
6701     /* f8 */
6702     { Bad_Opcode },
6703     { Bad_Opcode },
6704     { Bad_Opcode },
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     { Bad_Opcode },
6708     { Bad_Opcode },
6709     { Bad_Opcode },
6710   },
6711 };
6712
6713 #include "i386-dis-evex.h"
6714
6715 static const struct dis386 vex_len_table[][2] = {
6716   /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
6717   {
6718     { "vmovlpX",        { XM, Vex, EXq }, 0 },
6719   },
6720
6721   /* VEX_LEN_0F12_P_0_M_1 */
6722   {
6723     { "vmovhlps",       { XM, Vex, EXq }, 0 },
6724   },
6725
6726   /* VEX_LEN_0F13_M_0 */
6727   {
6728     { "vmovlpX",        { EXq, XM }, PREFIX_OPCODE },
6729   },
6730
6731   /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
6732   {
6733     { "vmovhpX",        { XM, Vex, EXq }, 0 },
6734   },
6735
6736   /* VEX_LEN_0F16_P_0_M_1 */
6737   {
6738     { "vmovlhps",       { XM, Vex, EXq }, 0 },
6739   },
6740
6741   /* VEX_LEN_0F17_M_0 */
6742   {
6743     { "vmovhpX",        { EXq, XM }, PREFIX_OPCODE },
6744   },
6745
6746   /* VEX_LEN_0F41_P_0 */
6747   {
6748     { Bad_Opcode },
6749     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
6750   },
6751   /* VEX_LEN_0F41_P_2 */
6752   {
6753     { Bad_Opcode },
6754     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
6755   },
6756   /* VEX_LEN_0F42_P_0 */
6757   {
6758     { Bad_Opcode },
6759     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
6760   },
6761   /* VEX_LEN_0F42_P_2 */
6762   {
6763     { Bad_Opcode },
6764     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
6765   },
6766   /* VEX_LEN_0F44_P_0 */
6767   {
6768     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
6769   },
6770   /* VEX_LEN_0F44_P_2 */
6771   {
6772     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
6773   },
6774   /* VEX_LEN_0F45_P_0 */
6775   {
6776     { Bad_Opcode },
6777     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
6778   },
6779   /* VEX_LEN_0F45_P_2 */
6780   {
6781     { Bad_Opcode },
6782     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
6783   },
6784   /* VEX_LEN_0F46_P_0 */
6785   {
6786     { Bad_Opcode },
6787     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
6788   },
6789   /* VEX_LEN_0F46_P_2 */
6790   {
6791     { Bad_Opcode },
6792     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
6793   },
6794   /* VEX_LEN_0F47_P_0 */
6795   {
6796     { Bad_Opcode },
6797     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
6798   },
6799   /* VEX_LEN_0F47_P_2 */
6800   {
6801     { Bad_Opcode },
6802     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
6803   },
6804   /* VEX_LEN_0F4A_P_0 */
6805   {
6806     { Bad_Opcode },
6807     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
6808   },
6809   /* VEX_LEN_0F4A_P_2 */
6810   {
6811     { Bad_Opcode },
6812     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
6813   },
6814   /* VEX_LEN_0F4B_P_0 */
6815   {
6816     { Bad_Opcode },
6817     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
6818   },
6819   /* VEX_LEN_0F4B_P_2 */
6820   {
6821     { Bad_Opcode },
6822     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
6823   },
6824
6825   /* VEX_LEN_0F6E */
6826   {
6827     { "vmovK",          { XMScalar, Edq }, PREFIX_DATA },
6828   },
6829
6830   /* VEX_LEN_0F77 */
6831   {
6832     { "vzeroupper",     { XX }, 0 },
6833     { "vzeroall",       { XX }, 0 },
6834   },
6835
6836   /* VEX_LEN_0F7E_P_1 */
6837   {
6838     { "vmovq",          { XMScalar, EXxmm_mq }, 0 },
6839   },
6840
6841   /* VEX_LEN_0F7E_P_2 */
6842   {
6843     { "vmovK",          { Edq, XMScalar }, 0 },
6844   },
6845
6846   /* VEX_LEN_0F90_P_0 */
6847   {
6848     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
6849   },
6850
6851   /* VEX_LEN_0F90_P_2 */
6852   {
6853     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
6854   },
6855
6856   /* VEX_LEN_0F91_P_0 */
6857   {
6858     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
6859   },
6860
6861   /* VEX_LEN_0F91_P_2 */
6862   {
6863     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
6864   },
6865
6866   /* VEX_LEN_0F92_P_0 */
6867   {
6868     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
6869   },
6870
6871   /* VEX_LEN_0F92_P_2 */
6872   {
6873     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
6874   },
6875
6876   /* VEX_LEN_0F92_P_3 */
6877   {
6878     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
6879   },
6880
6881   /* VEX_LEN_0F93_P_0 */
6882   {
6883     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
6884   },
6885
6886   /* VEX_LEN_0F93_P_2 */
6887   {
6888     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
6889   },
6890
6891   /* VEX_LEN_0F93_P_3 */
6892   {
6893     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
6894   },
6895
6896   /* VEX_LEN_0F98_P_0 */
6897   {
6898     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
6899   },
6900
6901   /* VEX_LEN_0F98_P_2 */
6902   {
6903     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
6904   },
6905
6906   /* VEX_LEN_0F99_P_0 */
6907   {
6908     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
6909   },
6910
6911   /* VEX_LEN_0F99_P_2 */
6912   {
6913     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
6914   },
6915
6916   /* VEX_LEN_0FAE_R_2_M_0 */
6917   {
6918     { "vldmxcsr",       { Md }, 0 },
6919   },
6920
6921   /* VEX_LEN_0FAE_R_3_M_0 */
6922   {
6923     { "vstmxcsr",       { Md }, 0 },
6924   },
6925
6926   /* VEX_LEN_0FC4 */
6927   {
6928     { "vpinsrw",        { XM, Vex, Edqw, Ib }, PREFIX_DATA },
6929   },
6930
6931   /* VEX_LEN_0FC5 */
6932   {
6933     { "vpextrw",        { Gdq, XS, Ib }, PREFIX_DATA },
6934   },
6935
6936   /* VEX_LEN_0FD6 */
6937   {
6938     { "vmovq",          { EXqS, XMScalar }, PREFIX_DATA },
6939   },
6940
6941   /* VEX_LEN_0FF7 */
6942   {
6943     { "vmaskmovdqu",    { XM, XS }, PREFIX_DATA },
6944   },
6945
6946   /* VEX_LEN_0F3816 */
6947   {
6948     { Bad_Opcode },
6949     { VEX_W_TABLE (VEX_W_0F3816_L_1) },
6950   },
6951
6952   /* VEX_LEN_0F3819 */
6953   {
6954     { Bad_Opcode },
6955     { VEX_W_TABLE (VEX_W_0F3819_L_1) },
6956   },
6957
6958   /* VEX_LEN_0F381A_M_0 */
6959   {
6960     { Bad_Opcode },
6961     { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1) },
6962   },
6963
6964   /* VEX_LEN_0F3836 */
6965   {
6966     { Bad_Opcode },
6967     { VEX_W_TABLE (VEX_W_0F3836) },
6968   },
6969
6970   /* VEX_LEN_0F3841 */
6971   {
6972     { "vphminposuw",    { XM, EXx }, PREFIX_DATA },
6973   },
6974
6975    /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
6976   {
6977     { "ldtilecfg", { M }, 0 },
6978   },
6979
6980   /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
6981   {
6982     { "tilerelease", { Skip_MODRM }, 0 },
6983   },
6984
6985   /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
6986   {
6987     { "sttilecfg", { M }, 0 },
6988   },
6989
6990   /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
6991   {
6992     { "tilezero", { TMM, Skip_MODRM }, 0 },
6993   },
6994
6995   /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
6996   {
6997     { "tilestored", { MVexSIBMEM, TMM }, 0 },
6998   },
6999   /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
7000   {
7001     { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
7002   },
7003
7004   /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
7005   {
7006     { "tileloadd", { TMM, MVexSIBMEM }, 0 },
7007   },
7008
7009   /* VEX_LEN_0F385A_M_0 */
7010   {
7011     { Bad_Opcode },
7012     { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0) },
7013   },
7014
7015   /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
7016   {
7017     { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
7018   },
7019
7020   /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
7021   {
7022     { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
7023   },
7024
7025   /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
7026   {
7027     { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 },
7028   },
7029
7030   /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
7031   {
7032     { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 },
7033   },
7034
7035   /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
7036   {
7037     { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 },
7038   },
7039
7040   /* VEX_LEN_0F38DB */
7041   {
7042     { "vaesimc",        { XM, EXx }, PREFIX_DATA },
7043   },
7044
7045   /* VEX_LEN_0F38F2 */
7046   {
7047     { "andnS",          { Gdq, VexGdq, Edq }, PREFIX_OPCODE },
7048   },
7049
7050   /* VEX_LEN_0F38F3_R_1 */
7051   {
7052     { "blsrS",          { VexGdq, Edq }, PREFIX_OPCODE },
7053   },
7054
7055   /* VEX_LEN_0F38F3_R_2 */
7056   {
7057     { "blsmskS",        { VexGdq, Edq }, PREFIX_OPCODE },
7058   },
7059
7060   /* VEX_LEN_0F38F3_R_3 */
7061   {
7062     { "blsiS",          { VexGdq, Edq }, PREFIX_OPCODE },
7063   },
7064
7065   /* VEX_LEN_0F38F5_P_0 */
7066   {
7067     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
7068   },
7069
7070   /* VEX_LEN_0F38F5_P_1 */
7071   {
7072     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
7073   },
7074
7075   /* VEX_LEN_0F38F5_P_3 */
7076   {
7077     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
7078   },
7079
7080   /* VEX_LEN_0F38F6_P_3 */
7081   {
7082     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
7083   },
7084
7085   /* VEX_LEN_0F38F7_P_0 */
7086   {
7087     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
7088   },
7089
7090   /* VEX_LEN_0F38F7_P_1 */
7091   {
7092     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
7093   },
7094
7095   /* VEX_LEN_0F38F7_P_2 */
7096   {
7097     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
7098   },
7099
7100   /* VEX_LEN_0F38F7_P_3 */
7101   {
7102     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
7103   },
7104
7105   /* VEX_LEN_0F3A00 */
7106   {
7107     { Bad_Opcode },
7108     { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
7109   },
7110
7111   /* VEX_LEN_0F3A01 */
7112   {
7113     { Bad_Opcode },
7114     { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
7115   },
7116
7117   /* VEX_LEN_0F3A06 */
7118   {
7119     { Bad_Opcode },
7120     { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
7121   },
7122
7123   /* VEX_LEN_0F3A14 */
7124   {
7125     { "vpextrb",        { Edqb, XM, Ib }, PREFIX_DATA },
7126   },
7127
7128   /* VEX_LEN_0F3A15 */
7129   {
7130     { "vpextrw",        { Edqw, XM, Ib }, PREFIX_DATA },
7131   },
7132
7133   /* VEX_LEN_0F3A16  */
7134   {
7135     { "vpextrK",        { Edq, XM, Ib }, PREFIX_DATA },
7136   },
7137
7138   /* VEX_LEN_0F3A17 */
7139   {
7140     { "vextractps",     { Edqd, XM, Ib }, PREFIX_DATA },
7141   },
7142
7143   /* VEX_LEN_0F3A18 */
7144   {
7145     { Bad_Opcode },
7146     { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
7147   },
7148
7149   /* VEX_LEN_0F3A19 */
7150   {
7151     { Bad_Opcode },
7152     { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
7153   },
7154
7155   /* VEX_LEN_0F3A20 */
7156   {
7157     { "vpinsrb",        { XM, Vex, Edqb, Ib }, PREFIX_DATA },
7158   },
7159
7160   /* VEX_LEN_0F3A21 */
7161   {
7162     { "vinsertps",      { XM, Vex, EXd, Ib }, PREFIX_DATA },
7163   },
7164
7165   /* VEX_LEN_0F3A22 */
7166   {
7167     { "vpinsrK",        { XM, Vex, Edq, Ib }, PREFIX_DATA },
7168   },
7169
7170   /* VEX_LEN_0F3A30 */
7171   {
7172     { MOD_TABLE (MOD_VEX_0F3A30_L_0) },
7173   },
7174
7175   /* VEX_LEN_0F3A31 */
7176   {
7177     { MOD_TABLE (MOD_VEX_0F3A31_L_0) },
7178   },
7179
7180   /* VEX_LEN_0F3A32 */
7181   {
7182     { MOD_TABLE (MOD_VEX_0F3A32_L_0) },
7183   },
7184
7185   /* VEX_LEN_0F3A33 */
7186   {
7187     { MOD_TABLE (MOD_VEX_0F3A33_L_0) },
7188   },
7189
7190   /* VEX_LEN_0F3A38 */
7191   {
7192     { Bad_Opcode },
7193     { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7194   },
7195
7196   /* VEX_LEN_0F3A39 */
7197   {
7198     { Bad_Opcode },
7199     { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7200   },
7201
7202   /* VEX_LEN_0F3A41 */
7203   {
7204     { "vdppd",          { XM, Vex, EXx, Ib }, PREFIX_DATA },
7205   },
7206
7207   /* VEX_LEN_0F3A46 */
7208   {
7209     { Bad_Opcode },
7210     { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7211   },
7212
7213   /* VEX_LEN_0F3A60 */
7214   {
7215     { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7216   },
7217
7218   /* VEX_LEN_0F3A61 */
7219   {
7220     { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7221   },
7222
7223   /* VEX_LEN_0F3A62 */
7224   {
7225     { "vpcmpistrm",     { XM, EXx, Ib }, PREFIX_DATA },
7226   },
7227
7228   /* VEX_LEN_0F3A63 */
7229   {
7230     { "vpcmpistri",     { XM, EXx, Ib }, PREFIX_DATA },
7231   },
7232
7233   /* VEX_LEN_0F3ADF */
7234   {
7235     { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7236   },
7237
7238   /* VEX_LEN_0F3AF0_P_3 */
7239   {
7240     { "rorxS",          { Gdq, Edq, Ib }, 0 },
7241   },
7242
7243   /* VEX_LEN_0FXOP_08_85 */
7244   {
7245     { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
7246   },
7247
7248   /* VEX_LEN_0FXOP_08_86 */
7249   {
7250     { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
7251   },
7252
7253   /* VEX_LEN_0FXOP_08_87 */
7254   {
7255     { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
7256   },
7257
7258   /* VEX_LEN_0FXOP_08_8E */
7259   {
7260     { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
7261   },
7262
7263   /* VEX_LEN_0FXOP_08_8F */
7264   {
7265     { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
7266   },
7267
7268   /* VEX_LEN_0FXOP_08_95 */
7269   {
7270     { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
7271   },
7272
7273   /* VEX_LEN_0FXOP_08_96 */
7274   {
7275     { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
7276   },
7277
7278   /* VEX_LEN_0FXOP_08_97 */
7279   {
7280     { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
7281   },
7282
7283   /* VEX_LEN_0FXOP_08_9E */
7284   {
7285     { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
7286   },
7287
7288   /* VEX_LEN_0FXOP_08_9F */
7289   {
7290     { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
7291   },
7292
7293   /* VEX_LEN_0FXOP_08_A3 */
7294   {
7295     { "vpperm",         { XM, Vex, EXx, XMVexI4 }, 0 },
7296   },
7297
7298   /* VEX_LEN_0FXOP_08_A6 */
7299   {
7300     { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
7301   },
7302
7303   /* VEX_LEN_0FXOP_08_B6 */
7304   {
7305     { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
7306   },
7307
7308   /* VEX_LEN_0FXOP_08_C0 */
7309   {
7310     { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
7311   },
7312
7313   /* VEX_LEN_0FXOP_08_C1 */
7314   {
7315     { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
7316   },
7317
7318   /* VEX_LEN_0FXOP_08_C2 */
7319   {
7320     { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
7321   },
7322
7323   /* VEX_LEN_0FXOP_08_C3 */
7324   {
7325     { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
7326   },
7327
7328   /* VEX_LEN_0FXOP_08_CC */
7329   {
7330     { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
7331   },
7332
7333   /* VEX_LEN_0FXOP_08_CD */
7334   {
7335     { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
7336   },
7337
7338   /* VEX_LEN_0FXOP_08_CE */
7339   {
7340     { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
7341   },
7342
7343   /* VEX_LEN_0FXOP_08_CF */
7344   {
7345     { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
7346   },
7347
7348   /* VEX_LEN_0FXOP_08_EC */
7349   {
7350     { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
7351   },
7352
7353   /* VEX_LEN_0FXOP_08_ED */
7354   {
7355     { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
7356   },
7357
7358   /* VEX_LEN_0FXOP_08_EE */
7359   {
7360     { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
7361   },
7362
7363   /* VEX_LEN_0FXOP_08_EF */
7364   {
7365     { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
7366   },
7367
7368   /* VEX_LEN_0FXOP_09_01 */
7369   {
7370     { REG_TABLE (REG_0FXOP_09_01_L_0) },
7371   },
7372
7373   /* VEX_LEN_0FXOP_09_02 */
7374   {
7375     { REG_TABLE (REG_0FXOP_09_02_L_0) },
7376   },
7377
7378   /* VEX_LEN_0FXOP_09_12_M_1 */
7379   {
7380     { REG_TABLE (REG_0FXOP_09_12_M_1_L_0) },
7381   },
7382
7383   /* VEX_LEN_0FXOP_09_82_W_0 */
7384   {
7385     { "vfrczss",        { XM, EXd }, 0 },
7386   },
7387
7388   /* VEX_LEN_0FXOP_09_83_W_0 */
7389   {
7390     { "vfrczsd",        { XM, EXq }, 0 },
7391   },
7392
7393   /* VEX_LEN_0FXOP_09_90 */
7394   {
7395     { "vprotb",         { XM, EXx, VexW }, 0 },
7396   },
7397
7398   /* VEX_LEN_0FXOP_09_91 */
7399   {
7400     { "vprotw",         { XM, EXx, VexW }, 0 },
7401   },
7402
7403   /* VEX_LEN_0FXOP_09_92 */
7404   {
7405     { "vprotd",         { XM, EXx, VexW }, 0 },
7406   },
7407
7408   /* VEX_LEN_0FXOP_09_93 */
7409   {
7410     { "vprotq",         { XM, EXx, VexW }, 0 },
7411   },
7412
7413   /* VEX_LEN_0FXOP_09_94 */
7414   {
7415     { "vpshlb",         { XM, EXx, VexW }, 0 },
7416   },
7417
7418   /* VEX_LEN_0FXOP_09_95 */
7419   {
7420     { "vpshlw",         { XM, EXx, VexW }, 0 },
7421   },
7422
7423   /* VEX_LEN_0FXOP_09_96 */
7424   {
7425     { "vpshld",         { XM, EXx, VexW }, 0 },
7426   },
7427
7428   /* VEX_LEN_0FXOP_09_97 */
7429   {
7430     { "vpshlq",         { XM, EXx, VexW }, 0 },
7431   },
7432
7433   /* VEX_LEN_0FXOP_09_98 */
7434   {
7435     { "vpshab",         { XM, EXx, VexW }, 0 },
7436   },
7437
7438   /* VEX_LEN_0FXOP_09_99 */
7439   {
7440     { "vpshaw",         { XM, EXx, VexW }, 0 },
7441   },
7442
7443   /* VEX_LEN_0FXOP_09_9A */
7444   {
7445     { "vpshad",         { XM, EXx, VexW }, 0 },
7446   },
7447
7448   /* VEX_LEN_0FXOP_09_9B */
7449   {
7450     { "vpshaq",         { XM, EXx, VexW }, 0 },
7451   },
7452
7453   /* VEX_LEN_0FXOP_09_C1 */
7454   {
7455     { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
7456   },
7457
7458   /* VEX_LEN_0FXOP_09_C2 */
7459   {
7460     { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
7461   },
7462
7463   /* VEX_LEN_0FXOP_09_C3 */
7464   {
7465     { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
7466   },
7467
7468   /* VEX_LEN_0FXOP_09_C6 */
7469   {
7470     { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
7471   },
7472
7473   /* VEX_LEN_0FXOP_09_C7 */
7474   {
7475     { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
7476   },
7477
7478   /* VEX_LEN_0FXOP_09_CB */
7479   {
7480     { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
7481   },
7482
7483   /* VEX_LEN_0FXOP_09_D1 */
7484   {
7485     { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
7486   },
7487
7488   /* VEX_LEN_0FXOP_09_D2 */
7489   {
7490     { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
7491   },
7492
7493   /* VEX_LEN_0FXOP_09_D3 */
7494   {
7495     { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
7496   },
7497
7498   /* VEX_LEN_0FXOP_09_D6 */
7499   {
7500     { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
7501   },
7502
7503   /* VEX_LEN_0FXOP_09_D7 */
7504   {
7505     { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
7506   },
7507
7508   /* VEX_LEN_0FXOP_09_DB */
7509   {
7510     { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
7511   },
7512
7513   /* VEX_LEN_0FXOP_09_E1 */
7514   {
7515     { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
7516   },
7517
7518   /* VEX_LEN_0FXOP_09_E2 */
7519   {
7520     { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
7521   },
7522
7523   /* VEX_LEN_0FXOP_09_E3 */
7524   {
7525     { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
7526   },
7527
7528   /* VEX_LEN_0FXOP_0A_12 */
7529   {
7530     { REG_TABLE (REG_0FXOP_0A_12_L_0) },
7531   },
7532 };
7533
7534 #include "i386-dis-evex-len.h"
7535
7536 static const struct dis386 vex_w_table[][2] = {
7537   {
7538     /* VEX_W_0F41_P_0_LEN_1 */
7539     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
7540     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
7541   },
7542   {
7543     /* VEX_W_0F41_P_2_LEN_1 */
7544     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
7545     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
7546   },
7547   {
7548     /* VEX_W_0F42_P_0_LEN_1 */
7549     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
7550     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
7551   },
7552   {
7553     /* VEX_W_0F42_P_2_LEN_1 */
7554     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
7555     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
7556   },
7557   {
7558     /* VEX_W_0F44_P_0_LEN_0 */
7559     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
7560     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
7561   },
7562   {
7563     /* VEX_W_0F44_P_2_LEN_0 */
7564     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
7565     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
7566   },
7567   {
7568     /* VEX_W_0F45_P_0_LEN_1 */
7569     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
7570     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
7571   },
7572   {
7573     /* VEX_W_0F45_P_2_LEN_1 */
7574     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
7575     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
7576   },
7577   {
7578     /* VEX_W_0F46_P_0_LEN_1 */
7579     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
7580     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
7581   },
7582   {
7583     /* VEX_W_0F46_P_2_LEN_1 */
7584     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
7585     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
7586   },
7587   {
7588     /* VEX_W_0F47_P_0_LEN_1 */
7589     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
7590     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
7591   },
7592   {
7593     /* VEX_W_0F47_P_2_LEN_1 */
7594     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
7595     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
7596   },
7597   {
7598     /* VEX_W_0F4A_P_0_LEN_1 */
7599     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
7600     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
7601   },
7602   {
7603     /* VEX_W_0F4A_P_2_LEN_1 */
7604     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
7605     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
7606   },
7607   {
7608     /* VEX_W_0F4B_P_0_LEN_1 */
7609     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
7610     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
7611   },
7612   {
7613     /* VEX_W_0F4B_P_2_LEN_1 */
7614     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
7615   },
7616   {
7617     /* VEX_W_0F90_P_0_LEN_0 */
7618     { "kmovw",          { MaskG, MaskE }, 0 },
7619     { "kmovq",          { MaskG, MaskE }, 0 },
7620   },
7621   {
7622     /* VEX_W_0F90_P_2_LEN_0 */
7623     { "kmovb",          { MaskG, MaskBDE }, 0 },
7624     { "kmovd",          { MaskG, MaskBDE }, 0 },
7625   },
7626   {
7627     /* VEX_W_0F91_P_0_LEN_0 */
7628     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
7629     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
7630   },
7631   {
7632     /* VEX_W_0F91_P_2_LEN_0 */
7633     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
7634     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
7635   },
7636   {
7637     /* VEX_W_0F92_P_0_LEN_0 */
7638     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
7639   },
7640   {
7641     /* VEX_W_0F92_P_2_LEN_0 */
7642     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
7643   },
7644   {
7645     /* VEX_W_0F93_P_0_LEN_0 */
7646     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
7647   },
7648   {
7649     /* VEX_W_0F93_P_2_LEN_0 */
7650     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
7651   },
7652   {
7653     /* VEX_W_0F98_P_0_LEN_0 */
7654     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
7655     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
7656   },
7657   {
7658     /* VEX_W_0F98_P_2_LEN_0 */
7659     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
7660     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
7661   },
7662   {
7663     /* VEX_W_0F99_P_0_LEN_0 */
7664     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
7665     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
7666   },
7667   {
7668     /* VEX_W_0F99_P_2_LEN_0 */
7669     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
7670     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
7671   },
7672   {
7673     /* VEX_W_0F380C  */
7674     { "vpermilps",      { XM, Vex, EXx }, PREFIX_DATA },
7675   },
7676   {
7677     /* VEX_W_0F380D  */
7678     { "vpermilpd",      { XM, Vex, EXx }, PREFIX_DATA },
7679   },
7680   {
7681     /* VEX_W_0F380E  */
7682     { "vtestps",        { XM, EXx }, PREFIX_DATA },
7683   },
7684   {
7685     /* VEX_W_0F380F  */
7686     { "vtestpd",        { XM, EXx }, PREFIX_DATA },
7687   },
7688   {
7689     /* VEX_W_0F3813 */
7690     { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
7691   },
7692   {
7693     /* VEX_W_0F3816_L_1  */
7694     { "vpermps",        { XM, Vex, EXx }, PREFIX_DATA },
7695   },
7696   {
7697     /* VEX_W_0F3818 */
7698     { "vbroadcastss",   { XM, EXxmm_md }, PREFIX_DATA },
7699   },
7700   {
7701     /* VEX_W_0F3819_L_1 */
7702     { "vbroadcastsd",   { XM, EXxmm_mq }, PREFIX_DATA },
7703   },
7704   {
7705     /* VEX_W_0F381A_M_0_L_1 */
7706     { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
7707   },
7708   {
7709     /* VEX_W_0F382C_M_0 */
7710     { "vmaskmovps",     { XM, Vex, Mx }, PREFIX_DATA },
7711   },
7712   {
7713     /* VEX_W_0F382D_M_0 */
7714     { "vmaskmovpd",     { XM, Vex, Mx }, PREFIX_DATA },
7715   },
7716   {
7717     /* VEX_W_0F382E_M_0 */
7718     { "vmaskmovps",     { Mx, Vex, XM }, PREFIX_DATA },
7719   },
7720   {
7721     /* VEX_W_0F382F_M_0 */
7722     { "vmaskmovpd",     { Mx, Vex, XM }, PREFIX_DATA },
7723   },
7724   {
7725     /* VEX_W_0F3836  */
7726     { "vpermd",         { XM, Vex, EXx }, PREFIX_DATA },
7727   },
7728   {
7729     /* VEX_W_0F3846 */
7730     { "vpsravd",        { XM, Vex, EXx }, PREFIX_DATA },
7731   },
7732   {
7733     /* VEX_W_0F3849_X86_64_P_0 */
7734     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) },
7735   },
7736   {
7737     /* VEX_W_0F3849_X86_64_P_2 */
7738     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) },
7739   },
7740   {
7741     /* VEX_W_0F3849_X86_64_P_3 */
7742     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) },
7743   },
7744   {
7745     /* VEX_W_0F384B_X86_64_P_1 */
7746     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) },
7747   },
7748   {
7749     /* VEX_W_0F384B_X86_64_P_2 */
7750     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) },
7751   },
7752   {
7753     /* VEX_W_0F384B_X86_64_P_3 */
7754     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) },
7755   },
7756   {
7757     /* VEX_W_0F3858 */
7758     { "vpbroadcastd", { XM, EXxmm_md }, PREFIX_DATA },
7759   },
7760   {
7761     /* VEX_W_0F3859 */
7762     { "vpbroadcastq",   { XM, EXxmm_mq }, PREFIX_DATA },
7763   },
7764   {
7765     /* VEX_W_0F385A_M_0_L_0 */
7766     { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
7767   },
7768   {
7769     /* VEX_W_0F385C_X86_64_P_1 */
7770     { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) },
7771   },
7772   {
7773     /* VEX_W_0F385E_X86_64_P_0 */
7774     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) },
7775   },
7776   {
7777     /* VEX_W_0F385E_X86_64_P_1 */
7778     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) },
7779   },
7780   {
7781     /* VEX_W_0F385E_X86_64_P_2 */
7782     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) },
7783   },
7784   {
7785     /* VEX_W_0F385E_X86_64_P_3 */
7786     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) },
7787   },
7788   {
7789     /* VEX_W_0F3878 */
7790     { "vpbroadcastb",   { XM, EXxmm_mb }, PREFIX_DATA },
7791   },
7792   {
7793     /* VEX_W_0F3879 */
7794     { "vpbroadcastw",   { XM, EXxmm_mw }, PREFIX_DATA },
7795   },
7796   {
7797     /* VEX_W_0F38CF */
7798     { "vgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
7799   },
7800   {
7801     /* VEX_W_0F3A00_L_1 */
7802     { Bad_Opcode },
7803     { "vpermq",         { XM, EXx, Ib }, PREFIX_DATA },
7804   },
7805   {
7806     /* VEX_W_0F3A01_L_1 */
7807     { Bad_Opcode },
7808     { "vpermpd",        { XM, EXx, Ib }, PREFIX_DATA },
7809   },
7810   {
7811     /* VEX_W_0F3A02 */
7812     { "vpblendd",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
7813   },
7814   {
7815     /* VEX_W_0F3A04 */
7816     { "vpermilps",      { XM, EXx, Ib }, PREFIX_DATA },
7817   },
7818   {
7819     /* VEX_W_0F3A05 */
7820     { "vpermilpd",      { XM, EXx, Ib }, PREFIX_DATA },
7821   },
7822   {
7823     /* VEX_W_0F3A06_L_1 */
7824     { "vperm2f128",     { XM, Vex, EXx, Ib }, PREFIX_DATA },
7825   },
7826   {
7827     /* VEX_W_0F3A18_L_1 */
7828     { "vinsertf128",    { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7829   },
7830   {
7831     /* VEX_W_0F3A19_L_1 */
7832     { "vextractf128",   { EXxmm, XM, Ib }, PREFIX_DATA },
7833   },
7834   {
7835     /* VEX_W_0F3A1D */
7836     { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
7837   },
7838   {
7839     /* VEX_W_0F3A38_L_1 */
7840     { "vinserti128",    { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7841   },
7842   {
7843     /* VEX_W_0F3A39_L_1 */
7844     { "vextracti128",   { EXxmm, XM, Ib }, PREFIX_DATA },
7845   },
7846   {
7847     /* VEX_W_0F3A46_L_1 */
7848     { "vperm2i128",     { XM, Vex, EXx, Ib }, PREFIX_DATA },
7849   },
7850   {
7851     /* VEX_W_0F3A4A */
7852     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7853   },
7854   {
7855     /* VEX_W_0F3A4B */
7856     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7857   },
7858   {
7859     /* VEX_W_0F3A4C */
7860     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7861   },
7862   {
7863     /* VEX_W_0F3ACE */
7864     { Bad_Opcode },
7865     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7866   },
7867   {
7868     /* VEX_W_0F3ACF */
7869     { Bad_Opcode },
7870     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, PREFIX_DATA },
7871   },
7872   /* VEX_W_0FXOP_08_85_L_0 */
7873   {
7874     { "vpmacssww",      { XM, Vex, EXx, XMVexI4 }, 0 },
7875   },
7876   /* VEX_W_0FXOP_08_86_L_0 */
7877   {
7878     { "vpmacsswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7879   },
7880   /* VEX_W_0FXOP_08_87_L_0 */
7881   {
7882     { "vpmacssdql",     { XM, Vex, EXx, XMVexI4 }, 0 },
7883   },
7884   /* VEX_W_0FXOP_08_8E_L_0 */
7885   {
7886     { "vpmacssdd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7887   },
7888   /* VEX_W_0FXOP_08_8F_L_0 */
7889   {
7890     { "vpmacssdqh",     { XM, Vex, EXx, XMVexI4 }, 0 },
7891   },
7892   /* VEX_W_0FXOP_08_95_L_0 */
7893   {
7894     { "vpmacsww",       { XM, Vex, EXx, XMVexI4 }, 0 },
7895   },
7896   /* VEX_W_0FXOP_08_96_L_0 */
7897   {
7898     { "vpmacswd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7899   },
7900   /* VEX_W_0FXOP_08_97_L_0 */
7901   {
7902     { "vpmacsdql",      { XM, Vex, EXx, XMVexI4 }, 0 },
7903   },
7904   /* VEX_W_0FXOP_08_9E_L_0 */
7905   {
7906     { "vpmacsdd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7907   },
7908   /* VEX_W_0FXOP_08_9F_L_0 */
7909   {
7910     { "vpmacsdqh",      { XM, Vex, EXx, XMVexI4 }, 0 },
7911   },
7912   /* VEX_W_0FXOP_08_A6_L_0 */
7913   {
7914     { "vpmadcsswd",     { XM, Vex, EXx, XMVexI4 }, 0 },
7915   },
7916   /* VEX_W_0FXOP_08_B6_L_0 */
7917   {
7918     { "vpmadcswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7919   },
7920   /* VEX_W_0FXOP_08_C0_L_0 */
7921   {
7922     { "vprotb",         { XM, EXx, Ib }, 0 },
7923   },
7924   /* VEX_W_0FXOP_08_C1_L_0 */
7925   {
7926     { "vprotw",         { XM, EXx, Ib }, 0 },
7927   },
7928   /* VEX_W_0FXOP_08_C2_L_0 */
7929   {
7930     { "vprotd",         { XM, EXx, Ib }, 0 },
7931   },
7932   /* VEX_W_0FXOP_08_C3_L_0 */
7933   {
7934     { "vprotq",         { XM, EXx, Ib }, 0 },
7935   },
7936   /* VEX_W_0FXOP_08_CC_L_0 */
7937   {
7938      { "vpcomb",        { XM, Vex, EXx, VPCOM }, 0 },
7939   },
7940   /* VEX_W_0FXOP_08_CD_L_0 */
7941   {
7942      { "vpcomw",        { XM, Vex, EXx, VPCOM }, 0 },
7943   },
7944   /* VEX_W_0FXOP_08_CE_L_0 */
7945   {
7946      { "vpcomd",        { XM, Vex, EXx, VPCOM }, 0 },
7947   },
7948   /* VEX_W_0FXOP_08_CF_L_0 */
7949   {
7950      { "vpcomq",        { XM, Vex, EXx, VPCOM }, 0 },
7951   },
7952   /* VEX_W_0FXOP_08_EC_L_0 */
7953   {
7954      { "vpcomub",       { XM, Vex, EXx, VPCOM }, 0 },
7955   },
7956   /* VEX_W_0FXOP_08_ED_L_0 */
7957   {
7958      { "vpcomuw",       { XM, Vex, EXx, VPCOM }, 0 },
7959   },
7960   /* VEX_W_0FXOP_08_EE_L_0 */
7961   {
7962      { "vpcomud",       { XM, Vex, EXx, VPCOM }, 0 },
7963   },
7964   /* VEX_W_0FXOP_08_EF_L_0 */
7965   {
7966      { "vpcomuq",       { XM, Vex, EXx, VPCOM }, 0 },
7967   },
7968   /* VEX_W_0FXOP_09_80 */
7969   {
7970     { "vfrczps",        { XM, EXx }, 0 },
7971   },
7972   /* VEX_W_0FXOP_09_81 */
7973   {
7974     { "vfrczpd",        { XM, EXx }, 0 },
7975   },
7976   /* VEX_W_0FXOP_09_82 */
7977   {
7978     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
7979   },
7980   /* VEX_W_0FXOP_09_83 */
7981   {
7982     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
7983   },
7984   /* VEX_W_0FXOP_09_C1_L_0 */
7985   {
7986     { "vphaddbw",       { XM, EXxmm }, 0 },
7987   },
7988   /* VEX_W_0FXOP_09_C2_L_0 */
7989   {
7990     { "vphaddbd",       { XM, EXxmm }, 0 },
7991   },
7992   /* VEX_W_0FXOP_09_C3_L_0 */
7993   {
7994     { "vphaddbq",       { XM, EXxmm }, 0 },
7995   },
7996   /* VEX_W_0FXOP_09_C6_L_0 */
7997   {
7998     { "vphaddwd",       { XM, EXxmm }, 0 },
7999   },
8000   /* VEX_W_0FXOP_09_C7_L_0 */
8001   {
8002     { "vphaddwq",       { XM, EXxmm }, 0 },
8003   },
8004   /* VEX_W_0FXOP_09_CB_L_0 */
8005   {
8006     { "vphadddq",       { XM, EXxmm }, 0 },
8007   },
8008   /* VEX_W_0FXOP_09_D1_L_0 */
8009   {
8010     { "vphaddubw",      { XM, EXxmm }, 0 },
8011   },
8012   /* VEX_W_0FXOP_09_D2_L_0 */
8013   {
8014     { "vphaddubd",      { XM, EXxmm }, 0 },
8015   },
8016   /* VEX_W_0FXOP_09_D3_L_0 */
8017   {
8018     { "vphaddubq",      { XM, EXxmm }, 0 },
8019   },
8020   /* VEX_W_0FXOP_09_D6_L_0 */
8021   {
8022     { "vphadduwd",      { XM, EXxmm }, 0 },
8023   },
8024   /* VEX_W_0FXOP_09_D7_L_0 */
8025   {
8026     { "vphadduwq",      { XM, EXxmm }, 0 },
8027   },
8028   /* VEX_W_0FXOP_09_DB_L_0 */
8029   {
8030     { "vphaddudq",      { XM, EXxmm }, 0 },
8031   },
8032   /* VEX_W_0FXOP_09_E1_L_0 */
8033   {
8034     { "vphsubbw",       { XM, EXxmm }, 0 },
8035   },
8036   /* VEX_W_0FXOP_09_E2_L_0 */
8037   {
8038     { "vphsubwd",       { XM, EXxmm }, 0 },
8039   },
8040   /* VEX_W_0FXOP_09_E3_L_0 */
8041   {
8042     { "vphsubdq",       { XM, EXxmm }, 0 },
8043   },
8044
8045 #include "i386-dis-evex-w.h"
8046 };
8047
8048 static const struct dis386 mod_table[][2] = {
8049   {
8050     /* MOD_8D */
8051     { "leaS",           { Gv, M }, 0 },
8052   },
8053   {
8054     /* MOD_C6_REG_7 */
8055     { Bad_Opcode },
8056     { RM_TABLE (RM_C6_REG_7) },
8057   },
8058   {
8059     /* MOD_C7_REG_7 */
8060     { Bad_Opcode },
8061     { RM_TABLE (RM_C7_REG_7) },
8062   },
8063   {
8064     /* MOD_FF_REG_3 */
8065     { "{l|}call^", { indirEp }, 0 },
8066   },
8067   {
8068     /* MOD_FF_REG_5 */
8069     { "{l|}jmp^", { indirEp }, 0 },
8070   },
8071   {
8072     /* MOD_0F01_REG_0 */
8073     { X86_64_TABLE (X86_64_0F01_REG_0) },
8074     { RM_TABLE (RM_0F01_REG_0) },
8075   },
8076   {
8077     /* MOD_0F01_REG_1 */
8078     { X86_64_TABLE (X86_64_0F01_REG_1) },
8079     { RM_TABLE (RM_0F01_REG_1) },
8080   },
8081   {
8082     /* MOD_0F01_REG_2 */
8083     { X86_64_TABLE (X86_64_0F01_REG_2) },
8084     { RM_TABLE (RM_0F01_REG_2) },
8085   },
8086   {
8087     /* MOD_0F01_REG_3 */
8088     { X86_64_TABLE (X86_64_0F01_REG_3) },
8089     { RM_TABLE (RM_0F01_REG_3) },
8090   },
8091   {
8092     /* MOD_0F01_REG_5 */
8093     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
8094     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
8095   },
8096   {
8097     /* MOD_0F01_REG_7 */
8098     { "invlpg",         { Mb }, 0 },
8099     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
8100   },
8101   {
8102     /* MOD_0F12_PREFIX_0 */
8103     { "movlpX",         { XM, EXq }, 0 },
8104     { "movhlps",        { XM, EXq }, 0 },
8105   },
8106   {
8107     /* MOD_0F12_PREFIX_2 */
8108     { "movlpX", { XM, EXq }, 0 },
8109   },
8110   {
8111     /* MOD_0F13 */
8112     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
8113   },
8114   {
8115     /* MOD_0F16_PREFIX_0 */
8116     { "movhpX",         { XM, EXq }, 0 },
8117     { "movlhps",        { XM, EXq }, 0 },
8118   },
8119   {
8120     /* MOD_0F16_PREFIX_2 */
8121     { "movhpX", { XM, EXq }, 0 },
8122   },
8123   {
8124     /* MOD_0F17 */
8125     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
8126   },
8127   {
8128     /* MOD_0F18_REG_0 */
8129     { "prefetchnta",    { Mb }, 0 },
8130   },
8131   {
8132     /* MOD_0F18_REG_1 */
8133     { "prefetcht0",     { Mb }, 0 },
8134   },
8135   {
8136     /* MOD_0F18_REG_2 */
8137     { "prefetcht1",     { Mb }, 0 },
8138   },
8139   {
8140     /* MOD_0F18_REG_3 */
8141     { "prefetcht2",     { Mb }, 0 },
8142   },
8143   {
8144     /* MOD_0F18_REG_4 */
8145     { "nop/reserved",   { Mb }, 0 },
8146   },
8147   {
8148     /* MOD_0F18_REG_5 */
8149     { "nop/reserved",   { Mb }, 0 },
8150   },
8151   {
8152     /* MOD_0F18_REG_6 */
8153     { "nop/reserved",   { Mb }, 0 },
8154   },
8155   {
8156     /* MOD_0F18_REG_7 */
8157     { "nop/reserved",   { Mb }, 0 },
8158   },
8159   {
8160     /* MOD_0F1A_PREFIX_0 */
8161     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
8162     { "nopQ",           { Ev }, 0 },
8163   },
8164   {
8165     /* MOD_0F1B_PREFIX_0 */
8166     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
8167     { "nopQ",           { Ev }, 0 },
8168   },
8169   {
8170     /* MOD_0F1B_PREFIX_1 */
8171     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
8172     { "nopQ",           { Ev }, 0 },
8173   },
8174   {
8175     /* MOD_0F1C_PREFIX_0 */
8176     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
8177     { "nopQ",           { Ev }, 0 },
8178   },
8179   {
8180     /* MOD_0F1E_PREFIX_1 */
8181     { "nopQ",           { Ev }, 0 },
8182     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
8183   },
8184   {
8185     /* MOD_0F2B_PREFIX_0 */
8186     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
8187   },
8188   {
8189     /* MOD_0F2B_PREFIX_1 */
8190     {"movntss",         { Md, XM }, PREFIX_OPCODE },
8191   },
8192   {
8193     /* MOD_0F2B_PREFIX_2 */
8194     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
8195   },
8196   {
8197     /* MOD_0F2B_PREFIX_3 */
8198     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
8199   },
8200   {
8201     /* MOD_0F50 */
8202     { Bad_Opcode },
8203     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
8204   },
8205   {
8206     /* MOD_0F71_REG_2 */
8207     { Bad_Opcode },
8208     { "psrlw",          { MS, Ib }, PREFIX_OPCODE },
8209   },
8210   {
8211     /* MOD_0F71_REG_4 */
8212     { Bad_Opcode },
8213     { "psraw",          { MS, Ib }, PREFIX_OPCODE },
8214   },
8215   {
8216     /* MOD_0F71_REG_6 */
8217     { Bad_Opcode },
8218     { "psllw",          { MS, Ib }, PREFIX_OPCODE },
8219   },
8220   {
8221     /* MOD_0F72_REG_2 */
8222     { Bad_Opcode },
8223     { "psrld",          { MS, Ib }, PREFIX_OPCODE },
8224   },
8225   {
8226     /* MOD_0F72_REG_4 */
8227     { Bad_Opcode },
8228     { "psrad",          { MS, Ib }, PREFIX_OPCODE },
8229   },
8230   {
8231     /* MOD_0F72_REG_6 */
8232     { Bad_Opcode },
8233     { "pslld",          { MS, Ib }, PREFIX_OPCODE },
8234   },
8235   {
8236     /* MOD_0F73_REG_2 */
8237     { Bad_Opcode },
8238     { "psrlq",          { MS, Ib }, PREFIX_OPCODE },
8239   },
8240   {
8241     /* MOD_0F73_REG_3 */
8242     { Bad_Opcode },
8243     { "psrldq",         { XS, Ib }, PREFIX_DATA },
8244   },
8245   {
8246     /* MOD_0F73_REG_6 */
8247     { Bad_Opcode },
8248     { "psllq",          { MS, Ib }, PREFIX_OPCODE },
8249   },
8250   {
8251     /* MOD_0F73_REG_7 */
8252     { Bad_Opcode },
8253     { "pslldq",         { XS, Ib }, PREFIX_DATA },
8254   },
8255   {
8256     /* MOD_0FAE_REG_0 */
8257     { "fxsave",         { FXSAVE }, 0 },
8258     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8259   },
8260   {
8261     /* MOD_0FAE_REG_1 */
8262     { "fxrstor",        { FXSAVE }, 0 },
8263     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8264   },
8265   {
8266     /* MOD_0FAE_REG_2 */
8267     { "ldmxcsr",        { Md }, 0 },
8268     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8269   },
8270   {
8271     /* MOD_0FAE_REG_3 */
8272     { "stmxcsr",        { Md }, 0 },
8273     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8274   },
8275   {
8276     /* MOD_0FAE_REG_4 */
8277     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8278     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8279   },
8280   {
8281     /* MOD_0FAE_REG_5 */
8282     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
8283     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8284   },
8285   {
8286     /* MOD_0FAE_REG_6 */
8287     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8288     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8289   },
8290   {
8291     /* MOD_0FAE_REG_7 */
8292     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8293     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8294   },
8295   {
8296     /* MOD_0FB2 */
8297     { "lssS",           { Gv, Mp }, 0 },
8298   },
8299   {
8300     /* MOD_0FB4 */
8301     { "lfsS",           { Gv, Mp }, 0 },
8302   },
8303   {
8304     /* MOD_0FB5 */
8305     { "lgsS",           { Gv, Mp }, 0 },
8306   },
8307   {
8308     /* MOD_0FC3 */
8309     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
8310   },
8311   {
8312     /* MOD_0FC7_REG_3 */
8313     { "xrstors",        { FXSAVE }, 0 },
8314   },
8315   {
8316     /* MOD_0FC7_REG_4 */
8317     { "xsavec",         { FXSAVE }, 0 },
8318   },
8319   {
8320     /* MOD_0FC7_REG_5 */
8321     { "xsaves",         { FXSAVE }, 0 },
8322   },
8323   {
8324     /* MOD_0FC7_REG_6 */
8325     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8326     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8327   },
8328   {
8329     /* MOD_0FC7_REG_7 */
8330     { "vmptrst",        { Mq }, 0 },
8331     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8332   },
8333   {
8334     /* MOD_0FD7 */
8335     { Bad_Opcode },
8336     { "pmovmskb",       { Gdq, MS }, 0 },
8337   },
8338   {
8339     /* MOD_0FE7_PREFIX_2 */
8340     { "movntdq",        { Mx, XM }, 0 },
8341   },
8342   {
8343     /* MOD_0FF0_PREFIX_3 */
8344     { "lddqu",          { XM, M }, 0 },
8345   },
8346   {
8347     /* MOD_0F382A */
8348     { "movntdqa",       { XM, Mx }, PREFIX_DATA },
8349   },
8350   {
8351     /* MOD_0F38DC_PREFIX_1 */
8352     { "aesenc128kl",    { XM, M }, 0 },
8353     { "loadiwkey",      { XM, EXx }, 0 },
8354   },
8355   {
8356     /* MOD_0F38DD_PREFIX_1 */
8357     { "aesdec128kl",    { XM, M }, 0 },
8358   },
8359   {
8360     /* MOD_0F38DE_PREFIX_1 */
8361     { "aesenc256kl",    { XM, M }, 0 },
8362   },
8363   {
8364     /* MOD_0F38DF_PREFIX_1 */
8365     { "aesdec256kl",    { XM, M }, 0 },
8366   },
8367   {
8368     /* MOD_0F38F5 */
8369     { "wrussK",         { M, Gdq }, PREFIX_DATA },
8370   },
8371   {
8372     /* MOD_0F38F6_PREFIX_0 */
8373     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
8374   },
8375   {
8376     /* MOD_0F38F8_PREFIX_1 */
8377     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
8378   },
8379   {
8380     /* MOD_0F38F8_PREFIX_2 */
8381     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
8382   },
8383   {
8384     /* MOD_0F38F8_PREFIX_3 */
8385     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
8386   },
8387   {
8388     /* MOD_0F38F9 */
8389     { "movdiri",        { Edq, Gdq }, PREFIX_OPCODE },
8390   },
8391   {
8392     /* MOD_0F38FA_PREFIX_1 */
8393     { Bad_Opcode },
8394     { "encodekey128", { Gd, Ed }, 0 },
8395   },
8396   {
8397     /* MOD_0F38FB_PREFIX_1 */
8398     { Bad_Opcode },
8399     { "encodekey256", { Gd, Ed }, 0 },
8400   },
8401   {
8402     /* MOD_62_32BIT */
8403     { "bound{S|}",      { Gv, Ma }, 0 },
8404     { EVEX_TABLE (EVEX_0F) },
8405   },
8406   {
8407     /* MOD_C4_32BIT */
8408     { "lesS",           { Gv, Mp }, 0 },
8409     { VEX_C4_TABLE (VEX_0F) },
8410   },
8411   {
8412     /* MOD_C5_32BIT */
8413     { "ldsS",           { Gv, Mp }, 0 },
8414     { VEX_C5_TABLE (VEX_0F) },
8415   },
8416   {
8417     /* MOD_VEX_0F12_PREFIX_0 */
8418     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
8419     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
8420   },
8421   {
8422     /* MOD_VEX_0F12_PREFIX_2 */
8423     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
8424   },
8425   {
8426     /* MOD_VEX_0F13 */
8427     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
8428   },
8429   {
8430     /* MOD_VEX_0F16_PREFIX_0 */
8431     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
8432     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
8433   },
8434   {
8435     /* MOD_VEX_0F16_PREFIX_2 */
8436     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
8437   },
8438   {
8439     /* MOD_VEX_0F17 */
8440     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
8441   },
8442   {
8443     /* MOD_VEX_0F2B */
8444     { "vmovntpX",       { Mx, XM }, PREFIX_OPCODE },
8445   },
8446   {
8447     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
8448     { Bad_Opcode },
8449     { "kandw",          { MaskG, MaskVex, MaskE }, 0 },
8450   },
8451   {
8452     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
8453     { Bad_Opcode },
8454     { "kandq",          { MaskG, MaskVex, MaskE }, 0 },
8455   },
8456   {
8457     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
8458     { Bad_Opcode },
8459     { "kandb",          { MaskG, MaskVex, MaskE }, 0 },
8460   },
8461   {
8462     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
8463     { Bad_Opcode },
8464     { "kandd",          { MaskG, MaskVex, MaskE }, 0 },
8465   },
8466   {
8467     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
8468     { Bad_Opcode },
8469     { "kandnw",         { MaskG, MaskVex, MaskE }, 0 },
8470   },
8471   {
8472     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
8473     { Bad_Opcode },
8474     { "kandnq",         { MaskG, MaskVex, MaskE }, 0 },
8475   },
8476   {
8477     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
8478     { Bad_Opcode },
8479     { "kandnb",         { MaskG, MaskVex, MaskE }, 0 },
8480   },
8481   {
8482     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
8483     { Bad_Opcode },
8484     { "kandnd",         { MaskG, MaskVex, MaskE }, 0 },
8485   },
8486   {
8487     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
8488     { Bad_Opcode },
8489     { "knotw",          { MaskG, MaskE }, 0 },
8490   },
8491   {
8492     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
8493     { Bad_Opcode },
8494     { "knotq",          { MaskG, MaskE }, 0 },
8495   },
8496   {
8497     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
8498     { Bad_Opcode },
8499     { "knotb",          { MaskG, MaskE }, 0 },
8500   },
8501   {
8502     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
8503     { Bad_Opcode },
8504     { "knotd",          { MaskG, MaskE }, 0 },
8505   },
8506   {
8507     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
8508     { Bad_Opcode },
8509     { "korw",       { MaskG, MaskVex, MaskE }, 0 },
8510   },
8511   {
8512     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
8513     { Bad_Opcode },
8514     { "korq",       { MaskG, MaskVex, MaskE }, 0 },
8515   },
8516   {
8517     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
8518     { Bad_Opcode },
8519     { "korb",       { MaskG, MaskVex, MaskE }, 0 },
8520   },
8521   {
8522     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
8523     { Bad_Opcode },
8524     { "kord",       { MaskG, MaskVex, MaskE }, 0 },
8525   },
8526  {
8527     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
8528     { Bad_Opcode },
8529     { "kxnorw",     { MaskG, MaskVex, MaskE }, 0 },
8530   },
8531   {
8532     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
8533     { Bad_Opcode },
8534     { "kxnorq",     { MaskG, MaskVex, MaskE }, 0 },
8535   },
8536   {
8537     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
8538     { Bad_Opcode },
8539     { "kxnorb",     { MaskG, MaskVex, MaskE }, 0 },
8540   },
8541   {
8542     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
8543     { Bad_Opcode },
8544     { "kxnord",     { MaskG, MaskVex, MaskE }, 0 },
8545   },
8546   {
8547     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
8548     { Bad_Opcode },
8549     { "kxorw",      { MaskG, MaskVex, MaskE }, 0 },
8550   },
8551   {
8552     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
8553     { Bad_Opcode },
8554     { "kxorq",      { MaskG, MaskVex, MaskE }, 0 },
8555   },
8556   {
8557     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
8558     { Bad_Opcode },
8559     { "kxorb",      { MaskG, MaskVex, MaskE }, 0 },
8560   },
8561   {
8562     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
8563     { Bad_Opcode },
8564     { "kxord",      { MaskG, MaskVex, MaskE }, 0 },
8565   },
8566   {
8567     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
8568     { Bad_Opcode },
8569     { "kaddw",          { MaskG, MaskVex, MaskE }, 0 },
8570   },
8571   {
8572     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
8573     { Bad_Opcode },
8574     { "kaddq",          { MaskG, MaskVex, MaskE }, 0 },
8575   },
8576   {
8577     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
8578     { Bad_Opcode },
8579     { "kaddb",          { MaskG, MaskVex, MaskE }, 0 },
8580   },
8581   {
8582     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
8583     { Bad_Opcode },
8584     { "kaddd",          { MaskG, MaskVex, MaskE }, 0 },
8585   },
8586   {
8587     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
8588     { Bad_Opcode },
8589     { "kunpckwd",   { MaskG, MaskVex, MaskE }, 0 },
8590   },
8591   {
8592     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
8593     { Bad_Opcode },
8594     { "kunpckdq",   { MaskG, MaskVex, MaskE }, 0 },
8595   },
8596   {
8597     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
8598     { Bad_Opcode },
8599     { "kunpckbw",   { MaskG, MaskVex, MaskE }, 0 },
8600   },
8601   {
8602     /* MOD_VEX_0F50 */
8603     { Bad_Opcode },
8604     { "vmovmskpX",      { Gdq, XS }, PREFIX_OPCODE },
8605   },
8606   {
8607     /* MOD_VEX_0F71_REG_2 */
8608     { Bad_Opcode },
8609     { "vpsrlw",         { Vex, XS, Ib }, PREFIX_DATA },
8610   },
8611   {
8612     /* MOD_VEX_0F71_REG_4 */
8613     { Bad_Opcode },
8614     { "vpsraw",         { Vex, XS, Ib }, PREFIX_DATA },
8615   },
8616   {
8617     /* MOD_VEX_0F71_REG_6 */
8618     { Bad_Opcode },
8619     { "vpsllw",         { Vex, XS, Ib }, PREFIX_DATA },
8620   },
8621   {
8622     /* MOD_VEX_0F72_REG_2 */
8623     { Bad_Opcode },
8624     { "vpsrld",         { Vex, XS, Ib }, PREFIX_DATA },
8625   },
8626   {
8627     /* MOD_VEX_0F72_REG_4 */
8628     { Bad_Opcode },
8629     { "vpsrad",         { Vex, XS, Ib }, PREFIX_DATA },
8630   },
8631   {
8632     /* MOD_VEX_0F72_REG_6 */
8633     { Bad_Opcode },
8634     { "vpslld",         { Vex, XS, Ib }, PREFIX_DATA },
8635   },
8636   {
8637     /* MOD_VEX_0F73_REG_2 */
8638     { Bad_Opcode },
8639     { "vpsrlq",         { Vex, XS, Ib }, PREFIX_DATA },
8640   },
8641   {
8642     /* MOD_VEX_0F73_REG_3 */
8643     { Bad_Opcode },
8644     { "vpsrldq",        { Vex, XS, Ib }, PREFIX_DATA },
8645   },
8646   {
8647     /* MOD_VEX_0F73_REG_6 */
8648     { Bad_Opcode },
8649     { "vpsllq",         { Vex, XS, Ib }, PREFIX_DATA },
8650   },
8651   {
8652     /* MOD_VEX_0F73_REG_7 */
8653     { Bad_Opcode },
8654     { "vpslldq",        { Vex, XS, Ib }, PREFIX_DATA },
8655   },
8656   {
8657     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
8658     { "kmovw",          { Ew, MaskG }, 0 },
8659     { Bad_Opcode },
8660   },
8661   {
8662     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
8663     { "kmovq",          { Eq, MaskG }, 0 },
8664     { Bad_Opcode },
8665   },
8666   {
8667     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
8668     { "kmovb",          { Eb, MaskG }, 0 },
8669     { Bad_Opcode },
8670   },
8671   {
8672     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
8673     { "kmovd",          { Ed, MaskG }, 0 },
8674     { Bad_Opcode },
8675   },
8676   {
8677     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
8678     { Bad_Opcode },
8679     { "kmovw",          { MaskG, Edq }, 0 },
8680   },
8681   {
8682     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
8683     { Bad_Opcode },
8684     { "kmovb",          { MaskG, Edq }, 0 },
8685   },
8686   {
8687     /* MOD_VEX_0F92_P_3_LEN_0 */
8688     { Bad_Opcode },
8689     { "kmovK",          { MaskG, Edq }, 0 },
8690   },
8691   {
8692     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
8693     { Bad_Opcode },
8694     { "kmovw",          { Gdq, MaskE }, 0 },
8695   },
8696   {
8697     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
8698     { Bad_Opcode },
8699     { "kmovb",          { Gdq, MaskE }, 0 },
8700   },
8701   {
8702     /* MOD_VEX_0F93_P_3_LEN_0 */
8703     { Bad_Opcode },
8704     { "kmovK",          { Gdq, MaskE }, 0 },
8705   },
8706   {
8707     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
8708     { Bad_Opcode },
8709     { "kortestw", { MaskG, MaskE }, 0 },
8710   },
8711   {
8712     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
8713     { Bad_Opcode },
8714     { "kortestq", { MaskG, MaskE }, 0 },
8715   },
8716   {
8717     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
8718     { Bad_Opcode },
8719     { "kortestb", { MaskG, MaskE }, 0 },
8720   },
8721   {
8722     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
8723     { Bad_Opcode },
8724     { "kortestd", { MaskG, MaskE }, 0 },
8725   },
8726   {
8727     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
8728     { Bad_Opcode },
8729     { "ktestw", { MaskG, MaskE }, 0 },
8730   },
8731   {
8732     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
8733     { Bad_Opcode },
8734     { "ktestq", { MaskG, MaskE }, 0 },
8735   },
8736   {
8737     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
8738     { Bad_Opcode },
8739     { "ktestb", { MaskG, MaskE }, 0 },
8740   },
8741   {
8742     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
8743     { Bad_Opcode },
8744     { "ktestd", { MaskG, MaskE }, 0 },
8745   },
8746   {
8747     /* MOD_VEX_0FAE_REG_2 */
8748     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
8749   },
8750   {
8751     /* MOD_VEX_0FAE_REG_3 */
8752     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
8753   },
8754   {
8755     /* MOD_VEX_0FD7 */
8756     { Bad_Opcode },
8757     { "vpmovmskb",      { Gdq, XS }, PREFIX_DATA },
8758   },
8759   {
8760     /* MOD_VEX_0FE7 */
8761     { "vmovntdq",       { Mx, XM }, PREFIX_DATA },
8762   },
8763   {
8764     /* MOD_VEX_0FF0_PREFIX_3 */
8765     { "vlddqu",         { XM, M }, 0 },
8766   },
8767   {
8768     /* MOD_VEX_0F381A */
8769     { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0) },
8770   },
8771   {
8772     /* MOD_VEX_0F382A */
8773     { "vmovntdqa",      { XM, Mx }, PREFIX_DATA },
8774   },
8775   {
8776     /* MOD_VEX_0F382C */
8777     { VEX_W_TABLE (VEX_W_0F382C_M_0) },
8778   },
8779   {
8780     /* MOD_VEX_0F382D */
8781     { VEX_W_TABLE (VEX_W_0F382D_M_0) },
8782   },
8783   {
8784     /* MOD_VEX_0F382E */
8785     { VEX_W_TABLE (VEX_W_0F382E_M_0) },
8786   },
8787   {
8788     /* MOD_VEX_0F382F */
8789     { VEX_W_TABLE (VEX_W_0F382F_M_0) },
8790   },
8791   {
8792     /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
8793     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) },
8794     { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) },
8795   },
8796   {
8797     /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
8798     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) },
8799   },
8800   {
8801     /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
8802     { Bad_Opcode },
8803     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) },
8804   },
8805   {
8806     /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
8807     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) },
8808   },
8809   {
8810     /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
8811     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) },
8812   },
8813   {
8814     /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
8815     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) },
8816   },
8817   {
8818     /* MOD_VEX_0F385A */
8819     { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0) },
8820   },
8821   {
8822     /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
8823     { Bad_Opcode },
8824     { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) },
8825   },
8826   {
8827     /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
8828     { Bad_Opcode },
8829     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) },
8830   },
8831   {
8832     /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
8833     { Bad_Opcode },
8834     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) },
8835   },
8836   {
8837     /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
8838     { Bad_Opcode },
8839     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) },
8840   },
8841   {
8842     /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
8843     { Bad_Opcode },
8844     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) },
8845   },
8846   {
8847     /* MOD_VEX_0F388C */
8848     { "vpmaskmov%DQ",   { XM, Vex, Mx }, PREFIX_DATA },
8849   },
8850   {
8851     /* MOD_VEX_0F388E */
8852     { "vpmaskmov%DQ",   { Mx, Vex, XM }, PREFIX_DATA },
8853   },
8854   {
8855     /* MOD_VEX_0F3A30_L_0 */
8856     { Bad_Opcode },
8857     { "kshiftr%BW",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8858   },
8859   {
8860     /* MOD_VEX_0F3A31_L_0 */
8861     { Bad_Opcode },
8862     { "kshiftr%DQ",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8863   },
8864   {
8865     /* MOD_VEX_0F3A32_L_0 */
8866     { Bad_Opcode },
8867     { "kshiftl%BW",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8868   },
8869   {
8870     /* MOD_VEX_0F3A33_L_0 */
8871     { Bad_Opcode },
8872     { "kshiftl%DQ",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8873   },
8874   {
8875     /* MOD_VEX_0FXOP_09_12 */
8876     { Bad_Opcode },
8877     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
8878   },
8879
8880 #include "i386-dis-evex-mod.h"
8881 };
8882
8883 static const struct dis386 rm_table[][8] = {
8884   {
8885     /* RM_C6_REG_7 */
8886     { "xabort",         { Skip_MODRM, Ib }, 0 },
8887   },
8888   {
8889     /* RM_C7_REG_7 */
8890     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
8891   },
8892   {
8893     /* RM_0F01_REG_0 */
8894     { "enclv",          { Skip_MODRM }, 0 },
8895     { "vmcall",         { Skip_MODRM }, 0 },
8896     { "vmlaunch",       { Skip_MODRM }, 0 },
8897     { "vmresume",       { Skip_MODRM }, 0 },
8898     { "vmxoff",         { Skip_MODRM }, 0 },
8899     { "pconfig",        { Skip_MODRM }, 0 },
8900   },
8901   {
8902     /* RM_0F01_REG_1 */
8903     { "monitor",        { { OP_Monitor, 0 } }, 0 },
8904     { "mwait",          { { OP_Mwait, 0 } }, 0 },
8905     { "clac",           { Skip_MODRM }, 0 },
8906     { "stac",           { Skip_MODRM }, 0 },
8907     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) },
8908     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) },
8909     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) },
8910     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) },
8911   },
8912   {
8913     /* RM_0F01_REG_2 */
8914     { "xgetbv",         { Skip_MODRM }, 0 },
8915     { "xsetbv",         { Skip_MODRM }, 0 },
8916     { Bad_Opcode },
8917     { Bad_Opcode },
8918     { "vmfunc",         { Skip_MODRM }, 0 },
8919     { "xend",           { Skip_MODRM }, 0 },
8920     { "xtest",          { Skip_MODRM }, 0 },
8921     { "enclu",          { Skip_MODRM }, 0 },
8922   },
8923   {
8924     /* RM_0F01_REG_3 */
8925     { "vmrun",          { Skip_MODRM }, 0 },
8926     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
8927     { "vmload",         { Skip_MODRM }, 0 },
8928     { "vmsave",         { Skip_MODRM }, 0 },
8929     { "stgi",           { Skip_MODRM }, 0 },
8930     { "clgi",           { Skip_MODRM }, 0 },
8931     { "skinit",         { Skip_MODRM }, 0 },
8932     { "invlpga",        { Skip_MODRM }, 0 },
8933   },
8934   {
8935     /* RM_0F01_REG_5_MOD_3 */
8936     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
8937     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
8938     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
8939     { Bad_Opcode },
8940     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4) },
8941     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5) },
8942     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6) },
8943     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7) },
8944   },
8945   {
8946     /* RM_0F01_REG_7_MOD_3 */
8947     { "swapgs",         { Skip_MODRM }, 0  },
8948     { "rdtscp",         { Skip_MODRM }, 0  },
8949     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
8950     { "mwaitx",         { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
8951     { "clzero",         { Skip_MODRM }, 0  },
8952     { "rdpru",          { Skip_MODRM }, 0  },
8953   },
8954   {
8955     /* RM_0F1E_P_1_MOD_3_REG_7 */
8956     { "nopQ",           { Ev }, 0 },
8957     { "nopQ",           { Ev }, 0 },
8958     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
8959     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
8960     { "nopQ",           { Ev }, 0 },
8961     { "nopQ",           { Ev }, 0 },
8962     { "nopQ",           { Ev }, 0 },
8963     { "nopQ",           { Ev }, 0 },
8964   },
8965   {
8966     /* RM_0FAE_REG_6_MOD_3 */
8967     { "mfence",         { Skip_MODRM }, 0 },
8968   },
8969   {
8970     /* RM_0FAE_REG_7_MOD_3 */
8971     { "sfence",         { Skip_MODRM }, 0 },
8972
8973   },
8974   {
8975     /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
8976     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) },
8977   },
8978 };
8979
8980 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8981
8982 /* We use the high bit to indicate different name for the same
8983    prefix.  */
8984 #define REP_PREFIX      (0xf3 | 0x100)
8985 #define XACQUIRE_PREFIX (0xf2 | 0x200)
8986 #define XRELEASE_PREFIX (0xf3 | 0x400)
8987 #define BND_PREFIX      (0xf2 | 0x400)
8988 #define NOTRACK_PREFIX  (0x3e | 0x100)
8989
8990 /* Remember if the current op is a jump instruction.  */
8991 static bfd_boolean op_is_jump = FALSE;
8992
8993 static int
8994 ckprefix (void)
8995 {
8996   int newrex, i, length;
8997   rex = 0;
8998   prefixes = 0;
8999   used_prefixes = 0;
9000   rex_used = 0;
9001   last_lock_prefix = -1;
9002   last_repz_prefix = -1;
9003   last_repnz_prefix = -1;
9004   last_data_prefix = -1;
9005   last_addr_prefix = -1;
9006   last_rex_prefix = -1;
9007   last_seg_prefix = -1;
9008   fwait_prefix = -1;
9009   active_seg_prefix = 0;
9010   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
9011     all_prefixes[i] = 0;
9012   i = 0;
9013   length = 0;
9014   /* The maximum instruction length is 15bytes.  */
9015   while (length < MAX_CODE_LENGTH - 1)
9016     {
9017       FETCH_DATA (the_info, codep + 1);
9018       newrex = 0;
9019       switch (*codep)
9020         {
9021         /* REX prefixes family.  */
9022         case 0x40:
9023         case 0x41:
9024         case 0x42:
9025         case 0x43:
9026         case 0x44:
9027         case 0x45:
9028         case 0x46:
9029         case 0x47:
9030         case 0x48:
9031         case 0x49:
9032         case 0x4a:
9033         case 0x4b:
9034         case 0x4c:
9035         case 0x4d:
9036         case 0x4e:
9037         case 0x4f:
9038           if (address_mode == mode_64bit)
9039             newrex = *codep;
9040           else
9041             return 1;
9042           last_rex_prefix = i;
9043           break;
9044         case 0xf3:
9045           prefixes |= PREFIX_REPZ;
9046           last_repz_prefix = i;
9047           break;
9048         case 0xf2:
9049           prefixes |= PREFIX_REPNZ;
9050           last_repnz_prefix = i;
9051           break;
9052         case 0xf0:
9053           prefixes |= PREFIX_LOCK;
9054           last_lock_prefix = i;
9055           break;
9056         case 0x2e:
9057           prefixes |= PREFIX_CS;
9058           last_seg_prefix = i;
9059           active_seg_prefix = PREFIX_CS;
9060           break;
9061         case 0x36:
9062           prefixes |= PREFIX_SS;
9063           last_seg_prefix = i;
9064           active_seg_prefix = PREFIX_SS;
9065           break;
9066         case 0x3e:
9067           prefixes |= PREFIX_DS;
9068           last_seg_prefix = i;
9069           active_seg_prefix = PREFIX_DS;
9070           break;
9071         case 0x26:
9072           prefixes |= PREFIX_ES;
9073           last_seg_prefix = i;
9074           active_seg_prefix = PREFIX_ES;
9075           break;
9076         case 0x64:
9077           prefixes |= PREFIX_FS;
9078           last_seg_prefix = i;
9079           active_seg_prefix = PREFIX_FS;
9080           break;
9081         case 0x65:
9082           prefixes |= PREFIX_GS;
9083           last_seg_prefix = i;
9084           active_seg_prefix = PREFIX_GS;
9085           break;
9086         case 0x66:
9087           prefixes |= PREFIX_DATA;
9088           last_data_prefix = i;
9089           break;
9090         case 0x67:
9091           prefixes |= PREFIX_ADDR;
9092           last_addr_prefix = i;
9093           break;
9094         case FWAIT_OPCODE:
9095           /* fwait is really an instruction.  If there are prefixes
9096              before the fwait, they belong to the fwait, *not* to the
9097              following instruction.  */
9098           fwait_prefix = i;
9099           if (prefixes || rex)
9100             {
9101               prefixes |= PREFIX_FWAIT;
9102               codep++;
9103               /* This ensures that the previous REX prefixes are noticed
9104                  as unused prefixes, as in the return case below.  */
9105               rex_used = rex;
9106               return 1;
9107             }
9108           prefixes = PREFIX_FWAIT;
9109           break;
9110         default:
9111           return 1;
9112         }
9113       /* Rex is ignored when followed by another prefix.  */
9114       if (rex)
9115         {
9116           rex_used = rex;
9117           return 1;
9118         }
9119       if (*codep != FWAIT_OPCODE)
9120         all_prefixes[i++] = *codep;
9121       rex = newrex;
9122       codep++;
9123       length++;
9124     }
9125   return 0;
9126 }
9127
9128 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
9129    prefix byte.  */
9130
9131 static const char *
9132 prefix_name (int pref, int sizeflag)
9133 {
9134   static const char *rexes [16] =
9135     {
9136       "rex",            /* 0x40 */
9137       "rex.B",          /* 0x41 */
9138       "rex.X",          /* 0x42 */
9139       "rex.XB",         /* 0x43 */
9140       "rex.R",          /* 0x44 */
9141       "rex.RB",         /* 0x45 */
9142       "rex.RX",         /* 0x46 */
9143       "rex.RXB",        /* 0x47 */
9144       "rex.W",          /* 0x48 */
9145       "rex.WB",         /* 0x49 */
9146       "rex.WX",         /* 0x4a */
9147       "rex.WXB",        /* 0x4b */
9148       "rex.WR",         /* 0x4c */
9149       "rex.WRB",        /* 0x4d */
9150       "rex.WRX",        /* 0x4e */
9151       "rex.WRXB",       /* 0x4f */
9152     };
9153
9154   switch (pref)
9155     {
9156     /* REX prefixes family.  */
9157     case 0x40:
9158     case 0x41:
9159     case 0x42:
9160     case 0x43:
9161     case 0x44:
9162     case 0x45:
9163     case 0x46:
9164     case 0x47:
9165     case 0x48:
9166     case 0x49:
9167     case 0x4a:
9168     case 0x4b:
9169     case 0x4c:
9170     case 0x4d:
9171     case 0x4e:
9172     case 0x4f:
9173       return rexes [pref - 0x40];
9174     case 0xf3:
9175       return "repz";
9176     case 0xf2:
9177       return "repnz";
9178     case 0xf0:
9179       return "lock";
9180     case 0x2e:
9181       return "cs";
9182     case 0x36:
9183       return "ss";
9184     case 0x3e:
9185       return "ds";
9186     case 0x26:
9187       return "es";
9188     case 0x64:
9189       return "fs";
9190     case 0x65:
9191       return "gs";
9192     case 0x66:
9193       return (sizeflag & DFLAG) ? "data16" : "data32";
9194     case 0x67:
9195       if (address_mode == mode_64bit)
9196         return (sizeflag & AFLAG) ? "addr32" : "addr64";
9197       else
9198         return (sizeflag & AFLAG) ? "addr16" : "addr32";
9199     case FWAIT_OPCODE:
9200       return "fwait";
9201     case REP_PREFIX:
9202       return "rep";
9203     case XACQUIRE_PREFIX:
9204       return "xacquire";
9205     case XRELEASE_PREFIX:
9206       return "xrelease";
9207     case BND_PREFIX:
9208       return "bnd";
9209     case NOTRACK_PREFIX:
9210       return "notrack";
9211     default:
9212       return NULL;
9213     }
9214 }
9215
9216 static char op_out[MAX_OPERANDS][100];
9217 static int op_ad, op_index[MAX_OPERANDS];
9218 static int two_source_ops;
9219 static bfd_vma op_address[MAX_OPERANDS];
9220 static bfd_vma op_riprel[MAX_OPERANDS];
9221 static bfd_vma start_pc;
9222
9223 /*
9224  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
9225  *   (see topic "Redundant prefixes" in the "Differences from 8086"
9226  *   section of the "Virtual 8086 Mode" chapter.)
9227  * 'pc' should be the address of this instruction, it will
9228  *   be used to print the target address if this is a relative jump or call
9229  * The function returns the length of this instruction in bytes.
9230  */
9231
9232 static char intel_syntax;
9233 static char intel_mnemonic = !SYSV386_COMPAT;
9234 static char open_char;
9235 static char close_char;
9236 static char separator_char;
9237 static char scale_char;
9238
9239 enum x86_64_isa
9240 {
9241   amd64 = 1,
9242   intel64
9243 };
9244
9245 static enum x86_64_isa isa64;
9246
9247 /* Here for backwards compatibility.  When gdb stops using
9248    print_insn_i386_att and print_insn_i386_intel these functions can
9249    disappear, and print_insn_i386 be merged into print_insn.  */
9250 int
9251 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
9252 {
9253   intel_syntax = 0;
9254
9255   return print_insn (pc, info);
9256 }
9257
9258 int
9259 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
9260 {
9261   intel_syntax = 1;
9262
9263   return print_insn (pc, info);
9264 }
9265
9266 int
9267 print_insn_i386 (bfd_vma pc, disassemble_info *info)
9268 {
9269   intel_syntax = -1;
9270
9271   return print_insn (pc, info);
9272 }
9273
9274 void
9275 print_i386_disassembler_options (FILE *stream)
9276 {
9277   fprintf (stream, _("\n\
9278 The following i386/x86-64 specific disassembler options are supported for use\n\
9279 with the -M switch (multiple options should be separated by commas):\n"));
9280
9281   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
9282   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
9283   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
9284   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
9285   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
9286   fprintf (stream, _("  att-mnemonic\n"
9287                      "              Display instruction in AT&T mnemonic\n"));
9288   fprintf (stream, _("  intel-mnemonic\n"
9289                      "              Display instruction in Intel mnemonic\n"));
9290   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
9291   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
9292   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
9293   fprintf (stream, _("  data32      Assume 32bit data size\n"));
9294   fprintf (stream, _("  data16      Assume 16bit data size\n"));
9295   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
9296   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
9297   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
9298 }
9299
9300 /* Bad opcode.  */
9301 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
9302
9303 /* Get a pointer to struct dis386 with a valid name.  */
9304
9305 static const struct dis386 *
9306 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
9307 {
9308   int vindex, vex_table_index;
9309
9310   if (dp->name != NULL)
9311     return dp;
9312
9313   switch (dp->op[0].bytemode)
9314     {
9315     case USE_REG_TABLE:
9316       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
9317       break;
9318
9319     case USE_MOD_TABLE:
9320       vindex = modrm.mod == 0x3 ? 1 : 0;
9321       dp = &mod_table[dp->op[1].bytemode][vindex];
9322       break;
9323
9324     case USE_RM_TABLE:
9325       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
9326       break;
9327
9328     case USE_PREFIX_TABLE:
9329       if (need_vex)
9330         {
9331           /* The prefix in VEX is implicit.  */
9332           switch (vex.prefix)
9333             {
9334             case 0:
9335               vindex = 0;
9336               break;
9337             case REPE_PREFIX_OPCODE:
9338               vindex = 1;
9339               break;
9340             case DATA_PREFIX_OPCODE:
9341               vindex = 2;
9342               break;
9343             case REPNE_PREFIX_OPCODE:
9344               vindex = 3;
9345               break;
9346             default:
9347               abort ();
9348               break;
9349             }
9350         }
9351       else
9352         {
9353           int last_prefix = -1;
9354           int prefix = 0;
9355           vindex = 0;
9356           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
9357              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
9358              last one wins.  */
9359           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9360             {
9361               if (last_repz_prefix > last_repnz_prefix)
9362                 {
9363                   vindex = 1;
9364                   prefix = PREFIX_REPZ;
9365                   last_prefix = last_repz_prefix;
9366                 }
9367               else
9368                 {
9369                   vindex = 3;
9370                   prefix = PREFIX_REPNZ;
9371                   last_prefix = last_repnz_prefix;
9372                 }
9373
9374               /* Check if prefix should be ignored.  */
9375               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
9376                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
9377                    & prefix) != 0)
9378                 vindex = 0;
9379             }
9380
9381           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
9382             {
9383               vindex = 2;
9384               prefix = PREFIX_DATA;
9385               last_prefix = last_data_prefix;
9386             }
9387
9388           if (vindex != 0)
9389             {
9390               used_prefixes |= prefix;
9391               all_prefixes[last_prefix] = 0;
9392             }
9393         }
9394       dp = &prefix_table[dp->op[1].bytemode][vindex];
9395       break;
9396
9397     case USE_X86_64_TABLE:
9398       vindex = address_mode == mode_64bit ? 1 : 0;
9399       dp = &x86_64_table[dp->op[1].bytemode][vindex];
9400       break;
9401
9402     case USE_3BYTE_TABLE:
9403       FETCH_DATA (info, codep + 2);
9404       vindex = *codep++;
9405       dp = &three_byte_table[dp->op[1].bytemode][vindex];
9406       end_codep = codep;
9407       modrm.mod = (*codep >> 6) & 3;
9408       modrm.reg = (*codep >> 3) & 7;
9409       modrm.rm = *codep & 7;
9410       break;
9411
9412     case USE_VEX_LEN_TABLE:
9413       if (!need_vex)
9414         abort ();
9415
9416       switch (vex.length)
9417         {
9418         case 128:
9419           vindex = 0;
9420           break;
9421         case 256:
9422           vindex = 1;
9423           break;
9424         default:
9425           abort ();
9426           break;
9427         }
9428
9429       dp = &vex_len_table[dp->op[1].bytemode][vindex];
9430       break;
9431
9432     case USE_EVEX_LEN_TABLE:
9433       if (!vex.evex)
9434         abort ();
9435
9436       switch (vex.length)
9437         {
9438         case 128:
9439           vindex = 0;
9440           break;
9441         case 256:
9442           vindex = 1;
9443           break;
9444         case 512:
9445           vindex = 2;
9446           break;
9447         default:
9448           abort ();
9449           break;
9450         }
9451
9452       dp = &evex_len_table[dp->op[1].bytemode][vindex];
9453       break;
9454
9455     case USE_XOP_8F_TABLE:
9456       FETCH_DATA (info, codep + 3);
9457       rex = ~(*codep >> 5) & 0x7;
9458
9459       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
9460       switch ((*codep & 0x1f))
9461         {
9462         default:
9463           dp = &bad_opcode;
9464           return dp;
9465         case 0x8:
9466           vex_table_index = XOP_08;
9467           break;
9468         case 0x9:
9469           vex_table_index = XOP_09;
9470           break;
9471         case 0xa:
9472           vex_table_index = XOP_0A;
9473           break;
9474         }
9475       codep++;
9476       vex.w = *codep & 0x80;
9477       if (vex.w && address_mode == mode_64bit)
9478         rex |= REX_W;
9479
9480       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9481       if (address_mode != mode_64bit)
9482         {
9483           /* In 16/32-bit mode REX_B is silently ignored.  */
9484           rex &= ~REX_B;
9485         }
9486
9487       vex.length = (*codep & 0x4) ? 256 : 128;
9488       switch ((*codep & 0x3))
9489         {
9490         case 0:
9491           break;
9492         case 1:
9493           vex.prefix = DATA_PREFIX_OPCODE;
9494           break;
9495         case 2:
9496           vex.prefix = REPE_PREFIX_OPCODE;
9497           break;
9498         case 3:
9499           vex.prefix = REPNE_PREFIX_OPCODE;
9500           break;
9501         }
9502       need_vex = 1;
9503       codep++;
9504       vindex = *codep++;
9505       dp = &xop_table[vex_table_index][vindex];
9506
9507       end_codep = codep;
9508       FETCH_DATA (info, codep + 1);
9509       modrm.mod = (*codep >> 6) & 3;
9510       modrm.reg = (*codep >> 3) & 7;
9511       modrm.rm = *codep & 7;
9512
9513       /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9514          having to decode the bits for every otherwise valid encoding.  */
9515       if (vex.prefix)
9516         return &bad_opcode;
9517       break;
9518
9519     case USE_VEX_C4_TABLE:
9520       /* VEX prefix.  */
9521       FETCH_DATA (info, codep + 3);
9522       rex = ~(*codep >> 5) & 0x7;
9523       switch ((*codep & 0x1f))
9524         {
9525         default:
9526           dp = &bad_opcode;
9527           return dp;
9528         case 0x1:
9529           vex_table_index = VEX_0F;
9530           break;
9531         case 0x2:
9532           vex_table_index = VEX_0F38;
9533           break;
9534         case 0x3:
9535           vex_table_index = VEX_0F3A;
9536           break;
9537         }
9538       codep++;
9539       vex.w = *codep & 0x80;
9540       if (address_mode == mode_64bit)
9541         {
9542           if (vex.w)
9543             rex |= REX_W;
9544         }
9545       else
9546         {
9547           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9548              is ignored, other REX bits are 0 and the highest bit in
9549              VEX.vvvv is also ignored (but we mustn't clear it here).  */
9550           rex = 0;
9551         }
9552       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9553       vex.length = (*codep & 0x4) ? 256 : 128;
9554       switch ((*codep & 0x3))
9555         {
9556         case 0:
9557           break;
9558         case 1:
9559           vex.prefix = DATA_PREFIX_OPCODE;
9560           break;
9561         case 2:
9562           vex.prefix = REPE_PREFIX_OPCODE;
9563           break;
9564         case 3:
9565           vex.prefix = REPNE_PREFIX_OPCODE;
9566           break;
9567         }
9568       need_vex = 1;
9569       codep++;
9570       vindex = *codep++;
9571       dp = &vex_table[vex_table_index][vindex];
9572       end_codep = codep;
9573       /* There is no MODRM byte for VEX0F 77.  */
9574       if (vex_table_index != VEX_0F || vindex != 0x77)
9575         {
9576           FETCH_DATA (info, codep + 1);
9577           modrm.mod = (*codep >> 6) & 3;
9578           modrm.reg = (*codep >> 3) & 7;
9579           modrm.rm = *codep & 7;
9580         }
9581       break;
9582
9583     case USE_VEX_C5_TABLE:
9584       /* VEX prefix.  */
9585       FETCH_DATA (info, codep + 2);
9586       rex = (*codep & 0x80) ? 0 : REX_R;
9587
9588       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9589          VEX.vvvv is 1.  */
9590       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9591       vex.length = (*codep & 0x4) ? 256 : 128;
9592       switch ((*codep & 0x3))
9593         {
9594         case 0:
9595           break;
9596         case 1:
9597           vex.prefix = DATA_PREFIX_OPCODE;
9598           break;
9599         case 2:
9600           vex.prefix = REPE_PREFIX_OPCODE;
9601           break;
9602         case 3:
9603           vex.prefix = REPNE_PREFIX_OPCODE;
9604           break;
9605         }
9606       need_vex = 1;
9607       codep++;
9608       vindex = *codep++;
9609       dp = &vex_table[dp->op[1].bytemode][vindex];
9610       end_codep = codep;
9611       /* There is no MODRM byte for VEX 77.  */
9612       if (vindex != 0x77)
9613         {
9614           FETCH_DATA (info, codep + 1);
9615           modrm.mod = (*codep >> 6) & 3;
9616           modrm.reg = (*codep >> 3) & 7;
9617           modrm.rm = *codep & 7;
9618         }
9619       break;
9620
9621     case USE_VEX_W_TABLE:
9622       if (!need_vex)
9623         abort ();
9624
9625       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
9626       break;
9627
9628     case USE_EVEX_TABLE:
9629       two_source_ops = 0;
9630       /* EVEX prefix.  */
9631       vex.evex = 1;
9632       FETCH_DATA (info, codep + 4);
9633       /* The first byte after 0x62.  */
9634       rex = ~(*codep >> 5) & 0x7;
9635       vex.r = *codep & 0x10;
9636       switch ((*codep & 0xf))
9637         {
9638         default:
9639           return &bad_opcode;
9640         case 0x1:
9641           vex_table_index = EVEX_0F;
9642           break;
9643         case 0x2:
9644           vex_table_index = EVEX_0F38;
9645           break;
9646         case 0x3:
9647           vex_table_index = EVEX_0F3A;
9648           break;
9649         }
9650
9651       /* The second byte after 0x62.  */
9652       codep++;
9653       vex.w = *codep & 0x80;
9654       if (vex.w && address_mode == mode_64bit)
9655         rex |= REX_W;
9656
9657       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9658
9659       /* The U bit.  */
9660       if (!(*codep & 0x4))
9661         return &bad_opcode;
9662
9663       switch ((*codep & 0x3))
9664         {
9665         case 0:
9666           break;
9667         case 1:
9668           vex.prefix = DATA_PREFIX_OPCODE;
9669           break;
9670         case 2:
9671           vex.prefix = REPE_PREFIX_OPCODE;
9672           break;
9673         case 3:
9674           vex.prefix = REPNE_PREFIX_OPCODE;
9675           break;
9676         }
9677
9678       /* The third byte after 0x62.  */
9679       codep++;
9680
9681       /* Remember the static rounding bits.  */
9682       vex.ll = (*codep >> 5) & 3;
9683       vex.b = (*codep & 0x10) != 0;
9684
9685       vex.v = *codep & 0x8;
9686       vex.mask_register_specifier = *codep & 0x7;
9687       vex.zeroing = *codep & 0x80;
9688
9689       if (address_mode != mode_64bit)
9690         {
9691           /* In 16/32-bit mode silently ignore following bits.  */
9692           rex &= ~REX_B;
9693           vex.r = 1;
9694           vex.v = 1;
9695         }
9696
9697       need_vex = 1;
9698       codep++;
9699       vindex = *codep++;
9700       dp = &evex_table[vex_table_index][vindex];
9701       end_codep = codep;
9702       FETCH_DATA (info, codep + 1);
9703       modrm.mod = (*codep >> 6) & 3;
9704       modrm.reg = (*codep >> 3) & 7;
9705       modrm.rm = *codep & 7;
9706
9707       /* Set vector length.  */
9708       if (modrm.mod == 3 && vex.b)
9709         vex.length = 512;
9710       else
9711         {
9712           switch (vex.ll)
9713             {
9714             case 0x0:
9715               vex.length = 128;
9716               break;
9717             case 0x1:
9718               vex.length = 256;
9719               break;
9720             case 0x2:
9721               vex.length = 512;
9722               break;
9723             default:
9724               return &bad_opcode;
9725             }
9726         }
9727       break;
9728
9729     case 0:
9730       dp = &bad_opcode;
9731       break;
9732
9733     default:
9734       abort ();
9735     }
9736
9737   if (dp->name != NULL)
9738     return dp;
9739   else
9740     return get_valid_dis386 (dp, info);
9741 }
9742
9743 static void
9744 get_sib (disassemble_info *info, int sizeflag)
9745 {
9746   /* If modrm.mod == 3, operand must be register.  */
9747   if (need_modrm
9748       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
9749       && modrm.mod != 3
9750       && modrm.rm == 4)
9751     {
9752       FETCH_DATA (info, codep + 2);
9753       sib.index = (codep [1] >> 3) & 7;
9754       sib.scale = (codep [1] >> 6) & 3;
9755       sib.base = codep [1] & 7;
9756     }
9757 }
9758
9759 static int
9760 print_insn (bfd_vma pc, disassemble_info *info)
9761 {
9762   const struct dis386 *dp;
9763   int i;
9764   char *op_txt[MAX_OPERANDS];
9765   int needcomma;
9766   int sizeflag, orig_sizeflag;
9767   const char *p;
9768   struct dis_private priv;
9769   int prefix_length;
9770
9771   priv.orig_sizeflag = AFLAG | DFLAG;
9772   if ((info->mach & bfd_mach_i386_i386) != 0)
9773     address_mode = mode_32bit;
9774   else if (info->mach == bfd_mach_i386_i8086)
9775     {
9776       address_mode = mode_16bit;
9777       priv.orig_sizeflag = 0;
9778     }
9779   else
9780     address_mode = mode_64bit;
9781
9782   if (intel_syntax == (char) -1)
9783     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
9784
9785   for (p = info->disassembler_options; p != NULL; )
9786     {
9787       if (CONST_STRNEQ (p, "amd64"))
9788         isa64 = amd64;
9789       else if (CONST_STRNEQ (p, "intel64"))
9790         isa64 = intel64;
9791       else if (CONST_STRNEQ (p, "x86-64"))
9792         {
9793           address_mode = mode_64bit;
9794           priv.orig_sizeflag |= AFLAG | DFLAG;
9795         }
9796       else if (CONST_STRNEQ (p, "i386"))
9797         {
9798           address_mode = mode_32bit;
9799           priv.orig_sizeflag |= AFLAG | DFLAG;
9800         }
9801       else if (CONST_STRNEQ (p, "i8086"))
9802         {
9803           address_mode = mode_16bit;
9804           priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9805         }
9806       else if (CONST_STRNEQ (p, "intel"))
9807         {
9808           intel_syntax = 1;
9809           if (CONST_STRNEQ (p + 5, "-mnemonic"))
9810             intel_mnemonic = 1;
9811         }
9812       else if (CONST_STRNEQ (p, "att"))
9813         {
9814           intel_syntax = 0;
9815           if (CONST_STRNEQ (p + 3, "-mnemonic"))
9816             intel_mnemonic = 0;
9817         }
9818       else if (CONST_STRNEQ (p, "addr"))
9819         {
9820           if (address_mode == mode_64bit)
9821             {
9822               if (p[4] == '3' && p[5] == '2')
9823                 priv.orig_sizeflag &= ~AFLAG;
9824               else if (p[4] == '6' && p[5] == '4')
9825                 priv.orig_sizeflag |= AFLAG;
9826             }
9827           else
9828             {
9829               if (p[4] == '1' && p[5] == '6')
9830                 priv.orig_sizeflag &= ~AFLAG;
9831               else if (p[4] == '3' && p[5] == '2')
9832                 priv.orig_sizeflag |= AFLAG;
9833             }
9834         }
9835       else if (CONST_STRNEQ (p, "data"))
9836         {
9837           if (p[4] == '1' && p[5] == '6')
9838             priv.orig_sizeflag &= ~DFLAG;
9839           else if (p[4] == '3' && p[5] == '2')
9840             priv.orig_sizeflag |= DFLAG;
9841         }
9842       else if (CONST_STRNEQ (p, "suffix"))
9843         priv.orig_sizeflag |= SUFFIX_ALWAYS;
9844
9845       p = strchr (p, ',');
9846       if (p != NULL)
9847         p++;
9848     }
9849
9850   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9851     {
9852       (*info->fprintf_func) (info->stream,
9853                              _("64-bit address is disabled"));
9854       return -1;
9855     }
9856
9857   if (intel_syntax)
9858     {
9859       names64 = intel_names64;
9860       names32 = intel_names32;
9861       names16 = intel_names16;
9862       names8 = intel_names8;
9863       names8rex = intel_names8rex;
9864       names_seg = intel_names_seg;
9865       names_mm = intel_names_mm;
9866       names_bnd = intel_names_bnd;
9867       names_xmm = intel_names_xmm;
9868       names_ymm = intel_names_ymm;
9869       names_zmm = intel_names_zmm;
9870       names_tmm = intel_names_tmm;
9871       index64 = intel_index64;
9872       index32 = intel_index32;
9873       names_mask = intel_names_mask;
9874       index16 = intel_index16;
9875       open_char = '[';
9876       close_char = ']';
9877       separator_char = '+';
9878       scale_char = '*';
9879     }
9880   else
9881     {
9882       names64 = att_names64;
9883       names32 = att_names32;
9884       names16 = att_names16;
9885       names8 = att_names8;
9886       names8rex = att_names8rex;
9887       names_seg = att_names_seg;
9888       names_mm = att_names_mm;
9889       names_bnd = att_names_bnd;
9890       names_xmm = att_names_xmm;
9891       names_ymm = att_names_ymm;
9892       names_zmm = att_names_zmm;
9893       names_tmm = att_names_tmm;
9894       index64 = att_index64;
9895       index32 = att_index32;
9896       names_mask = att_names_mask;
9897       index16 = att_index16;
9898       open_char = '(';
9899       close_char =  ')';
9900       separator_char = ',';
9901       scale_char = ',';
9902     }
9903
9904   /* The output looks better if we put 7 bytes on a line, since that
9905      puts most long word instructions on a single line.  Use 8 bytes
9906      for Intel L1OM.  */
9907   if ((info->mach & bfd_mach_l1om) != 0)
9908     info->bytes_per_line = 8;
9909   else
9910     info->bytes_per_line = 7;
9911
9912   info->private_data = &priv;
9913   priv.max_fetched = priv.the_buffer;
9914   priv.insn_start = pc;
9915
9916   obuf[0] = 0;
9917   for (i = 0; i < MAX_OPERANDS; ++i)
9918     {
9919       op_out[i][0] = 0;
9920       op_index[i] = -1;
9921     }
9922
9923   the_info = info;
9924   start_pc = pc;
9925   start_codep = priv.the_buffer;
9926   codep = priv.the_buffer;
9927
9928   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
9929     {
9930       const char *name;
9931
9932       /* Getting here means we tried for data but didn't get it.  That
9933          means we have an incomplete instruction of some sort.  Just
9934          print the first byte as a prefix or a .byte pseudo-op.  */
9935       if (codep > priv.the_buffer)
9936         {
9937           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
9938           if (name != NULL)
9939             (*info->fprintf_func) (info->stream, "%s", name);
9940           else
9941             {
9942               /* Just print the first byte as a .byte instruction.  */
9943               (*info->fprintf_func) (info->stream, ".byte 0x%x",
9944                                      (unsigned int) priv.the_buffer[0]);
9945             }
9946
9947           return 1;
9948         }
9949
9950       return -1;
9951     }
9952
9953   obufp = obuf;
9954   sizeflag = priv.orig_sizeflag;
9955
9956   if (!ckprefix () || rex_used)
9957     {
9958       /* Too many prefixes or unused REX prefixes.  */
9959       for (i = 0;
9960            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
9961            i++)
9962         (*info->fprintf_func) (info->stream, "%s%s",
9963                                i == 0 ? "" : " ",
9964                                prefix_name (all_prefixes[i], sizeflag));
9965       return i;
9966     }
9967
9968   insn_codep = codep;
9969
9970   FETCH_DATA (info, codep + 1);
9971   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
9972
9973   if (((prefixes & PREFIX_FWAIT)
9974        && ((*codep < 0xd8) || (*codep > 0xdf))))
9975     {
9976       /* Handle prefixes before fwait.  */
9977       for (i = 0; i < fwait_prefix && all_prefixes[i];
9978            i++)
9979         (*info->fprintf_func) (info->stream, "%s ",
9980                                prefix_name (all_prefixes[i], sizeflag));
9981       (*info->fprintf_func) (info->stream, "fwait");
9982       return i + 1;
9983     }
9984
9985   if (*codep == 0x0f)
9986     {
9987       unsigned char threebyte;
9988
9989       codep++;
9990       FETCH_DATA (info, codep + 1);
9991       threebyte = *codep;
9992       dp = &dis386_twobyte[threebyte];
9993       need_modrm = twobyte_has_modrm[threebyte];
9994       codep++;
9995     }
9996   else
9997     {
9998       dp = &dis386[*codep];
9999       need_modrm = onebyte_has_modrm[*codep];
10000       codep++;
10001     }
10002
10003   /* Save sizeflag for printing the extra prefixes later before updating
10004      it for mnemonic and operand processing.  The prefix names depend
10005      only on the address mode.  */
10006   orig_sizeflag = sizeflag;
10007   if (prefixes & PREFIX_ADDR)
10008     sizeflag ^= AFLAG;
10009   if ((prefixes & PREFIX_DATA))
10010     sizeflag ^= DFLAG;
10011
10012   end_codep = codep;
10013   if (need_modrm)
10014     {
10015       FETCH_DATA (info, codep + 1);
10016       modrm.mod = (*codep >> 6) & 3;
10017       modrm.reg = (*codep >> 3) & 7;
10018       modrm.rm = *codep & 7;
10019     }
10020   else
10021     memset (&modrm, 0, sizeof (modrm));
10022
10023   need_vex = 0;
10024   memset (&vex, 0, sizeof (vex));
10025
10026   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
10027     {
10028       get_sib (info, sizeflag);
10029       dofloat (sizeflag);
10030     }
10031   else
10032     {
10033       dp = get_valid_dis386 (dp, info);
10034       if (dp != NULL && putop (dp->name, sizeflag) == 0)
10035         {
10036           get_sib (info, sizeflag);
10037           for (i = 0; i < MAX_OPERANDS; ++i)
10038             {
10039               obufp = op_out[i];
10040               op_ad = MAX_OPERANDS - 1 - i;
10041               if (dp->op[i].rtn)
10042                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
10043               /* For EVEX instruction after the last operand masking
10044                  should be printed.  */
10045               if (i == 0 && vex.evex)
10046                 {
10047                   /* Don't print {%k0}.  */
10048                   if (vex.mask_register_specifier)
10049                     {
10050                       oappend ("{");
10051                       oappend (names_mask[vex.mask_register_specifier]);
10052                       oappend ("}");
10053                     }
10054                   if (vex.zeroing)
10055                     oappend ("{z}");
10056                 }
10057             }
10058         }
10059     }
10060
10061   /* Clear instruction information.  */
10062   if (the_info)
10063     {
10064       the_info->insn_info_valid = 0;
10065       the_info->branch_delay_insns = 0;
10066       the_info->data_size = 0;
10067       the_info->insn_type = dis_noninsn;
10068       the_info->target = 0;
10069       the_info->target2 = 0;
10070     }
10071
10072   /* Reset jump operation indicator.  */
10073   op_is_jump = FALSE;
10074
10075   {
10076     int jump_detection = 0;
10077
10078     /* Extract flags.  */
10079     for (i = 0; i < MAX_OPERANDS; ++i)
10080       {
10081         if ((dp->op[i].rtn == OP_J)
10082             || (dp->op[i].rtn == OP_indirE))
10083           jump_detection |= 1;
10084         else if ((dp->op[i].rtn == BND_Fixup)
10085                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
10086           jump_detection |= 2;
10087         else if ((dp->op[i].bytemode == cond_jump_mode)
10088                  || (dp->op[i].bytemode == loop_jcxz_mode))
10089           jump_detection |= 4;
10090       }
10091
10092     /* Determine if this is a jump or branch.  */
10093     if ((jump_detection & 0x3) == 0x3)
10094       {
10095         op_is_jump = TRUE;
10096         if (jump_detection & 0x4)
10097           the_info->insn_type = dis_condbranch;
10098         else
10099           the_info->insn_type =
10100             (dp->name && !strncmp(dp->name, "call", 4))
10101             ? dis_jsr : dis_branch;
10102       }
10103   }
10104
10105   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
10106      are all 0s in inverted form.  */
10107   if (need_vex && vex.register_specifier != 0)
10108     {
10109       (*info->fprintf_func) (info->stream, "(bad)");
10110       return end_codep - priv.the_buffer;
10111     }
10112
10113   switch (dp->prefix_requirement)
10114     {
10115     case PREFIX_DATA:
10116       /* If only the data prefix is marked as mandatory, its absence renders
10117          the encoding invalid.  Most other PREFIX_OPCODE rules still apply.  */
10118       if (need_vex ? !vex.prefix : !(prefixes & PREFIX_DATA))
10119         {
10120           (*info->fprintf_func) (info->stream, "(bad)");
10121           return end_codep - priv.the_buffer;
10122         }
10123       used_prefixes |= PREFIX_DATA;
10124       /* Fall through.  */
10125     case PREFIX_OPCODE:
10126       /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
10127          unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
10128          used by putop and MMX/SSE operand and may be overridden by the
10129          PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
10130          separately.  */
10131       if (((need_vex
10132             ? vex.prefix == REPE_PREFIX_OPCODE
10133               || vex.prefix == REPNE_PREFIX_OPCODE
10134             : (prefixes
10135                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
10136            && (used_prefixes
10137                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
10138           || (((need_vex
10139                 ? vex.prefix == DATA_PREFIX_OPCODE
10140                 : ((prefixes
10141                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
10142                    == PREFIX_DATA))
10143                && (used_prefixes & PREFIX_DATA) == 0))
10144           || (vex.evex && dp->prefix_requirement != PREFIX_DATA
10145               && !vex.w != !(used_prefixes & PREFIX_DATA)))
10146         {
10147           (*info->fprintf_func) (info->stream, "(bad)");
10148           return end_codep - priv.the_buffer;
10149         }
10150       break;
10151     }
10152
10153   /* Check if the REX prefix is used.  */
10154   if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
10155     all_prefixes[last_rex_prefix] = 0;
10156
10157   /* Check if the SEG prefix is used.  */
10158   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
10159                    | PREFIX_FS | PREFIX_GS)) != 0
10160       && (used_prefixes & active_seg_prefix) != 0)
10161     all_prefixes[last_seg_prefix] = 0;
10162
10163   /* Check if the ADDR prefix is used.  */
10164   if ((prefixes & PREFIX_ADDR) != 0
10165       && (used_prefixes & PREFIX_ADDR) != 0)
10166     all_prefixes[last_addr_prefix] = 0;
10167
10168   /* Check if the DATA prefix is used.  */
10169   if ((prefixes & PREFIX_DATA) != 0
10170       && (used_prefixes & PREFIX_DATA) != 0
10171       && !need_vex)
10172     all_prefixes[last_data_prefix] = 0;
10173
10174   /* Print the extra prefixes.  */
10175   prefix_length = 0;
10176   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10177     if (all_prefixes[i])
10178       {
10179         const char *name;
10180         name = prefix_name (all_prefixes[i], orig_sizeflag);
10181         if (name == NULL)
10182           abort ();
10183         prefix_length += strlen (name) + 1;
10184         (*info->fprintf_func) (info->stream, "%s ", name);
10185       }
10186
10187   /* Check maximum code length.  */
10188   if ((codep - start_codep) > MAX_CODE_LENGTH)
10189     {
10190       (*info->fprintf_func) (info->stream, "(bad)");
10191       return MAX_CODE_LENGTH;
10192     }
10193
10194   obufp = mnemonicendp;
10195   for (i = strlen (obuf) + prefix_length; i < 6; i++)
10196     oappend (" ");
10197   oappend (" ");
10198   (*info->fprintf_func) (info->stream, "%s", obuf);
10199
10200   /* The enter and bound instructions are printed with operands in the same
10201      order as the intel book; everything else is printed in reverse order.  */
10202   if (intel_syntax || two_source_ops)
10203     {
10204       bfd_vma riprel;
10205
10206       for (i = 0; i < MAX_OPERANDS; ++i)
10207         op_txt[i] = op_out[i];
10208
10209       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
10210           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
10211         {
10212           op_txt[2] = op_out[3];
10213           op_txt[3] = op_out[2];
10214         }
10215
10216       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
10217         {
10218           op_ad = op_index[i];
10219           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
10220           op_index[MAX_OPERANDS - 1 - i] = op_ad;
10221           riprel = op_riprel[i];
10222           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
10223           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
10224         }
10225     }
10226   else
10227     {
10228       for (i = 0; i < MAX_OPERANDS; ++i)
10229         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
10230     }
10231
10232   needcomma = 0;
10233   for (i = 0; i < MAX_OPERANDS; ++i)
10234     if (*op_txt[i])
10235       {
10236         if (needcomma)
10237           (*info->fprintf_func) (info->stream, ",");
10238         if (op_index[i] != -1 && !op_riprel[i])
10239           {
10240             bfd_vma target = (bfd_vma) op_address[op_index[i]];
10241
10242             if (the_info && op_is_jump)
10243               {
10244                 the_info->insn_info_valid = 1;
10245                 the_info->branch_delay_insns = 0;
10246                 the_info->data_size = 0;
10247                 the_info->target = target;
10248                 the_info->target2 = 0;
10249               }
10250             (*info->print_address_func) (target, info);
10251           }
10252         else
10253           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
10254         needcomma = 1;
10255       }
10256
10257   for (i = 0; i < MAX_OPERANDS; i++)
10258     if (op_index[i] != -1 && op_riprel[i])
10259       {
10260         (*info->fprintf_func) (info->stream, "        # ");
10261         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
10262                                                 + op_address[op_index[i]]), info);
10263         break;
10264       }
10265   return codep - priv.the_buffer;
10266 }
10267
10268 static const char *float_mem[] = {
10269   /* d8 */
10270   "fadd{s|}",
10271   "fmul{s|}",
10272   "fcom{s|}",
10273   "fcomp{s|}",
10274   "fsub{s|}",
10275   "fsubr{s|}",
10276   "fdiv{s|}",
10277   "fdivr{s|}",
10278   /* d9 */
10279   "fld{s|}",
10280   "(bad)",
10281   "fst{s|}",
10282   "fstp{s|}",
10283   "fldenv{C|C}",
10284   "fldcw",
10285   "fNstenv{C|C}",
10286   "fNstcw",
10287   /* da */
10288   "fiadd{l|}",
10289   "fimul{l|}",
10290   "ficom{l|}",
10291   "ficomp{l|}",
10292   "fisub{l|}",
10293   "fisubr{l|}",
10294   "fidiv{l|}",
10295   "fidivr{l|}",
10296   /* db */
10297   "fild{l|}",
10298   "fisttp{l|}",
10299   "fist{l|}",
10300   "fistp{l|}",
10301   "(bad)",
10302   "fld{t|}",
10303   "(bad)",
10304   "fstp{t|}",
10305   /* dc */
10306   "fadd{l|}",
10307   "fmul{l|}",
10308   "fcom{l|}",
10309   "fcomp{l|}",
10310   "fsub{l|}",
10311   "fsubr{l|}",
10312   "fdiv{l|}",
10313   "fdivr{l|}",
10314   /* dd */
10315   "fld{l|}",
10316   "fisttp{ll|}",
10317   "fst{l||}",
10318   "fstp{l|}",
10319   "frstor{C|C}",
10320   "(bad)",
10321   "fNsave{C|C}",
10322   "fNstsw",
10323   /* de */
10324   "fiadd{s|}",
10325   "fimul{s|}",
10326   "ficom{s|}",
10327   "ficomp{s|}",
10328   "fisub{s|}",
10329   "fisubr{s|}",
10330   "fidiv{s|}",
10331   "fidivr{s|}",
10332   /* df */
10333   "fild{s|}",
10334   "fisttp{s|}",
10335   "fist{s|}",
10336   "fistp{s|}",
10337   "fbld",
10338   "fild{ll|}",
10339   "fbstp",
10340   "fistp{ll|}",
10341 };
10342
10343 static const unsigned char float_mem_mode[] = {
10344   /* d8 */
10345   d_mode,
10346   d_mode,
10347   d_mode,
10348   d_mode,
10349   d_mode,
10350   d_mode,
10351   d_mode,
10352   d_mode,
10353   /* d9 */
10354   d_mode,
10355   0,
10356   d_mode,
10357   d_mode,
10358   0,
10359   w_mode,
10360   0,
10361   w_mode,
10362   /* da */
10363   d_mode,
10364   d_mode,
10365   d_mode,
10366   d_mode,
10367   d_mode,
10368   d_mode,
10369   d_mode,
10370   d_mode,
10371   /* db */
10372   d_mode,
10373   d_mode,
10374   d_mode,
10375   d_mode,
10376   0,
10377   t_mode,
10378   0,
10379   t_mode,
10380   /* dc */
10381   q_mode,
10382   q_mode,
10383   q_mode,
10384   q_mode,
10385   q_mode,
10386   q_mode,
10387   q_mode,
10388   q_mode,
10389   /* dd */
10390   q_mode,
10391   q_mode,
10392   q_mode,
10393   q_mode,
10394   0,
10395   0,
10396   0,
10397   w_mode,
10398   /* de */
10399   w_mode,
10400   w_mode,
10401   w_mode,
10402   w_mode,
10403   w_mode,
10404   w_mode,
10405   w_mode,
10406   w_mode,
10407   /* df */
10408   w_mode,
10409   w_mode,
10410   w_mode,
10411   w_mode,
10412   t_mode,
10413   q_mode,
10414   t_mode,
10415   q_mode
10416 };
10417
10418 #define ST { OP_ST, 0 }
10419 #define STi { OP_STi, 0 }
10420
10421 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10422 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10423 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10424 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10425 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10426 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10427 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10428 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10429 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10430
10431 static const struct dis386 float_reg[][8] = {
10432   /* d8 */
10433   {
10434     { "fadd",   { ST, STi }, 0 },
10435     { "fmul",   { ST, STi }, 0 },
10436     { "fcom",   { STi }, 0 },
10437     { "fcomp",  { STi }, 0 },
10438     { "fsub",   { ST, STi }, 0 },
10439     { "fsubr",  { ST, STi }, 0 },
10440     { "fdiv",   { ST, STi }, 0 },
10441     { "fdivr",  { ST, STi }, 0 },
10442   },
10443   /* d9 */
10444   {
10445     { "fld",    { STi }, 0 },
10446     { "fxch",   { STi }, 0 },
10447     { FGRPd9_2 },
10448     { Bad_Opcode },
10449     { FGRPd9_4 },
10450     { FGRPd9_5 },
10451     { FGRPd9_6 },
10452     { FGRPd9_7 },
10453   },
10454   /* da */
10455   {
10456     { "fcmovb", { ST, STi }, 0 },
10457     { "fcmove", { ST, STi }, 0 },
10458     { "fcmovbe",{ ST, STi }, 0 },
10459     { "fcmovu", { ST, STi }, 0 },
10460     { Bad_Opcode },
10461     { FGRPda_5 },
10462     { Bad_Opcode },
10463     { Bad_Opcode },
10464   },
10465   /* db */
10466   {
10467     { "fcmovnb",{ ST, STi }, 0 },
10468     { "fcmovne",{ ST, STi }, 0 },
10469     { "fcmovnbe",{ ST, STi }, 0 },
10470     { "fcmovnu",{ ST, STi }, 0 },
10471     { FGRPdb_4 },
10472     { "fucomi", { ST, STi }, 0 },
10473     { "fcomi",  { ST, STi }, 0 },
10474     { Bad_Opcode },
10475   },
10476   /* dc */
10477   {
10478     { "fadd",   { STi, ST }, 0 },
10479     { "fmul",   { STi, ST }, 0 },
10480     { Bad_Opcode },
10481     { Bad_Opcode },
10482     { "fsub{!M|r}",     { STi, ST }, 0 },
10483     { "fsub{M|}",       { STi, ST }, 0 },
10484     { "fdiv{!M|r}",     { STi, ST }, 0 },
10485     { "fdiv{M|}",       { STi, ST }, 0 },
10486   },
10487   /* dd */
10488   {
10489     { "ffree",  { STi }, 0 },
10490     { Bad_Opcode },
10491     { "fst",    { STi }, 0 },
10492     { "fstp",   { STi }, 0 },
10493     { "fucom",  { STi }, 0 },
10494     { "fucomp", { STi }, 0 },
10495     { Bad_Opcode },
10496     { Bad_Opcode },
10497   },
10498   /* de */
10499   {
10500     { "faddp",  { STi, ST }, 0 },
10501     { "fmulp",  { STi, ST }, 0 },
10502     { Bad_Opcode },
10503     { FGRPde_3 },
10504     { "fsub{!M|r}p",    { STi, ST }, 0 },
10505     { "fsub{M|}p",      { STi, ST }, 0 },
10506     { "fdiv{!M|r}p",    { STi, ST }, 0 },
10507     { "fdiv{M|}p",      { STi, ST }, 0 },
10508   },
10509   /* df */
10510   {
10511     { "ffreep", { STi }, 0 },
10512     { Bad_Opcode },
10513     { Bad_Opcode },
10514     { Bad_Opcode },
10515     { FGRPdf_4 },
10516     { "fucomip", { ST, STi }, 0 },
10517     { "fcomip", { ST, STi }, 0 },
10518     { Bad_Opcode },
10519   },
10520 };
10521
10522 static char *fgrps[][8] = {
10523   /* Bad opcode 0 */
10524   {
10525     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10526   },
10527
10528   /* d9_2  1 */
10529   {
10530     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10531   },
10532
10533   /* d9_4  2 */
10534   {
10535     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10536   },
10537
10538   /* d9_5  3 */
10539   {
10540     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10541   },
10542
10543   /* d9_6  4 */
10544   {
10545     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10546   },
10547
10548   /* d9_7  5 */
10549   {
10550     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10551   },
10552
10553   /* da_5  6 */
10554   {
10555     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10556   },
10557
10558   /* db_4  7 */
10559   {
10560     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10561     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10562   },
10563
10564   /* de_3  8 */
10565   {
10566     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10567   },
10568
10569   /* df_4  9 */
10570   {
10571     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10572   },
10573 };
10574
10575 static void
10576 swap_operand (void)
10577 {
10578   mnemonicendp[0] = '.';
10579   mnemonicendp[1] = 's';
10580   mnemonicendp += 2;
10581 }
10582
10583 static void
10584 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
10585                int sizeflag ATTRIBUTE_UNUSED)
10586 {
10587   /* Skip mod/rm byte.  */
10588   MODRM_CHECK;
10589   codep++;
10590 }
10591
10592 static void
10593 dofloat (int sizeflag)
10594 {
10595   const struct dis386 *dp;
10596   unsigned char floatop;
10597
10598   floatop = codep[-1];
10599
10600   if (modrm.mod != 3)
10601     {
10602       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
10603
10604       putop (float_mem[fp_indx], sizeflag);
10605       obufp = op_out[0];
10606       op_ad = 2;
10607       OP_E (float_mem_mode[fp_indx], sizeflag);
10608       return;
10609     }
10610   /* Skip mod/rm byte.  */
10611   MODRM_CHECK;
10612   codep++;
10613
10614   dp = &float_reg[floatop - 0xd8][modrm.reg];
10615   if (dp->name == NULL)
10616     {
10617       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
10618
10619       /* Instruction fnstsw is only one with strange arg.  */
10620       if (floatop == 0xdf && codep[-1] == 0xe0)
10621         strcpy (op_out[0], names16[0]);
10622     }
10623   else
10624     {
10625       putop (dp->name, sizeflag);
10626
10627       obufp = op_out[0];
10628       op_ad = 2;
10629       if (dp->op[0].rtn)
10630         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
10631
10632       obufp = op_out[1];
10633       op_ad = 1;
10634       if (dp->op[1].rtn)
10635         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
10636     }
10637 }
10638
10639 /* Like oappend (below), but S is a string starting with '%'.
10640    In Intel syntax, the '%' is elided.  */
10641 static void
10642 oappend_maybe_intel (const char *s)
10643 {
10644   oappend (s + intel_syntax);
10645 }
10646
10647 static void
10648 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10649 {
10650   oappend_maybe_intel ("%st");
10651 }
10652
10653 static void
10654 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10655 {
10656   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
10657   oappend_maybe_intel (scratchbuf);
10658 }
10659
10660 /* Capital letters in template are macros.  */
10661 static int
10662 putop (const char *in_template, int sizeflag)
10663 {
10664   const char *p;
10665   int alt = 0;
10666   int cond = 1;
10667   unsigned int l = 0, len = 0;
10668   char last[4];
10669
10670   for (p = in_template; *p; p++)
10671     {
10672       if (len > l)
10673         {
10674           if (l >= sizeof (last) || !ISUPPER (*p))
10675             abort ();
10676           last[l++] = *p;
10677           continue;
10678         }
10679       switch (*p)
10680         {
10681         default:
10682           *obufp++ = *p;
10683           break;
10684         case '%':
10685           len++;
10686           break;
10687         case '!':
10688           cond = 0;
10689           break;
10690         case '{':
10691           if (intel_syntax)
10692             {
10693               while (*++p != '|')
10694                 if (*p == '}' || *p == '\0')
10695                   abort ();
10696               alt = 1;
10697             }
10698           break;
10699         case '|':
10700           while (*++p != '}')
10701             {
10702               if (*p == '\0')
10703                 abort ();
10704             }
10705           break;
10706         case '}':
10707           alt = 0;
10708           break;
10709         case 'A':
10710           if (intel_syntax)
10711             break;
10712           if ((need_modrm && modrm.mod != 3)
10713               || (sizeflag & SUFFIX_ALWAYS))
10714             *obufp++ = 'b';
10715           break;
10716         case 'B':
10717           if (l == 0)
10718             {
10719             case_B:
10720               if (intel_syntax)
10721                 break;
10722               if (sizeflag & SUFFIX_ALWAYS)
10723                 *obufp++ = 'b';
10724             }
10725           else if (l == 1 && last[0] == 'L')
10726             {
10727               if (address_mode == mode_64bit
10728                   && !(prefixes & PREFIX_ADDR))
10729                 {
10730                   *obufp++ = 'a';
10731                   *obufp++ = 'b';
10732                   *obufp++ = 's';
10733                 }
10734
10735               goto case_B;
10736             }
10737           else
10738             abort ();
10739           break;
10740         case 'C':
10741           if (intel_syntax && !alt)
10742             break;
10743           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10744             {
10745               if (sizeflag & DFLAG)
10746                 *obufp++ = intel_syntax ? 'd' : 'l';
10747               else
10748                 *obufp++ = intel_syntax ? 'w' : 's';
10749               used_prefixes |= (prefixes & PREFIX_DATA);
10750             }
10751           break;
10752         case 'D':
10753           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10754             break;
10755           USED_REX (REX_W);
10756           if (modrm.mod == 3)
10757             {
10758               if (rex & REX_W)
10759                 *obufp++ = 'q';
10760               else
10761                 {
10762                   if (sizeflag & DFLAG)
10763                     *obufp++ = intel_syntax ? 'd' : 'l';
10764                   else
10765                     *obufp++ = 'w';
10766                   used_prefixes |= (prefixes & PREFIX_DATA);
10767                 }
10768             }
10769           else
10770             *obufp++ = 'w';
10771           break;
10772         case 'E':               /* For jcxz/jecxz */
10773           if (address_mode == mode_64bit)
10774             {
10775               if (sizeflag & AFLAG)
10776                 *obufp++ = 'r';
10777               else
10778                 *obufp++ = 'e';
10779             }
10780           else
10781             if (sizeflag & AFLAG)
10782               *obufp++ = 'e';
10783           used_prefixes |= (prefixes & PREFIX_ADDR);
10784           break;
10785         case 'F':
10786           if (intel_syntax)
10787             break;
10788           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10789             {
10790               if (sizeflag & AFLAG)
10791                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10792               else
10793                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
10794               used_prefixes |= (prefixes & PREFIX_ADDR);
10795             }
10796           break;
10797         case 'G':
10798           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
10799             break;
10800           if ((rex & REX_W) || (sizeflag & DFLAG))
10801             *obufp++ = 'l';
10802           else
10803             *obufp++ = 'w';
10804           if (!(rex & REX_W))
10805             used_prefixes |= (prefixes & PREFIX_DATA);
10806           break;
10807         case 'H':
10808           if (intel_syntax)
10809             break;
10810           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10811               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10812             {
10813               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
10814               *obufp++ = ',';
10815               *obufp++ = 'p';
10816               if (prefixes & PREFIX_DS)
10817                 *obufp++ = 't';
10818               else
10819                 *obufp++ = 'n';
10820             }
10821           break;
10822         case 'K':
10823           USED_REX (REX_W);
10824           if (rex & REX_W)
10825             *obufp++ = 'q';
10826           else
10827             *obufp++ = 'd';
10828           break;
10829         case 'L':
10830           abort ();
10831         case 'M':
10832           if (intel_mnemonic != cond)
10833             *obufp++ = 'r';
10834           break;
10835         case 'N':
10836           if ((prefixes & PREFIX_FWAIT) == 0)
10837             *obufp++ = 'n';
10838           else
10839             used_prefixes |= PREFIX_FWAIT;
10840           break;
10841         case 'O':
10842           USED_REX (REX_W);
10843           if (rex & REX_W)
10844             *obufp++ = 'o';
10845           else if (intel_syntax && (sizeflag & DFLAG))
10846             *obufp++ = 'q';
10847           else
10848             *obufp++ = 'd';
10849           if (!(rex & REX_W))
10850             used_prefixes |= (prefixes & PREFIX_DATA);
10851           break;
10852         case '@':
10853           if (address_mode == mode_64bit
10854               && (isa64 == intel64 || (rex & REX_W)
10855                   || !(prefixes & PREFIX_DATA)))
10856             {
10857               if (sizeflag & SUFFIX_ALWAYS)
10858                 *obufp++ = 'q';
10859               break;
10860             }
10861           /* Fall through.  */
10862         case 'P':
10863           if (l == 0)
10864             {
10865               if ((modrm.mod == 3 || !cond)
10866                   && !(sizeflag & SUFFIX_ALWAYS))
10867                 break;
10868           /* Fall through.  */
10869         case 'T':
10870               if ((!(rex & REX_W) && (prefixes & PREFIX_DATA))
10871                   || ((sizeflag & SUFFIX_ALWAYS)
10872                       && address_mode != mode_64bit))
10873                 {
10874                   *obufp++ = (sizeflag & DFLAG) ?
10875                              intel_syntax ? 'd' : 'l' : 'w';
10876                   used_prefixes |= (prefixes & PREFIX_DATA);
10877                 }
10878               else if (sizeflag & SUFFIX_ALWAYS)
10879                 *obufp++ = 'q';
10880             }
10881           else if (l == 1 && last[0] == 'L')
10882             {
10883               if ((prefixes & PREFIX_DATA)
10884                   || (rex & REX_W)
10885                   || (sizeflag & SUFFIX_ALWAYS))
10886                 {
10887                   USED_REX (REX_W);
10888                   if (rex & REX_W)
10889                     *obufp++ = 'q';
10890                   else
10891                     {
10892                       if (sizeflag & DFLAG)
10893                         *obufp++ = intel_syntax ? 'd' : 'l';
10894                       else
10895                         *obufp++ = 'w';
10896                       used_prefixes |= (prefixes & PREFIX_DATA);
10897                     }
10898                 }
10899             }
10900           else
10901             abort ();
10902           break;
10903         case 'Q':
10904           if (l == 0)
10905             {
10906               if (intel_syntax && !alt)
10907                 break;
10908               USED_REX (REX_W);
10909               if ((need_modrm && modrm.mod != 3)
10910                   || (sizeflag & SUFFIX_ALWAYS))
10911                 {
10912                   if (rex & REX_W)
10913                     *obufp++ = 'q';
10914                   else
10915                     {
10916                       if (sizeflag & DFLAG)
10917                         *obufp++ = intel_syntax ? 'd' : 'l';
10918                       else
10919                         *obufp++ = 'w';
10920                       used_prefixes |= (prefixes & PREFIX_DATA);
10921                     }
10922                 }
10923             }
10924           else if (l == 1 && last[0] == 'D')
10925             *obufp++ = vex.w ? 'q' : 'd';
10926           else if (l == 1 && last[0] == 'L')
10927             {
10928               if (cond ? modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
10929                        : address_mode != mode_64bit)
10930                 break;
10931               if ((rex & REX_W))
10932                 {
10933                   USED_REX (REX_W);
10934                   *obufp++ = 'q';
10935                 }
10936               else if((address_mode == mode_64bit && cond)
10937                       || (sizeflag & SUFFIX_ALWAYS))
10938                 *obufp++ = intel_syntax? 'd' : 'l';
10939             }
10940           else
10941             abort ();
10942           break;
10943         case 'R':
10944           USED_REX (REX_W);
10945           if (rex & REX_W)
10946             *obufp++ = 'q';
10947           else if (sizeflag & DFLAG)
10948             {
10949               if (intel_syntax)
10950                   *obufp++ = 'd';
10951               else
10952                   *obufp++ = 'l';
10953             }
10954           else
10955             *obufp++ = 'w';
10956           if (intel_syntax && !p[1]
10957               && ((rex & REX_W) || (sizeflag & DFLAG)))
10958             *obufp++ = 'e';
10959           if (!(rex & REX_W))
10960             used_prefixes |= (prefixes & PREFIX_DATA);
10961           break;
10962         case 'S':
10963           if (l == 0)
10964             {
10965             case_S:
10966               if (intel_syntax)
10967                 break;
10968               if (sizeflag & SUFFIX_ALWAYS)
10969                 {
10970                   if (rex & REX_W)
10971                     *obufp++ = 'q';
10972                   else
10973                     {
10974                       if (sizeflag & DFLAG)
10975                         *obufp++ = 'l';
10976                       else
10977                         *obufp++ = 'w';
10978                       used_prefixes |= (prefixes & PREFIX_DATA);
10979                     }
10980                 }
10981             }
10982           else if (l == 1 && last[0] == 'L')
10983             {
10984               if (address_mode == mode_64bit
10985                   && !(prefixes & PREFIX_ADDR))
10986                 {
10987                   *obufp++ = 'a';
10988                   *obufp++ = 'b';
10989                   *obufp++ = 's';
10990                 }
10991
10992               goto case_S;
10993             }
10994           else
10995             abort ();
10996           break;
10997         case 'V':
10998           if (l == 0)
10999             abort ();
11000           else if (l == 1 && last[0] == 'L')
11001             {
11002               if (rex & REX_W)
11003                 {
11004                   *obufp++ = 'a';
11005                   *obufp++ = 'b';
11006                   *obufp++ = 's';
11007                 }
11008             }
11009           else
11010             abort ();
11011           goto case_S;
11012         case 'W':
11013           if (l == 0)
11014             {
11015               /* operand size flag for cwtl, cbtw */
11016               USED_REX (REX_W);
11017               if (rex & REX_W)
11018                 {
11019                   if (intel_syntax)
11020                     *obufp++ = 'd';
11021                   else
11022                     *obufp++ = 'l';
11023                 }
11024               else if (sizeflag & DFLAG)
11025                 *obufp++ = 'w';
11026               else
11027                 *obufp++ = 'b';
11028               if (!(rex & REX_W))
11029                 used_prefixes |= (prefixes & PREFIX_DATA);
11030             }
11031           else if (l == 1)
11032             {
11033               if (!need_vex)
11034                 abort ();
11035               if (last[0] == 'X')
11036                 *obufp++ = vex.w ? 'd': 's';
11037               else if (last[0] == 'B')
11038                 *obufp++ = vex.w ? 'w': 'b';
11039               else
11040                 abort ();
11041             }
11042           else
11043             abort ();
11044           break;
11045         case 'X':
11046           if (l != 0)
11047             abort ();
11048           if (need_vex
11049               ? vex.prefix == DATA_PREFIX_OPCODE
11050               : prefixes & PREFIX_DATA)
11051             {
11052               *obufp++ = 'd';
11053               used_prefixes |= PREFIX_DATA;
11054             }
11055           else
11056             *obufp++ = 's';
11057           break;
11058         case 'Y':
11059           if (l == 1 && last[0] == 'X')
11060             {
11061               if (!need_vex)
11062                 abort ();
11063               if (intel_syntax
11064                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
11065                 break;
11066               switch (vex.length)
11067                 {
11068                 case 128:
11069                   *obufp++ = 'x';
11070                   break;
11071                 case 256:
11072                   *obufp++ = 'y';
11073                   break;
11074                 case 512:
11075                   if (!vex.evex)
11076                 default:
11077                     abort ();
11078                 }
11079             }
11080           else
11081             abort ();
11082           break;
11083         case 'Z':
11084           if (l == 0)
11085             {
11086               /* These insns ignore ModR/M.mod: Force it to 3 for OP_E().  */
11087               modrm.mod = 3;
11088               if (!intel_syntax && (sizeflag & SUFFIX_ALWAYS))
11089                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
11090             }
11091           else if (l == 1 && last[0] == 'X')
11092             {
11093               if (!need_vex || !vex.evex)
11094                 abort ();
11095               if (intel_syntax
11096                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
11097                 break;
11098               switch (vex.length)
11099                 {
11100                 case 128:
11101                   *obufp++ = 'x';
11102                   break;
11103                 case 256:
11104                   *obufp++ = 'y';
11105                   break;
11106                 case 512:
11107                   *obufp++ = 'z';
11108                   break;
11109                 default:
11110                   abort ();
11111                 }
11112             }
11113           else
11114             abort ();
11115           break;
11116         case '^':
11117           if (intel_syntax)
11118             break;
11119           if (isa64 == intel64 && (rex & REX_W))
11120             {
11121               USED_REX (REX_W);
11122               *obufp++ = 'q';
11123               break;
11124             }
11125           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
11126             {
11127               if (sizeflag & DFLAG)
11128                 *obufp++ = 'l';
11129               else
11130                 *obufp++ = 'w';
11131               used_prefixes |= (prefixes & PREFIX_DATA);
11132             }
11133           break;
11134         }
11135
11136       if (len == l)
11137         len = l = 0;
11138     }
11139   *obufp = 0;
11140   mnemonicendp = obufp;
11141   return 0;
11142 }
11143
11144 static void
11145 oappend (const char *s)
11146 {
11147   obufp = stpcpy (obufp, s);
11148 }
11149
11150 static void
11151 append_seg (void)
11152 {
11153   /* Only print the active segment register.  */
11154   if (!active_seg_prefix)
11155     return;
11156
11157   used_prefixes |= active_seg_prefix;
11158   switch (active_seg_prefix)
11159     {
11160     case PREFIX_CS:
11161       oappend_maybe_intel ("%cs:");
11162       break;
11163     case PREFIX_DS:
11164       oappend_maybe_intel ("%ds:");
11165       break;
11166     case PREFIX_SS:
11167       oappend_maybe_intel ("%ss:");
11168       break;
11169     case PREFIX_ES:
11170       oappend_maybe_intel ("%es:");
11171       break;
11172     case PREFIX_FS:
11173       oappend_maybe_intel ("%fs:");
11174       break;
11175     case PREFIX_GS:
11176       oappend_maybe_intel ("%gs:");
11177       break;
11178     default:
11179       break;
11180     }
11181 }
11182
11183 static void
11184 OP_indirE (int bytemode, int sizeflag)
11185 {
11186   if (!intel_syntax)
11187     oappend ("*");
11188   OP_E (bytemode, sizeflag);
11189 }
11190
11191 static void
11192 print_operand_value (char *buf, int hex, bfd_vma disp)
11193 {
11194   if (address_mode == mode_64bit)
11195     {
11196       if (hex)
11197         {
11198           char tmp[30];
11199           int i;
11200           buf[0] = '0';
11201           buf[1] = 'x';
11202           sprintf_vma (tmp, disp);
11203           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
11204           strcpy (buf + 2, tmp + i);
11205         }
11206       else
11207         {
11208           bfd_signed_vma v = disp;
11209           char tmp[30];
11210           int i;
11211           if (v < 0)
11212             {
11213               *(buf++) = '-';
11214               v = -disp;
11215               /* Check for possible overflow on 0x8000000000000000.  */
11216               if (v < 0)
11217                 {
11218                   strcpy (buf, "9223372036854775808");
11219                   return;
11220                 }
11221             }
11222           if (!v)
11223             {
11224               strcpy (buf, "0");
11225               return;
11226             }
11227
11228           i = 0;
11229           tmp[29] = 0;
11230           while (v)
11231             {
11232               tmp[28 - i] = (v % 10) + '0';
11233               v /= 10;
11234               i++;
11235             }
11236           strcpy (buf, tmp + 29 - i);
11237         }
11238     }
11239   else
11240     {
11241       if (hex)
11242         sprintf (buf, "0x%x", (unsigned int) disp);
11243       else
11244         sprintf (buf, "%d", (int) disp);
11245     }
11246 }
11247
11248 /* Put DISP in BUF as signed hex number.  */
11249
11250 static void
11251 print_displacement (char *buf, bfd_vma disp)
11252 {
11253   bfd_signed_vma val = disp;
11254   char tmp[30];
11255   int i, j = 0;
11256
11257   if (val < 0)
11258     {
11259       buf[j++] = '-';
11260       val = -disp;
11261
11262       /* Check for possible overflow.  */
11263       if (val < 0)
11264         {
11265           switch (address_mode)
11266             {
11267             case mode_64bit:
11268               strcpy (buf + j, "0x8000000000000000");
11269               break;
11270             case mode_32bit:
11271               strcpy (buf + j, "0x80000000");
11272               break;
11273             case mode_16bit:
11274               strcpy (buf + j, "0x8000");
11275               break;
11276             }
11277           return;
11278         }
11279     }
11280
11281   buf[j++] = '0';
11282   buf[j++] = 'x';
11283
11284   sprintf_vma (tmp, (bfd_vma) val);
11285   for (i = 0; tmp[i] == '0'; i++)
11286     continue;
11287   if (tmp[i] == '\0')
11288     i--;
11289   strcpy (buf + j, tmp + i);
11290 }
11291
11292 static void
11293 intel_operand_size (int bytemode, int sizeflag)
11294 {
11295   if (vex.evex
11296       && vex.b
11297       && (bytemode == x_mode
11298           || bytemode == evex_half_bcst_xmmq_mode))
11299     {
11300       if (vex.w)
11301         oappend ("QWORD PTR ");
11302       else
11303         oappend ("DWORD PTR ");
11304       return;
11305     }
11306   switch (bytemode)
11307     {
11308     case b_mode:
11309     case b_swap_mode:
11310     case dqb_mode:
11311     case db_mode:
11312       oappend ("BYTE PTR ");
11313       break;
11314     case w_mode:
11315     case dw_mode:
11316     case dqw_mode:
11317       oappend ("WORD PTR ");
11318       break;
11319     case indir_v_mode:
11320       if (address_mode == mode_64bit && isa64 == intel64)
11321         {
11322           oappend ("QWORD PTR ");
11323           break;
11324         }
11325       /* Fall through.  */
11326     case stack_v_mode:
11327       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
11328         {
11329           oappend ("QWORD PTR ");
11330           break;
11331         }
11332       /* Fall through.  */
11333     case v_mode:
11334     case v_swap_mode:
11335     case dq_mode:
11336       USED_REX (REX_W);
11337       if (rex & REX_W)
11338         oappend ("QWORD PTR ");
11339       else if (bytemode == dq_mode)
11340         oappend ("DWORD PTR ");
11341       else
11342         {
11343           if (sizeflag & DFLAG)
11344             oappend ("DWORD PTR ");
11345           else
11346             oappend ("WORD PTR ");
11347           used_prefixes |= (prefixes & PREFIX_DATA);
11348         }
11349       break;
11350     case z_mode:
11351       if ((rex & REX_W) || (sizeflag & DFLAG))
11352         *obufp++ = 'D';
11353       oappend ("WORD PTR ");
11354       if (!(rex & REX_W))
11355         used_prefixes |= (prefixes & PREFIX_DATA);
11356       break;
11357     case a_mode:
11358       if (sizeflag & DFLAG)
11359         oappend ("QWORD PTR ");
11360       else
11361         oappend ("DWORD PTR ");
11362       used_prefixes |= (prefixes & PREFIX_DATA);
11363       break;
11364     case movsxd_mode:
11365       if (!(sizeflag & DFLAG) && isa64 == intel64)
11366         oappend ("WORD PTR ");
11367       else
11368         oappend ("DWORD PTR ");
11369       used_prefixes |= (prefixes & PREFIX_DATA);
11370       break;
11371     case d_mode:
11372     case d_swap_mode:
11373     case dqd_mode:
11374       oappend ("DWORD PTR ");
11375       break;
11376     case q_mode:
11377     case q_swap_mode:
11378       oappend ("QWORD PTR ");
11379       break;
11380     case m_mode:
11381       if (address_mode == mode_64bit)
11382         oappend ("QWORD PTR ");
11383       else
11384         oappend ("DWORD PTR ");
11385       break;
11386     case f_mode:
11387       if (sizeflag & DFLAG)
11388         oappend ("FWORD PTR ");
11389       else
11390         oappend ("DWORD PTR ");
11391       used_prefixes |= (prefixes & PREFIX_DATA);
11392       break;
11393     case t_mode:
11394       oappend ("TBYTE PTR ");
11395       break;
11396     case x_mode:
11397     case x_swap_mode:
11398     case evex_x_gscat_mode:
11399     case evex_x_nobcst_mode:
11400     case bw_unit_mode:
11401       if (need_vex)
11402         {
11403           switch (vex.length)
11404             {
11405             case 128:
11406               oappend ("XMMWORD PTR ");
11407               break;
11408             case 256:
11409               oappend ("YMMWORD PTR ");
11410               break;
11411             case 512:
11412               oappend ("ZMMWORD PTR ");
11413               break;
11414             default:
11415               abort ();
11416             }
11417         }
11418       else
11419         oappend ("XMMWORD PTR ");
11420       break;
11421     case xmm_mode:
11422       oappend ("XMMWORD PTR ");
11423       break;
11424     case ymm_mode:
11425       oappend ("YMMWORD PTR ");
11426       break;
11427     case xmmq_mode:
11428     case evex_half_bcst_xmmq_mode:
11429       if (!need_vex)
11430         abort ();
11431
11432       switch (vex.length)
11433         {
11434         case 128:
11435           oappend ("QWORD PTR ");
11436           break;
11437         case 256:
11438           oappend ("XMMWORD PTR ");
11439           break;
11440         case 512:
11441           oappend ("YMMWORD PTR ");
11442           break;
11443         default:
11444           abort ();
11445         }
11446       break;
11447     case xmm_mb_mode:
11448       if (!need_vex)
11449         abort ();
11450
11451       switch (vex.length)
11452         {
11453         case 128:
11454         case 256:
11455         case 512:
11456           oappend ("BYTE PTR ");
11457           break;
11458         default:
11459           abort ();
11460         }
11461       break;
11462     case xmm_mw_mode:
11463       if (!need_vex)
11464         abort ();
11465
11466       switch (vex.length)
11467         {
11468         case 128:
11469         case 256:
11470         case 512:
11471           oappend ("WORD PTR ");
11472           break;
11473         default:
11474           abort ();
11475         }
11476       break;
11477     case xmm_md_mode:
11478       if (!need_vex)
11479         abort ();
11480
11481       switch (vex.length)
11482         {
11483         case 128:
11484         case 256:
11485         case 512:
11486           oappend ("DWORD PTR ");
11487           break;
11488         default:
11489           abort ();
11490         }
11491       break;
11492     case xmm_mq_mode:
11493       if (!need_vex)
11494         abort ();
11495
11496       switch (vex.length)
11497         {
11498         case 128:
11499         case 256:
11500         case 512:
11501           oappend ("QWORD PTR ");
11502           break;
11503         default:
11504           abort ();
11505         }
11506       break;
11507     case xmmdw_mode:
11508       if (!need_vex)
11509         abort ();
11510
11511       switch (vex.length)
11512         {
11513         case 128:
11514           oappend ("WORD PTR ");
11515           break;
11516         case 256:
11517           oappend ("DWORD PTR ");
11518           break;
11519         case 512:
11520           oappend ("QWORD PTR ");
11521           break;
11522         default:
11523           abort ();
11524         }
11525       break;
11526     case xmmqd_mode:
11527       if (!need_vex)
11528         abort ();
11529
11530       switch (vex.length)
11531         {
11532         case 128:
11533           oappend ("DWORD PTR ");
11534           break;
11535         case 256:
11536           oappend ("QWORD PTR ");
11537           break;
11538         case 512:
11539           oappend ("XMMWORD PTR ");
11540           break;
11541         default:
11542           abort ();
11543         }
11544       break;
11545     case ymmq_mode:
11546       if (!need_vex)
11547         abort ();
11548
11549       switch (vex.length)
11550         {
11551         case 128:
11552           oappend ("QWORD PTR ");
11553           break;
11554         case 256:
11555           oappend ("YMMWORD PTR ");
11556           break;
11557         case 512:
11558           oappend ("ZMMWORD PTR ");
11559           break;
11560         default:
11561           abort ();
11562         }
11563       break;
11564     case ymmxmm_mode:
11565       if (!need_vex)
11566         abort ();
11567
11568       switch (vex.length)
11569         {
11570         case 128:
11571         case 256:
11572           oappend ("XMMWORD PTR ");
11573           break;
11574         default:
11575           abort ();
11576         }
11577       break;
11578     case o_mode:
11579       oappend ("OWORD PTR ");
11580       break;
11581     case vex_scalar_w_dq_mode:
11582       if (!need_vex)
11583         abort ();
11584
11585       if (vex.w)
11586         oappend ("QWORD PTR ");
11587       else
11588         oappend ("DWORD PTR ");
11589       break;
11590     case vex_vsib_d_w_dq_mode:
11591     case vex_vsib_q_w_dq_mode:
11592       if (!need_vex)
11593         abort ();
11594
11595       if (!vex.evex)
11596         {
11597           if (vex.w)
11598             oappend ("QWORD PTR ");
11599           else
11600             oappend ("DWORD PTR ");
11601         }
11602       else
11603         {
11604           switch (vex.length)
11605             {
11606             case 128:
11607               oappend ("XMMWORD PTR ");
11608               break;
11609             case 256:
11610               oappend ("YMMWORD PTR ");
11611               break;
11612             case 512:
11613               oappend ("ZMMWORD PTR ");
11614               break;
11615             default:
11616               abort ();
11617             }
11618         }
11619       break;
11620     case vex_vsib_q_w_d_mode:
11621     case vex_vsib_d_w_d_mode:
11622       if (!need_vex || !vex.evex)
11623         abort ();
11624
11625       switch (vex.length)
11626         {
11627         case 128:
11628           oappend ("QWORD PTR ");
11629           break;
11630         case 256:
11631           oappend ("XMMWORD PTR ");
11632           break;
11633         case 512:
11634           oappend ("YMMWORD PTR ");
11635           break;
11636         default:
11637           abort ();
11638         }
11639
11640       break;
11641     case mask_bd_mode:
11642       if (!need_vex || vex.length != 128)
11643         abort ();
11644       if (vex.w)
11645         oappend ("DWORD PTR ");
11646       else
11647         oappend ("BYTE PTR ");
11648       break;
11649     case mask_mode:
11650       if (!need_vex)
11651         abort ();
11652       if (vex.w)
11653         oappend ("QWORD PTR ");
11654       else
11655         oappend ("WORD PTR ");
11656       break;
11657     case v_bnd_mode:
11658     case v_bndmk_mode:
11659     default:
11660       break;
11661     }
11662 }
11663
11664 static void
11665 OP_E_register (int bytemode, int sizeflag)
11666 {
11667   int reg = modrm.rm;
11668   const char **names;
11669
11670   USED_REX (REX_B);
11671   if ((rex & REX_B))
11672     reg += 8;
11673
11674   if ((sizeflag & SUFFIX_ALWAYS)
11675       && (bytemode == b_swap_mode
11676           || bytemode == bnd_swap_mode
11677           || bytemode == v_swap_mode))
11678     swap_operand ();
11679
11680   switch (bytemode)
11681     {
11682     case b_mode:
11683     case b_swap_mode:
11684       if (reg & 4)
11685         USED_REX (0);
11686       if (rex)
11687         names = names8rex;
11688       else
11689         names = names8;
11690       break;
11691     case w_mode:
11692       names = names16;
11693       break;
11694     case d_mode:
11695     case dw_mode:
11696     case db_mode:
11697       names = names32;
11698       break;
11699     case q_mode:
11700       names = names64;
11701       break;
11702     case m_mode:
11703     case v_bnd_mode:
11704       names = address_mode == mode_64bit ? names64 : names32;
11705       break;
11706     case bnd_mode:
11707     case bnd_swap_mode:
11708       if (reg > 0x3)
11709         {
11710           oappend ("(bad)");
11711           return;
11712         }
11713       names = names_bnd;
11714       break;
11715     case indir_v_mode:
11716       if (address_mode == mode_64bit && isa64 == intel64)
11717         {
11718           names = names64;
11719           break;
11720         }
11721       /* Fall through.  */
11722     case stack_v_mode:
11723       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
11724         {
11725           names = names64;
11726           break;
11727         }
11728       bytemode = v_mode;
11729       /* Fall through.  */
11730     case v_mode:
11731     case v_swap_mode:
11732     case dq_mode:
11733     case dqb_mode:
11734     case dqd_mode:
11735     case dqw_mode:
11736       USED_REX (REX_W);
11737       if (rex & REX_W)
11738         names = names64;
11739       else if (bytemode != v_mode && bytemode != v_swap_mode)
11740         names = names32;
11741       else
11742         {
11743           if (sizeflag & DFLAG)
11744             names = names32;
11745           else
11746             names = names16;
11747           used_prefixes |= (prefixes & PREFIX_DATA);
11748         }
11749       break;
11750     case movsxd_mode:
11751       if (!(sizeflag & DFLAG) && isa64 == intel64)
11752         names = names16;
11753       else
11754         names = names32;
11755       used_prefixes |= (prefixes & PREFIX_DATA);
11756       break;
11757     case va_mode:
11758       names = (address_mode == mode_64bit
11759                ? names64 : names32);
11760       if (!(prefixes & PREFIX_ADDR))
11761         names = (address_mode == mode_16bit
11762                      ? names16 : names);
11763       else
11764         {
11765           /* Remove "addr16/addr32".  */
11766           all_prefixes[last_addr_prefix] = 0;
11767           names = (address_mode != mode_32bit
11768                        ? names32 : names16);
11769           used_prefixes |= PREFIX_ADDR;
11770         }
11771       break;
11772     case mask_bd_mode:
11773     case mask_mode:
11774       if (reg > 0x7)
11775         {
11776           oappend ("(bad)");
11777           return;
11778         }
11779       names = names_mask;
11780       break;
11781     case 0:
11782       return;
11783     default:
11784       oappend (INTERNAL_DISASSEMBLER_ERROR);
11785       return;
11786     }
11787   oappend (names[reg]);
11788 }
11789
11790 static void
11791 OP_E_memory (int bytemode, int sizeflag)
11792 {
11793   bfd_vma disp = 0;
11794   int add = (rex & REX_B) ? 8 : 0;
11795   int riprel = 0;
11796   int shift;
11797
11798   if (vex.evex)
11799     {
11800       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
11801       if (vex.b
11802           && bytemode != x_mode
11803           && bytemode != xmmq_mode
11804           && bytemode != evex_half_bcst_xmmq_mode)
11805         {
11806           BadOp ();
11807           return;
11808         }
11809       switch (bytemode)
11810         {
11811         case dqw_mode:
11812         case dw_mode:
11813         case xmm_mw_mode:
11814           shift = 1;
11815           break;
11816         case dqb_mode:
11817         case db_mode:
11818         case xmm_mb_mode:
11819           shift = 0;
11820           break;
11821         case dq_mode:
11822           if (address_mode != mode_64bit)
11823             {
11824         case dqd_mode:
11825         case xmm_md_mode:
11826         case d_mode:
11827         case d_swap_mode:
11828               shift = 2;
11829               break;
11830             }
11831             /* fall through */
11832         case vex_scalar_w_dq_mode:
11833         case vex_vsib_d_w_dq_mode:
11834         case vex_vsib_d_w_d_mode:
11835         case vex_vsib_q_w_dq_mode:
11836         case vex_vsib_q_w_d_mode:
11837         case evex_x_gscat_mode:
11838           shift = vex.w ? 3 : 2;
11839           break;
11840         case x_mode:
11841         case evex_half_bcst_xmmq_mode:
11842         case xmmq_mode:
11843           if (vex.b)
11844             {
11845               shift = vex.w ? 3 : 2;
11846               break;
11847             }
11848           /* Fall through.  */
11849         case xmmqd_mode:
11850         case xmmdw_mode:
11851         case ymmq_mode:
11852         case evex_x_nobcst_mode:
11853         case x_swap_mode:
11854           switch (vex.length)
11855             {
11856             case 128:
11857               shift = 4;
11858               break;
11859             case 256:
11860               shift = 5;
11861               break;
11862             case 512:
11863               shift = 6;
11864               break;
11865             default:
11866               abort ();
11867             }
11868           /* Make necessary corrections to shift for modes that need it.  */
11869           if (bytemode == xmmq_mode
11870               || bytemode == evex_half_bcst_xmmq_mode
11871               || (bytemode == ymmq_mode && vex.length == 128))
11872             shift -= 1;
11873           else if (bytemode == xmmqd_mode)
11874             shift -= 2;
11875           else if (bytemode == xmmdw_mode)
11876             shift -= 3;
11877           break;
11878         case ymm_mode:
11879           shift = 5;
11880           break;
11881         case xmm_mode:
11882           shift = 4;
11883           break;
11884         case xmm_mq_mode:
11885         case q_mode:
11886         case q_swap_mode:
11887           shift = 3;
11888           break;
11889         case bw_unit_mode:
11890           shift = vex.w ? 1 : 0;
11891           break;
11892         default:
11893           abort ();
11894         }
11895     }
11896   else
11897     shift = 0;
11898
11899   USED_REX (REX_B);
11900   if (intel_syntax)
11901     intel_operand_size (bytemode, sizeflag);
11902   append_seg ();
11903
11904   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11905     {
11906       /* 32/64 bit address mode */
11907       int havedisp;
11908       int havesib;
11909       int havebase;
11910       int haveindex;
11911       int needindex;
11912       int needaddr32;
11913       int base, rbase;
11914       int vindex = 0;
11915       int scale = 0;
11916       int addr32flag = !((sizeflag & AFLAG)
11917                          || bytemode == v_bnd_mode
11918                          || bytemode == v_bndmk_mode
11919                          || bytemode == bnd_mode
11920                          || bytemode == bnd_swap_mode);
11921       const char **indexes64 = names64;
11922       const char **indexes32 = names32;
11923
11924       havesib = 0;
11925       havebase = 1;
11926       haveindex = 0;
11927       base = modrm.rm;
11928
11929       if (base == 4)
11930         {
11931           havesib = 1;
11932           vindex = sib.index;
11933           USED_REX (REX_X);
11934           if (rex & REX_X)
11935             vindex += 8;
11936           switch (bytemode)
11937             {
11938             case vex_vsib_d_w_dq_mode:
11939             case vex_vsib_d_w_d_mode:
11940             case vex_vsib_q_w_dq_mode:
11941             case vex_vsib_q_w_d_mode:
11942               if (!need_vex)
11943                 abort ();
11944               if (vex.evex)
11945                 {
11946                   if (!vex.v)
11947                     vindex += 16;
11948                 }
11949
11950               haveindex = 1;
11951               switch (vex.length)
11952                 {
11953                 case 128:
11954                   indexes64 = indexes32 = names_xmm;
11955                   break;
11956                 case 256:
11957                   if (!vex.w
11958                       || bytemode == vex_vsib_q_w_dq_mode
11959                       || bytemode == vex_vsib_q_w_d_mode)
11960                     indexes64 = indexes32 = names_ymm;
11961                   else
11962                     indexes64 = indexes32 = names_xmm;
11963                   break;
11964                 case 512:
11965                   if (!vex.w
11966                       || bytemode == vex_vsib_q_w_dq_mode
11967                       || bytemode == vex_vsib_q_w_d_mode)
11968                     indexes64 = indexes32 = names_zmm;
11969                   else
11970                     indexes64 = indexes32 = names_ymm;
11971                   break;
11972                 default:
11973                   abort ();
11974                 }
11975               break;
11976             default:
11977               haveindex = vindex != 4;
11978               break;
11979             }
11980           scale = sib.scale;
11981           base = sib.base;
11982           codep++;
11983         }
11984       else
11985         {
11986           /* mandatory non-vector SIB must have sib */
11987           if (bytemode == vex_sibmem_mode)
11988             {
11989               oappend ("(bad)");
11990               return;
11991             }
11992         }
11993       rbase = base + add;
11994
11995       switch (modrm.mod)
11996         {
11997         case 0:
11998           if (base == 5)
11999             {
12000               havebase = 0;
12001               if (address_mode == mode_64bit && !havesib)
12002                 riprel = 1;
12003               disp = get32s ();
12004               if (riprel && bytemode == v_bndmk_mode)
12005                 {
12006                   oappend ("(bad)");
12007                   return;
12008                 }
12009             }
12010           break;
12011         case 1:
12012           FETCH_DATA (the_info, codep + 1);
12013           disp = *codep++;
12014           if ((disp & 0x80) != 0)
12015             disp -= 0x100;
12016           if (vex.evex && shift > 0)
12017             disp <<= shift;
12018           break;
12019         case 2:
12020           disp = get32s ();
12021           break;
12022         }
12023
12024       needindex = 0;
12025       needaddr32 = 0;
12026       if (havesib
12027           && !havebase
12028           && !haveindex
12029           && address_mode != mode_16bit)
12030         {
12031           if (address_mode == mode_64bit)
12032             {
12033               if (addr32flag)
12034                 {
12035                   /* Without base nor index registers, zero-extend the
12036                      lower 32-bit displacement to 64 bits.  */
12037                   disp = (unsigned int) disp;
12038                   needindex = 1;
12039                 }
12040               needaddr32 = 1;
12041             }
12042           else
12043             {
12044               /* In 32-bit mode, we need index register to tell [offset]
12045                  from [eiz*1 + offset].  */
12046               needindex = 1;
12047             }
12048         }
12049
12050       havedisp = (havebase
12051                   || needindex
12052                   || (havesib && (haveindex || scale != 0)));
12053
12054       if (!intel_syntax)
12055         if (modrm.mod != 0 || base == 5)
12056           {
12057             if (havedisp || riprel)
12058               print_displacement (scratchbuf, disp);
12059             else
12060               print_operand_value (scratchbuf, 1, disp);
12061             oappend (scratchbuf);
12062             if (riprel)
12063               {
12064                 set_op (disp, 1);
12065                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
12066               }
12067           }
12068
12069       if ((havebase || haveindex || needindex || needaddr32 || riprel)
12070           && (address_mode != mode_64bit
12071               || ((bytemode != v_bnd_mode)
12072                   && (bytemode != v_bndmk_mode)
12073                   && (bytemode != bnd_mode)
12074                   && (bytemode != bnd_swap_mode))))
12075         used_prefixes |= PREFIX_ADDR;
12076
12077       if (havedisp || (intel_syntax && riprel))
12078         {
12079           *obufp++ = open_char;
12080           if (intel_syntax && riprel)
12081             {
12082               set_op (disp, 1);
12083               oappend (!addr32flag ? "rip" : "eip");
12084             }
12085           *obufp = '\0';
12086           if (havebase)
12087             oappend (address_mode == mode_64bit && !addr32flag
12088                      ? names64[rbase] : names32[rbase]);
12089           if (havesib)
12090             {
12091               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
12092                  print index to tell base + index from base.  */
12093               if (scale != 0
12094                   || needindex
12095                   || haveindex
12096                   || (havebase && base != ESP_REG_NUM))
12097                 {
12098                   if (!intel_syntax || havebase)
12099                     {
12100                       *obufp++ = separator_char;
12101                       *obufp = '\0';
12102                     }
12103                   if (haveindex)
12104                     oappend (address_mode == mode_64bit && !addr32flag
12105                              ? indexes64[vindex] : indexes32[vindex]);
12106                   else
12107                     oappend (address_mode == mode_64bit && !addr32flag
12108                              ? index64 : index32);
12109
12110                   *obufp++ = scale_char;
12111                   *obufp = '\0';
12112                   sprintf (scratchbuf, "%d", 1 << scale);
12113                   oappend (scratchbuf);
12114                 }
12115             }
12116           if (intel_syntax
12117               && (disp || modrm.mod != 0 || base == 5))
12118             {
12119               if (!havedisp || (bfd_signed_vma) disp >= 0)
12120                 {
12121                   *obufp++ = '+';
12122                   *obufp = '\0';
12123                 }
12124               else if (modrm.mod != 1 && disp != -disp)
12125                 {
12126                   *obufp++ = '-';
12127                   *obufp = '\0';
12128                   disp = -disp;
12129                 }
12130
12131               if (havedisp)
12132                 print_displacement (scratchbuf, disp);
12133               else
12134                 print_operand_value (scratchbuf, 1, disp);
12135               oappend (scratchbuf);
12136             }
12137
12138           *obufp++ = close_char;
12139           *obufp = '\0';
12140         }
12141       else if (intel_syntax)
12142         {
12143           if (modrm.mod != 0 || base == 5)
12144             {
12145               if (!active_seg_prefix)
12146                 {
12147                   oappend (names_seg[ds_reg - es_reg]);
12148                   oappend (":");
12149                 }
12150               print_operand_value (scratchbuf, 1, disp);
12151               oappend (scratchbuf);
12152             }
12153         }
12154     }
12155   else if (bytemode == v_bnd_mode
12156            || bytemode == v_bndmk_mode
12157            || bytemode == bnd_mode
12158            || bytemode == bnd_swap_mode)
12159     {
12160       oappend ("(bad)");
12161       return;
12162     }
12163   else
12164     {
12165       /* 16 bit address mode */
12166       used_prefixes |= prefixes & PREFIX_ADDR;
12167       switch (modrm.mod)
12168         {
12169         case 0:
12170           if (modrm.rm == 6)
12171             {
12172               disp = get16 ();
12173               if ((disp & 0x8000) != 0)
12174                 disp -= 0x10000;
12175             }
12176           break;
12177         case 1:
12178           FETCH_DATA (the_info, codep + 1);
12179           disp = *codep++;
12180           if ((disp & 0x80) != 0)
12181             disp -= 0x100;
12182           if (vex.evex && shift > 0)
12183             disp <<= shift;
12184           break;
12185         case 2:
12186           disp = get16 ();
12187           if ((disp & 0x8000) != 0)
12188             disp -= 0x10000;
12189           break;
12190         }
12191
12192       if (!intel_syntax)
12193         if (modrm.mod != 0 || modrm.rm == 6)
12194           {
12195             print_displacement (scratchbuf, disp);
12196             oappend (scratchbuf);
12197           }
12198
12199       if (modrm.mod != 0 || modrm.rm != 6)
12200         {
12201           *obufp++ = open_char;
12202           *obufp = '\0';
12203           oappend (index16[modrm.rm]);
12204           if (intel_syntax
12205               && (disp || modrm.mod != 0 || modrm.rm == 6))
12206             {
12207               if ((bfd_signed_vma) disp >= 0)
12208                 {
12209                   *obufp++ = '+';
12210                   *obufp = '\0';
12211                 }
12212               else if (modrm.mod != 1)
12213                 {
12214                   *obufp++ = '-';
12215                   *obufp = '\0';
12216                   disp = -disp;
12217                 }
12218
12219               print_displacement (scratchbuf, disp);
12220               oappend (scratchbuf);
12221             }
12222
12223           *obufp++ = close_char;
12224           *obufp = '\0';
12225         }
12226       else if (intel_syntax)
12227         {
12228           if (!active_seg_prefix)
12229             {
12230               oappend (names_seg[ds_reg - es_reg]);
12231               oappend (":");
12232             }
12233           print_operand_value (scratchbuf, 1, disp & 0xffff);
12234           oappend (scratchbuf);
12235         }
12236     }
12237   if (vex.evex && vex.b
12238       && (bytemode == x_mode
12239           || bytemode == xmmq_mode
12240           || bytemode == evex_half_bcst_xmmq_mode))
12241     {
12242       if (vex.w
12243           || bytemode == xmmq_mode
12244           || bytemode == evex_half_bcst_xmmq_mode)
12245         {
12246           switch (vex.length)
12247             {
12248             case 128:
12249               oappend ("{1to2}");
12250               break;
12251             case 256:
12252               oappend ("{1to4}");
12253               break;
12254             case 512:
12255               oappend ("{1to8}");
12256               break;
12257             default:
12258               abort ();
12259             }
12260         }
12261       else
12262         {
12263           switch (vex.length)
12264             {
12265             case 128:
12266               oappend ("{1to4}");
12267               break;
12268             case 256:
12269               oappend ("{1to8}");
12270               break;
12271             case 512:
12272               oappend ("{1to16}");
12273               break;
12274             default:
12275               abort ();
12276             }
12277         }
12278     }
12279 }
12280
12281 static void
12282 OP_E (int bytemode, int sizeflag)
12283 {
12284   /* Skip mod/rm byte.  */
12285   MODRM_CHECK;
12286   codep++;
12287
12288   if (modrm.mod == 3)
12289     OP_E_register (bytemode, sizeflag);
12290   else
12291     OP_E_memory (bytemode, sizeflag);
12292 }
12293
12294 static void
12295 OP_G (int bytemode, int sizeflag)
12296 {
12297   int add = 0;
12298   const char **names;
12299   USED_REX (REX_R);
12300   if (rex & REX_R)
12301     add += 8;
12302   switch (bytemode)
12303     {
12304     case b_mode:
12305       if (modrm.reg & 4)
12306         USED_REX (0);
12307       if (rex)
12308         oappend (names8rex[modrm.reg + add]);
12309       else
12310         oappend (names8[modrm.reg + add]);
12311       break;
12312     case w_mode:
12313       oappend (names16[modrm.reg + add]);
12314       break;
12315     case d_mode:
12316     case db_mode:
12317     case dw_mode:
12318       oappend (names32[modrm.reg + add]);
12319       break;
12320     case q_mode:
12321       oappend (names64[modrm.reg + add]);
12322       break;
12323     case bnd_mode:
12324       if (modrm.reg > 0x3)
12325         {
12326           oappend ("(bad)");
12327           return;
12328         }
12329       oappend (names_bnd[modrm.reg]);
12330       break;
12331     case v_mode:
12332     case dq_mode:
12333     case dqb_mode:
12334     case dqd_mode:
12335     case dqw_mode:
12336     case movsxd_mode:
12337       USED_REX (REX_W);
12338       if (rex & REX_W)
12339         oappend (names64[modrm.reg + add]);
12340       else if (bytemode != v_mode && bytemode != movsxd_mode)
12341         oappend (names32[modrm.reg + add]);
12342       else
12343         {
12344           if (sizeflag & DFLAG)
12345             oappend (names32[modrm.reg + add]);
12346           else
12347             oappend (names16[modrm.reg + add]);
12348           used_prefixes |= (prefixes & PREFIX_DATA);
12349         }
12350       break;
12351     case va_mode:
12352       names = (address_mode == mode_64bit
12353                ? names64 : names32);
12354       if (!(prefixes & PREFIX_ADDR))
12355         {
12356           if (address_mode == mode_16bit)
12357             names = names16;
12358         }
12359       else
12360         {
12361           /* Remove "addr16/addr32".  */
12362           all_prefixes[last_addr_prefix] = 0;
12363           names = (address_mode != mode_32bit
12364                        ? names32 : names16);
12365           used_prefixes |= PREFIX_ADDR;
12366         }
12367       oappend (names[modrm.reg + add]);
12368       break;
12369     case m_mode:
12370       if (address_mode == mode_64bit)
12371         oappend (names64[modrm.reg + add]);
12372       else
12373         oappend (names32[modrm.reg + add]);
12374       break;
12375     case mask_bd_mode:
12376     case mask_mode:
12377       if ((modrm.reg + add) > 0x7)
12378         {
12379           oappend ("(bad)");
12380           return;
12381         }
12382       oappend (names_mask[modrm.reg + add]);
12383       break;
12384     default:
12385       oappend (INTERNAL_DISASSEMBLER_ERROR);
12386       break;
12387     }
12388 }
12389
12390 static bfd_vma
12391 get64 (void)
12392 {
12393   bfd_vma x;
12394 #ifdef BFD64
12395   unsigned int a;
12396   unsigned int b;
12397
12398   FETCH_DATA (the_info, codep + 8);
12399   a = *codep++ & 0xff;
12400   a |= (*codep++ & 0xff) << 8;
12401   a |= (*codep++ & 0xff) << 16;
12402   a |= (*codep++ & 0xffu) << 24;
12403   b = *codep++ & 0xff;
12404   b |= (*codep++ & 0xff) << 8;
12405   b |= (*codep++ & 0xff) << 16;
12406   b |= (*codep++ & 0xffu) << 24;
12407   x = a + ((bfd_vma) b << 32);
12408 #else
12409   abort ();
12410   x = 0;
12411 #endif
12412   return x;
12413 }
12414
12415 static bfd_signed_vma
12416 get32 (void)
12417 {
12418   bfd_vma x = 0;
12419
12420   FETCH_DATA (the_info, codep + 4);
12421   x = *codep++ & (bfd_vma) 0xff;
12422   x |= (*codep++ & (bfd_vma) 0xff) << 8;
12423   x |= (*codep++ & (bfd_vma) 0xff) << 16;
12424   x |= (*codep++ & (bfd_vma) 0xff) << 24;
12425   return x;
12426 }
12427
12428 static bfd_signed_vma
12429 get32s (void)
12430 {
12431   bfd_vma x = 0;
12432
12433   FETCH_DATA (the_info, codep + 4);
12434   x = *codep++ & (bfd_vma) 0xff;
12435   x |= (*codep++ & (bfd_vma) 0xff) << 8;
12436   x |= (*codep++ & (bfd_vma) 0xff) << 16;
12437   x |= (*codep++ & (bfd_vma) 0xff) << 24;
12438
12439   x = (x ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31);
12440
12441   return x;
12442 }
12443
12444 static int
12445 get16 (void)
12446 {
12447   int x = 0;
12448
12449   FETCH_DATA (the_info, codep + 2);
12450   x = *codep++ & 0xff;
12451   x |= (*codep++ & 0xff) << 8;
12452   return x;
12453 }
12454
12455 static void
12456 set_op (bfd_vma op, int riprel)
12457 {
12458   op_index[op_ad] = op_ad;
12459   if (address_mode == mode_64bit)
12460     {
12461       op_address[op_ad] = op;
12462       op_riprel[op_ad] = riprel;
12463     }
12464   else
12465     {
12466       /* Mask to get a 32-bit address.  */
12467       op_address[op_ad] = op & 0xffffffff;
12468       op_riprel[op_ad] = riprel & 0xffffffff;
12469     }
12470 }
12471
12472 static void
12473 OP_REG (int code, int sizeflag)
12474 {
12475   const char *s;
12476   int add;
12477
12478   switch (code)
12479     {
12480     case es_reg: case ss_reg: case cs_reg:
12481     case ds_reg: case fs_reg: case gs_reg:
12482       oappend (names_seg[code - es_reg]);
12483       return;
12484     }
12485
12486   USED_REX (REX_B);
12487   if (rex & REX_B)
12488     add = 8;
12489   else
12490     add = 0;
12491
12492   switch (code)
12493     {
12494     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12495     case sp_reg: case bp_reg: case si_reg: case di_reg:
12496       s = names16[code - ax_reg + add];
12497       break;
12498     case ah_reg: case ch_reg: case dh_reg: case bh_reg:
12499       USED_REX (0);
12500       /* Fall through.  */
12501     case al_reg: case cl_reg: case dl_reg: case bl_reg:
12502       if (rex)
12503         s = names8rex[code - al_reg + add];
12504       else
12505         s = names8[code - al_reg];
12506       break;
12507     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12508     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12509       if (address_mode == mode_64bit
12510           && ((sizeflag & DFLAG) || (rex & REX_W)))
12511         {
12512           s = names64[code - rAX_reg + add];
12513           break;
12514         }
12515       code += eAX_reg - rAX_reg;
12516       /* Fall through.  */
12517     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12518     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12519       USED_REX (REX_W);
12520       if (rex & REX_W)
12521         s = names64[code - eAX_reg + add];
12522       else
12523         {
12524           if (sizeflag & DFLAG)
12525             s = names32[code - eAX_reg + add];
12526           else
12527             s = names16[code - eAX_reg + add];
12528           used_prefixes |= (prefixes & PREFIX_DATA);
12529         }
12530       break;
12531     default:
12532       s = INTERNAL_DISASSEMBLER_ERROR;
12533       break;
12534     }
12535   oappend (s);
12536 }
12537
12538 static void
12539 OP_IMREG (int code, int sizeflag)
12540 {
12541   const char *s;
12542
12543   switch (code)
12544     {
12545     case indir_dx_reg:
12546       if (intel_syntax)
12547         s = "dx";
12548       else
12549         s = "(%dx)";
12550       break;
12551     case al_reg: case cl_reg:
12552       s = names8[code - al_reg];
12553       break;
12554     case eAX_reg:
12555       USED_REX (REX_W);
12556       if (rex & REX_W)
12557         {
12558           s = *names64;
12559           break;
12560         }
12561       /* Fall through.  */
12562     case z_mode_ax_reg:
12563       if ((rex & REX_W) || (sizeflag & DFLAG))
12564         s = *names32;
12565       else
12566         s = *names16;
12567       if (!(rex & REX_W))
12568         used_prefixes |= (prefixes & PREFIX_DATA);
12569       break;
12570     default:
12571       s = INTERNAL_DISASSEMBLER_ERROR;
12572       break;
12573     }
12574   oappend (s);
12575 }
12576
12577 static void
12578 OP_I (int bytemode, int sizeflag)
12579 {
12580   bfd_signed_vma op;
12581   bfd_signed_vma mask = -1;
12582
12583   switch (bytemode)
12584     {
12585     case b_mode:
12586       FETCH_DATA (the_info, codep + 1);
12587       op = *codep++;
12588       mask = 0xff;
12589       break;
12590     case v_mode:
12591       USED_REX (REX_W);
12592       if (rex & REX_W)
12593         op = get32s ();
12594       else
12595         {
12596           if (sizeflag & DFLAG)
12597             {
12598               op = get32 ();
12599               mask = 0xffffffff;
12600             }
12601           else
12602             {
12603               op = get16 ();
12604               mask = 0xfffff;
12605             }
12606           used_prefixes |= (prefixes & PREFIX_DATA);
12607         }
12608       break;
12609     case d_mode:
12610       mask = 0xffffffff;
12611       op = get32 ();
12612       break;
12613     case w_mode:
12614       mask = 0xfffff;
12615       op = get16 ();
12616       break;
12617     case const_1_mode:
12618       if (intel_syntax)
12619         oappend ("1");
12620       return;
12621     default:
12622       oappend (INTERNAL_DISASSEMBLER_ERROR);
12623       return;
12624     }
12625
12626   op &= mask;
12627   scratchbuf[0] = '$';
12628   print_operand_value (scratchbuf + 1, 1, op);
12629   oappend_maybe_intel (scratchbuf);
12630   scratchbuf[0] = '\0';
12631 }
12632
12633 static void
12634 OP_I64 (int bytemode, int sizeflag)
12635 {
12636   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
12637     {
12638       OP_I (bytemode, sizeflag);
12639       return;
12640     }
12641
12642   USED_REX (REX_W);
12643
12644   scratchbuf[0] = '$';
12645   print_operand_value (scratchbuf + 1, 1, get64 ());
12646   oappend_maybe_intel (scratchbuf);
12647   scratchbuf[0] = '\0';
12648 }
12649
12650 static void
12651 OP_sI (int bytemode, int sizeflag)
12652 {
12653   bfd_signed_vma op;
12654
12655   switch (bytemode)
12656     {
12657     case b_mode:
12658     case b_T_mode:
12659       FETCH_DATA (the_info, codep + 1);
12660       op = *codep++;
12661       if ((op & 0x80) != 0)
12662         op -= 0x100;
12663       if (bytemode == b_T_mode)
12664         {
12665           if (address_mode != mode_64bit
12666               || !((sizeflag & DFLAG) || (rex & REX_W)))
12667             {
12668               /* The operand-size prefix is overridden by a REX prefix.  */
12669               if ((sizeflag & DFLAG) || (rex & REX_W))
12670                 op &= 0xffffffff;
12671               else
12672                 op &= 0xffff;
12673           }
12674         }
12675       else
12676         {
12677           if (!(rex & REX_W))
12678             {
12679               if (sizeflag & DFLAG)
12680                 op &= 0xffffffff;
12681               else
12682                 op &= 0xffff;
12683             }
12684         }
12685       break;
12686     case v_mode:
12687       /* The operand-size prefix is overridden by a REX prefix.  */
12688       if ((sizeflag & DFLAG) || (rex & REX_W))
12689         op = get32s ();
12690       else
12691         op = get16 ();
12692       break;
12693     default:
12694       oappend (INTERNAL_DISASSEMBLER_ERROR);
12695       return;
12696     }
12697
12698   scratchbuf[0] = '$';
12699   print_operand_value (scratchbuf + 1, 1, op);
12700   oappend_maybe_intel (scratchbuf);
12701 }
12702
12703 static void
12704 OP_J (int bytemode, int sizeflag)
12705 {
12706   bfd_vma disp;
12707   bfd_vma mask = -1;
12708   bfd_vma segment = 0;
12709
12710   switch (bytemode)
12711     {
12712     case b_mode:
12713       FETCH_DATA (the_info, codep + 1);
12714       disp = *codep++;
12715       if ((disp & 0x80) != 0)
12716         disp -= 0x100;
12717       break;
12718     case v_mode:
12719     case dqw_mode:
12720       if ((sizeflag & DFLAG)
12721           || (address_mode == mode_64bit
12722               && ((isa64 == intel64 && bytemode != dqw_mode)
12723                   || (rex & REX_W))))
12724         disp = get32s ();
12725       else
12726         {
12727           disp = get16 ();
12728           if ((disp & 0x8000) != 0)
12729             disp -= 0x10000;
12730           /* In 16bit mode, address is wrapped around at 64k within
12731              the same segment.  Otherwise, a data16 prefix on a jump
12732              instruction means that the pc is masked to 16 bits after
12733              the displacement is added!  */
12734           mask = 0xffff;
12735           if ((prefixes & PREFIX_DATA) == 0)
12736             segment = ((start_pc + (codep - start_codep))
12737                        & ~((bfd_vma) 0xffff));
12738         }
12739       if (address_mode != mode_64bit
12740           || (isa64 != intel64 && !(rex & REX_W)))
12741         used_prefixes |= (prefixes & PREFIX_DATA);
12742       break;
12743     default:
12744       oappend (INTERNAL_DISASSEMBLER_ERROR);
12745       return;
12746     }
12747   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
12748   set_op (disp, 0);
12749   print_operand_value (scratchbuf, 1, disp);
12750   oappend (scratchbuf);
12751 }
12752
12753 static void
12754 OP_SEG (int bytemode, int sizeflag)
12755 {
12756   if (bytemode == w_mode)
12757     oappend (names_seg[modrm.reg]);
12758   else
12759     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12760 }
12761
12762 static void
12763 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
12764 {
12765   int seg, offset;
12766
12767   if (sizeflag & DFLAG)
12768     {
12769       offset = get32 ();
12770       seg = get16 ();
12771     }
12772   else
12773     {
12774       offset = get16 ();
12775       seg = get16 ();
12776     }
12777   used_prefixes |= (prefixes & PREFIX_DATA);
12778   if (intel_syntax)
12779     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
12780   else
12781     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
12782   oappend (scratchbuf);
12783 }
12784
12785 static void
12786 OP_OFF (int bytemode, int sizeflag)
12787 {
12788   bfd_vma off;
12789
12790   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12791     intel_operand_size (bytemode, sizeflag);
12792   append_seg ();
12793
12794   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12795     off = get32 ();
12796   else
12797     off = get16 ();
12798
12799   if (intel_syntax)
12800     {
12801       if (!active_seg_prefix)
12802         {
12803           oappend (names_seg[ds_reg - es_reg]);
12804           oappend (":");
12805         }
12806     }
12807   print_operand_value (scratchbuf, 1, off);
12808   oappend (scratchbuf);
12809 }
12810
12811 static void
12812 OP_OFF64 (int bytemode, int sizeflag)
12813 {
12814   bfd_vma off;
12815
12816   if (address_mode != mode_64bit
12817       || (prefixes & PREFIX_ADDR))
12818     {
12819       OP_OFF (bytemode, sizeflag);
12820       return;
12821     }
12822
12823   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12824     intel_operand_size (bytemode, sizeflag);
12825   append_seg ();
12826
12827   off = get64 ();
12828
12829   if (intel_syntax)
12830     {
12831       if (!active_seg_prefix)
12832         {
12833           oappend (names_seg[ds_reg - es_reg]);
12834           oappend (":");
12835         }
12836     }
12837   print_operand_value (scratchbuf, 1, off);
12838   oappend (scratchbuf);
12839 }
12840
12841 static void
12842 ptr_reg (int code, int sizeflag)
12843 {
12844   const char *s;
12845
12846   *obufp++ = open_char;
12847   used_prefixes |= (prefixes & PREFIX_ADDR);
12848   if (address_mode == mode_64bit)
12849     {
12850       if (!(sizeflag & AFLAG))
12851         s = names32[code - eAX_reg];
12852       else
12853         s = names64[code - eAX_reg];
12854     }
12855   else if (sizeflag & AFLAG)
12856     s = names32[code - eAX_reg];
12857   else
12858     s = names16[code - eAX_reg];
12859   oappend (s);
12860   *obufp++ = close_char;
12861   *obufp = 0;
12862 }
12863
12864 static void
12865 OP_ESreg (int code, int sizeflag)
12866 {
12867   if (intel_syntax)
12868     {
12869       switch (codep[-1])
12870         {
12871         case 0x6d:      /* insw/insl */
12872           intel_operand_size (z_mode, sizeflag);
12873           break;
12874         case 0xa5:      /* movsw/movsl/movsq */
12875         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12876         case 0xab:      /* stosw/stosl */
12877         case 0xaf:      /* scasw/scasl */
12878           intel_operand_size (v_mode, sizeflag);
12879           break;
12880         default:
12881           intel_operand_size (b_mode, sizeflag);
12882         }
12883     }
12884   oappend_maybe_intel ("%es:");
12885   ptr_reg (code, sizeflag);
12886 }
12887
12888 static void
12889 OP_DSreg (int code, int sizeflag)
12890 {
12891   if (intel_syntax)
12892     {
12893       switch (codep[-1])
12894         {
12895         case 0x6f:      /* outsw/outsl */
12896           intel_operand_size (z_mode, sizeflag);
12897           break;
12898         case 0xa5:      /* movsw/movsl/movsq */
12899         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12900         case 0xad:      /* lodsw/lodsl/lodsq */
12901           intel_operand_size (v_mode, sizeflag);
12902           break;
12903         default:
12904           intel_operand_size (b_mode, sizeflag);
12905         }
12906     }
12907   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
12908      default segment register DS is printed.  */
12909   if (!active_seg_prefix)
12910     active_seg_prefix = PREFIX_DS;
12911   append_seg ();
12912   ptr_reg (code, sizeflag);
12913 }
12914
12915 static void
12916 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12917 {
12918   int add;
12919   if (rex & REX_R)
12920     {
12921       USED_REX (REX_R);
12922       add = 8;
12923     }
12924   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
12925     {
12926       all_prefixes[last_lock_prefix] = 0;
12927       used_prefixes |= PREFIX_LOCK;
12928       add = 8;
12929     }
12930   else
12931     add = 0;
12932   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
12933   oappend_maybe_intel (scratchbuf);
12934 }
12935
12936 static void
12937 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12938 {
12939   int add;
12940   USED_REX (REX_R);
12941   if (rex & REX_R)
12942     add = 8;
12943   else
12944     add = 0;
12945   if (intel_syntax)
12946     sprintf (scratchbuf, "dr%d", modrm.reg + add);
12947   else
12948     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
12949   oappend (scratchbuf);
12950 }
12951
12952 static void
12953 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12954 {
12955   sprintf (scratchbuf, "%%tr%d", modrm.reg);
12956   oappend_maybe_intel (scratchbuf);
12957 }
12958
12959 static void
12960 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12961 {
12962   int reg = modrm.reg;
12963   const char **names;
12964
12965   used_prefixes |= (prefixes & PREFIX_DATA);
12966   if (prefixes & PREFIX_DATA)
12967     {
12968       names = names_xmm;
12969       USED_REX (REX_R);
12970       if (rex & REX_R)
12971         reg += 8;
12972     }
12973   else
12974     names = names_mm;
12975   oappend (names[reg]);
12976 }
12977
12978 static void
12979 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12980 {
12981   int reg = modrm.reg;
12982   const char **names;
12983
12984   USED_REX (REX_R);
12985   if (rex & REX_R)
12986     reg += 8;
12987   if (vex.evex)
12988     {
12989       if (!vex.r)
12990         reg += 16;
12991     }
12992
12993   if (need_vex
12994       && bytemode != xmm_mode
12995       && bytemode != xmmq_mode
12996       && bytemode != evex_half_bcst_xmmq_mode
12997       && bytemode != ymm_mode
12998       && bytemode != tmm_mode
12999       && bytemode != scalar_mode)
13000     {
13001       switch (vex.length)
13002         {
13003         case 128:
13004           names = names_xmm;
13005           break;
13006         case 256:
13007           if (vex.w
13008               || (bytemode != vex_vsib_q_w_dq_mode
13009                   && bytemode != vex_vsib_q_w_d_mode))
13010             names = names_ymm;
13011           else
13012             names = names_xmm;
13013           break;
13014         case 512:
13015           names = names_zmm;
13016           break;
13017         default:
13018           abort ();
13019         }
13020     }
13021   else if (bytemode == xmmq_mode
13022            || bytemode == evex_half_bcst_xmmq_mode)
13023     {
13024       switch (vex.length)
13025         {
13026         case 128:
13027         case 256:
13028           names = names_xmm;
13029           break;
13030         case 512:
13031           names = names_ymm;
13032           break;
13033         default:
13034           abort ();
13035         }
13036     }
13037   else if (bytemode == tmm_mode)
13038     {
13039       modrm.reg = reg;
13040       if (reg >= 8)
13041         {
13042           oappend ("(bad)");
13043           return;
13044         }
13045       names = names_tmm;
13046     }
13047   else if (bytemode == ymm_mode)
13048     names = names_ymm;
13049   else
13050     names = names_xmm;
13051   oappend (names[reg]);
13052 }
13053
13054 static void
13055 OP_EM (int bytemode, int sizeflag)
13056 {
13057   int reg;
13058   const char **names;
13059
13060   if (modrm.mod != 3)
13061     {
13062       if (intel_syntax
13063           && (bytemode == v_mode || bytemode == v_swap_mode))
13064         {
13065           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
13066           used_prefixes |= (prefixes & PREFIX_DATA);
13067         }
13068       OP_E (bytemode, sizeflag);
13069       return;
13070     }
13071
13072   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
13073     swap_operand ();
13074
13075   /* Skip mod/rm byte.  */
13076   MODRM_CHECK;
13077   codep++;
13078   used_prefixes |= (prefixes & PREFIX_DATA);
13079   reg = modrm.rm;
13080   if (prefixes & PREFIX_DATA)
13081     {
13082       names = names_xmm;
13083       USED_REX (REX_B);
13084       if (rex & REX_B)
13085         reg += 8;
13086     }
13087   else
13088     names = names_mm;
13089   oappend (names[reg]);
13090 }
13091
13092 /* cvt* are the only instructions in sse2 which have
13093    both SSE and MMX operands and also have 0x66 prefix
13094    in their opcode. 0x66 was originally used to differentiate
13095    between SSE and MMX instruction(operands). So we have to handle the
13096    cvt* separately using OP_EMC and OP_MXC */
13097 static void
13098 OP_EMC (int bytemode, int sizeflag)
13099 {
13100   if (modrm.mod != 3)
13101     {
13102       if (intel_syntax && bytemode == v_mode)
13103         {
13104           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
13105           used_prefixes |= (prefixes & PREFIX_DATA);
13106         }
13107       OP_E (bytemode, sizeflag);
13108       return;
13109     }
13110
13111   /* Skip mod/rm byte.  */
13112   MODRM_CHECK;
13113   codep++;
13114   used_prefixes |= (prefixes & PREFIX_DATA);
13115   oappend (names_mm[modrm.rm]);
13116 }
13117
13118 static void
13119 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13120 {
13121   used_prefixes |= (prefixes & PREFIX_DATA);
13122   oappend (names_mm[modrm.reg]);
13123 }
13124
13125 static void
13126 OP_EX (int bytemode, int sizeflag)
13127 {
13128   int reg;
13129   const char **names;
13130
13131   /* Skip mod/rm byte.  */
13132   MODRM_CHECK;
13133   codep++;
13134
13135   if (modrm.mod != 3)
13136     {
13137       OP_E_memory (bytemode, sizeflag);
13138       return;
13139     }
13140
13141   reg = modrm.rm;
13142   USED_REX (REX_B);
13143   if (rex & REX_B)
13144     reg += 8;
13145   if (vex.evex)
13146     {
13147       USED_REX (REX_X);
13148       if ((rex & REX_X))
13149         reg += 16;
13150     }
13151
13152   if ((sizeflag & SUFFIX_ALWAYS)
13153       && (bytemode == x_swap_mode
13154           || bytemode == d_swap_mode
13155           || bytemode == q_swap_mode))
13156     swap_operand ();
13157
13158   if (need_vex
13159       && bytemode != xmm_mode
13160       && bytemode != xmmdw_mode
13161       && bytemode != xmmqd_mode
13162       && bytemode != xmm_mb_mode
13163       && bytemode != xmm_mw_mode
13164       && bytemode != xmm_md_mode
13165       && bytemode != xmm_mq_mode
13166       && bytemode != xmmq_mode
13167       && bytemode != evex_half_bcst_xmmq_mode
13168       && bytemode != ymm_mode
13169       && bytemode != tmm_mode
13170       && bytemode != vex_scalar_w_dq_mode)
13171     {
13172       switch (vex.length)
13173         {
13174         case 128:
13175           names = names_xmm;
13176           break;
13177         case 256:
13178           names = names_ymm;
13179           break;
13180         case 512:
13181           names = names_zmm;
13182           break;
13183         default:
13184           abort ();
13185         }
13186     }
13187   else if (bytemode == xmmq_mode
13188            || bytemode == evex_half_bcst_xmmq_mode)
13189     {
13190       switch (vex.length)
13191         {
13192         case 128:
13193         case 256:
13194           names = names_xmm;
13195           break;
13196         case 512:
13197           names = names_ymm;
13198           break;
13199         default:
13200           abort ();
13201         }
13202     }
13203   else if (bytemode == tmm_mode)
13204     {
13205       modrm.rm = reg;
13206       if (reg >= 8)
13207         {
13208           oappend ("(bad)");
13209           return;
13210         }
13211       names = names_tmm;
13212     }
13213   else if (bytemode == ymm_mode)
13214     names = names_ymm;
13215   else
13216     names = names_xmm;
13217   oappend (names[reg]);
13218 }
13219
13220 static void
13221 OP_MS (int bytemode, int sizeflag)
13222 {
13223   if (modrm.mod == 3)
13224     OP_EM (bytemode, sizeflag);
13225   else
13226     BadOp ();
13227 }
13228
13229 static void
13230 OP_XS (int bytemode, int sizeflag)
13231 {
13232   if (modrm.mod == 3)
13233     OP_EX (bytemode, sizeflag);
13234   else
13235     BadOp ();
13236 }
13237
13238 static void
13239 OP_M (int bytemode, int sizeflag)
13240 {
13241   if (modrm.mod == 3)
13242     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
13243     BadOp ();
13244   else
13245     OP_E (bytemode, sizeflag);
13246 }
13247
13248 static void
13249 OP_0f07 (int bytemode, int sizeflag)
13250 {
13251   if (modrm.mod != 3 || modrm.rm != 0)
13252     BadOp ();
13253   else
13254     OP_E (bytemode, sizeflag);
13255 }
13256
13257 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
13258    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
13259
13260 static void
13261 NOP_Fixup1 (int bytemode, int sizeflag)
13262 {
13263   if ((prefixes & PREFIX_DATA) != 0
13264       || (rex != 0
13265           && rex != 0x48
13266           && address_mode == mode_64bit))
13267     OP_REG (bytemode, sizeflag);
13268   else
13269     strcpy (obuf, "nop");
13270 }
13271
13272 static void
13273 NOP_Fixup2 (int bytemode, int sizeflag)
13274 {
13275   if ((prefixes & PREFIX_DATA) != 0
13276       || (rex != 0
13277           && rex != 0x48
13278           && address_mode == mode_64bit))
13279     OP_IMREG (bytemode, sizeflag);
13280 }
13281
13282 static const char *const Suffix3DNow[] = {
13283 /* 00 */        NULL,           NULL,           NULL,           NULL,
13284 /* 04 */        NULL,           NULL,           NULL,           NULL,
13285 /* 08 */        NULL,           NULL,           NULL,           NULL,
13286 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
13287 /* 10 */        NULL,           NULL,           NULL,           NULL,
13288 /* 14 */        NULL,           NULL,           NULL,           NULL,
13289 /* 18 */        NULL,           NULL,           NULL,           NULL,
13290 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
13291 /* 20 */        NULL,           NULL,           NULL,           NULL,
13292 /* 24 */        NULL,           NULL,           NULL,           NULL,
13293 /* 28 */        NULL,           NULL,           NULL,           NULL,
13294 /* 2C */        NULL,           NULL,           NULL,           NULL,
13295 /* 30 */        NULL,           NULL,           NULL,           NULL,
13296 /* 34 */        NULL,           NULL,           NULL,           NULL,
13297 /* 38 */        NULL,           NULL,           NULL,           NULL,
13298 /* 3C */        NULL,           NULL,           NULL,           NULL,
13299 /* 40 */        NULL,           NULL,           NULL,           NULL,
13300 /* 44 */        NULL,           NULL,           NULL,           NULL,
13301 /* 48 */        NULL,           NULL,           NULL,           NULL,
13302 /* 4C */        NULL,           NULL,           NULL,           NULL,
13303 /* 50 */        NULL,           NULL,           NULL,           NULL,
13304 /* 54 */        NULL,           NULL,           NULL,           NULL,
13305 /* 58 */        NULL,           NULL,           NULL,           NULL,
13306 /* 5C */        NULL,           NULL,           NULL,           NULL,
13307 /* 60 */        NULL,           NULL,           NULL,           NULL,
13308 /* 64 */        NULL,           NULL,           NULL,           NULL,
13309 /* 68 */        NULL,           NULL,           NULL,           NULL,
13310 /* 6C */        NULL,           NULL,           NULL,           NULL,
13311 /* 70 */        NULL,           NULL,           NULL,           NULL,
13312 /* 74 */        NULL,           NULL,           NULL,           NULL,
13313 /* 78 */        NULL,           NULL,           NULL,           NULL,
13314 /* 7C */        NULL,           NULL,           NULL,           NULL,
13315 /* 80 */        NULL,           NULL,           NULL,           NULL,
13316 /* 84 */        NULL,           NULL,           NULL,           NULL,
13317 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
13318 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
13319 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
13320 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
13321 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
13322 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
13323 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
13324 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
13325 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
13326 /* AC */        NULL,           NULL,           "pfacc",        NULL,
13327 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
13328 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
13329 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
13330 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
13331 /* C0 */        NULL,           NULL,           NULL,           NULL,
13332 /* C4 */        NULL,           NULL,           NULL,           NULL,
13333 /* C8 */        NULL,           NULL,           NULL,           NULL,
13334 /* CC */        NULL,           NULL,           NULL,           NULL,
13335 /* D0 */        NULL,           NULL,           NULL,           NULL,
13336 /* D4 */        NULL,           NULL,           NULL,           NULL,
13337 /* D8 */        NULL,           NULL,           NULL,           NULL,
13338 /* DC */        NULL,           NULL,           NULL,           NULL,
13339 /* E0 */        NULL,           NULL,           NULL,           NULL,
13340 /* E4 */        NULL,           NULL,           NULL,           NULL,
13341 /* E8 */        NULL,           NULL,           NULL,           NULL,
13342 /* EC */        NULL,           NULL,           NULL,           NULL,
13343 /* F0 */        NULL,           NULL,           NULL,           NULL,
13344 /* F4 */        NULL,           NULL,           NULL,           NULL,
13345 /* F8 */        NULL,           NULL,           NULL,           NULL,
13346 /* FC */        NULL,           NULL,           NULL,           NULL,
13347 };
13348
13349 static void
13350 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13351 {
13352   const char *mnemonic;
13353
13354   FETCH_DATA (the_info, codep + 1);
13355   /* AMD 3DNow! instructions are specified by an opcode suffix in the
13356      place where an 8-bit immediate would normally go.  ie. the last
13357      byte of the instruction.  */
13358   obufp = mnemonicendp;
13359   mnemonic = Suffix3DNow[*codep++ & 0xff];
13360   if (mnemonic)
13361     oappend (mnemonic);
13362   else
13363     {
13364       /* Since a variable sized modrm/sib chunk is between the start
13365          of the opcode (0x0f0f) and the opcode suffix, we need to do
13366          all the modrm processing first, and don't know until now that
13367          we have a bad opcode.  This necessitates some cleaning up.  */
13368       op_out[0][0] = '\0';
13369       op_out[1][0] = '\0';
13370       BadOp ();
13371     }
13372   mnemonicendp = obufp;
13373 }
13374
13375 static const struct op simd_cmp_op[] =
13376 {
13377   { STRING_COMMA_LEN ("eq") },
13378   { STRING_COMMA_LEN ("lt") },
13379   { STRING_COMMA_LEN ("le") },
13380   { STRING_COMMA_LEN ("unord") },
13381   { STRING_COMMA_LEN ("neq") },
13382   { STRING_COMMA_LEN ("nlt") },
13383   { STRING_COMMA_LEN ("nle") },
13384   { STRING_COMMA_LEN ("ord") }
13385 };
13386
13387 static const struct op vex_cmp_op[] =
13388 {
13389   { STRING_COMMA_LEN ("eq_uq") },
13390   { STRING_COMMA_LEN ("nge") },
13391   { STRING_COMMA_LEN ("ngt") },
13392   { STRING_COMMA_LEN ("false") },
13393   { STRING_COMMA_LEN ("neq_oq") },
13394   { STRING_COMMA_LEN ("ge") },
13395   { STRING_COMMA_LEN ("gt") },
13396   { STRING_COMMA_LEN ("true") },
13397   { STRING_COMMA_LEN ("eq_os") },
13398   { STRING_COMMA_LEN ("lt_oq") },
13399   { STRING_COMMA_LEN ("le_oq") },
13400   { STRING_COMMA_LEN ("unord_s") },
13401   { STRING_COMMA_LEN ("neq_us") },
13402   { STRING_COMMA_LEN ("nlt_uq") },
13403   { STRING_COMMA_LEN ("nle_uq") },
13404   { STRING_COMMA_LEN ("ord_s") },
13405   { STRING_COMMA_LEN ("eq_us") },
13406   { STRING_COMMA_LEN ("nge_uq") },
13407   { STRING_COMMA_LEN ("ngt_uq") },
13408   { STRING_COMMA_LEN ("false_os") },
13409   { STRING_COMMA_LEN ("neq_os") },
13410   { STRING_COMMA_LEN ("ge_oq") },
13411   { STRING_COMMA_LEN ("gt_oq") },
13412   { STRING_COMMA_LEN ("true_us") },
13413 };
13414
13415 static void
13416 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13417 {
13418   unsigned int cmp_type;
13419
13420   FETCH_DATA (the_info, codep + 1);
13421   cmp_type = *codep++ & 0xff;
13422   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
13423     {
13424       char suffix [3];
13425       char *p = mnemonicendp - 2;
13426       suffix[0] = p[0];
13427       suffix[1] = p[1];
13428       suffix[2] = '\0';
13429       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13430       mnemonicendp += simd_cmp_op[cmp_type].len;
13431     }
13432   else if (need_vex
13433            && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
13434     {
13435       char suffix [3];
13436       char *p = mnemonicendp - 2;
13437       suffix[0] = p[0];
13438       suffix[1] = p[1];
13439       suffix[2] = '\0';
13440       cmp_type -= ARRAY_SIZE (simd_cmp_op);
13441       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13442       mnemonicendp += vex_cmp_op[cmp_type].len;
13443     }
13444   else
13445     {
13446       /* We have a reserved extension byte.  Output it directly.  */
13447       scratchbuf[0] = '$';
13448       print_operand_value (scratchbuf + 1, 1, cmp_type);
13449       oappend_maybe_intel (scratchbuf);
13450       scratchbuf[0] = '\0';
13451     }
13452 }
13453
13454 static void
13455 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13456 {
13457   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
13458   if (!intel_syntax)
13459     {
13460       strcpy (op_out[0], names32[0]);
13461       strcpy (op_out[1], names32[1]);
13462       if (bytemode == eBX_reg)
13463         strcpy (op_out[2], names32[3]);
13464       two_source_ops = 1;
13465     }
13466   /* Skip mod/rm byte.  */
13467   MODRM_CHECK;
13468   codep++;
13469 }
13470
13471 static void
13472 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
13473             int sizeflag ATTRIBUTE_UNUSED)
13474 {
13475   /* monitor %{e,r,}ax,%ecx,%edx"  */
13476   if (!intel_syntax)
13477     {
13478       const char **names = (address_mode == mode_64bit
13479                             ? names64 : names32);
13480
13481       if (prefixes & PREFIX_ADDR)
13482         {
13483           /* Remove "addr16/addr32".  */
13484           all_prefixes[last_addr_prefix] = 0;
13485           names = (address_mode != mode_32bit
13486                    ? names32 : names16);
13487           used_prefixes |= PREFIX_ADDR;
13488         }
13489       else if (address_mode == mode_16bit)
13490         names = names16;
13491       strcpy (op_out[0], names[0]);
13492       strcpy (op_out[1], names32[1]);
13493       strcpy (op_out[2], names32[2]);
13494       two_source_ops = 1;
13495     }
13496   /* Skip mod/rm byte.  */
13497   MODRM_CHECK;
13498   codep++;
13499 }
13500
13501 static void
13502 BadOp (void)
13503 {
13504   /* Throw away prefixes and 1st. opcode byte.  */
13505   codep = insn_codep + 1;
13506   oappend ("(bad)");
13507 }
13508
13509 static void
13510 REP_Fixup (int bytemode, int sizeflag)
13511 {
13512   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13513      lods and stos.  */
13514   if (prefixes & PREFIX_REPZ)
13515     all_prefixes[last_repz_prefix] = REP_PREFIX;
13516
13517   switch (bytemode)
13518     {
13519     case al_reg:
13520     case eAX_reg:
13521     case indir_dx_reg:
13522       OP_IMREG (bytemode, sizeflag);
13523       break;
13524     case eDI_reg:
13525       OP_ESreg (bytemode, sizeflag);
13526       break;
13527     case eSI_reg:
13528       OP_DSreg (bytemode, sizeflag);
13529       break;
13530     default:
13531       abort ();
13532       break;
13533     }
13534 }
13535
13536 static void
13537 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13538 {
13539   if ( isa64 != amd64 )
13540     return;
13541
13542   obufp = obuf;
13543   BadOp ();
13544   mnemonicendp = obufp;
13545   ++codep;
13546 }
13547
13548 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13549    "bnd".  */
13550
13551 static void
13552 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13553 {
13554   if (prefixes & PREFIX_REPNZ)
13555     all_prefixes[last_repnz_prefix] = BND_PREFIX;
13556 }
13557
13558 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13559    "notrack".  */
13560
13561 static void
13562 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
13563                int sizeflag ATTRIBUTE_UNUSED)
13564 {
13565   if (active_seg_prefix == PREFIX_DS
13566       && (address_mode != mode_64bit || last_data_prefix < 0))
13567     {
13568       /* NOTRACK prefix is only valid on indirect branch instructions.
13569          NB: DATA prefix is unsupported for Intel64.  */
13570       active_seg_prefix = 0;
13571       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
13572     }
13573 }
13574
13575 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
13576    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13577  */
13578
13579 static void
13580 HLE_Fixup1 (int bytemode, int sizeflag)
13581 {
13582   if (modrm.mod != 3
13583       && (prefixes & PREFIX_LOCK) != 0)
13584     {
13585       if (prefixes & PREFIX_REPZ)
13586         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13587       if (prefixes & PREFIX_REPNZ)
13588         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13589     }
13590
13591   OP_E (bytemode, sizeflag);
13592 }
13593
13594 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
13595    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
13596  */
13597
13598 static void
13599 HLE_Fixup2 (int bytemode, int sizeflag)
13600 {
13601   if (modrm.mod != 3)
13602     {
13603       if (prefixes & PREFIX_REPZ)
13604         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13605       if (prefixes & PREFIX_REPNZ)
13606         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13607     }
13608
13609   OP_E (bytemode, sizeflag);
13610 }
13611
13612 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
13613    "xrelease" for memory operand.  No check for LOCK prefix.   */
13614
13615 static void
13616 HLE_Fixup3 (int bytemode, int sizeflag)
13617 {
13618   if (modrm.mod != 3
13619       && last_repz_prefix > last_repnz_prefix
13620       && (prefixes & PREFIX_REPZ) != 0)
13621     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13622
13623   OP_E (bytemode, sizeflag);
13624 }
13625
13626 static void
13627 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
13628 {
13629   USED_REX (REX_W);
13630   if (rex & REX_W)
13631     {
13632       /* Change cmpxchg8b to cmpxchg16b.  */
13633       char *p = mnemonicendp - 2;
13634       mnemonicendp = stpcpy (p, "16b");
13635       bytemode = o_mode;
13636     }
13637   else if ((prefixes & PREFIX_LOCK) != 0)
13638     {
13639       if (prefixes & PREFIX_REPZ)
13640         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13641       if (prefixes & PREFIX_REPNZ)
13642         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13643     }
13644
13645   OP_M (bytemode, sizeflag);
13646 }
13647
13648 static void
13649 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
13650 {
13651   const char **names;
13652
13653   if (need_vex)
13654     {
13655       switch (vex.length)
13656         {
13657         case 128:
13658           names = names_xmm;
13659           break;
13660         case 256:
13661           names = names_ymm;
13662           break;
13663         default:
13664           abort ();
13665         }
13666     }
13667   else
13668     names = names_xmm;
13669   oappend (names[reg]);
13670 }
13671
13672 static void
13673 FXSAVE_Fixup (int bytemode, int sizeflag)
13674 {
13675   /* Add proper suffix to "fxsave" and "fxrstor".  */
13676   USED_REX (REX_W);
13677   if (rex & REX_W)
13678     {
13679       char *p = mnemonicendp;
13680       *p++ = '6';
13681       *p++ = '4';
13682       *p = '\0';
13683       mnemonicendp = p;
13684     }
13685   OP_M (bytemode, sizeflag);
13686 }
13687
13688 /* Display the destination register operand for instructions with
13689    VEX. */
13690
13691 static void
13692 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13693 {
13694   int reg;
13695   const char **names;
13696
13697   if (!need_vex)
13698     abort ();
13699
13700   reg = vex.register_specifier;
13701   vex.register_specifier = 0;
13702   if (address_mode != mode_64bit)
13703     reg &= 7;
13704   else if (vex.evex && !vex.v)
13705     reg += 16;
13706
13707   if (bytemode == vex_scalar_mode)
13708     {
13709       oappend (names_xmm[reg]);
13710       return;
13711     }
13712
13713   if (bytemode == tmm_mode)
13714     {
13715       /* All 3 TMM registers must be distinct.  */
13716       if (reg >= 8)
13717         oappend ("(bad)");
13718       else
13719         {
13720           /* This must be the 3rd operand.  */
13721           if (obufp != op_out[2])
13722             abort ();
13723           oappend (names_tmm[reg]);
13724           if (reg == modrm.reg || reg == modrm.rm)
13725             strcpy (obufp, "/(bad)");
13726         }
13727
13728       if (modrm.reg == modrm.rm || modrm.reg == reg || modrm.rm == reg)
13729         {
13730           if (modrm.reg <= 8
13731               && (modrm.reg == modrm.rm || modrm.reg == reg))
13732             strcat (op_out[0], "/(bad)");
13733           if (modrm.rm <= 8
13734               && (modrm.rm == modrm.reg || modrm.rm == reg))
13735             strcat (op_out[1], "/(bad)");
13736         }
13737
13738       return;
13739     }
13740
13741   switch (vex.length)
13742     {
13743     case 128:
13744       switch (bytemode)
13745         {
13746         case vex_mode:
13747         case vex_vsib_q_w_dq_mode:
13748         case vex_vsib_q_w_d_mode:
13749           names = names_xmm;
13750           break;
13751         case dq_mode:
13752           if (rex & REX_W)
13753             names = names64;
13754           else
13755             names = names32;
13756           break;
13757         case mask_bd_mode:
13758         case mask_mode:
13759           if (reg > 0x7)
13760             {
13761               oappend ("(bad)");
13762               return;
13763             }
13764           names = names_mask;
13765           break;
13766         default:
13767           abort ();
13768           return;
13769         }
13770       break;
13771     case 256:
13772       switch (bytemode)
13773         {
13774         case vex_mode:
13775           names = names_ymm;
13776           break;
13777         case vex_vsib_q_w_dq_mode:
13778         case vex_vsib_q_w_d_mode:
13779           names = vex.w ? names_ymm : names_xmm;
13780           break;
13781         case mask_bd_mode:
13782         case mask_mode:
13783           if (reg > 0x7)
13784             {
13785               oappend ("(bad)");
13786               return;
13787             }
13788           names = names_mask;
13789           break;
13790         default:
13791           /* See PR binutils/20893 for a reproducer.  */
13792           oappend ("(bad)");
13793           return;
13794         }
13795       break;
13796     case 512:
13797       names = names_zmm;
13798       break;
13799     default:
13800       abort ();
13801       break;
13802     }
13803   oappend (names[reg]);
13804 }
13805
13806 static void
13807 OP_VexR (int bytemode, int sizeflag)
13808 {
13809   if (modrm.mod == 3)
13810     OP_VEX (bytemode, sizeflag);
13811 }
13812
13813 static void
13814 OP_VexW (int bytemode, int sizeflag)
13815 {
13816   OP_VEX (bytemode, sizeflag);
13817
13818   if (vex.w)
13819     {
13820       /* Swap 2nd and 3rd operands.  */
13821       strcpy (scratchbuf, op_out[2]);
13822       strcpy (op_out[2], op_out[1]);
13823       strcpy (op_out[1], scratchbuf);
13824     }
13825 }
13826
13827 static void
13828 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13829 {
13830   int reg;
13831   const char **names = names_xmm;
13832
13833   FETCH_DATA (the_info, codep + 1);
13834   reg = *codep++;
13835
13836   if (bytemode != x_mode && bytemode != scalar_mode)
13837     abort ();
13838
13839   reg >>= 4;
13840   if (address_mode != mode_64bit)
13841     reg &= 7;
13842
13843   if (bytemode == x_mode && vex.length == 256)
13844     names = names_ymm;
13845
13846   oappend (names[reg]);
13847
13848   if (vex.w)
13849     {
13850       /* Swap 3rd and 4th operands.  */
13851       strcpy (scratchbuf, op_out[3]);
13852       strcpy (op_out[3], op_out[2]);
13853       strcpy (op_out[2], scratchbuf);
13854     }
13855 }
13856
13857 static void
13858 OP_VexI4 (int bytemode ATTRIBUTE_UNUSED,
13859           int sizeflag ATTRIBUTE_UNUSED)
13860 {
13861   scratchbuf[0] = '$';
13862   print_operand_value (scratchbuf + 1, 1, codep[-1] & 0xf);
13863   oappend_maybe_intel (scratchbuf);
13864 }
13865
13866 static void
13867 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
13868              int sizeflag ATTRIBUTE_UNUSED)
13869 {
13870   unsigned int cmp_type;
13871
13872   if (!vex.evex)
13873     abort ();
13874
13875   FETCH_DATA (the_info, codep + 1);
13876   cmp_type = *codep++ & 0xff;
13877   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13878      If it's the case, print suffix, otherwise - print the immediate.  */
13879   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
13880       && cmp_type != 3
13881       && cmp_type != 7)
13882     {
13883       char suffix [3];
13884       char *p = mnemonicendp - 2;
13885
13886       /* vpcmp* can have both one- and two-lettered suffix.  */
13887       if (p[0] == 'p')
13888         {
13889           p++;
13890           suffix[0] = p[0];
13891           suffix[1] = '\0';
13892         }
13893       else
13894         {
13895           suffix[0] = p[0];
13896           suffix[1] = p[1];
13897           suffix[2] = '\0';
13898         }
13899
13900       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13901       mnemonicendp += simd_cmp_op[cmp_type].len;
13902     }
13903   else
13904     {
13905       /* We have a reserved extension byte.  Output it directly.  */
13906       scratchbuf[0] = '$';
13907       print_operand_value (scratchbuf + 1, 1, cmp_type);
13908       oappend_maybe_intel (scratchbuf);
13909       scratchbuf[0] = '\0';
13910     }
13911 }
13912
13913 static const struct op xop_cmp_op[] =
13914 {
13915   { STRING_COMMA_LEN ("lt") },
13916   { STRING_COMMA_LEN ("le") },
13917   { STRING_COMMA_LEN ("gt") },
13918   { STRING_COMMA_LEN ("ge") },
13919   { STRING_COMMA_LEN ("eq") },
13920   { STRING_COMMA_LEN ("neq") },
13921   { STRING_COMMA_LEN ("false") },
13922   { STRING_COMMA_LEN ("true") }
13923 };
13924
13925 static void
13926 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
13927              int sizeflag ATTRIBUTE_UNUSED)
13928 {
13929   unsigned int cmp_type;
13930
13931   FETCH_DATA (the_info, codep + 1);
13932   cmp_type = *codep++ & 0xff;
13933   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
13934     {
13935       char suffix[3];
13936       char *p = mnemonicendp - 2;
13937
13938       /* vpcom* can have both one- and two-lettered suffix.  */
13939       if (p[0] == 'm')
13940         {
13941           p++;
13942           suffix[0] = p[0];
13943           suffix[1] = '\0';
13944         }
13945       else
13946         {
13947           suffix[0] = p[0];
13948           suffix[1] = p[1];
13949           suffix[2] = '\0';
13950         }
13951
13952       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
13953       mnemonicendp += xop_cmp_op[cmp_type].len;
13954     }
13955   else
13956     {
13957       /* We have a reserved extension byte.  Output it directly.  */
13958       scratchbuf[0] = '$';
13959       print_operand_value (scratchbuf + 1, 1, cmp_type);
13960       oappend_maybe_intel (scratchbuf);
13961       scratchbuf[0] = '\0';
13962     }
13963 }
13964
13965 static const struct op pclmul_op[] =
13966 {
13967   { STRING_COMMA_LEN ("lql") },
13968   { STRING_COMMA_LEN ("hql") },
13969   { STRING_COMMA_LEN ("lqh") },
13970   { STRING_COMMA_LEN ("hqh") }
13971 };
13972
13973 static void
13974 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
13975               int sizeflag ATTRIBUTE_UNUSED)
13976 {
13977   unsigned int pclmul_type;
13978
13979   FETCH_DATA (the_info, codep + 1);
13980   pclmul_type = *codep++ & 0xff;
13981   switch (pclmul_type)
13982     {
13983     case 0x10:
13984       pclmul_type = 2;
13985       break;
13986     case 0x11:
13987       pclmul_type = 3;
13988       break;
13989     default:
13990       break;
13991     }
13992   if (pclmul_type < ARRAY_SIZE (pclmul_op))
13993     {
13994       char suffix [4];
13995       char *p = mnemonicendp - 3;
13996       suffix[0] = p[0];
13997       suffix[1] = p[1];
13998       suffix[2] = p[2];
13999       suffix[3] = '\0';
14000       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
14001       mnemonicendp += pclmul_op[pclmul_type].len;
14002     }
14003   else
14004     {
14005       /* We have a reserved extension byte.  Output it directly.  */
14006       scratchbuf[0] = '$';
14007       print_operand_value (scratchbuf + 1, 1, pclmul_type);
14008       oappend_maybe_intel (scratchbuf);
14009       scratchbuf[0] = '\0';
14010     }
14011 }
14012
14013 static void
14014 MOVSXD_Fixup (int bytemode, int sizeflag)
14015 {
14016   /* Add proper suffix to "movsxd".  */
14017   char *p = mnemonicendp;
14018
14019   switch (bytemode)
14020     {
14021     case movsxd_mode:
14022       if (intel_syntax)
14023         {
14024           *p++ = 'x';
14025           *p++ = 'd';
14026           goto skip;
14027         }
14028
14029       USED_REX (REX_W);
14030       if (rex & REX_W)
14031         {
14032           *p++ = 'l';
14033           *p++ = 'q';
14034         }
14035       else
14036         {
14037           *p++ = 'x';
14038           *p++ = 'd';
14039         }
14040       break;
14041     default:
14042       oappend (INTERNAL_DISASSEMBLER_ERROR);
14043       break;
14044     }
14045
14046  skip:
14047   mnemonicendp = p;
14048   *p = '\0';
14049   OP_E (bytemode, sizeflag);
14050 }
14051
14052 static void
14053 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14054 {
14055   if (!vex.evex
14056       || (bytemode != mask_mode && bytemode != mask_bd_mode))
14057     abort ();
14058
14059   USED_REX (REX_R);
14060   if ((rex & REX_R) != 0 || !vex.r)
14061     {
14062       BadOp ();
14063       return;
14064     }
14065
14066   oappend (names_mask [modrm.reg]);
14067 }
14068
14069 static void
14070 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14071 {
14072   if (modrm.mod == 3 && vex.b)
14073     switch (bytemode)
14074       {
14075       case evex_rounding_64_mode:
14076         if (address_mode != mode_64bit)
14077           {
14078             oappend ("(bad)");
14079             break;
14080           }
14081         /* Fall through.  */
14082       case evex_rounding_mode:
14083         oappend (names_rounding[vex.ll]);
14084         break;
14085       case evex_sae_mode:
14086         oappend ("{sae}");
14087         break;
14088       default:
14089         abort ();
14090         break;
14091       }
14092 }