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x86: re-arrange order of decode for various EVEX opcodes
[deliverable/binutils-gdb.git] / opcodes / i386-dis.c
1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2021 Free Software Foundation, Inc.
3
4 This file is part of the GNU opcodes library.
5
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
21
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
23 July 1988
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
27
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
34
35 #include "sysdep.h"
36 #include "disassemble.h"
37 #include "opintl.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
40 #include "safe-ctype.h"
41
42 #include <setjmp.h>
43
44 static int print_insn (bfd_vma, disassemble_info *);
45 static void dofloat (int);
46 static void OP_ST (int, int);
47 static void OP_STi (int, int);
48 static int putop (const char *, int);
49 static void oappend (const char *);
50 static void append_seg (void);
51 static void OP_indirE (int, int);
52 static void print_operand_value (char *, int, bfd_vma);
53 static void OP_E_register (int, int);
54 static void OP_E_memory (int, int);
55 static void print_displacement (char *, bfd_vma);
56 static void OP_E (int, int);
57 static void OP_G (int, int);
58 static bfd_vma get64 (void);
59 static bfd_signed_vma get32 (void);
60 static bfd_signed_vma get32s (void);
61 static int get16 (void);
62 static void set_op (bfd_vma, int);
63 static void OP_Skip_MODRM (int, int);
64 static void OP_REG (int, int);
65 static void OP_IMREG (int, int);
66 static void OP_I (int, int);
67 static void OP_I64 (int, int);
68 static void OP_sI (int, int);
69 static void OP_J (int, int);
70 static void OP_SEG (int, int);
71 static void OP_DIR (int, int);
72 static void OP_OFF (int, int);
73 static void OP_OFF64 (int, int);
74 static void ptr_reg (int, int);
75 static void OP_ESreg (int, int);
76 static void OP_DSreg (int, int);
77 static void OP_C (int, int);
78 static void OP_D (int, int);
79 static void OP_T (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_VexR (int, int);
91 static void OP_VexW (int, int);
92 static void OP_Rounding (int, int);
93 static void OP_REG_VexI4 (int, int);
94 static void OP_VexI4 (int, int);
95 static void PCLMUL_Fixup (int, int);
96 static void VPCMP_Fixup (int, int);
97 static void VPCOM_Fixup (int, int);
98 static void OP_0f07 (int, int);
99 static void OP_Monitor (int, int);
100 static void OP_Mwait (int, int);
101 static void NOP_Fixup1 (int, int);
102 static void NOP_Fixup2 (int, int);
103 static void OP_3DNowSuffix (int, int);
104 static void CMP_Fixup (int, int);
105 static void BadOp (void);
106 static void REP_Fixup (int, int);
107 static void SEP_Fixup (int, int);
108 static void BND_Fixup (int, int);
109 static void NOTRACK_Fixup (int, int);
110 static void HLE_Fixup1 (int, int);
111 static void HLE_Fixup2 (int, int);
112 static void HLE_Fixup3 (int, int);
113 static void CMPXCHG8B_Fixup (int, int);
114 static void XMM_Fixup (int, int);
115 static void FXSAVE_Fixup (int, int);
116
117 static void MOVSXD_Fixup (int, int);
118
119 static void OP_Mask (int, int);
120
121 struct dis_private {
122 /* Points to first byte not fetched. */
123 bfd_byte *max_fetched;
124 bfd_byte the_buffer[MAX_MNEM_SIZE];
125 bfd_vma insn_start;
126 int orig_sizeflag;
127 OPCODES_SIGJMP_BUF bailout;
128 };
129
130 enum address_mode
131 {
132 mode_16bit,
133 mode_32bit,
134 mode_64bit
135 };
136
137 enum address_mode address_mode;
138
139 /* Flags for the prefixes for the current instruction. See below. */
140 static int prefixes;
141
142 /* REX prefix the current instruction. See below. */
143 static int rex;
144 /* Bits of REX we've already used. */
145 static int rex_used;
146 /* Mark parts used in the REX prefix. When we are testing for
147 empty prefix (for 8bit register REX extension), just mask it
148 out. Otherwise test for REX bit is excuse for existence of REX
149 only in case value is nonzero. */
150 #define USED_REX(value) \
151 { \
152 if (value) \
153 { \
154 if ((rex & value)) \
155 rex_used |= (value) | REX_OPCODE; \
156 } \
157 else \
158 rex_used |= REX_OPCODE; \
159 }
160
161 /* Flags for prefixes which we somehow handled when printing the
162 current instruction. */
163 static int used_prefixes;
164
165 /* Flags stored in PREFIXES. */
166 #define PREFIX_REPZ 1
167 #define PREFIX_REPNZ 2
168 #define PREFIX_LOCK 4
169 #define PREFIX_CS 8
170 #define PREFIX_SS 0x10
171 #define PREFIX_DS 0x20
172 #define PREFIX_ES 0x40
173 #define PREFIX_FS 0x80
174 #define PREFIX_GS 0x100
175 #define PREFIX_DATA 0x200
176 #define PREFIX_ADDR 0x400
177 #define PREFIX_FWAIT 0x800
178
179 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
180 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
181 on error. */
182 #define FETCH_DATA(info, addr) \
183 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
184 ? 1 : fetch_data ((info), (addr)))
185
186 static int
187 fetch_data (struct disassemble_info *info, bfd_byte *addr)
188 {
189 int status;
190 struct dis_private *priv = (struct dis_private *) info->private_data;
191 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
192
193 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
194 status = (*info->read_memory_func) (start,
195 priv->max_fetched,
196 addr - priv->max_fetched,
197 info);
198 else
199 status = -1;
200 if (status != 0)
201 {
202 /* If we did manage to read at least one byte, then
203 print_insn_i386 will do something sensible. Otherwise, print
204 an error. We do that here because this is where we know
205 STATUS. */
206 if (priv->max_fetched == priv->the_buffer)
207 (*info->memory_error_func) (status, start, info);
208 OPCODES_SIGLONGJMP (priv->bailout, 1);
209 }
210 else
211 priv->max_fetched = addr;
212 return 1;
213 }
214
215 /* Possible values for prefix requirement. */
216 #define PREFIX_IGNORED_SHIFT 16
217 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
218 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
219 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
220 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
221 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
222
223 /* Opcode prefixes. */
224 #define PREFIX_OPCODE (PREFIX_REPZ \
225 | PREFIX_REPNZ \
226 | PREFIX_DATA)
227
228 /* Prefixes ignored. */
229 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
230 | PREFIX_IGNORED_REPNZ \
231 | PREFIX_IGNORED_DATA)
232
233 #define XX { NULL, 0 }
234 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
235
236 #define Eb { OP_E, b_mode }
237 #define Ebnd { OP_E, bnd_mode }
238 #define EbS { OP_E, b_swap_mode }
239 #define EbndS { OP_E, bnd_swap_mode }
240 #define Ev { OP_E, v_mode }
241 #define Eva { OP_E, va_mode }
242 #define Ev_bnd { OP_E, v_bnd_mode }
243 #define EvS { OP_E, v_swap_mode }
244 #define Ed { OP_E, d_mode }
245 #define Edq { OP_E, dq_mode }
246 #define Edqw { OP_E, dqw_mode }
247 #define Edqb { OP_E, dqb_mode }
248 #define Edb { OP_E, db_mode }
249 #define Edw { OP_E, dw_mode }
250 #define Edqd { OP_E, dqd_mode }
251 #define Eq { OP_E, q_mode }
252 #define indirEv { OP_indirE, indir_v_mode }
253 #define indirEp { OP_indirE, f_mode }
254 #define stackEv { OP_E, stack_v_mode }
255 #define Em { OP_E, m_mode }
256 #define Ew { OP_E, w_mode }
257 #define M { OP_M, 0 } /* lea, lgdt, etc. */
258 #define Ma { OP_M, a_mode }
259 #define Mb { OP_M, b_mode }
260 #define Md { OP_M, d_mode }
261 #define Mo { OP_M, o_mode }
262 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
263 #define Mq { OP_M, q_mode }
264 #define Mv { OP_M, v_mode }
265 #define Mv_bnd { OP_M, v_bndmk_mode }
266 #define Mx { OP_M, x_mode }
267 #define Mxmm { OP_M, xmm_mode }
268 #define Gb { OP_G, b_mode }
269 #define Gbnd { OP_G, bnd_mode }
270 #define Gv { OP_G, v_mode }
271 #define Gd { OP_G, d_mode }
272 #define Gdq { OP_G, dq_mode }
273 #define Gm { OP_G, m_mode }
274 #define Gva { OP_G, va_mode }
275 #define Gw { OP_G, w_mode }
276 #define Ib { OP_I, b_mode }
277 #define sIb { OP_sI, b_mode } /* sign extened byte */
278 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
279 #define Iv { OP_I, v_mode }
280 #define sIv { OP_sI, v_mode }
281 #define Iv64 { OP_I64, v_mode }
282 #define Id { OP_I, d_mode }
283 #define Iw { OP_I, w_mode }
284 #define I1 { OP_I, const_1_mode }
285 #define Jb { OP_J, b_mode }
286 #define Jv { OP_J, v_mode }
287 #define Jdqw { OP_J, dqw_mode }
288 #define Cm { OP_C, m_mode }
289 #define Dm { OP_D, m_mode }
290 #define Td { OP_T, d_mode }
291 #define Skip_MODRM { OP_Skip_MODRM, 0 }
292
293 #define RMeAX { OP_REG, eAX_reg }
294 #define RMeBX { OP_REG, eBX_reg }
295 #define RMeCX { OP_REG, eCX_reg }
296 #define RMeDX { OP_REG, eDX_reg }
297 #define RMeSP { OP_REG, eSP_reg }
298 #define RMeBP { OP_REG, eBP_reg }
299 #define RMeSI { OP_REG, eSI_reg }
300 #define RMeDI { OP_REG, eDI_reg }
301 #define RMrAX { OP_REG, rAX_reg }
302 #define RMrBX { OP_REG, rBX_reg }
303 #define RMrCX { OP_REG, rCX_reg }
304 #define RMrDX { OP_REG, rDX_reg }
305 #define RMrSP { OP_REG, rSP_reg }
306 #define RMrBP { OP_REG, rBP_reg }
307 #define RMrSI { OP_REG, rSI_reg }
308 #define RMrDI { OP_REG, rDI_reg }
309 #define RMAL { OP_REG, al_reg }
310 #define RMCL { OP_REG, cl_reg }
311 #define RMDL { OP_REG, dl_reg }
312 #define RMBL { OP_REG, bl_reg }
313 #define RMAH { OP_REG, ah_reg }
314 #define RMCH { OP_REG, ch_reg }
315 #define RMDH { OP_REG, dh_reg }
316 #define RMBH { OP_REG, bh_reg }
317 #define RMAX { OP_REG, ax_reg }
318 #define RMDX { OP_REG, dx_reg }
319
320 #define eAX { OP_IMREG, eAX_reg }
321 #define AL { OP_IMREG, al_reg }
322 #define CL { OP_IMREG, cl_reg }
323 #define zAX { OP_IMREG, z_mode_ax_reg }
324 #define indirDX { OP_IMREG, indir_dx_reg }
325
326 #define Sw { OP_SEG, w_mode }
327 #define Sv { OP_SEG, v_mode }
328 #define Ap { OP_DIR, 0 }
329 #define Ob { OP_OFF64, b_mode }
330 #define Ov { OP_OFF64, v_mode }
331 #define Xb { OP_DSreg, eSI_reg }
332 #define Xv { OP_DSreg, eSI_reg }
333 #define Xz { OP_DSreg, eSI_reg }
334 #define Yb { OP_ESreg, eDI_reg }
335 #define Yv { OP_ESreg, eDI_reg }
336 #define DSBX { OP_DSreg, eBX_reg }
337
338 #define es { OP_REG, es_reg }
339 #define ss { OP_REG, ss_reg }
340 #define cs { OP_REG, cs_reg }
341 #define ds { OP_REG, ds_reg }
342 #define fs { OP_REG, fs_reg }
343 #define gs { OP_REG, gs_reg }
344
345 #define MX { OP_MMX, 0 }
346 #define XM { OP_XMM, 0 }
347 #define XMScalar { OP_XMM, scalar_mode }
348 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
349 #define XMM { OP_XMM, xmm_mode }
350 #define TMM { OP_XMM, tmm_mode }
351 #define XMxmmq { OP_XMM, xmmq_mode }
352 #define EM { OP_EM, v_mode }
353 #define EMS { OP_EM, v_swap_mode }
354 #define EMd { OP_EM, d_mode }
355 #define EMx { OP_EM, x_mode }
356 #define EXbwUnit { OP_EX, bw_unit_mode }
357 #define EXw { OP_EX, w_mode }
358 #define EXd { OP_EX, d_mode }
359 #define EXdS { OP_EX, d_swap_mode }
360 #define EXq { OP_EX, q_mode }
361 #define EXqS { OP_EX, q_swap_mode }
362 #define EXx { OP_EX, x_mode }
363 #define EXxS { OP_EX, x_swap_mode }
364 #define EXxmm { OP_EX, xmm_mode }
365 #define EXymm { OP_EX, ymm_mode }
366 #define EXtmm { OP_EX, tmm_mode }
367 #define EXxmmq { OP_EX, xmmq_mode }
368 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
369 #define EXxmm_mb { OP_EX, xmm_mb_mode }
370 #define EXxmm_mw { OP_EX, xmm_mw_mode }
371 #define EXxmm_md { OP_EX, xmm_md_mode }
372 #define EXxmm_mq { OP_EX, xmm_mq_mode }
373 #define EXxmmdw { OP_EX, xmmdw_mode }
374 #define EXxmmqd { OP_EX, xmmqd_mode }
375 #define EXymmq { OP_EX, ymmq_mode }
376 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
377 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
378 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
379 #define MS { OP_MS, v_mode }
380 #define XS { OP_XS, v_mode }
381 #define EMCq { OP_EMC, q_mode }
382 #define MXC { OP_MXC, 0 }
383 #define OPSUF { OP_3DNowSuffix, 0 }
384 #define SEP { SEP_Fixup, 0 }
385 #define CMP { CMP_Fixup, 0 }
386 #define XMM0 { XMM_Fixup, 0 }
387 #define FXSAVE { FXSAVE_Fixup, 0 }
388
389 #define Vex { OP_VEX, vex_mode }
390 #define VexW { OP_VexW, vex_mode }
391 #define VexScalar { OP_VEX, vex_scalar_mode }
392 #define VexScalarR { OP_VexR, vex_scalar_mode }
393 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
394 #define VexGdq { OP_VEX, dq_mode }
395 #define VexTmm { OP_VEX, tmm_mode }
396 #define XMVexI4 { OP_REG_VexI4, x_mode }
397 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
398 #define VexI4 { OP_VexI4, 0 }
399 #define PCLMUL { PCLMUL_Fixup, 0 }
400 #define VPCMP { VPCMP_Fixup, 0 }
401 #define VPCOM { VPCOM_Fixup, 0 }
402
403 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
404 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
405 #define EXxEVexS { OP_Rounding, evex_sae_mode }
406
407 #define XMask { OP_Mask, mask_mode }
408 #define MaskG { OP_G, mask_mode }
409 #define MaskE { OP_E, mask_mode }
410 #define MaskBDE { OP_E, mask_bd_mode }
411 #define MaskVex { OP_VEX, mask_mode }
412
413 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
414 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
415 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
416 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
417
418 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
419
420 /* Used handle "rep" prefix for string instructions. */
421 #define Xbr { REP_Fixup, eSI_reg }
422 #define Xvr { REP_Fixup, eSI_reg }
423 #define Ybr { REP_Fixup, eDI_reg }
424 #define Yvr { REP_Fixup, eDI_reg }
425 #define Yzr { REP_Fixup, eDI_reg }
426 #define indirDXr { REP_Fixup, indir_dx_reg }
427 #define ALr { REP_Fixup, al_reg }
428 #define eAXr { REP_Fixup, eAX_reg }
429
430 /* Used handle HLE prefix for lockable instructions. */
431 #define Ebh1 { HLE_Fixup1, b_mode }
432 #define Evh1 { HLE_Fixup1, v_mode }
433 #define Ebh2 { HLE_Fixup2, b_mode }
434 #define Evh2 { HLE_Fixup2, v_mode }
435 #define Ebh3 { HLE_Fixup3, b_mode }
436 #define Evh3 { HLE_Fixup3, v_mode }
437
438 #define BND { BND_Fixup, 0 }
439 #define NOTRACK { NOTRACK_Fixup, 0 }
440
441 #define cond_jump_flag { NULL, cond_jump_mode }
442 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
443
444 /* bits in sizeflag */
445 #define SUFFIX_ALWAYS 4
446 #define AFLAG 2
447 #define DFLAG 1
448
449 enum
450 {
451 /* byte operand */
452 b_mode = 1,
453 /* byte operand with operand swapped */
454 b_swap_mode,
455 /* byte operand, sign extend like 'T' suffix */
456 b_T_mode,
457 /* operand size depends on prefixes */
458 v_mode,
459 /* operand size depends on prefixes with operand swapped */
460 v_swap_mode,
461 /* operand size depends on address prefix */
462 va_mode,
463 /* word operand */
464 w_mode,
465 /* double word operand */
466 d_mode,
467 /* double word operand with operand swapped */
468 d_swap_mode,
469 /* quad word operand */
470 q_mode,
471 /* quad word operand with operand swapped */
472 q_swap_mode,
473 /* ten-byte operand */
474 t_mode,
475 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
476 broadcast enabled. */
477 x_mode,
478 /* Similar to x_mode, but with different EVEX mem shifts. */
479 evex_x_gscat_mode,
480 /* Similar to x_mode, but with yet different EVEX mem shifts. */
481 bw_unit_mode,
482 /* Similar to x_mode, but with disabled broadcast. */
483 evex_x_nobcst_mode,
484 /* Similar to x_mode, but with operands swapped and disabled broadcast
485 in EVEX. */
486 x_swap_mode,
487 /* 16-byte XMM operand */
488 xmm_mode,
489 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
490 memory operand (depending on vector length). Broadcast isn't
491 allowed. */
492 xmmq_mode,
493 /* Same as xmmq_mode, but broadcast is allowed. */
494 evex_half_bcst_xmmq_mode,
495 /* XMM register or byte memory operand */
496 xmm_mb_mode,
497 /* XMM register or word memory operand */
498 xmm_mw_mode,
499 /* XMM register or double word memory operand */
500 xmm_md_mode,
501 /* XMM register or quad word memory operand */
502 xmm_mq_mode,
503 /* 16-byte XMM, word, double word or quad word operand. */
504 xmmdw_mode,
505 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
506 xmmqd_mode,
507 /* 32-byte YMM operand */
508 ymm_mode,
509 /* quad word, ymmword or zmmword memory operand. */
510 ymmq_mode,
511 /* 32-byte YMM or 16-byte word operand */
512 ymmxmm_mode,
513 /* TMM operand */
514 tmm_mode,
515 /* d_mode in 32bit, q_mode in 64bit mode. */
516 m_mode,
517 /* pair of v_mode operands */
518 a_mode,
519 cond_jump_mode,
520 loop_jcxz_mode,
521 movsxd_mode,
522 v_bnd_mode,
523 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
524 v_bndmk_mode,
525 /* operand size depends on REX prefixes. */
526 dq_mode,
527 /* registers like dq_mode, memory like w_mode, displacements like
528 v_mode without considering Intel64 ISA. */
529 dqw_mode,
530 /* bounds operand */
531 bnd_mode,
532 /* bounds operand with operand swapped */
533 bnd_swap_mode,
534 /* 4- or 6-byte pointer operand */
535 f_mode,
536 const_1_mode,
537 /* v_mode for indirect branch opcodes. */
538 indir_v_mode,
539 /* v_mode for stack-related opcodes. */
540 stack_v_mode,
541 /* non-quad operand size depends on prefixes */
542 z_mode,
543 /* 16-byte operand */
544 o_mode,
545 /* registers like dq_mode, memory like b_mode. */
546 dqb_mode,
547 /* registers like d_mode, memory like b_mode. */
548 db_mode,
549 /* registers like d_mode, memory like w_mode. */
550 dw_mode,
551 /* registers like dq_mode, memory like d_mode. */
552 dqd_mode,
553 /* normal vex mode */
554 vex_mode,
555
556 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
557 vex_vsib_d_w_dq_mode,
558 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
559 vex_vsib_d_w_d_mode,
560 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
561 vex_vsib_q_w_dq_mode,
562 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
563 vex_vsib_q_w_d_mode,
564 /* mandatory non-vector SIB. */
565 vex_sibmem_mode,
566
567 /* scalar, ignore vector length. */
568 scalar_mode,
569 /* like vex_mode, ignore vector length. */
570 vex_scalar_mode,
571 /* Operand size depends on the VEX.W bit, ignore vector length. */
572 vex_scalar_w_dq_mode,
573
574 /* Static rounding. */
575 evex_rounding_mode,
576 /* Static rounding, 64-bit mode only. */
577 evex_rounding_64_mode,
578 /* Supress all exceptions. */
579 evex_sae_mode,
580
581 /* Mask register operand. */
582 mask_mode,
583 /* Mask register operand. */
584 mask_bd_mode,
585
586 es_reg,
587 cs_reg,
588 ss_reg,
589 ds_reg,
590 fs_reg,
591 gs_reg,
592
593 eAX_reg,
594 eCX_reg,
595 eDX_reg,
596 eBX_reg,
597 eSP_reg,
598 eBP_reg,
599 eSI_reg,
600 eDI_reg,
601
602 al_reg,
603 cl_reg,
604 dl_reg,
605 bl_reg,
606 ah_reg,
607 ch_reg,
608 dh_reg,
609 bh_reg,
610
611 ax_reg,
612 cx_reg,
613 dx_reg,
614 bx_reg,
615 sp_reg,
616 bp_reg,
617 si_reg,
618 di_reg,
619
620 rAX_reg,
621 rCX_reg,
622 rDX_reg,
623 rBX_reg,
624 rSP_reg,
625 rBP_reg,
626 rSI_reg,
627 rDI_reg,
628
629 z_mode_ax_reg,
630 indir_dx_reg
631 };
632
633 enum
634 {
635 FLOATCODE = 1,
636 USE_REG_TABLE,
637 USE_MOD_TABLE,
638 USE_RM_TABLE,
639 USE_PREFIX_TABLE,
640 USE_X86_64_TABLE,
641 USE_3BYTE_TABLE,
642 USE_XOP_8F_TABLE,
643 USE_VEX_C4_TABLE,
644 USE_VEX_C5_TABLE,
645 USE_VEX_LEN_TABLE,
646 USE_VEX_W_TABLE,
647 USE_EVEX_TABLE,
648 USE_EVEX_LEN_TABLE
649 };
650
651 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
652
653 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
654 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
655 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
656 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
657 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
658 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
659 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
660 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
661 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
662 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
663 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
664 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
665 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
666 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
667 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
668 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
669
670 enum
671 {
672 REG_80 = 0,
673 REG_81,
674 REG_83,
675 REG_8F,
676 REG_C0,
677 REG_C1,
678 REG_C6,
679 REG_C7,
680 REG_D0,
681 REG_D1,
682 REG_D2,
683 REG_D3,
684 REG_F6,
685 REG_F7,
686 REG_FE,
687 REG_FF,
688 REG_0F00,
689 REG_0F01,
690 REG_0F0D,
691 REG_0F18,
692 REG_0F1C_P_0_MOD_0,
693 REG_0F1E_P_1_MOD_3,
694 REG_0F38D8_PREFIX_1,
695 REG_0F3A0F_PREFIX_1_MOD_3,
696 REG_0F71_MOD_0,
697 REG_0F72_MOD_0,
698 REG_0F73_MOD_0,
699 REG_0FA6,
700 REG_0FA7,
701 REG_0FAE,
702 REG_0FBA,
703 REG_0FC7,
704 REG_VEX_0F71_M_0,
705 REG_VEX_0F72_M_0,
706 REG_VEX_0F73_M_0,
707 REG_VEX_0FAE,
708 REG_VEX_0F3849_X86_64_P_0_W_0_M_1,
709 REG_VEX_0F38F3_L_0,
710
711 REG_0FXOP_09_01_L_0,
712 REG_0FXOP_09_02_L_0,
713 REG_0FXOP_09_12_M_1_L_0,
714 REG_0FXOP_0A_12_L_0,
715
716 REG_EVEX_0F71,
717 REG_EVEX_0F72,
718 REG_EVEX_0F73,
719 REG_EVEX_0F38C6_M_0_L_2,
720 REG_EVEX_0F38C7_M_0_L_2_W_0,
721 REG_EVEX_0F38C7_M_0_L_2_W_1
722 };
723
724 enum
725 {
726 MOD_8D = 0,
727 MOD_C6_REG_7,
728 MOD_C7_REG_7,
729 MOD_FF_REG_3,
730 MOD_FF_REG_5,
731 MOD_0F01_REG_0,
732 MOD_0F01_REG_1,
733 MOD_0F01_REG_2,
734 MOD_0F01_REG_3,
735 MOD_0F01_REG_5,
736 MOD_0F01_REG_7,
737 MOD_0F12_PREFIX_0,
738 MOD_0F12_PREFIX_2,
739 MOD_0F13,
740 MOD_0F16_PREFIX_0,
741 MOD_0F16_PREFIX_2,
742 MOD_0F17,
743 MOD_0F18_REG_0,
744 MOD_0F18_REG_1,
745 MOD_0F18_REG_2,
746 MOD_0F18_REG_3,
747 MOD_0F1A_PREFIX_0,
748 MOD_0F1B_PREFIX_0,
749 MOD_0F1B_PREFIX_1,
750 MOD_0F1C_PREFIX_0,
751 MOD_0F1E_PREFIX_1,
752 MOD_0F2B_PREFIX_0,
753 MOD_0F2B_PREFIX_1,
754 MOD_0F2B_PREFIX_2,
755 MOD_0F2B_PREFIX_3,
756 MOD_0F50,
757 MOD_0F71,
758 MOD_0F72,
759 MOD_0F73,
760 MOD_0FAE_REG_0,
761 MOD_0FAE_REG_1,
762 MOD_0FAE_REG_2,
763 MOD_0FAE_REG_3,
764 MOD_0FAE_REG_4,
765 MOD_0FAE_REG_5,
766 MOD_0FAE_REG_6,
767 MOD_0FAE_REG_7,
768 MOD_0FB2,
769 MOD_0FB4,
770 MOD_0FB5,
771 MOD_0FC3,
772 MOD_0FC7_REG_3,
773 MOD_0FC7_REG_4,
774 MOD_0FC7_REG_5,
775 MOD_0FC7_REG_6,
776 MOD_0FC7_REG_7,
777 MOD_0FD7,
778 MOD_0FE7_PREFIX_2,
779 MOD_0FF0_PREFIX_3,
780 MOD_0F382A,
781 MOD_0F38DC_PREFIX_1,
782 MOD_0F38DD_PREFIX_1,
783 MOD_0F38DE_PREFIX_1,
784 MOD_0F38DF_PREFIX_1,
785 MOD_0F38F5,
786 MOD_0F38F6_PREFIX_0,
787 MOD_0F38F8_PREFIX_1,
788 MOD_0F38F8_PREFIX_2,
789 MOD_0F38F8_PREFIX_3,
790 MOD_0F38F9,
791 MOD_0F38FA_PREFIX_1,
792 MOD_0F38FB_PREFIX_1,
793 MOD_0F3A0F_PREFIX_1,
794 MOD_62_32BIT,
795 MOD_C4_32BIT,
796 MOD_C5_32BIT,
797 MOD_VEX_0F12_PREFIX_0,
798 MOD_VEX_0F12_PREFIX_2,
799 MOD_VEX_0F13,
800 MOD_VEX_0F16_PREFIX_0,
801 MOD_VEX_0F16_PREFIX_2,
802 MOD_VEX_0F17,
803 MOD_VEX_0F2B,
804 MOD_VEX_0F41_L_1,
805 MOD_VEX_0F42_L_1,
806 MOD_VEX_0F44_L_0,
807 MOD_VEX_0F45_L_1,
808 MOD_VEX_0F46_L_1,
809 MOD_VEX_0F47_L_1,
810 MOD_VEX_0F4A_L_1,
811 MOD_VEX_0F4B_L_1,
812 MOD_VEX_0F50,
813 MOD_VEX_0F71,
814 MOD_VEX_0F72,
815 MOD_VEX_0F73,
816 MOD_VEX_0F91_L_0,
817 MOD_VEX_0F92_L_0,
818 MOD_VEX_0F93_L_0,
819 MOD_VEX_0F98_L_0,
820 MOD_VEX_0F99_L_0,
821 MOD_VEX_0FAE_REG_2,
822 MOD_VEX_0FAE_REG_3,
823 MOD_VEX_0FD7,
824 MOD_VEX_0FE7,
825 MOD_VEX_0FF0_PREFIX_3,
826 MOD_VEX_0F381A,
827 MOD_VEX_0F382A,
828 MOD_VEX_0F382C,
829 MOD_VEX_0F382D,
830 MOD_VEX_0F382E,
831 MOD_VEX_0F382F,
832 MOD_VEX_0F3849_X86_64_P_0_W_0,
833 MOD_VEX_0F3849_X86_64_P_2_W_0,
834 MOD_VEX_0F3849_X86_64_P_3_W_0,
835 MOD_VEX_0F384B_X86_64_P_1_W_0,
836 MOD_VEX_0F384B_X86_64_P_2_W_0,
837 MOD_VEX_0F384B_X86_64_P_3_W_0,
838 MOD_VEX_0F385A,
839 MOD_VEX_0F385C_X86_64_P_1_W_0,
840 MOD_VEX_0F385E_X86_64_P_0_W_0,
841 MOD_VEX_0F385E_X86_64_P_1_W_0,
842 MOD_VEX_0F385E_X86_64_P_2_W_0,
843 MOD_VEX_0F385E_X86_64_P_3_W_0,
844 MOD_VEX_0F388C,
845 MOD_VEX_0F388E,
846 MOD_VEX_0F3A30_L_0,
847 MOD_VEX_0F3A31_L_0,
848 MOD_VEX_0F3A32_L_0,
849 MOD_VEX_0F3A33_L_0,
850
851 MOD_VEX_0FXOP_09_12,
852
853 MOD_EVEX_0F12_PREFIX_0,
854 MOD_EVEX_0F12_PREFIX_2,
855 MOD_EVEX_0F13,
856 MOD_EVEX_0F16_PREFIX_0,
857 MOD_EVEX_0F16_PREFIX_2,
858 MOD_EVEX_0F17,
859 MOD_EVEX_0F2B,
860 MOD_EVEX_0F381A,
861 MOD_EVEX_0F381B,
862 MOD_EVEX_0F3828_P_1,
863 MOD_EVEX_0F382A_P_1_W_1,
864 MOD_EVEX_0F3838_P_1,
865 MOD_EVEX_0F383A_P_1_W_0,
866 MOD_EVEX_0F385A,
867 MOD_EVEX_0F385B,
868 MOD_EVEX_0F387A_W_0,
869 MOD_EVEX_0F387B_W_0,
870 MOD_EVEX_0F387C,
871 MOD_EVEX_0F38C6,
872 MOD_EVEX_0F38C7
873 };
874
875 enum
876 {
877 RM_C6_REG_7 = 0,
878 RM_C7_REG_7,
879 RM_0F01_REG_0,
880 RM_0F01_REG_1,
881 RM_0F01_REG_2,
882 RM_0F01_REG_3,
883 RM_0F01_REG_5_MOD_3,
884 RM_0F01_REG_7_MOD_3,
885 RM_0F1E_P_1_MOD_3_REG_7,
886 RM_0F3A0F_P_1_MOD_3_REG_0,
887 RM_0FAE_REG_6_MOD_3_P_0,
888 RM_0FAE_REG_7_MOD_3,
889 RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
890 };
891
892 enum
893 {
894 PREFIX_90 = 0,
895 PREFIX_0F01_REG_1_RM_4,
896 PREFIX_0F01_REG_1_RM_5,
897 PREFIX_0F01_REG_1_RM_6,
898 PREFIX_0F01_REG_1_RM_7,
899 PREFIX_0F01_REG_3_RM_1,
900 PREFIX_0F01_REG_5_MOD_0,
901 PREFIX_0F01_REG_5_MOD_3_RM_0,
902 PREFIX_0F01_REG_5_MOD_3_RM_1,
903 PREFIX_0F01_REG_5_MOD_3_RM_2,
904 PREFIX_0F01_REG_5_MOD_3_RM_4,
905 PREFIX_0F01_REG_5_MOD_3_RM_5,
906 PREFIX_0F01_REG_5_MOD_3_RM_6,
907 PREFIX_0F01_REG_5_MOD_3_RM_7,
908 PREFIX_0F01_REG_7_MOD_3_RM_2,
909 PREFIX_0F01_REG_7_MOD_3_RM_6,
910 PREFIX_0F01_REG_7_MOD_3_RM_7,
911 PREFIX_0F09,
912 PREFIX_0F10,
913 PREFIX_0F11,
914 PREFIX_0F12,
915 PREFIX_0F16,
916 PREFIX_0F1A,
917 PREFIX_0F1B,
918 PREFIX_0F1C,
919 PREFIX_0F1E,
920 PREFIX_0F2A,
921 PREFIX_0F2B,
922 PREFIX_0F2C,
923 PREFIX_0F2D,
924 PREFIX_0F2E,
925 PREFIX_0F2F,
926 PREFIX_0F51,
927 PREFIX_0F52,
928 PREFIX_0F53,
929 PREFIX_0F58,
930 PREFIX_0F59,
931 PREFIX_0F5A,
932 PREFIX_0F5B,
933 PREFIX_0F5C,
934 PREFIX_0F5D,
935 PREFIX_0F5E,
936 PREFIX_0F5F,
937 PREFIX_0F60,
938 PREFIX_0F61,
939 PREFIX_0F62,
940 PREFIX_0F6F,
941 PREFIX_0F70,
942 PREFIX_0F78,
943 PREFIX_0F79,
944 PREFIX_0F7C,
945 PREFIX_0F7D,
946 PREFIX_0F7E,
947 PREFIX_0F7F,
948 PREFIX_0FAE_REG_0_MOD_3,
949 PREFIX_0FAE_REG_1_MOD_3,
950 PREFIX_0FAE_REG_2_MOD_3,
951 PREFIX_0FAE_REG_3_MOD_3,
952 PREFIX_0FAE_REG_4_MOD_0,
953 PREFIX_0FAE_REG_4_MOD_3,
954 PREFIX_0FAE_REG_5_MOD_3,
955 PREFIX_0FAE_REG_6_MOD_0,
956 PREFIX_0FAE_REG_6_MOD_3,
957 PREFIX_0FAE_REG_7_MOD_0,
958 PREFIX_0FB8,
959 PREFIX_0FBC,
960 PREFIX_0FBD,
961 PREFIX_0FC2,
962 PREFIX_0FC7_REG_6_MOD_0,
963 PREFIX_0FC7_REG_6_MOD_3,
964 PREFIX_0FC7_REG_7_MOD_3,
965 PREFIX_0FD0,
966 PREFIX_0FD6,
967 PREFIX_0FE6,
968 PREFIX_0FE7,
969 PREFIX_0FF0,
970 PREFIX_0FF7,
971 PREFIX_0F38D8,
972 PREFIX_0F38DC,
973 PREFIX_0F38DD,
974 PREFIX_0F38DE,
975 PREFIX_0F38DF,
976 PREFIX_0F38F0,
977 PREFIX_0F38F1,
978 PREFIX_0F38F6,
979 PREFIX_0F38F8,
980 PREFIX_0F38FA,
981 PREFIX_0F38FB,
982 PREFIX_0F3A0F,
983 PREFIX_VEX_0F10,
984 PREFIX_VEX_0F11,
985 PREFIX_VEX_0F12,
986 PREFIX_VEX_0F16,
987 PREFIX_VEX_0F2A,
988 PREFIX_VEX_0F2C,
989 PREFIX_VEX_0F2D,
990 PREFIX_VEX_0F2E,
991 PREFIX_VEX_0F2F,
992 PREFIX_VEX_0F41_L_1_M_1_W_0,
993 PREFIX_VEX_0F41_L_1_M_1_W_1,
994 PREFIX_VEX_0F42_L_1_M_1_W_0,
995 PREFIX_VEX_0F42_L_1_M_1_W_1,
996 PREFIX_VEX_0F44_L_0_M_1_W_0,
997 PREFIX_VEX_0F44_L_0_M_1_W_1,
998 PREFIX_VEX_0F45_L_1_M_1_W_0,
999 PREFIX_VEX_0F45_L_1_M_1_W_1,
1000 PREFIX_VEX_0F46_L_1_M_1_W_0,
1001 PREFIX_VEX_0F46_L_1_M_1_W_1,
1002 PREFIX_VEX_0F47_L_1_M_1_W_0,
1003 PREFIX_VEX_0F47_L_1_M_1_W_1,
1004 PREFIX_VEX_0F4A_L_1_M_1_W_0,
1005 PREFIX_VEX_0F4A_L_1_M_1_W_1,
1006 PREFIX_VEX_0F4B_L_1_M_1_W_0,
1007 PREFIX_VEX_0F4B_L_1_M_1_W_1,
1008 PREFIX_VEX_0F51,
1009 PREFIX_VEX_0F52,
1010 PREFIX_VEX_0F53,
1011 PREFIX_VEX_0F58,
1012 PREFIX_VEX_0F59,
1013 PREFIX_VEX_0F5A,
1014 PREFIX_VEX_0F5B,
1015 PREFIX_VEX_0F5C,
1016 PREFIX_VEX_0F5D,
1017 PREFIX_VEX_0F5E,
1018 PREFIX_VEX_0F5F,
1019 PREFIX_VEX_0F6F,
1020 PREFIX_VEX_0F70,
1021 PREFIX_VEX_0F7C,
1022 PREFIX_VEX_0F7D,
1023 PREFIX_VEX_0F7E,
1024 PREFIX_VEX_0F7F,
1025 PREFIX_VEX_0F90_L_0_W_0,
1026 PREFIX_VEX_0F90_L_0_W_1,
1027 PREFIX_VEX_0F91_L_0_M_0_W_0,
1028 PREFIX_VEX_0F91_L_0_M_0_W_1,
1029 PREFIX_VEX_0F92_L_0_M_1_W_0,
1030 PREFIX_VEX_0F92_L_0_M_1_W_1,
1031 PREFIX_VEX_0F93_L_0_M_1_W_0,
1032 PREFIX_VEX_0F93_L_0_M_1_W_1,
1033 PREFIX_VEX_0F98_L_0_M_1_W_0,
1034 PREFIX_VEX_0F98_L_0_M_1_W_1,
1035 PREFIX_VEX_0F99_L_0_M_1_W_0,
1036 PREFIX_VEX_0F99_L_0_M_1_W_1,
1037 PREFIX_VEX_0FC2,
1038 PREFIX_VEX_0FD0,
1039 PREFIX_VEX_0FE6,
1040 PREFIX_VEX_0FF0,
1041 PREFIX_VEX_0F3849_X86_64,
1042 PREFIX_VEX_0F384B_X86_64,
1043 PREFIX_VEX_0F385C_X86_64,
1044 PREFIX_VEX_0F385E_X86_64,
1045 PREFIX_VEX_0F38F5_L_0,
1046 PREFIX_VEX_0F38F6_L_0,
1047 PREFIX_VEX_0F38F7_L_0,
1048 PREFIX_VEX_0F3AF0_L_0,
1049
1050 PREFIX_EVEX_0F10,
1051 PREFIX_EVEX_0F11,
1052 PREFIX_EVEX_0F12,
1053 PREFIX_EVEX_0F16,
1054 PREFIX_EVEX_0F2A,
1055 PREFIX_EVEX_0F51,
1056 PREFIX_EVEX_0F58,
1057 PREFIX_EVEX_0F59,
1058 PREFIX_EVEX_0F5A,
1059 PREFIX_EVEX_0F5B,
1060 PREFIX_EVEX_0F5C,
1061 PREFIX_EVEX_0F5D,
1062 PREFIX_EVEX_0F5E,
1063 PREFIX_EVEX_0F5F,
1064 PREFIX_EVEX_0F6F,
1065 PREFIX_EVEX_0F70,
1066 PREFIX_EVEX_0F78,
1067 PREFIX_EVEX_0F79,
1068 PREFIX_EVEX_0F7A,
1069 PREFIX_EVEX_0F7B,
1070 PREFIX_EVEX_0F7E,
1071 PREFIX_EVEX_0F7F,
1072 PREFIX_EVEX_0FC2,
1073 PREFIX_EVEX_0FE6,
1074 PREFIX_EVEX_0F3810,
1075 PREFIX_EVEX_0F3811,
1076 PREFIX_EVEX_0F3812,
1077 PREFIX_EVEX_0F3813,
1078 PREFIX_EVEX_0F3814,
1079 PREFIX_EVEX_0F3815,
1080 PREFIX_EVEX_0F3820,
1081 PREFIX_EVEX_0F3821,
1082 PREFIX_EVEX_0F3822,
1083 PREFIX_EVEX_0F3823,
1084 PREFIX_EVEX_0F3824,
1085 PREFIX_EVEX_0F3825,
1086 PREFIX_EVEX_0F3826,
1087 PREFIX_EVEX_0F3827,
1088 PREFIX_EVEX_0F3828,
1089 PREFIX_EVEX_0F3829,
1090 PREFIX_EVEX_0F382A,
1091 PREFIX_EVEX_0F3830,
1092 PREFIX_EVEX_0F3831,
1093 PREFIX_EVEX_0F3832,
1094 PREFIX_EVEX_0F3833,
1095 PREFIX_EVEX_0F3834,
1096 PREFIX_EVEX_0F3835,
1097 PREFIX_EVEX_0F3838,
1098 PREFIX_EVEX_0F3839,
1099 PREFIX_EVEX_0F383A,
1100 PREFIX_EVEX_0F3852,
1101 PREFIX_EVEX_0F3853,
1102 PREFIX_EVEX_0F3868,
1103 PREFIX_EVEX_0F3872,
1104 PREFIX_EVEX_0F389A,
1105 PREFIX_EVEX_0F389B,
1106 PREFIX_EVEX_0F38AA,
1107 PREFIX_EVEX_0F38AB,
1108 };
1109
1110 enum
1111 {
1112 X86_64_06 = 0,
1113 X86_64_07,
1114 X86_64_0E,
1115 X86_64_16,
1116 X86_64_17,
1117 X86_64_1E,
1118 X86_64_1F,
1119 X86_64_27,
1120 X86_64_2F,
1121 X86_64_37,
1122 X86_64_3F,
1123 X86_64_60,
1124 X86_64_61,
1125 X86_64_62,
1126 X86_64_63,
1127 X86_64_6D,
1128 X86_64_6F,
1129 X86_64_82,
1130 X86_64_9A,
1131 X86_64_C2,
1132 X86_64_C3,
1133 X86_64_C4,
1134 X86_64_C5,
1135 X86_64_CE,
1136 X86_64_D4,
1137 X86_64_D5,
1138 X86_64_E8,
1139 X86_64_E9,
1140 X86_64_EA,
1141 X86_64_0F01_REG_0,
1142 X86_64_0F01_REG_1,
1143 X86_64_0F01_REG_1_RM_5_PREFIX_2,
1144 X86_64_0F01_REG_1_RM_6_PREFIX_2,
1145 X86_64_0F01_REG_1_RM_7_PREFIX_2,
1146 X86_64_0F01_REG_2,
1147 X86_64_0F01_REG_3,
1148 X86_64_0F24,
1149 X86_64_0F26,
1150 X86_64_VEX_0F3849,
1151 X86_64_VEX_0F384B,
1152 X86_64_VEX_0F385C,
1153 X86_64_VEX_0F385E,
1154 X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
1155 X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
1156 X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
1157 X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
1158 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
1159 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
1160 X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
1161 X86_64_0FC7_REG_6_MOD_3_PREFIX_1
1162 };
1163
1164 enum
1165 {
1166 THREE_BYTE_0F38 = 0,
1167 THREE_BYTE_0F3A
1168 };
1169
1170 enum
1171 {
1172 XOP_08 = 0,
1173 XOP_09,
1174 XOP_0A
1175 };
1176
1177 enum
1178 {
1179 VEX_0F = 0,
1180 VEX_0F38,
1181 VEX_0F3A
1182 };
1183
1184 enum
1185 {
1186 EVEX_0F = 0,
1187 EVEX_0F38,
1188 EVEX_0F3A
1189 };
1190
1191 enum
1192 {
1193 VEX_LEN_0F12_P_0_M_0 = 0,
1194 VEX_LEN_0F12_P_0_M_1,
1195 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1196 VEX_LEN_0F13_M_0,
1197 VEX_LEN_0F16_P_0_M_0,
1198 VEX_LEN_0F16_P_0_M_1,
1199 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1200 VEX_LEN_0F17_M_0,
1201 VEX_LEN_0F41,
1202 VEX_LEN_0F42,
1203 VEX_LEN_0F44,
1204 VEX_LEN_0F45,
1205 VEX_LEN_0F46,
1206 VEX_LEN_0F47,
1207 VEX_LEN_0F4A,
1208 VEX_LEN_0F4B,
1209 VEX_LEN_0F6E,
1210 VEX_LEN_0F77,
1211 VEX_LEN_0F7E_P_1,
1212 VEX_LEN_0F7E_P_2,
1213 VEX_LEN_0F90,
1214 VEX_LEN_0F91,
1215 VEX_LEN_0F92,
1216 VEX_LEN_0F93,
1217 VEX_LEN_0F98,
1218 VEX_LEN_0F99,
1219 VEX_LEN_0FAE_R_2_M_0,
1220 VEX_LEN_0FAE_R_3_M_0,
1221 VEX_LEN_0FC4,
1222 VEX_LEN_0FC5,
1223 VEX_LEN_0FD6,
1224 VEX_LEN_0FF7,
1225 VEX_LEN_0F3816,
1226 VEX_LEN_0F3819,
1227 VEX_LEN_0F381A_M_0,
1228 VEX_LEN_0F3836,
1229 VEX_LEN_0F3841,
1230 VEX_LEN_0F3849_X86_64_P_0_W_0_M_0,
1231 VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0,
1232 VEX_LEN_0F3849_X86_64_P_2_W_0_M_0,
1233 VEX_LEN_0F3849_X86_64_P_3_W_0_M_0,
1234 VEX_LEN_0F384B_X86_64_P_1_W_0_M_0,
1235 VEX_LEN_0F384B_X86_64_P_2_W_0_M_0,
1236 VEX_LEN_0F384B_X86_64_P_3_W_0_M_0,
1237 VEX_LEN_0F385A_M_0,
1238 VEX_LEN_0F385C_X86_64_P_1_W_0_M_0,
1239 VEX_LEN_0F385E_X86_64_P_0_W_0_M_0,
1240 VEX_LEN_0F385E_X86_64_P_1_W_0_M_0,
1241 VEX_LEN_0F385E_X86_64_P_2_W_0_M_0,
1242 VEX_LEN_0F385E_X86_64_P_3_W_0_M_0,
1243 VEX_LEN_0F38DB,
1244 VEX_LEN_0F38F2,
1245 VEX_LEN_0F38F3,
1246 VEX_LEN_0F38F5,
1247 VEX_LEN_0F38F6,
1248 VEX_LEN_0F38F7,
1249 VEX_LEN_0F3A00,
1250 VEX_LEN_0F3A01,
1251 VEX_LEN_0F3A06,
1252 VEX_LEN_0F3A14,
1253 VEX_LEN_0F3A15,
1254 VEX_LEN_0F3A16,
1255 VEX_LEN_0F3A17,
1256 VEX_LEN_0F3A18,
1257 VEX_LEN_0F3A19,
1258 VEX_LEN_0F3A20,
1259 VEX_LEN_0F3A21,
1260 VEX_LEN_0F3A22,
1261 VEX_LEN_0F3A30,
1262 VEX_LEN_0F3A31,
1263 VEX_LEN_0F3A32,
1264 VEX_LEN_0F3A33,
1265 VEX_LEN_0F3A38,
1266 VEX_LEN_0F3A39,
1267 VEX_LEN_0F3A41,
1268 VEX_LEN_0F3A46,
1269 VEX_LEN_0F3A60,
1270 VEX_LEN_0F3A61,
1271 VEX_LEN_0F3A62,
1272 VEX_LEN_0F3A63,
1273 VEX_LEN_0F3ADF,
1274 VEX_LEN_0F3AF0,
1275 VEX_LEN_0FXOP_08_85,
1276 VEX_LEN_0FXOP_08_86,
1277 VEX_LEN_0FXOP_08_87,
1278 VEX_LEN_0FXOP_08_8E,
1279 VEX_LEN_0FXOP_08_8F,
1280 VEX_LEN_0FXOP_08_95,
1281 VEX_LEN_0FXOP_08_96,
1282 VEX_LEN_0FXOP_08_97,
1283 VEX_LEN_0FXOP_08_9E,
1284 VEX_LEN_0FXOP_08_9F,
1285 VEX_LEN_0FXOP_08_A3,
1286 VEX_LEN_0FXOP_08_A6,
1287 VEX_LEN_0FXOP_08_B6,
1288 VEX_LEN_0FXOP_08_C0,
1289 VEX_LEN_0FXOP_08_C1,
1290 VEX_LEN_0FXOP_08_C2,
1291 VEX_LEN_0FXOP_08_C3,
1292 VEX_LEN_0FXOP_08_CC,
1293 VEX_LEN_0FXOP_08_CD,
1294 VEX_LEN_0FXOP_08_CE,
1295 VEX_LEN_0FXOP_08_CF,
1296 VEX_LEN_0FXOP_08_EC,
1297 VEX_LEN_0FXOP_08_ED,
1298 VEX_LEN_0FXOP_08_EE,
1299 VEX_LEN_0FXOP_08_EF,
1300 VEX_LEN_0FXOP_09_01,
1301 VEX_LEN_0FXOP_09_02,
1302 VEX_LEN_0FXOP_09_12_M_1,
1303 VEX_LEN_0FXOP_09_82_W_0,
1304 VEX_LEN_0FXOP_09_83_W_0,
1305 VEX_LEN_0FXOP_09_90,
1306 VEX_LEN_0FXOP_09_91,
1307 VEX_LEN_0FXOP_09_92,
1308 VEX_LEN_0FXOP_09_93,
1309 VEX_LEN_0FXOP_09_94,
1310 VEX_LEN_0FXOP_09_95,
1311 VEX_LEN_0FXOP_09_96,
1312 VEX_LEN_0FXOP_09_97,
1313 VEX_LEN_0FXOP_09_98,
1314 VEX_LEN_0FXOP_09_99,
1315 VEX_LEN_0FXOP_09_9A,
1316 VEX_LEN_0FXOP_09_9B,
1317 VEX_LEN_0FXOP_09_C1,
1318 VEX_LEN_0FXOP_09_C2,
1319 VEX_LEN_0FXOP_09_C3,
1320 VEX_LEN_0FXOP_09_C6,
1321 VEX_LEN_0FXOP_09_C7,
1322 VEX_LEN_0FXOP_09_CB,
1323 VEX_LEN_0FXOP_09_D1,
1324 VEX_LEN_0FXOP_09_D2,
1325 VEX_LEN_0FXOP_09_D3,
1326 VEX_LEN_0FXOP_09_D6,
1327 VEX_LEN_0FXOP_09_D7,
1328 VEX_LEN_0FXOP_09_DB,
1329 VEX_LEN_0FXOP_09_E1,
1330 VEX_LEN_0FXOP_09_E2,
1331 VEX_LEN_0FXOP_09_E3,
1332 VEX_LEN_0FXOP_0A_12,
1333 };
1334
1335 enum
1336 {
1337 EVEX_LEN_0F6E = 0,
1338 EVEX_LEN_0F7E_P_1,
1339 EVEX_LEN_0F7E_P_2,
1340 EVEX_LEN_0FC4,
1341 EVEX_LEN_0FC5,
1342 EVEX_LEN_0FD6,
1343 EVEX_LEN_0F3816,
1344 EVEX_LEN_0F3819,
1345 EVEX_LEN_0F381A_M_0,
1346 EVEX_LEN_0F381B_M_0,
1347 EVEX_LEN_0F3836,
1348 EVEX_LEN_0F385A_M_0,
1349 EVEX_LEN_0F385B_M_0,
1350 EVEX_LEN_0F38C6_M_0,
1351 EVEX_LEN_0F38C7_M_0,
1352 EVEX_LEN_0F3A00_W_1,
1353 EVEX_LEN_0F3A01_W_1,
1354 EVEX_LEN_0F3A14,
1355 EVEX_LEN_0F3A15,
1356 EVEX_LEN_0F3A16,
1357 EVEX_LEN_0F3A17,
1358 EVEX_LEN_0F3A18,
1359 EVEX_LEN_0F3A19,
1360 EVEX_LEN_0F3A1A,
1361 EVEX_LEN_0F3A1B,
1362 EVEX_LEN_0F3A20,
1363 EVEX_LEN_0F3A21_W_0,
1364 EVEX_LEN_0F3A22,
1365 EVEX_LEN_0F3A23,
1366 EVEX_LEN_0F3A38,
1367 EVEX_LEN_0F3A39,
1368 EVEX_LEN_0F3A3A,
1369 EVEX_LEN_0F3A3B,
1370 EVEX_LEN_0F3A43
1371 };
1372
1373 enum
1374 {
1375 VEX_W_0F41_L_1_M_1 = 0,
1376 VEX_W_0F42_L_1_M_1,
1377 VEX_W_0F44_L_0_M_1,
1378 VEX_W_0F45_L_1_M_1,
1379 VEX_W_0F46_L_1_M_1,
1380 VEX_W_0F47_L_1_M_1,
1381 VEX_W_0F4A_L_1_M_1,
1382 VEX_W_0F4B_L_1_M_1,
1383 VEX_W_0F90_L_0,
1384 VEX_W_0F91_L_0_M_0,
1385 VEX_W_0F92_L_0_M_1,
1386 VEX_W_0F93_L_0_M_1,
1387 VEX_W_0F98_L_0_M_1,
1388 VEX_W_0F99_L_0_M_1,
1389 VEX_W_0F380C,
1390 VEX_W_0F380D,
1391 VEX_W_0F380E,
1392 VEX_W_0F380F,
1393 VEX_W_0F3813,
1394 VEX_W_0F3816_L_1,
1395 VEX_W_0F3818,
1396 VEX_W_0F3819_L_1,
1397 VEX_W_0F381A_M_0_L_1,
1398 VEX_W_0F382C_M_0,
1399 VEX_W_0F382D_M_0,
1400 VEX_W_0F382E_M_0,
1401 VEX_W_0F382F_M_0,
1402 VEX_W_0F3836,
1403 VEX_W_0F3846,
1404 VEX_W_0F3849_X86_64_P_0,
1405 VEX_W_0F3849_X86_64_P_2,
1406 VEX_W_0F3849_X86_64_P_3,
1407 VEX_W_0F384B_X86_64_P_1,
1408 VEX_W_0F384B_X86_64_P_2,
1409 VEX_W_0F384B_X86_64_P_3,
1410 VEX_W_0F3850,
1411 VEX_W_0F3851,
1412 VEX_W_0F3852,
1413 VEX_W_0F3853,
1414 VEX_W_0F3858,
1415 VEX_W_0F3859,
1416 VEX_W_0F385A_M_0_L_0,
1417 VEX_W_0F385C_X86_64_P_1,
1418 VEX_W_0F385E_X86_64_P_0,
1419 VEX_W_0F385E_X86_64_P_1,
1420 VEX_W_0F385E_X86_64_P_2,
1421 VEX_W_0F385E_X86_64_P_3,
1422 VEX_W_0F3878,
1423 VEX_W_0F3879,
1424 VEX_W_0F38CF,
1425 VEX_W_0F3A00_L_1,
1426 VEX_W_0F3A01_L_1,
1427 VEX_W_0F3A02,
1428 VEX_W_0F3A04,
1429 VEX_W_0F3A05,
1430 VEX_W_0F3A06_L_1,
1431 VEX_W_0F3A18_L_1,
1432 VEX_W_0F3A19_L_1,
1433 VEX_W_0F3A1D,
1434 VEX_W_0F3A38_L_1,
1435 VEX_W_0F3A39_L_1,
1436 VEX_W_0F3A46_L_1,
1437 VEX_W_0F3A4A,
1438 VEX_W_0F3A4B,
1439 VEX_W_0F3A4C,
1440 VEX_W_0F3ACE,
1441 VEX_W_0F3ACF,
1442
1443 VEX_W_0FXOP_08_85_L_0,
1444 VEX_W_0FXOP_08_86_L_0,
1445 VEX_W_0FXOP_08_87_L_0,
1446 VEX_W_0FXOP_08_8E_L_0,
1447 VEX_W_0FXOP_08_8F_L_0,
1448 VEX_W_0FXOP_08_95_L_0,
1449 VEX_W_0FXOP_08_96_L_0,
1450 VEX_W_0FXOP_08_97_L_0,
1451 VEX_W_0FXOP_08_9E_L_0,
1452 VEX_W_0FXOP_08_9F_L_0,
1453 VEX_W_0FXOP_08_A6_L_0,
1454 VEX_W_0FXOP_08_B6_L_0,
1455 VEX_W_0FXOP_08_C0_L_0,
1456 VEX_W_0FXOP_08_C1_L_0,
1457 VEX_W_0FXOP_08_C2_L_0,
1458 VEX_W_0FXOP_08_C3_L_0,
1459 VEX_W_0FXOP_08_CC_L_0,
1460 VEX_W_0FXOP_08_CD_L_0,
1461 VEX_W_0FXOP_08_CE_L_0,
1462 VEX_W_0FXOP_08_CF_L_0,
1463 VEX_W_0FXOP_08_EC_L_0,
1464 VEX_W_0FXOP_08_ED_L_0,
1465 VEX_W_0FXOP_08_EE_L_0,
1466 VEX_W_0FXOP_08_EF_L_0,
1467
1468 VEX_W_0FXOP_09_80,
1469 VEX_W_0FXOP_09_81,
1470 VEX_W_0FXOP_09_82,
1471 VEX_W_0FXOP_09_83,
1472 VEX_W_0FXOP_09_C1_L_0,
1473 VEX_W_0FXOP_09_C2_L_0,
1474 VEX_W_0FXOP_09_C3_L_0,
1475 VEX_W_0FXOP_09_C6_L_0,
1476 VEX_W_0FXOP_09_C7_L_0,
1477 VEX_W_0FXOP_09_CB_L_0,
1478 VEX_W_0FXOP_09_D1_L_0,
1479 VEX_W_0FXOP_09_D2_L_0,
1480 VEX_W_0FXOP_09_D3_L_0,
1481 VEX_W_0FXOP_09_D6_L_0,
1482 VEX_W_0FXOP_09_D7_L_0,
1483 VEX_W_0FXOP_09_DB_L_0,
1484 VEX_W_0FXOP_09_E1_L_0,
1485 VEX_W_0FXOP_09_E2_L_0,
1486 VEX_W_0FXOP_09_E3_L_0,
1487
1488 EVEX_W_0F10_P_1,
1489 EVEX_W_0F10_P_3,
1490 EVEX_W_0F11_P_1,
1491 EVEX_W_0F11_P_3,
1492 EVEX_W_0F12_P_0_M_1,
1493 EVEX_W_0F12_P_1,
1494 EVEX_W_0F12_P_3,
1495 EVEX_W_0F16_P_0_M_1,
1496 EVEX_W_0F16_P_1,
1497 EVEX_W_0F2A_P_3,
1498 EVEX_W_0F51_P_1,
1499 EVEX_W_0F51_P_3,
1500 EVEX_W_0F58_P_1,
1501 EVEX_W_0F58_P_3,
1502 EVEX_W_0F59_P_1,
1503 EVEX_W_0F59_P_3,
1504 EVEX_W_0F5A_P_0,
1505 EVEX_W_0F5A_P_1,
1506 EVEX_W_0F5A_P_2,
1507 EVEX_W_0F5A_P_3,
1508 EVEX_W_0F5B_P_0,
1509 EVEX_W_0F5B_P_1,
1510 EVEX_W_0F5B_P_2,
1511 EVEX_W_0F5C_P_1,
1512 EVEX_W_0F5C_P_3,
1513 EVEX_W_0F5D_P_1,
1514 EVEX_W_0F5D_P_3,
1515 EVEX_W_0F5E_P_1,
1516 EVEX_W_0F5E_P_3,
1517 EVEX_W_0F5F_P_1,
1518 EVEX_W_0F5F_P_3,
1519 EVEX_W_0F62,
1520 EVEX_W_0F66,
1521 EVEX_W_0F6A,
1522 EVEX_W_0F6B,
1523 EVEX_W_0F6C,
1524 EVEX_W_0F6D,
1525 EVEX_W_0F6F_P_1,
1526 EVEX_W_0F6F_P_2,
1527 EVEX_W_0F6F_P_3,
1528 EVEX_W_0F70_P_2,
1529 EVEX_W_0F72_R_2,
1530 EVEX_W_0F72_R_6,
1531 EVEX_W_0F73_R_2,
1532 EVEX_W_0F73_R_6,
1533 EVEX_W_0F76,
1534 EVEX_W_0F78_P_0,
1535 EVEX_W_0F78_P_2,
1536 EVEX_W_0F79_P_0,
1537 EVEX_W_0F79_P_2,
1538 EVEX_W_0F7A_P_1,
1539 EVEX_W_0F7A_P_2,
1540 EVEX_W_0F7A_P_3,
1541 EVEX_W_0F7B_P_2,
1542 EVEX_W_0F7B_P_3,
1543 EVEX_W_0F7E_P_1,
1544 EVEX_W_0F7F_P_1,
1545 EVEX_W_0F7F_P_2,
1546 EVEX_W_0F7F_P_3,
1547 EVEX_W_0FC2_P_1,
1548 EVEX_W_0FC2_P_3,
1549 EVEX_W_0FD2,
1550 EVEX_W_0FD3,
1551 EVEX_W_0FD4,
1552 EVEX_W_0FD6_L_0,
1553 EVEX_W_0FE6_P_1,
1554 EVEX_W_0FE6_P_2,
1555 EVEX_W_0FE6_P_3,
1556 EVEX_W_0FE7,
1557 EVEX_W_0FF2,
1558 EVEX_W_0FF3,
1559 EVEX_W_0FF4,
1560 EVEX_W_0FFA,
1561 EVEX_W_0FFB,
1562 EVEX_W_0FFE,
1563 EVEX_W_0F380D,
1564 EVEX_W_0F3810_P_1,
1565 EVEX_W_0F3810_P_2,
1566 EVEX_W_0F3811_P_1,
1567 EVEX_W_0F3811_P_2,
1568 EVEX_W_0F3812_P_1,
1569 EVEX_W_0F3812_P_2,
1570 EVEX_W_0F3813_P_1,
1571 EVEX_W_0F3813_P_2,
1572 EVEX_W_0F3814_P_1,
1573 EVEX_W_0F3815_P_1,
1574 EVEX_W_0F3819_L_n,
1575 EVEX_W_0F381A_M_0_L_n,
1576 EVEX_W_0F381B_M_0_L_2,
1577 EVEX_W_0F381E,
1578 EVEX_W_0F381F,
1579 EVEX_W_0F3820_P_1,
1580 EVEX_W_0F3821_P_1,
1581 EVEX_W_0F3822_P_1,
1582 EVEX_W_0F3823_P_1,
1583 EVEX_W_0F3824_P_1,
1584 EVEX_W_0F3825_P_1,
1585 EVEX_W_0F3825_P_2,
1586 EVEX_W_0F3828_P_2,
1587 EVEX_W_0F3829_P_2,
1588 EVEX_W_0F382A_P_1,
1589 EVEX_W_0F382A_P_2,
1590 EVEX_W_0F382B,
1591 EVEX_W_0F3830_P_1,
1592 EVEX_W_0F3831_P_1,
1593 EVEX_W_0F3832_P_1,
1594 EVEX_W_0F3833_P_1,
1595 EVEX_W_0F3834_P_1,
1596 EVEX_W_0F3835_P_1,
1597 EVEX_W_0F3835_P_2,
1598 EVEX_W_0F3837,
1599 EVEX_W_0F383A_P_1,
1600 EVEX_W_0F3852_P_1,
1601 EVEX_W_0F3859,
1602 EVEX_W_0F385A_M_0_L_n,
1603 EVEX_W_0F385B_M_0_L_2,
1604 EVEX_W_0F3870,
1605 EVEX_W_0F3872_P_1,
1606 EVEX_W_0F3872_P_2,
1607 EVEX_W_0F3872_P_3,
1608 EVEX_W_0F387A,
1609 EVEX_W_0F387B,
1610 EVEX_W_0F3883,
1611 EVEX_W_0F3891,
1612 EVEX_W_0F3893,
1613 EVEX_W_0F38A1,
1614 EVEX_W_0F38A3,
1615 EVEX_W_0F38C7_M_0_L_2,
1616
1617 EVEX_W_0F3A00,
1618 EVEX_W_0F3A01,
1619 EVEX_W_0F3A05,
1620 EVEX_W_0F3A08,
1621 EVEX_W_0F3A09,
1622 EVEX_W_0F3A0A,
1623 EVEX_W_0F3A0B,
1624 EVEX_W_0F3A18_L_n,
1625 EVEX_W_0F3A19_L_n,
1626 EVEX_W_0F3A1A_L_2,
1627 EVEX_W_0F3A1B_L_2,
1628 EVEX_W_0F3A21,
1629 EVEX_W_0F3A23_L_n,
1630 EVEX_W_0F3A38_L_n,
1631 EVEX_W_0F3A39_L_n,
1632 EVEX_W_0F3A3A_L_2,
1633 EVEX_W_0F3A3B_L_2,
1634 EVEX_W_0F3A42,
1635 EVEX_W_0F3A43_L_n,
1636 EVEX_W_0F3A70,
1637 EVEX_W_0F3A72,
1638 };
1639
1640 typedef void (*op_rtn) (int bytemode, int sizeflag);
1641
1642 struct dis386 {
1643 const char *name;
1644 struct
1645 {
1646 op_rtn rtn;
1647 int bytemode;
1648 } op[MAX_OPERANDS];
1649 unsigned int prefix_requirement;
1650 };
1651
1652 /* Upper case letters in the instruction names here are macros.
1653 'A' => print 'b' if no register operands or suffix_always is true
1654 'B' => print 'b' if suffix_always is true
1655 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1656 size prefix
1657 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1658 suffix_always is true
1659 'E' => print 'e' if 32-bit form of jcxz
1660 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1661 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1662 'H' => print ",pt" or ",pn" branch hint
1663 'I' unused.
1664 'J' unused.
1665 'K' => print 'd' or 'q' if rex prefix is present.
1666 'L' unused.
1667 'M' => print 'r' if intel_mnemonic is false.
1668 'N' => print 'n' if instruction has no wait "prefix"
1669 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1670 'P' => behave as 'T' except with register operand outside of suffix_always
1671 mode
1672 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1673 is true
1674 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1675 'S' => print 'w', 'l' or 'q' if suffix_always is true
1676 'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1677 prefix or if suffix_always is true.
1678 'U' unused.
1679 'V' unused.
1680 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1681 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1682 'Y' unused.
1683 'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1684 '!' => change condition from true to false or from false to true.
1685 '%' => add 1 upper case letter to the macro.
1686 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1687 prefix or suffix_always is true (lcall/ljmp).
1688 '@' => in 64bit mode for Intel64 ISA or if instruction
1689 has no operand sizing prefix, print 'q' if suffix_always is true or
1690 nothing otherwise; behave as 'P' in all other cases
1691
1692 2 upper case letter macros:
1693 "XY" => print 'x' or 'y' if suffix_always is true or no register
1694 operands and no broadcast.
1695 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1696 register operands and no broadcast.
1697 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1698 "XV" => print "{vex3}" pseudo prefix
1699 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1700 being false, or no operand at all in 64bit mode, or if suffix_always
1701 is true.
1702 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1703 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1704 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1705 "DQ" => print 'd' or 'q' depending on the VEX.W bit
1706 "BW" => print 'b' or 'w' depending on the VEX.W bit
1707 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1708 an operand size prefix, or suffix_always is true. print
1709 'q' if rex prefix is present.
1710
1711 Many of the above letters print nothing in Intel mode. See "putop"
1712 for the details.
1713
1714 Braces '{' and '}', and vertical bars '|', indicate alternative
1715 mnemonic strings for AT&T and Intel. */
1716
1717 static const struct dis386 dis386[] = {
1718 /* 00 */
1719 { "addB", { Ebh1, Gb }, 0 },
1720 { "addS", { Evh1, Gv }, 0 },
1721 { "addB", { Gb, EbS }, 0 },
1722 { "addS", { Gv, EvS }, 0 },
1723 { "addB", { AL, Ib }, 0 },
1724 { "addS", { eAX, Iv }, 0 },
1725 { X86_64_TABLE (X86_64_06) },
1726 { X86_64_TABLE (X86_64_07) },
1727 /* 08 */
1728 { "orB", { Ebh1, Gb }, 0 },
1729 { "orS", { Evh1, Gv }, 0 },
1730 { "orB", { Gb, EbS }, 0 },
1731 { "orS", { Gv, EvS }, 0 },
1732 { "orB", { AL, Ib }, 0 },
1733 { "orS", { eAX, Iv }, 0 },
1734 { X86_64_TABLE (X86_64_0E) },
1735 { Bad_Opcode }, /* 0x0f extended opcode escape */
1736 /* 10 */
1737 { "adcB", { Ebh1, Gb }, 0 },
1738 { "adcS", { Evh1, Gv }, 0 },
1739 { "adcB", { Gb, EbS }, 0 },
1740 { "adcS", { Gv, EvS }, 0 },
1741 { "adcB", { AL, Ib }, 0 },
1742 { "adcS", { eAX, Iv }, 0 },
1743 { X86_64_TABLE (X86_64_16) },
1744 { X86_64_TABLE (X86_64_17) },
1745 /* 18 */
1746 { "sbbB", { Ebh1, Gb }, 0 },
1747 { "sbbS", { Evh1, Gv }, 0 },
1748 { "sbbB", { Gb, EbS }, 0 },
1749 { "sbbS", { Gv, EvS }, 0 },
1750 { "sbbB", { AL, Ib }, 0 },
1751 { "sbbS", { eAX, Iv }, 0 },
1752 { X86_64_TABLE (X86_64_1E) },
1753 { X86_64_TABLE (X86_64_1F) },
1754 /* 20 */
1755 { "andB", { Ebh1, Gb }, 0 },
1756 { "andS", { Evh1, Gv }, 0 },
1757 { "andB", { Gb, EbS }, 0 },
1758 { "andS", { Gv, EvS }, 0 },
1759 { "andB", { AL, Ib }, 0 },
1760 { "andS", { eAX, Iv }, 0 },
1761 { Bad_Opcode }, /* SEG ES prefix */
1762 { X86_64_TABLE (X86_64_27) },
1763 /* 28 */
1764 { "subB", { Ebh1, Gb }, 0 },
1765 { "subS", { Evh1, Gv }, 0 },
1766 { "subB", { Gb, EbS }, 0 },
1767 { "subS", { Gv, EvS }, 0 },
1768 { "subB", { AL, Ib }, 0 },
1769 { "subS", { eAX, Iv }, 0 },
1770 { Bad_Opcode }, /* SEG CS prefix */
1771 { X86_64_TABLE (X86_64_2F) },
1772 /* 30 */
1773 { "xorB", { Ebh1, Gb }, 0 },
1774 { "xorS", { Evh1, Gv }, 0 },
1775 { "xorB", { Gb, EbS }, 0 },
1776 { "xorS", { Gv, EvS }, 0 },
1777 { "xorB", { AL, Ib }, 0 },
1778 { "xorS", { eAX, Iv }, 0 },
1779 { Bad_Opcode }, /* SEG SS prefix */
1780 { X86_64_TABLE (X86_64_37) },
1781 /* 38 */
1782 { "cmpB", { Eb, Gb }, 0 },
1783 { "cmpS", { Ev, Gv }, 0 },
1784 { "cmpB", { Gb, EbS }, 0 },
1785 { "cmpS", { Gv, EvS }, 0 },
1786 { "cmpB", { AL, Ib }, 0 },
1787 { "cmpS", { eAX, Iv }, 0 },
1788 { Bad_Opcode }, /* SEG DS prefix */
1789 { X86_64_TABLE (X86_64_3F) },
1790 /* 40 */
1791 { "inc{S|}", { RMeAX }, 0 },
1792 { "inc{S|}", { RMeCX }, 0 },
1793 { "inc{S|}", { RMeDX }, 0 },
1794 { "inc{S|}", { RMeBX }, 0 },
1795 { "inc{S|}", { RMeSP }, 0 },
1796 { "inc{S|}", { RMeBP }, 0 },
1797 { "inc{S|}", { RMeSI }, 0 },
1798 { "inc{S|}", { RMeDI }, 0 },
1799 /* 48 */
1800 { "dec{S|}", { RMeAX }, 0 },
1801 { "dec{S|}", { RMeCX }, 0 },
1802 { "dec{S|}", { RMeDX }, 0 },
1803 { "dec{S|}", { RMeBX }, 0 },
1804 { "dec{S|}", { RMeSP }, 0 },
1805 { "dec{S|}", { RMeBP }, 0 },
1806 { "dec{S|}", { RMeSI }, 0 },
1807 { "dec{S|}", { RMeDI }, 0 },
1808 /* 50 */
1809 { "push{!P|}", { RMrAX }, 0 },
1810 { "push{!P|}", { RMrCX }, 0 },
1811 { "push{!P|}", { RMrDX }, 0 },
1812 { "push{!P|}", { RMrBX }, 0 },
1813 { "push{!P|}", { RMrSP }, 0 },
1814 { "push{!P|}", { RMrBP }, 0 },
1815 { "push{!P|}", { RMrSI }, 0 },
1816 { "push{!P|}", { RMrDI }, 0 },
1817 /* 58 */
1818 { "pop{!P|}", { RMrAX }, 0 },
1819 { "pop{!P|}", { RMrCX }, 0 },
1820 { "pop{!P|}", { RMrDX }, 0 },
1821 { "pop{!P|}", { RMrBX }, 0 },
1822 { "pop{!P|}", { RMrSP }, 0 },
1823 { "pop{!P|}", { RMrBP }, 0 },
1824 { "pop{!P|}", { RMrSI }, 0 },
1825 { "pop{!P|}", { RMrDI }, 0 },
1826 /* 60 */
1827 { X86_64_TABLE (X86_64_60) },
1828 { X86_64_TABLE (X86_64_61) },
1829 { X86_64_TABLE (X86_64_62) },
1830 { X86_64_TABLE (X86_64_63) },
1831 { Bad_Opcode }, /* seg fs */
1832 { Bad_Opcode }, /* seg gs */
1833 { Bad_Opcode }, /* op size prefix */
1834 { Bad_Opcode }, /* adr size prefix */
1835 /* 68 */
1836 { "pushP", { sIv }, 0 },
1837 { "imulS", { Gv, Ev, Iv }, 0 },
1838 { "pushP", { sIbT }, 0 },
1839 { "imulS", { Gv, Ev, sIb }, 0 },
1840 { "ins{b|}", { Ybr, indirDX }, 0 },
1841 { X86_64_TABLE (X86_64_6D) },
1842 { "outs{b|}", { indirDXr, Xb }, 0 },
1843 { X86_64_TABLE (X86_64_6F) },
1844 /* 70 */
1845 { "joH", { Jb, BND, cond_jump_flag }, 0 },
1846 { "jnoH", { Jb, BND, cond_jump_flag }, 0 },
1847 { "jbH", { Jb, BND, cond_jump_flag }, 0 },
1848 { "jaeH", { Jb, BND, cond_jump_flag }, 0 },
1849 { "jeH", { Jb, BND, cond_jump_flag }, 0 },
1850 { "jneH", { Jb, BND, cond_jump_flag }, 0 },
1851 { "jbeH", { Jb, BND, cond_jump_flag }, 0 },
1852 { "jaH", { Jb, BND, cond_jump_flag }, 0 },
1853 /* 78 */
1854 { "jsH", { Jb, BND, cond_jump_flag }, 0 },
1855 { "jnsH", { Jb, BND, cond_jump_flag }, 0 },
1856 { "jpH", { Jb, BND, cond_jump_flag }, 0 },
1857 { "jnpH", { Jb, BND, cond_jump_flag }, 0 },
1858 { "jlH", { Jb, BND, cond_jump_flag }, 0 },
1859 { "jgeH", { Jb, BND, cond_jump_flag }, 0 },
1860 { "jleH", { Jb, BND, cond_jump_flag }, 0 },
1861 { "jgH", { Jb, BND, cond_jump_flag }, 0 },
1862 /* 80 */
1863 { REG_TABLE (REG_80) },
1864 { REG_TABLE (REG_81) },
1865 { X86_64_TABLE (X86_64_82) },
1866 { REG_TABLE (REG_83) },
1867 { "testB", { Eb, Gb }, 0 },
1868 { "testS", { Ev, Gv }, 0 },
1869 { "xchgB", { Ebh2, Gb }, 0 },
1870 { "xchgS", { Evh2, Gv }, 0 },
1871 /* 88 */
1872 { "movB", { Ebh3, Gb }, 0 },
1873 { "movS", { Evh3, Gv }, 0 },
1874 { "movB", { Gb, EbS }, 0 },
1875 { "movS", { Gv, EvS }, 0 },
1876 { "movD", { Sv, Sw }, 0 },
1877 { MOD_TABLE (MOD_8D) },
1878 { "movD", { Sw, Sv }, 0 },
1879 { REG_TABLE (REG_8F) },
1880 /* 90 */
1881 { PREFIX_TABLE (PREFIX_90) },
1882 { "xchgS", { RMeCX, eAX }, 0 },
1883 { "xchgS", { RMeDX, eAX }, 0 },
1884 { "xchgS", { RMeBX, eAX }, 0 },
1885 { "xchgS", { RMeSP, eAX }, 0 },
1886 { "xchgS", { RMeBP, eAX }, 0 },
1887 { "xchgS", { RMeSI, eAX }, 0 },
1888 { "xchgS", { RMeDI, eAX }, 0 },
1889 /* 98 */
1890 { "cW{t|}R", { XX }, 0 },
1891 { "cR{t|}O", { XX }, 0 },
1892 { X86_64_TABLE (X86_64_9A) },
1893 { Bad_Opcode }, /* fwait */
1894 { "pushfP", { XX }, 0 },
1895 { "popfP", { XX }, 0 },
1896 { "sahf", { XX }, 0 },
1897 { "lahf", { XX }, 0 },
1898 /* a0 */
1899 { "mov%LB", { AL, Ob }, 0 },
1900 { "mov%LS", { eAX, Ov }, 0 },
1901 { "mov%LB", { Ob, AL }, 0 },
1902 { "mov%LS", { Ov, eAX }, 0 },
1903 { "movs{b|}", { Ybr, Xb }, 0 },
1904 { "movs{R|}", { Yvr, Xv }, 0 },
1905 { "cmps{b|}", { Xb, Yb }, 0 },
1906 { "cmps{R|}", { Xv, Yv }, 0 },
1907 /* a8 */
1908 { "testB", { AL, Ib }, 0 },
1909 { "testS", { eAX, Iv }, 0 },
1910 { "stosB", { Ybr, AL }, 0 },
1911 { "stosS", { Yvr, eAX }, 0 },
1912 { "lodsB", { ALr, Xb }, 0 },
1913 { "lodsS", { eAXr, Xv }, 0 },
1914 { "scasB", { AL, Yb }, 0 },
1915 { "scasS", { eAX, Yv }, 0 },
1916 /* b0 */
1917 { "movB", { RMAL, Ib }, 0 },
1918 { "movB", { RMCL, Ib }, 0 },
1919 { "movB", { RMDL, Ib }, 0 },
1920 { "movB", { RMBL, Ib }, 0 },
1921 { "movB", { RMAH, Ib }, 0 },
1922 { "movB", { RMCH, Ib }, 0 },
1923 { "movB", { RMDH, Ib }, 0 },
1924 { "movB", { RMBH, Ib }, 0 },
1925 /* b8 */
1926 { "mov%LV", { RMeAX, Iv64 }, 0 },
1927 { "mov%LV", { RMeCX, Iv64 }, 0 },
1928 { "mov%LV", { RMeDX, Iv64 }, 0 },
1929 { "mov%LV", { RMeBX, Iv64 }, 0 },
1930 { "mov%LV", { RMeSP, Iv64 }, 0 },
1931 { "mov%LV", { RMeBP, Iv64 }, 0 },
1932 { "mov%LV", { RMeSI, Iv64 }, 0 },
1933 { "mov%LV", { RMeDI, Iv64 }, 0 },
1934 /* c0 */
1935 { REG_TABLE (REG_C0) },
1936 { REG_TABLE (REG_C1) },
1937 { X86_64_TABLE (X86_64_C2) },
1938 { X86_64_TABLE (X86_64_C3) },
1939 { X86_64_TABLE (X86_64_C4) },
1940 { X86_64_TABLE (X86_64_C5) },
1941 { REG_TABLE (REG_C6) },
1942 { REG_TABLE (REG_C7) },
1943 /* c8 */
1944 { "enterP", { Iw, Ib }, 0 },
1945 { "leaveP", { XX }, 0 },
1946 { "{l|}ret{|f}%LP", { Iw }, 0 },
1947 { "{l|}ret{|f}%LP", { XX }, 0 },
1948 { "int3", { XX }, 0 },
1949 { "int", { Ib }, 0 },
1950 { X86_64_TABLE (X86_64_CE) },
1951 { "iret%LP", { XX }, 0 },
1952 /* d0 */
1953 { REG_TABLE (REG_D0) },
1954 { REG_TABLE (REG_D1) },
1955 { REG_TABLE (REG_D2) },
1956 { REG_TABLE (REG_D3) },
1957 { X86_64_TABLE (X86_64_D4) },
1958 { X86_64_TABLE (X86_64_D5) },
1959 { Bad_Opcode },
1960 { "xlat", { DSBX }, 0 },
1961 /* d8 */
1962 { FLOAT },
1963 { FLOAT },
1964 { FLOAT },
1965 { FLOAT },
1966 { FLOAT },
1967 { FLOAT },
1968 { FLOAT },
1969 { FLOAT },
1970 /* e0 */
1971 { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 },
1972 { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 },
1973 { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 },
1974 { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 },
1975 { "inB", { AL, Ib }, 0 },
1976 { "inG", { zAX, Ib }, 0 },
1977 { "outB", { Ib, AL }, 0 },
1978 { "outG", { Ib, zAX }, 0 },
1979 /* e8 */
1980 { X86_64_TABLE (X86_64_E8) },
1981 { X86_64_TABLE (X86_64_E9) },
1982 { X86_64_TABLE (X86_64_EA) },
1983 { "jmp", { Jb, BND }, 0 },
1984 { "inB", { AL, indirDX }, 0 },
1985 { "inG", { zAX, indirDX }, 0 },
1986 { "outB", { indirDX, AL }, 0 },
1987 { "outG", { indirDX, zAX }, 0 },
1988 /* f0 */
1989 { Bad_Opcode }, /* lock prefix */
1990 { "icebp", { XX }, 0 },
1991 { Bad_Opcode }, /* repne */
1992 { Bad_Opcode }, /* repz */
1993 { "hlt", { XX }, 0 },
1994 { "cmc", { XX }, 0 },
1995 { REG_TABLE (REG_F6) },
1996 { REG_TABLE (REG_F7) },
1997 /* f8 */
1998 { "clc", { XX }, 0 },
1999 { "stc", { XX }, 0 },
2000 { "cli", { XX }, 0 },
2001 { "sti", { XX }, 0 },
2002 { "cld", { XX }, 0 },
2003 { "std", { XX }, 0 },
2004 { REG_TABLE (REG_FE) },
2005 { REG_TABLE (REG_FF) },
2006 };
2007
2008 static const struct dis386 dis386_twobyte[] = {
2009 /* 00 */
2010 { REG_TABLE (REG_0F00 ) },
2011 { REG_TABLE (REG_0F01 ) },
2012 { "larS", { Gv, Ew }, 0 },
2013 { "lslS", { Gv, Ew }, 0 },
2014 { Bad_Opcode },
2015 { "syscall", { XX }, 0 },
2016 { "clts", { XX }, 0 },
2017 { "sysret%LQ", { XX }, 0 },
2018 /* 08 */
2019 { "invd", { XX }, 0 },
2020 { PREFIX_TABLE (PREFIX_0F09) },
2021 { Bad_Opcode },
2022 { "ud2", { XX }, 0 },
2023 { Bad_Opcode },
2024 { REG_TABLE (REG_0F0D) },
2025 { "femms", { XX }, 0 },
2026 { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */
2027 /* 10 */
2028 { PREFIX_TABLE (PREFIX_0F10) },
2029 { PREFIX_TABLE (PREFIX_0F11) },
2030 { PREFIX_TABLE (PREFIX_0F12) },
2031 { MOD_TABLE (MOD_0F13) },
2032 { "unpcklpX", { XM, EXx }, PREFIX_OPCODE },
2033 { "unpckhpX", { XM, EXx }, PREFIX_OPCODE },
2034 { PREFIX_TABLE (PREFIX_0F16) },
2035 { MOD_TABLE (MOD_0F17) },
2036 /* 18 */
2037 { REG_TABLE (REG_0F18) },
2038 { "nopQ", { Ev }, 0 },
2039 { PREFIX_TABLE (PREFIX_0F1A) },
2040 { PREFIX_TABLE (PREFIX_0F1B) },
2041 { PREFIX_TABLE (PREFIX_0F1C) },
2042 { "nopQ", { Ev }, 0 },
2043 { PREFIX_TABLE (PREFIX_0F1E) },
2044 { "nopQ", { Ev }, 0 },
2045 /* 20 */
2046 { "movZ", { Em, Cm }, 0 },
2047 { "movZ", { Em, Dm }, 0 },
2048 { "movZ", { Cm, Em }, 0 },
2049 { "movZ", { Dm, Em }, 0 },
2050 { X86_64_TABLE (X86_64_0F24) },
2051 { Bad_Opcode },
2052 { X86_64_TABLE (X86_64_0F26) },
2053 { Bad_Opcode },
2054 /* 28 */
2055 { "movapX", { XM, EXx }, PREFIX_OPCODE },
2056 { "movapX", { EXxS, XM }, PREFIX_OPCODE },
2057 { PREFIX_TABLE (PREFIX_0F2A) },
2058 { PREFIX_TABLE (PREFIX_0F2B) },
2059 { PREFIX_TABLE (PREFIX_0F2C) },
2060 { PREFIX_TABLE (PREFIX_0F2D) },
2061 { PREFIX_TABLE (PREFIX_0F2E) },
2062 { PREFIX_TABLE (PREFIX_0F2F) },
2063 /* 30 */
2064 { "wrmsr", { XX }, 0 },
2065 { "rdtsc", { XX }, 0 },
2066 { "rdmsr", { XX }, 0 },
2067 { "rdpmc", { XX }, 0 },
2068 { "sysenter", { SEP }, 0 },
2069 { "sysexit%LQ", { SEP }, 0 },
2070 { Bad_Opcode },
2071 { "getsec", { XX }, 0 },
2072 /* 38 */
2073 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2074 { Bad_Opcode },
2075 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2076 { Bad_Opcode },
2077 { Bad_Opcode },
2078 { Bad_Opcode },
2079 { Bad_Opcode },
2080 { Bad_Opcode },
2081 /* 40 */
2082 { "cmovoS", { Gv, Ev }, 0 },
2083 { "cmovnoS", { Gv, Ev }, 0 },
2084 { "cmovbS", { Gv, Ev }, 0 },
2085 { "cmovaeS", { Gv, Ev }, 0 },
2086 { "cmoveS", { Gv, Ev }, 0 },
2087 { "cmovneS", { Gv, Ev }, 0 },
2088 { "cmovbeS", { Gv, Ev }, 0 },
2089 { "cmovaS", { Gv, Ev }, 0 },
2090 /* 48 */
2091 { "cmovsS", { Gv, Ev }, 0 },
2092 { "cmovnsS", { Gv, Ev }, 0 },
2093 { "cmovpS", { Gv, Ev }, 0 },
2094 { "cmovnpS", { Gv, Ev }, 0 },
2095 { "cmovlS", { Gv, Ev }, 0 },
2096 { "cmovgeS", { Gv, Ev }, 0 },
2097 { "cmovleS", { Gv, Ev }, 0 },
2098 { "cmovgS", { Gv, Ev }, 0 },
2099 /* 50 */
2100 { MOD_TABLE (MOD_0F50) },
2101 { PREFIX_TABLE (PREFIX_0F51) },
2102 { PREFIX_TABLE (PREFIX_0F52) },
2103 { PREFIX_TABLE (PREFIX_0F53) },
2104 { "andpX", { XM, EXx }, PREFIX_OPCODE },
2105 { "andnpX", { XM, EXx }, PREFIX_OPCODE },
2106 { "orpX", { XM, EXx }, PREFIX_OPCODE },
2107 { "xorpX", { XM, EXx }, PREFIX_OPCODE },
2108 /* 58 */
2109 { PREFIX_TABLE (PREFIX_0F58) },
2110 { PREFIX_TABLE (PREFIX_0F59) },
2111 { PREFIX_TABLE (PREFIX_0F5A) },
2112 { PREFIX_TABLE (PREFIX_0F5B) },
2113 { PREFIX_TABLE (PREFIX_0F5C) },
2114 { PREFIX_TABLE (PREFIX_0F5D) },
2115 { PREFIX_TABLE (PREFIX_0F5E) },
2116 { PREFIX_TABLE (PREFIX_0F5F) },
2117 /* 60 */
2118 { PREFIX_TABLE (PREFIX_0F60) },
2119 { PREFIX_TABLE (PREFIX_0F61) },
2120 { PREFIX_TABLE (PREFIX_0F62) },
2121 { "packsswb", { MX, EM }, PREFIX_OPCODE },
2122 { "pcmpgtb", { MX, EM }, PREFIX_OPCODE },
2123 { "pcmpgtw", { MX, EM }, PREFIX_OPCODE },
2124 { "pcmpgtd", { MX, EM }, PREFIX_OPCODE },
2125 { "packuswb", { MX, EM }, PREFIX_OPCODE },
2126 /* 68 */
2127 { "punpckhbw", { MX, EM }, PREFIX_OPCODE },
2128 { "punpckhwd", { MX, EM }, PREFIX_OPCODE },
2129 { "punpckhdq", { MX, EM }, PREFIX_OPCODE },
2130 { "packssdw", { MX, EM }, PREFIX_OPCODE },
2131 { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2132 { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2133 { "movK", { MX, Edq }, PREFIX_OPCODE },
2134 { PREFIX_TABLE (PREFIX_0F6F) },
2135 /* 70 */
2136 { PREFIX_TABLE (PREFIX_0F70) },
2137 { MOD_TABLE (MOD_0F71) },
2138 { MOD_TABLE (MOD_0F72) },
2139 { MOD_TABLE (MOD_0F73) },
2140 { "pcmpeqb", { MX, EM }, PREFIX_OPCODE },
2141 { "pcmpeqw", { MX, EM }, PREFIX_OPCODE },
2142 { "pcmpeqd", { MX, EM }, PREFIX_OPCODE },
2143 { "emms", { XX }, PREFIX_OPCODE },
2144 /* 78 */
2145 { PREFIX_TABLE (PREFIX_0F78) },
2146 { PREFIX_TABLE (PREFIX_0F79) },
2147 { Bad_Opcode },
2148 { Bad_Opcode },
2149 { PREFIX_TABLE (PREFIX_0F7C) },
2150 { PREFIX_TABLE (PREFIX_0F7D) },
2151 { PREFIX_TABLE (PREFIX_0F7E) },
2152 { PREFIX_TABLE (PREFIX_0F7F) },
2153 /* 80 */
2154 { "joH", { Jv, BND, cond_jump_flag }, 0 },
2155 { "jnoH", { Jv, BND, cond_jump_flag }, 0 },
2156 { "jbH", { Jv, BND, cond_jump_flag }, 0 },
2157 { "jaeH", { Jv, BND, cond_jump_flag }, 0 },
2158 { "jeH", { Jv, BND, cond_jump_flag }, 0 },
2159 { "jneH", { Jv, BND, cond_jump_flag }, 0 },
2160 { "jbeH", { Jv, BND, cond_jump_flag }, 0 },
2161 { "jaH", { Jv, BND, cond_jump_flag }, 0 },
2162 /* 88 */
2163 { "jsH", { Jv, BND, cond_jump_flag }, 0 },
2164 { "jnsH", { Jv, BND, cond_jump_flag }, 0 },
2165 { "jpH", { Jv, BND, cond_jump_flag }, 0 },
2166 { "jnpH", { Jv, BND, cond_jump_flag }, 0 },
2167 { "jlH", { Jv, BND, cond_jump_flag }, 0 },
2168 { "jgeH", { Jv, BND, cond_jump_flag }, 0 },
2169 { "jleH", { Jv, BND, cond_jump_flag }, 0 },
2170 { "jgH", { Jv, BND, cond_jump_flag }, 0 },
2171 /* 90 */
2172 { "seto", { Eb }, 0 },
2173 { "setno", { Eb }, 0 },
2174 { "setb", { Eb }, 0 },
2175 { "setae", { Eb }, 0 },
2176 { "sete", { Eb }, 0 },
2177 { "setne", { Eb }, 0 },
2178 { "setbe", { Eb }, 0 },
2179 { "seta", { Eb }, 0 },
2180 /* 98 */
2181 { "sets", { Eb }, 0 },
2182 { "setns", { Eb }, 0 },
2183 { "setp", { Eb }, 0 },
2184 { "setnp", { Eb }, 0 },
2185 { "setl", { Eb }, 0 },
2186 { "setge", { Eb }, 0 },
2187 { "setle", { Eb }, 0 },
2188 { "setg", { Eb }, 0 },
2189 /* a0 */
2190 { "pushP", { fs }, 0 },
2191 { "popP", { fs }, 0 },
2192 { "cpuid", { XX }, 0 },
2193 { "btS", { Ev, Gv }, 0 },
2194 { "shldS", { Ev, Gv, Ib }, 0 },
2195 { "shldS", { Ev, Gv, CL }, 0 },
2196 { REG_TABLE (REG_0FA6) },
2197 { REG_TABLE (REG_0FA7) },
2198 /* a8 */
2199 { "pushP", { gs }, 0 },
2200 { "popP", { gs }, 0 },
2201 { "rsm", { XX }, 0 },
2202 { "btsS", { Evh1, Gv }, 0 },
2203 { "shrdS", { Ev, Gv, Ib }, 0 },
2204 { "shrdS", { Ev, Gv, CL }, 0 },
2205 { REG_TABLE (REG_0FAE) },
2206 { "imulS", { Gv, Ev }, 0 },
2207 /* b0 */
2208 { "cmpxchgB", { Ebh1, Gb }, 0 },
2209 { "cmpxchgS", { Evh1, Gv }, 0 },
2210 { MOD_TABLE (MOD_0FB2) },
2211 { "btrS", { Evh1, Gv }, 0 },
2212 { MOD_TABLE (MOD_0FB4) },
2213 { MOD_TABLE (MOD_0FB5) },
2214 { "movz{bR|x}", { Gv, Eb }, 0 },
2215 { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2216 /* b8 */
2217 { PREFIX_TABLE (PREFIX_0FB8) },
2218 { "ud1S", { Gv, Ev }, 0 },
2219 { REG_TABLE (REG_0FBA) },
2220 { "btcS", { Evh1, Gv }, 0 },
2221 { PREFIX_TABLE (PREFIX_0FBC) },
2222 { PREFIX_TABLE (PREFIX_0FBD) },
2223 { "movs{bR|x}", { Gv, Eb }, 0 },
2224 { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2225 /* c0 */
2226 { "xaddB", { Ebh1, Gb }, 0 },
2227 { "xaddS", { Evh1, Gv }, 0 },
2228 { PREFIX_TABLE (PREFIX_0FC2) },
2229 { MOD_TABLE (MOD_0FC3) },
2230 { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE },
2231 { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE },
2232 { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
2233 { REG_TABLE (REG_0FC7) },
2234 /* c8 */
2235 { "bswap", { RMeAX }, 0 },
2236 { "bswap", { RMeCX }, 0 },
2237 { "bswap", { RMeDX }, 0 },
2238 { "bswap", { RMeBX }, 0 },
2239 { "bswap", { RMeSP }, 0 },
2240 { "bswap", { RMeBP }, 0 },
2241 { "bswap", { RMeSI }, 0 },
2242 { "bswap", { RMeDI }, 0 },
2243 /* d0 */
2244 { PREFIX_TABLE (PREFIX_0FD0) },
2245 { "psrlw", { MX, EM }, PREFIX_OPCODE },
2246 { "psrld", { MX, EM }, PREFIX_OPCODE },
2247 { "psrlq", { MX, EM }, PREFIX_OPCODE },
2248 { "paddq", { MX, EM }, PREFIX_OPCODE },
2249 { "pmullw", { MX, EM }, PREFIX_OPCODE },
2250 { PREFIX_TABLE (PREFIX_0FD6) },
2251 { MOD_TABLE (MOD_0FD7) },
2252 /* d8 */
2253 { "psubusb", { MX, EM }, PREFIX_OPCODE },
2254 { "psubusw", { MX, EM }, PREFIX_OPCODE },
2255 { "pminub", { MX, EM }, PREFIX_OPCODE },
2256 { "pand", { MX, EM }, PREFIX_OPCODE },
2257 { "paddusb", { MX, EM }, PREFIX_OPCODE },
2258 { "paddusw", { MX, EM }, PREFIX_OPCODE },
2259 { "pmaxub", { MX, EM }, PREFIX_OPCODE },
2260 { "pandn", { MX, EM }, PREFIX_OPCODE },
2261 /* e0 */
2262 { "pavgb", { MX, EM }, PREFIX_OPCODE },
2263 { "psraw", { MX, EM }, PREFIX_OPCODE },
2264 { "psrad", { MX, EM }, PREFIX_OPCODE },
2265 { "pavgw", { MX, EM }, PREFIX_OPCODE },
2266 { "pmulhuw", { MX, EM }, PREFIX_OPCODE },
2267 { "pmulhw", { MX, EM }, PREFIX_OPCODE },
2268 { PREFIX_TABLE (PREFIX_0FE6) },
2269 { PREFIX_TABLE (PREFIX_0FE7) },
2270 /* e8 */
2271 { "psubsb", { MX, EM }, PREFIX_OPCODE },
2272 { "psubsw", { MX, EM }, PREFIX_OPCODE },
2273 { "pminsw", { MX, EM }, PREFIX_OPCODE },
2274 { "por", { MX, EM }, PREFIX_OPCODE },
2275 { "paddsb", { MX, EM }, PREFIX_OPCODE },
2276 { "paddsw", { MX, EM }, PREFIX_OPCODE },
2277 { "pmaxsw", { MX, EM }, PREFIX_OPCODE },
2278 { "pxor", { MX, EM }, PREFIX_OPCODE },
2279 /* f0 */
2280 { PREFIX_TABLE (PREFIX_0FF0) },
2281 { "psllw", { MX, EM }, PREFIX_OPCODE },
2282 { "pslld", { MX, EM }, PREFIX_OPCODE },
2283 { "psllq", { MX, EM }, PREFIX_OPCODE },
2284 { "pmuludq", { MX, EM }, PREFIX_OPCODE },
2285 { "pmaddwd", { MX, EM }, PREFIX_OPCODE },
2286 { "psadbw", { MX, EM }, PREFIX_OPCODE },
2287 { PREFIX_TABLE (PREFIX_0FF7) },
2288 /* f8 */
2289 { "psubb", { MX, EM }, PREFIX_OPCODE },
2290 { "psubw", { MX, EM }, PREFIX_OPCODE },
2291 { "psubd", { MX, EM }, PREFIX_OPCODE },
2292 { "psubq", { MX, EM }, PREFIX_OPCODE },
2293 { "paddb", { MX, EM }, PREFIX_OPCODE },
2294 { "paddw", { MX, EM }, PREFIX_OPCODE },
2295 { "paddd", { MX, EM }, PREFIX_OPCODE },
2296 { "ud0S", { Gv, Ev }, 0 },
2297 };
2298
2299 static const unsigned char onebyte_has_modrm[256] = {
2300 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2301 /* ------------------------------- */
2302 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2303 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2304 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2305 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2306 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2307 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2308 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2309 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2310 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2311 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2312 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2313 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2314 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2315 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2316 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2317 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2318 /* ------------------------------- */
2319 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2320 };
2321
2322 static const unsigned char twobyte_has_modrm[256] = {
2323 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2324 /* ------------------------------- */
2325 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2326 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2327 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2328 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2329 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2330 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2331 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2332 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2333 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2334 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2335 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2336 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2337 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2338 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2339 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2340 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2341 /* ------------------------------- */
2342 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2343 };
2344
2345 static char obuf[100];
2346 static char *obufp;
2347 static char *mnemonicendp;
2348 static char scratchbuf[100];
2349 static unsigned char *start_codep;
2350 static unsigned char *insn_codep;
2351 static unsigned char *codep;
2352 static unsigned char *end_codep;
2353 static int last_lock_prefix;
2354 static int last_repz_prefix;
2355 static int last_repnz_prefix;
2356 static int last_data_prefix;
2357 static int last_addr_prefix;
2358 static int last_rex_prefix;
2359 static int last_seg_prefix;
2360 static int fwait_prefix;
2361 /* The active segment register prefix. */
2362 static int active_seg_prefix;
2363 #define MAX_CODE_LENGTH 15
2364 /* We can up to 14 prefixes since the maximum instruction length is
2365 15bytes. */
2366 static int all_prefixes[MAX_CODE_LENGTH - 1];
2367 static disassemble_info *the_info;
2368 static struct
2369 {
2370 int mod;
2371 int reg;
2372 int rm;
2373 }
2374 modrm;
2375 static unsigned char need_modrm;
2376 static struct
2377 {
2378 int scale;
2379 int index;
2380 int base;
2381 }
2382 sib;
2383 static struct
2384 {
2385 int register_specifier;
2386 int length;
2387 int prefix;
2388 int w;
2389 int evex;
2390 int r;
2391 int v;
2392 int mask_register_specifier;
2393 int zeroing;
2394 int ll;
2395 int b;
2396 }
2397 vex;
2398 static unsigned char need_vex;
2399
2400 struct op
2401 {
2402 const char *name;
2403 unsigned int len;
2404 };
2405
2406 /* If we are accessing mod/rm/reg without need_modrm set, then the
2407 values are stale. Hitting this abort likely indicates that you
2408 need to update onebyte_has_modrm or twobyte_has_modrm. */
2409 #define MODRM_CHECK if (!need_modrm) abort ()
2410
2411 static const char **names64;
2412 static const char **names32;
2413 static const char **names16;
2414 static const char **names8;
2415 static const char **names8rex;
2416 static const char **names_seg;
2417 static const char *index64;
2418 static const char *index32;
2419 static const char **index16;
2420 static const char **names_bnd;
2421
2422 static const char *intel_names64[] = {
2423 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2424 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2425 };
2426 static const char *intel_names32[] = {
2427 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2428 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2429 };
2430 static const char *intel_names16[] = {
2431 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2432 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2433 };
2434 static const char *intel_names8[] = {
2435 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2436 };
2437 static const char *intel_names8rex[] = {
2438 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2439 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2440 };
2441 static const char *intel_names_seg[] = {
2442 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2443 };
2444 static const char *intel_index64 = "riz";
2445 static const char *intel_index32 = "eiz";
2446 static const char *intel_index16[] = {
2447 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2448 };
2449
2450 static const char *att_names64[] = {
2451 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2452 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2453 };
2454 static const char *att_names32[] = {
2455 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2456 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2457 };
2458 static const char *att_names16[] = {
2459 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2460 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2461 };
2462 static const char *att_names8[] = {
2463 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2464 };
2465 static const char *att_names8rex[] = {
2466 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2467 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2468 };
2469 static const char *att_names_seg[] = {
2470 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2471 };
2472 static const char *att_index64 = "%riz";
2473 static const char *att_index32 = "%eiz";
2474 static const char *att_index16[] = {
2475 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2476 };
2477
2478 static const char **names_mm;
2479 static const char *intel_names_mm[] = {
2480 "mm0", "mm1", "mm2", "mm3",
2481 "mm4", "mm5", "mm6", "mm7"
2482 };
2483 static const char *att_names_mm[] = {
2484 "%mm0", "%mm1", "%mm2", "%mm3",
2485 "%mm4", "%mm5", "%mm6", "%mm7"
2486 };
2487
2488 static const char *intel_names_bnd[] = {
2489 "bnd0", "bnd1", "bnd2", "bnd3"
2490 };
2491
2492 static const char *att_names_bnd[] = {
2493 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2494 };
2495
2496 static const char **names_xmm;
2497 static const char *intel_names_xmm[] = {
2498 "xmm0", "xmm1", "xmm2", "xmm3",
2499 "xmm4", "xmm5", "xmm6", "xmm7",
2500 "xmm8", "xmm9", "xmm10", "xmm11",
2501 "xmm12", "xmm13", "xmm14", "xmm15",
2502 "xmm16", "xmm17", "xmm18", "xmm19",
2503 "xmm20", "xmm21", "xmm22", "xmm23",
2504 "xmm24", "xmm25", "xmm26", "xmm27",
2505 "xmm28", "xmm29", "xmm30", "xmm31"
2506 };
2507 static const char *att_names_xmm[] = {
2508 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2509 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2510 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2511 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2512 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2513 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2514 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2515 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2516 };
2517
2518 static const char **names_ymm;
2519 static const char *intel_names_ymm[] = {
2520 "ymm0", "ymm1", "ymm2", "ymm3",
2521 "ymm4", "ymm5", "ymm6", "ymm7",
2522 "ymm8", "ymm9", "ymm10", "ymm11",
2523 "ymm12", "ymm13", "ymm14", "ymm15",
2524 "ymm16", "ymm17", "ymm18", "ymm19",
2525 "ymm20", "ymm21", "ymm22", "ymm23",
2526 "ymm24", "ymm25", "ymm26", "ymm27",
2527 "ymm28", "ymm29", "ymm30", "ymm31"
2528 };
2529 static const char *att_names_ymm[] = {
2530 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2531 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2532 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2533 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2534 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2535 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2536 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2537 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2538 };
2539
2540 static const char **names_zmm;
2541 static const char *intel_names_zmm[] = {
2542 "zmm0", "zmm1", "zmm2", "zmm3",
2543 "zmm4", "zmm5", "zmm6", "zmm7",
2544 "zmm8", "zmm9", "zmm10", "zmm11",
2545 "zmm12", "zmm13", "zmm14", "zmm15",
2546 "zmm16", "zmm17", "zmm18", "zmm19",
2547 "zmm20", "zmm21", "zmm22", "zmm23",
2548 "zmm24", "zmm25", "zmm26", "zmm27",
2549 "zmm28", "zmm29", "zmm30", "zmm31"
2550 };
2551 static const char *att_names_zmm[] = {
2552 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2553 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2554 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2555 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2556 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2557 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2558 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2559 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2560 };
2561
2562 static const char **names_tmm;
2563 static const char *intel_names_tmm[] = {
2564 "tmm0", "tmm1", "tmm2", "tmm3",
2565 "tmm4", "tmm5", "tmm6", "tmm7"
2566 };
2567 static const char *att_names_tmm[] = {
2568 "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2569 "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2570 };
2571
2572 static const char **names_mask;
2573 static const char *intel_names_mask[] = {
2574 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
2575 };
2576 static const char *att_names_mask[] = {
2577 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2578 };
2579
2580 static const char *names_rounding[] =
2581 {
2582 "{rn-sae}",
2583 "{rd-sae}",
2584 "{ru-sae}",
2585 "{rz-sae}"
2586 };
2587
2588 static const struct dis386 reg_table[][8] = {
2589 /* REG_80 */
2590 {
2591 { "addA", { Ebh1, Ib }, 0 },
2592 { "orA", { Ebh1, Ib }, 0 },
2593 { "adcA", { Ebh1, Ib }, 0 },
2594 { "sbbA", { Ebh1, Ib }, 0 },
2595 { "andA", { Ebh1, Ib }, 0 },
2596 { "subA", { Ebh1, Ib }, 0 },
2597 { "xorA", { Ebh1, Ib }, 0 },
2598 { "cmpA", { Eb, Ib }, 0 },
2599 },
2600 /* REG_81 */
2601 {
2602 { "addQ", { Evh1, Iv }, 0 },
2603 { "orQ", { Evh1, Iv }, 0 },
2604 { "adcQ", { Evh1, Iv }, 0 },
2605 { "sbbQ", { Evh1, Iv }, 0 },
2606 { "andQ", { Evh1, Iv }, 0 },
2607 { "subQ", { Evh1, Iv }, 0 },
2608 { "xorQ", { Evh1, Iv }, 0 },
2609 { "cmpQ", { Ev, Iv }, 0 },
2610 },
2611 /* REG_83 */
2612 {
2613 { "addQ", { Evh1, sIb }, 0 },
2614 { "orQ", { Evh1, sIb }, 0 },
2615 { "adcQ", { Evh1, sIb }, 0 },
2616 { "sbbQ", { Evh1, sIb }, 0 },
2617 { "andQ", { Evh1, sIb }, 0 },
2618 { "subQ", { Evh1, sIb }, 0 },
2619 { "xorQ", { Evh1, sIb }, 0 },
2620 { "cmpQ", { Ev, sIb }, 0 },
2621 },
2622 /* REG_8F */
2623 {
2624 { "pop{P|}", { stackEv }, 0 },
2625 { XOP_8F_TABLE (XOP_09) },
2626 { Bad_Opcode },
2627 { Bad_Opcode },
2628 { Bad_Opcode },
2629 { XOP_8F_TABLE (XOP_09) },
2630 },
2631 /* REG_C0 */
2632 {
2633 { "rolA", { Eb, Ib }, 0 },
2634 { "rorA", { Eb, Ib }, 0 },
2635 { "rclA", { Eb, Ib }, 0 },
2636 { "rcrA", { Eb, Ib }, 0 },
2637 { "shlA", { Eb, Ib }, 0 },
2638 { "shrA", { Eb, Ib }, 0 },
2639 { "shlA", { Eb, Ib }, 0 },
2640 { "sarA", { Eb, Ib }, 0 },
2641 },
2642 /* REG_C1 */
2643 {
2644 { "rolQ", { Ev, Ib }, 0 },
2645 { "rorQ", { Ev, Ib }, 0 },
2646 { "rclQ", { Ev, Ib }, 0 },
2647 { "rcrQ", { Ev, Ib }, 0 },
2648 { "shlQ", { Ev, Ib }, 0 },
2649 { "shrQ", { Ev, Ib }, 0 },
2650 { "shlQ", { Ev, Ib }, 0 },
2651 { "sarQ", { Ev, Ib }, 0 },
2652 },
2653 /* REG_C6 */
2654 {
2655 { "movA", { Ebh3, Ib }, 0 },
2656 { Bad_Opcode },
2657 { Bad_Opcode },
2658 { Bad_Opcode },
2659 { Bad_Opcode },
2660 { Bad_Opcode },
2661 { Bad_Opcode },
2662 { MOD_TABLE (MOD_C6_REG_7) },
2663 },
2664 /* REG_C7 */
2665 {
2666 { "movQ", { Evh3, Iv }, 0 },
2667 { Bad_Opcode },
2668 { Bad_Opcode },
2669 { Bad_Opcode },
2670 { Bad_Opcode },
2671 { Bad_Opcode },
2672 { Bad_Opcode },
2673 { MOD_TABLE (MOD_C7_REG_7) },
2674 },
2675 /* REG_D0 */
2676 {
2677 { "rolA", { Eb, I1 }, 0 },
2678 { "rorA", { Eb, I1 }, 0 },
2679 { "rclA", { Eb, I1 }, 0 },
2680 { "rcrA", { Eb, I1 }, 0 },
2681 { "shlA", { Eb, I1 }, 0 },
2682 { "shrA", { Eb, I1 }, 0 },
2683 { "shlA", { Eb, I1 }, 0 },
2684 { "sarA", { Eb, I1 }, 0 },
2685 },
2686 /* REG_D1 */
2687 {
2688 { "rolQ", { Ev, I1 }, 0 },
2689 { "rorQ", { Ev, I1 }, 0 },
2690 { "rclQ", { Ev, I1 }, 0 },
2691 { "rcrQ", { Ev, I1 }, 0 },
2692 { "shlQ", { Ev, I1 }, 0 },
2693 { "shrQ", { Ev, I1 }, 0 },
2694 { "shlQ", { Ev, I1 }, 0 },
2695 { "sarQ", { Ev, I1 }, 0 },
2696 },
2697 /* REG_D2 */
2698 {
2699 { "rolA", { Eb, CL }, 0 },
2700 { "rorA", { Eb, CL }, 0 },
2701 { "rclA", { Eb, CL }, 0 },
2702 { "rcrA", { Eb, CL }, 0 },
2703 { "shlA", { Eb, CL }, 0 },
2704 { "shrA", { Eb, CL }, 0 },
2705 { "shlA", { Eb, CL }, 0 },
2706 { "sarA", { Eb, CL }, 0 },
2707 },
2708 /* REG_D3 */
2709 {
2710 { "rolQ", { Ev, CL }, 0 },
2711 { "rorQ", { Ev, CL }, 0 },
2712 { "rclQ", { Ev, CL }, 0 },
2713 { "rcrQ", { Ev, CL }, 0 },
2714 { "shlQ", { Ev, CL }, 0 },
2715 { "shrQ", { Ev, CL }, 0 },
2716 { "shlQ", { Ev, CL }, 0 },
2717 { "sarQ", { Ev, CL }, 0 },
2718 },
2719 /* REG_F6 */
2720 {
2721 { "testA", { Eb, Ib }, 0 },
2722 { "testA", { Eb, Ib }, 0 },
2723 { "notA", { Ebh1 }, 0 },
2724 { "negA", { Ebh1 }, 0 },
2725 { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
2726 { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */
2727 { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */
2728 { "idivA", { Eb }, 0 }, /* and idiv for consistency. */
2729 },
2730 /* REG_F7 */
2731 {
2732 { "testQ", { Ev, Iv }, 0 },
2733 { "testQ", { Ev, Iv }, 0 },
2734 { "notQ", { Evh1 }, 0 },
2735 { "negQ", { Evh1 }, 0 },
2736 { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */
2737 { "imulQ", { Ev }, 0 },
2738 { "divQ", { Ev }, 0 },
2739 { "idivQ", { Ev }, 0 },
2740 },
2741 /* REG_FE */
2742 {
2743 { "incA", { Ebh1 }, 0 },
2744 { "decA", { Ebh1 }, 0 },
2745 },
2746 /* REG_FF */
2747 {
2748 { "incQ", { Evh1 }, 0 },
2749 { "decQ", { Evh1 }, 0 },
2750 { "call{@|}", { NOTRACK, indirEv, BND }, 0 },
2751 { MOD_TABLE (MOD_FF_REG_3) },
2752 { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 },
2753 { MOD_TABLE (MOD_FF_REG_5) },
2754 { "push{P|}", { stackEv }, 0 },
2755 { Bad_Opcode },
2756 },
2757 /* REG_0F00 */
2758 {
2759 { "sldtD", { Sv }, 0 },
2760 { "strD", { Sv }, 0 },
2761 { "lldt", { Ew }, 0 },
2762 { "ltr", { Ew }, 0 },
2763 { "verr", { Ew }, 0 },
2764 { "verw", { Ew }, 0 },
2765 { Bad_Opcode },
2766 { Bad_Opcode },
2767 },
2768 /* REG_0F01 */
2769 {
2770 { MOD_TABLE (MOD_0F01_REG_0) },
2771 { MOD_TABLE (MOD_0F01_REG_1) },
2772 { MOD_TABLE (MOD_0F01_REG_2) },
2773 { MOD_TABLE (MOD_0F01_REG_3) },
2774 { "smswD", { Sv }, 0 },
2775 { MOD_TABLE (MOD_0F01_REG_5) },
2776 { "lmsw", { Ew }, 0 },
2777 { MOD_TABLE (MOD_0F01_REG_7) },
2778 },
2779 /* REG_0F0D */
2780 {
2781 { "prefetch", { Mb }, 0 },
2782 { "prefetchw", { Mb }, 0 },
2783 { "prefetchwt1", { Mb }, 0 },
2784 { "prefetch", { Mb }, 0 },
2785 { "prefetch", { Mb }, 0 },
2786 { "prefetch", { Mb }, 0 },
2787 { "prefetch", { Mb }, 0 },
2788 { "prefetch", { Mb }, 0 },
2789 },
2790 /* REG_0F18 */
2791 {
2792 { MOD_TABLE (MOD_0F18_REG_0) },
2793 { MOD_TABLE (MOD_0F18_REG_1) },
2794 { MOD_TABLE (MOD_0F18_REG_2) },
2795 { MOD_TABLE (MOD_0F18_REG_3) },
2796 { "nopQ", { Ev }, 0 },
2797 { "nopQ", { Ev }, 0 },
2798 { "nopQ", { Ev }, 0 },
2799 { "nopQ", { Ev }, 0 },
2800 },
2801 /* REG_0F1C_P_0_MOD_0 */
2802 {
2803 { "cldemote", { Mb }, 0 },
2804 { "nopQ", { Ev }, 0 },
2805 { "nopQ", { Ev }, 0 },
2806 { "nopQ", { Ev }, 0 },
2807 { "nopQ", { Ev }, 0 },
2808 { "nopQ", { Ev }, 0 },
2809 { "nopQ", { Ev }, 0 },
2810 { "nopQ", { Ev }, 0 },
2811 },
2812 /* REG_0F1E_P_1_MOD_3 */
2813 {
2814 { "nopQ", { Ev }, PREFIX_IGNORED },
2815 { "rdsspK", { Edq }, 0 },
2816 { "nopQ", { Ev }, PREFIX_IGNORED },
2817 { "nopQ", { Ev }, PREFIX_IGNORED },
2818 { "nopQ", { Ev }, PREFIX_IGNORED },
2819 { "nopQ", { Ev }, PREFIX_IGNORED },
2820 { "nopQ", { Ev }, PREFIX_IGNORED },
2821 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2822 },
2823 /* REG_0F38D8_PREFIX_1 */
2824 {
2825 { "aesencwide128kl", { M }, 0 },
2826 { "aesdecwide128kl", { M }, 0 },
2827 { "aesencwide256kl", { M }, 0 },
2828 { "aesdecwide256kl", { M }, 0 },
2829 },
2830 /* REG_0F3A0F_PREFIX_1_MOD_3 */
2831 {
2832 { RM_TABLE (RM_0F3A0F_P_1_MOD_3_REG_0) },
2833 },
2834 /* REG_0F71_MOD_0 */
2835 {
2836 { Bad_Opcode },
2837 { Bad_Opcode },
2838 { "psrlw", { MS, Ib }, PREFIX_OPCODE },
2839 { Bad_Opcode },
2840 { "psraw", { MS, Ib }, PREFIX_OPCODE },
2841 { Bad_Opcode },
2842 { "psllw", { MS, Ib }, PREFIX_OPCODE },
2843 },
2844 /* REG_0F72_MOD_0 */
2845 {
2846 { Bad_Opcode },
2847 { Bad_Opcode },
2848 { "psrld", { MS, Ib }, PREFIX_OPCODE },
2849 { Bad_Opcode },
2850 { "psrad", { MS, Ib }, PREFIX_OPCODE },
2851 { Bad_Opcode },
2852 { "pslld", { MS, Ib }, PREFIX_OPCODE },
2853 },
2854 /* REG_0F73_MOD_0 */
2855 {
2856 { Bad_Opcode },
2857 { Bad_Opcode },
2858 { "psrlq", { MS, Ib }, PREFIX_OPCODE },
2859 { "psrldq", { XS, Ib }, PREFIX_DATA },
2860 { Bad_Opcode },
2861 { Bad_Opcode },
2862 { "psllq", { MS, Ib }, PREFIX_OPCODE },
2863 { "pslldq", { XS, Ib }, PREFIX_DATA },
2864 },
2865 /* REG_0FA6 */
2866 {
2867 { "montmul", { { OP_0f07, 0 } }, 0 },
2868 { "xsha1", { { OP_0f07, 0 } }, 0 },
2869 { "xsha256", { { OP_0f07, 0 } }, 0 },
2870 },
2871 /* REG_0FA7 */
2872 {
2873 { "xstore-rng", { { OP_0f07, 0 } }, 0 },
2874 { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 },
2875 { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 },
2876 { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 },
2877 { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 },
2878 { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 },
2879 },
2880 /* REG_0FAE */
2881 {
2882 { MOD_TABLE (MOD_0FAE_REG_0) },
2883 { MOD_TABLE (MOD_0FAE_REG_1) },
2884 { MOD_TABLE (MOD_0FAE_REG_2) },
2885 { MOD_TABLE (MOD_0FAE_REG_3) },
2886 { MOD_TABLE (MOD_0FAE_REG_4) },
2887 { MOD_TABLE (MOD_0FAE_REG_5) },
2888 { MOD_TABLE (MOD_0FAE_REG_6) },
2889 { MOD_TABLE (MOD_0FAE_REG_7) },
2890 },
2891 /* REG_0FBA */
2892 {
2893 { Bad_Opcode },
2894 { Bad_Opcode },
2895 { Bad_Opcode },
2896 { Bad_Opcode },
2897 { "btQ", { Ev, Ib }, 0 },
2898 { "btsQ", { Evh1, Ib }, 0 },
2899 { "btrQ", { Evh1, Ib }, 0 },
2900 { "btcQ", { Evh1, Ib }, 0 },
2901 },
2902 /* REG_0FC7 */
2903 {
2904 { Bad_Opcode },
2905 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
2906 { Bad_Opcode },
2907 { MOD_TABLE (MOD_0FC7_REG_3) },
2908 { MOD_TABLE (MOD_0FC7_REG_4) },
2909 { MOD_TABLE (MOD_0FC7_REG_5) },
2910 { MOD_TABLE (MOD_0FC7_REG_6) },
2911 { MOD_TABLE (MOD_0FC7_REG_7) },
2912 },
2913 /* REG_VEX_0F71_M_0 */
2914 {
2915 { Bad_Opcode },
2916 { Bad_Opcode },
2917 { "vpsrlw", { Vex, XS, Ib }, PREFIX_DATA },
2918 { Bad_Opcode },
2919 { "vpsraw", { Vex, XS, Ib }, PREFIX_DATA },
2920 { Bad_Opcode },
2921 { "vpsllw", { Vex, XS, Ib }, PREFIX_DATA },
2922 },
2923 /* REG_VEX_0F72_M_0 */
2924 {
2925 { Bad_Opcode },
2926 { Bad_Opcode },
2927 { "vpsrld", { Vex, XS, Ib }, PREFIX_DATA },
2928 { Bad_Opcode },
2929 { "vpsrad", { Vex, XS, Ib }, PREFIX_DATA },
2930 { Bad_Opcode },
2931 { "vpslld", { Vex, XS, Ib }, PREFIX_DATA },
2932 },
2933 /* REG_VEX_0F73_M_0 */
2934 {
2935 { Bad_Opcode },
2936 { Bad_Opcode },
2937 { "vpsrlq", { Vex, XS, Ib }, PREFIX_DATA },
2938 { "vpsrldq", { Vex, XS, Ib }, PREFIX_DATA },
2939 { Bad_Opcode },
2940 { Bad_Opcode },
2941 { "vpsllq", { Vex, XS, Ib }, PREFIX_DATA },
2942 { "vpslldq", { Vex, XS, Ib }, PREFIX_DATA },
2943 },
2944 /* REG_VEX_0FAE */
2945 {
2946 { Bad_Opcode },
2947 { Bad_Opcode },
2948 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
2949 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
2950 },
2951 /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
2952 {
2953 { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) },
2954 },
2955 /* REG_VEX_0F38F3_L_0 */
2956 {
2957 { Bad_Opcode },
2958 { "blsrS", { VexGdq, Edq }, PREFIX_OPCODE },
2959 { "blsmskS", { VexGdq, Edq }, PREFIX_OPCODE },
2960 { "blsiS", { VexGdq, Edq }, PREFIX_OPCODE },
2961 },
2962 /* REG_0FXOP_09_01_L_0 */
2963 {
2964 { Bad_Opcode },
2965 { "blcfill", { VexGdq, Edq }, 0 },
2966 { "blsfill", { VexGdq, Edq }, 0 },
2967 { "blcs", { VexGdq, Edq }, 0 },
2968 { "tzmsk", { VexGdq, Edq }, 0 },
2969 { "blcic", { VexGdq, Edq }, 0 },
2970 { "blsic", { VexGdq, Edq }, 0 },
2971 { "t1mskc", { VexGdq, Edq }, 0 },
2972 },
2973 /* REG_0FXOP_09_02_L_0 */
2974 {
2975 { Bad_Opcode },
2976 { "blcmsk", { VexGdq, Edq }, 0 },
2977 { Bad_Opcode },
2978 { Bad_Opcode },
2979 { Bad_Opcode },
2980 { Bad_Opcode },
2981 { "blci", { VexGdq, Edq }, 0 },
2982 },
2983 /* REG_0FXOP_09_12_M_1_L_0 */
2984 {
2985 { "llwpcb", { Edq }, 0 },
2986 { "slwpcb", { Edq }, 0 },
2987 },
2988 /* REG_0FXOP_0A_12_L_0 */
2989 {
2990 { "lwpins", { VexGdq, Ed, Id }, 0 },
2991 { "lwpval", { VexGdq, Ed, Id }, 0 },
2992 },
2993
2994 #include "i386-dis-evex-reg.h"
2995 };
2996
2997 static const struct dis386 prefix_table[][4] = {
2998 /* PREFIX_90 */
2999 {
3000 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3001 { "pause", { XX }, 0 },
3002 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3003 { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3004 },
3005
3006 /* PREFIX_0F01_REG_1_RM_4 */
3007 {
3008 { Bad_Opcode },
3009 { Bad_Opcode },
3010 { "tdcall", { Skip_MODRM }, 0 },
3011 { Bad_Opcode },
3012 },
3013
3014 /* PREFIX_0F01_REG_1_RM_5 */
3015 {
3016 { Bad_Opcode },
3017 { Bad_Opcode },
3018 { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) },
3019 { Bad_Opcode },
3020 },
3021
3022 /* PREFIX_0F01_REG_1_RM_6 */
3023 {
3024 { Bad_Opcode },
3025 { Bad_Opcode },
3026 { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) },
3027 { Bad_Opcode },
3028 },
3029
3030 /* PREFIX_0F01_REG_1_RM_7 */
3031 {
3032 { "encls", { Skip_MODRM }, 0 },
3033 { Bad_Opcode },
3034 { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) },
3035 { Bad_Opcode },
3036 },
3037
3038 /* PREFIX_0F01_REG_3_RM_1 */
3039 {
3040 { "vmmcall", { Skip_MODRM }, 0 },
3041 { "vmgexit", { Skip_MODRM }, 0 },
3042 { Bad_Opcode },
3043 { "vmgexit", { Skip_MODRM }, 0 },
3044 },
3045
3046 /* PREFIX_0F01_REG_5_MOD_0 */
3047 {
3048 { Bad_Opcode },
3049 { "rstorssp", { Mq }, PREFIX_OPCODE },
3050 },
3051
3052 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3053 {
3054 { "serialize", { Skip_MODRM }, PREFIX_OPCODE },
3055 { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
3056 { Bad_Opcode },
3057 { "xsusldtrk", { Skip_MODRM }, PREFIX_OPCODE },
3058 },
3059
3060 /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3061 {
3062 { Bad_Opcode },
3063 { Bad_Opcode },
3064 { Bad_Opcode },
3065 { "xresldtrk", { Skip_MODRM }, PREFIX_OPCODE },
3066 },
3067
3068 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3069 {
3070 { Bad_Opcode },
3071 { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE },
3072 },
3073
3074 /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
3075 {
3076 { Bad_Opcode },
3077 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1) },
3078 },
3079
3080 /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
3081 {
3082 { Bad_Opcode },
3083 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1) },
3084 },
3085
3086 /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3087 {
3088 { "rdpkru", { Skip_MODRM }, 0 },
3089 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1) },
3090 },
3091
3092 /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3093 {
3094 { "wrpkru", { Skip_MODRM }, 0 },
3095 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1) },
3096 },
3097
3098 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3099 {
3100 { "monitorx", { { OP_Monitor, 0 } }, 0 },
3101 { "mcommit", { Skip_MODRM }, 0 },
3102 },
3103
3104 /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
3105 {
3106 { "invlpgb", { Skip_MODRM }, 0 },
3107 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1) },
3108 { Bad_Opcode },
3109 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3) },
3110 },
3111
3112 /* PREFIX_0F01_REG_7_MOD_3_RM_7 */
3113 {
3114 { "tlbsync", { Skip_MODRM }, 0 },
3115 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1) },
3116 { Bad_Opcode },
3117 { "pvalidate", { Skip_MODRM }, 0 },
3118 },
3119
3120 /* PREFIX_0F09 */
3121 {
3122 { "wbinvd", { XX }, 0 },
3123 { "wbnoinvd", { XX }, 0 },
3124 },
3125
3126 /* PREFIX_0F10 */
3127 {
3128 { "movups", { XM, EXx }, PREFIX_OPCODE },
3129 { "movss", { XM, EXd }, PREFIX_OPCODE },
3130 { "movupd", { XM, EXx }, PREFIX_OPCODE },
3131 { "movsd", { XM, EXq }, PREFIX_OPCODE },
3132 },
3133
3134 /* PREFIX_0F11 */
3135 {
3136 { "movups", { EXxS, XM }, PREFIX_OPCODE },
3137 { "movss", { EXdS, XM }, PREFIX_OPCODE },
3138 { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3139 { "movsd", { EXqS, XM }, PREFIX_OPCODE },
3140 },
3141
3142 /* PREFIX_0F12 */
3143 {
3144 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3145 { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3146 { MOD_TABLE (MOD_0F12_PREFIX_2) },
3147 { "movddup", { XM, EXq }, PREFIX_OPCODE },
3148 },
3149
3150 /* PREFIX_0F16 */
3151 {
3152 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3153 { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3154 { MOD_TABLE (MOD_0F16_PREFIX_2) },
3155 },
3156
3157 /* PREFIX_0F1A */
3158 {
3159 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3160 { "bndcl", { Gbnd, Ev_bnd }, 0 },
3161 { "bndmov", { Gbnd, Ebnd }, 0 },
3162 { "bndcu", { Gbnd, Ev_bnd }, 0 },
3163 },
3164
3165 /* PREFIX_0F1B */
3166 {
3167 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3168 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3169 { "bndmov", { EbndS, Gbnd }, 0 },
3170 { "bndcn", { Gbnd, Ev_bnd }, 0 },
3171 },
3172
3173 /* PREFIX_0F1C */
3174 {
3175 { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3176 { "nopQ", { Ev }, PREFIX_IGNORED },
3177 { "nopQ", { Ev }, 0 },
3178 { "nopQ", { Ev }, PREFIX_IGNORED },
3179 },
3180
3181 /* PREFIX_0F1E */
3182 {
3183 { "nopQ", { Ev }, 0 },
3184 { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3185 { "nopQ", { Ev }, 0 },
3186 { NULL, { XX }, PREFIX_IGNORED },
3187 },
3188
3189 /* PREFIX_0F2A */
3190 {
3191 { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3192 { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3193 { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3194 { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3195 },
3196
3197 /* PREFIX_0F2B */
3198 {
3199 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3200 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3201 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3202 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3203 },
3204
3205 /* PREFIX_0F2C */
3206 {
3207 { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3208 { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3209 { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3210 { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3211 },
3212
3213 /* PREFIX_0F2D */
3214 {
3215 { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3216 { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3217 { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3218 { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3219 },
3220
3221 /* PREFIX_0F2E */
3222 {
3223 { "ucomiss",{ XM, EXd }, 0 },
3224 { Bad_Opcode },
3225 { "ucomisd",{ XM, EXq }, 0 },
3226 },
3227
3228 /* PREFIX_0F2F */
3229 {
3230 { "comiss", { XM, EXd }, 0 },
3231 { Bad_Opcode },
3232 { "comisd", { XM, EXq }, 0 },
3233 },
3234
3235 /* PREFIX_0F51 */
3236 {
3237 { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3238 { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3239 { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3240 { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3241 },
3242
3243 /* PREFIX_0F52 */
3244 {
3245 { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3246 { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3247 },
3248
3249 /* PREFIX_0F53 */
3250 {
3251 { "rcpps", { XM, EXx }, PREFIX_OPCODE },
3252 { "rcpss", { XM, EXd }, PREFIX_OPCODE },
3253 },
3254
3255 /* PREFIX_0F58 */
3256 {
3257 { "addps", { XM, EXx }, PREFIX_OPCODE },
3258 { "addss", { XM, EXd }, PREFIX_OPCODE },
3259 { "addpd", { XM, EXx }, PREFIX_OPCODE },
3260 { "addsd", { XM, EXq }, PREFIX_OPCODE },
3261 },
3262
3263 /* PREFIX_0F59 */
3264 {
3265 { "mulps", { XM, EXx }, PREFIX_OPCODE },
3266 { "mulss", { XM, EXd }, PREFIX_OPCODE },
3267 { "mulpd", { XM, EXx }, PREFIX_OPCODE },
3268 { "mulsd", { XM, EXq }, PREFIX_OPCODE },
3269 },
3270
3271 /* PREFIX_0F5A */
3272 {
3273 { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3274 { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3275 { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3276 { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3277 },
3278
3279 /* PREFIX_0F5B */
3280 {
3281 { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3282 { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3283 { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3284 },
3285
3286 /* PREFIX_0F5C */
3287 {
3288 { "subps", { XM, EXx }, PREFIX_OPCODE },
3289 { "subss", { XM, EXd }, PREFIX_OPCODE },
3290 { "subpd", { XM, EXx }, PREFIX_OPCODE },
3291 { "subsd", { XM, EXq }, PREFIX_OPCODE },
3292 },
3293
3294 /* PREFIX_0F5D */
3295 {
3296 { "minps", { XM, EXx }, PREFIX_OPCODE },
3297 { "minss", { XM, EXd }, PREFIX_OPCODE },
3298 { "minpd", { XM, EXx }, PREFIX_OPCODE },
3299 { "minsd", { XM, EXq }, PREFIX_OPCODE },
3300 },
3301
3302 /* PREFIX_0F5E */
3303 {
3304 { "divps", { XM, EXx }, PREFIX_OPCODE },
3305 { "divss", { XM, EXd }, PREFIX_OPCODE },
3306 { "divpd", { XM, EXx }, PREFIX_OPCODE },
3307 { "divsd", { XM, EXq }, PREFIX_OPCODE },
3308 },
3309
3310 /* PREFIX_0F5F */
3311 {
3312 { "maxps", { XM, EXx }, PREFIX_OPCODE },
3313 { "maxss", { XM, EXd }, PREFIX_OPCODE },
3314 { "maxpd", { XM, EXx }, PREFIX_OPCODE },
3315 { "maxsd", { XM, EXq }, PREFIX_OPCODE },
3316 },
3317
3318 /* PREFIX_0F60 */
3319 {
3320 { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3321 { Bad_Opcode },
3322 { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3323 },
3324
3325 /* PREFIX_0F61 */
3326 {
3327 { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3328 { Bad_Opcode },
3329 { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3330 },
3331
3332 /* PREFIX_0F62 */
3333 {
3334 { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3335 { Bad_Opcode },
3336 { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3337 },
3338
3339 /* PREFIX_0F6F */
3340 {
3341 { "movq", { MX, EM }, PREFIX_OPCODE },
3342 { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3343 { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3344 },
3345
3346 /* PREFIX_0F70 */
3347 {
3348 { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3349 { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3350 { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3351 { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3352 },
3353
3354 /* PREFIX_0F78 */
3355 {
3356 {"vmread", { Em, Gm }, 0 },
3357 { Bad_Opcode },
3358 {"extrq", { XS, Ib, Ib }, 0 },
3359 {"insertq", { XM, XS, Ib, Ib }, 0 },
3360 },
3361
3362 /* PREFIX_0F79 */
3363 {
3364 {"vmwrite", { Gm, Em }, 0 },
3365 { Bad_Opcode },
3366 {"extrq", { XM, XS }, 0 },
3367 {"insertq", { XM, XS }, 0 },
3368 },
3369
3370 /* PREFIX_0F7C */
3371 {
3372 { Bad_Opcode },
3373 { Bad_Opcode },
3374 { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3375 { "haddps", { XM, EXx }, PREFIX_OPCODE },
3376 },
3377
3378 /* PREFIX_0F7D */
3379 {
3380 { Bad_Opcode },
3381 { Bad_Opcode },
3382 { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3383 { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3384 },
3385
3386 /* PREFIX_0F7E */
3387 {
3388 { "movK", { Edq, MX }, PREFIX_OPCODE },
3389 { "movq", { XM, EXq }, PREFIX_OPCODE },
3390 { "movK", { Edq, XM }, PREFIX_OPCODE },
3391 },
3392
3393 /* PREFIX_0F7F */
3394 {
3395 { "movq", { EMS, MX }, PREFIX_OPCODE },
3396 { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3397 { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3398 },
3399
3400 /* PREFIX_0FAE_REG_0_MOD_3 */
3401 {
3402 { Bad_Opcode },
3403 { "rdfsbase", { Ev }, 0 },
3404 },
3405
3406 /* PREFIX_0FAE_REG_1_MOD_3 */
3407 {
3408 { Bad_Opcode },
3409 { "rdgsbase", { Ev }, 0 },
3410 },
3411
3412 /* PREFIX_0FAE_REG_2_MOD_3 */
3413 {
3414 { Bad_Opcode },
3415 { "wrfsbase", { Ev }, 0 },
3416 },
3417
3418 /* PREFIX_0FAE_REG_3_MOD_3 */
3419 {
3420 { Bad_Opcode },
3421 { "wrgsbase", { Ev }, 0 },
3422 },
3423
3424 /* PREFIX_0FAE_REG_4_MOD_0 */
3425 {
3426 { "xsave", { FXSAVE }, 0 },
3427 { "ptwrite{%LQ|}", { Edq }, 0 },
3428 },
3429
3430 /* PREFIX_0FAE_REG_4_MOD_3 */
3431 {
3432 { Bad_Opcode },
3433 { "ptwrite{%LQ|}", { Edq }, 0 },
3434 },
3435
3436 /* PREFIX_0FAE_REG_5_MOD_3 */
3437 {
3438 { "lfence", { Skip_MODRM }, 0 },
3439 { "incsspK", { Edq }, PREFIX_OPCODE },
3440 },
3441
3442 /* PREFIX_0FAE_REG_6_MOD_0 */
3443 {
3444 { "xsaveopt", { FXSAVE }, PREFIX_OPCODE },
3445 { "clrssbsy", { Mq }, PREFIX_OPCODE },
3446 { "clwb", { Mb }, PREFIX_OPCODE },
3447 },
3448
3449 /* PREFIX_0FAE_REG_6_MOD_3 */
3450 {
3451 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3452 { "umonitor", { Eva }, PREFIX_OPCODE },
3453 { "tpause", { Edq }, PREFIX_OPCODE },
3454 { "umwait", { Edq }, PREFIX_OPCODE },
3455 },
3456
3457 /* PREFIX_0FAE_REG_7_MOD_0 */
3458 {
3459 { "clflush", { Mb }, 0 },
3460 { Bad_Opcode },
3461 { "clflushopt", { Mb }, 0 },
3462 },
3463
3464 /* PREFIX_0FB8 */
3465 {
3466 { Bad_Opcode },
3467 { "popcntS", { Gv, Ev }, 0 },
3468 },
3469
3470 /* PREFIX_0FBC */
3471 {
3472 { "bsfS", { Gv, Ev }, 0 },
3473 { "tzcntS", { Gv, Ev }, 0 },
3474 { "bsfS", { Gv, Ev }, 0 },
3475 },
3476
3477 /* PREFIX_0FBD */
3478 {
3479 { "bsrS", { Gv, Ev }, 0 },
3480 { "lzcntS", { Gv, Ev }, 0 },
3481 { "bsrS", { Gv, Ev }, 0 },
3482 },
3483
3484 /* PREFIX_0FC2 */
3485 {
3486 { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE },
3487 { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE },
3488 { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE },
3489 { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE },
3490 },
3491
3492 /* PREFIX_0FC7_REG_6_MOD_0 */
3493 {
3494 { "vmptrld",{ Mq }, 0 },
3495 { "vmxon", { Mq }, 0 },
3496 { "vmclear",{ Mq }, 0 },
3497 },
3498
3499 /* PREFIX_0FC7_REG_6_MOD_3 */
3500 {
3501 { "rdrand", { Ev }, 0 },
3502 { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1) },
3503 { "rdrand", { Ev }, 0 }
3504 },
3505
3506 /* PREFIX_0FC7_REG_7_MOD_3 */
3507 {
3508 { "rdseed", { Ev }, 0 },
3509 { "rdpid", { Em }, 0 },
3510 { "rdseed", { Ev }, 0 },
3511 },
3512
3513 /* PREFIX_0FD0 */
3514 {
3515 { Bad_Opcode },
3516 { Bad_Opcode },
3517 { "addsubpd", { XM, EXx }, 0 },
3518 { "addsubps", { XM, EXx }, 0 },
3519 },
3520
3521 /* PREFIX_0FD6 */
3522 {
3523 { Bad_Opcode },
3524 { "movq2dq",{ XM, MS }, 0 },
3525 { "movq", { EXqS, XM }, 0 },
3526 { "movdq2q",{ MX, XS }, 0 },
3527 },
3528
3529 /* PREFIX_0FE6 */
3530 {
3531 { Bad_Opcode },
3532 { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
3533 { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
3534 { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
3535 },
3536
3537 /* PREFIX_0FE7 */
3538 {
3539 { "movntq", { Mq, MX }, PREFIX_OPCODE },
3540 { Bad_Opcode },
3541 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3542 },
3543
3544 /* PREFIX_0FF0 */
3545 {
3546 { Bad_Opcode },
3547 { Bad_Opcode },
3548 { Bad_Opcode },
3549 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3550 },
3551
3552 /* PREFIX_0FF7 */
3553 {
3554 { "maskmovq", { MX, MS }, PREFIX_OPCODE },
3555 { Bad_Opcode },
3556 { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
3557 },
3558
3559 /* PREFIX_0F38D8 */
3560 {
3561 { Bad_Opcode },
3562 { REG_TABLE (REG_0F38D8_PREFIX_1) },
3563 },
3564
3565 /* PREFIX_0F38DC */
3566 {
3567 { Bad_Opcode },
3568 { MOD_TABLE (MOD_0F38DC_PREFIX_1) },
3569 { "aesenc", { XM, EXx }, 0 },
3570 },
3571
3572 /* PREFIX_0F38DD */
3573 {
3574 { Bad_Opcode },
3575 { MOD_TABLE (MOD_0F38DD_PREFIX_1) },
3576 { "aesenclast", { XM, EXx }, 0 },
3577 },
3578
3579 /* PREFIX_0F38DE */
3580 {
3581 { Bad_Opcode },
3582 { MOD_TABLE (MOD_0F38DE_PREFIX_1) },
3583 { "aesdec", { XM, EXx }, 0 },
3584 },
3585
3586 /* PREFIX_0F38DF */
3587 {
3588 { Bad_Opcode },
3589 { MOD_TABLE (MOD_0F38DF_PREFIX_1) },
3590 { "aesdeclast", { XM, EXx }, 0 },
3591 },
3592
3593 /* PREFIX_0F38F0 */
3594 {
3595 { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3596 { Bad_Opcode },
3597 { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3598 { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
3599 },
3600
3601 /* PREFIX_0F38F1 */
3602 {
3603 { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3604 { Bad_Opcode },
3605 { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3606 { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
3607 },
3608
3609 /* PREFIX_0F38F6 */
3610 {
3611 { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
3612 { "adoxS", { Gdq, Edq}, PREFIX_OPCODE },
3613 { "adcxS", { Gdq, Edq}, PREFIX_OPCODE },
3614 { Bad_Opcode },
3615 },
3616
3617 /* PREFIX_0F38F8 */
3618 {
3619 { Bad_Opcode },
3620 { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
3621 { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
3622 { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
3623 },
3624 /* PREFIX_0F38FA */
3625 {
3626 { Bad_Opcode },
3627 { MOD_TABLE (MOD_0F38FA_PREFIX_1) },
3628 },
3629
3630 /* PREFIX_0F38FB */
3631 {
3632 { Bad_Opcode },
3633 { MOD_TABLE (MOD_0F38FB_PREFIX_1) },
3634 },
3635
3636 /* PREFIX_0F3A0F */
3637 {
3638 { Bad_Opcode },
3639 { MOD_TABLE (MOD_0F3A0F_PREFIX_1)},
3640 },
3641
3642 /* PREFIX_VEX_0F10 */
3643 {
3644 { "vmovups", { XM, EXx }, 0 },
3645 { "vmovss", { XMScalar, VexScalarR, EXxmm_md }, 0 },
3646 { "vmovupd", { XM, EXx }, 0 },
3647 { "vmovsd", { XMScalar, VexScalarR, EXxmm_mq }, 0 },
3648 },
3649
3650 /* PREFIX_VEX_0F11 */
3651 {
3652 { "vmovups", { EXxS, XM }, 0 },
3653 { "vmovss", { EXdS, VexScalarR, XMScalar }, 0 },
3654 { "vmovupd", { EXxS, XM }, 0 },
3655 { "vmovsd", { EXqS, VexScalarR, XMScalar }, 0 },
3656 },
3657
3658 /* PREFIX_VEX_0F12 */
3659 {
3660 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3661 { "vmovsldup", { XM, EXx }, 0 },
3662 { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
3663 { "vmovddup", { XM, EXymmq }, 0 },
3664 },
3665
3666 /* PREFIX_VEX_0F16 */
3667 {
3668 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3669 { "vmovshdup", { XM, EXx }, 0 },
3670 { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
3671 },
3672
3673 /* PREFIX_VEX_0F2A */
3674 {
3675 { Bad_Opcode },
3676 { "vcvtsi2ss{%LQ|}", { XMScalar, VexScalar, Edq }, 0 },
3677 { Bad_Opcode },
3678 { "vcvtsi2sd{%LQ|}", { XMScalar, VexScalar, Edq }, 0 },
3679 },
3680
3681 /* PREFIX_VEX_0F2C */
3682 {
3683 { Bad_Opcode },
3684 { "vcvttss2si", { Gdq, EXxmm_md, EXxEVexS }, 0 },
3685 { Bad_Opcode },
3686 { "vcvttsd2si", { Gdq, EXxmm_mq, EXxEVexS }, 0 },
3687 },
3688
3689 /* PREFIX_VEX_0F2D */
3690 {
3691 { Bad_Opcode },
3692 { "vcvtss2si", { Gdq, EXxmm_md, EXxEVexR }, 0 },
3693 { Bad_Opcode },
3694 { "vcvtsd2si", { Gdq, EXxmm_mq, EXxEVexR }, 0 },
3695 },
3696
3697 /* PREFIX_VEX_0F2E */
3698 {
3699 { "vucomisX", { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
3700 { Bad_Opcode },
3701 { "vucomisX", { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
3702 },
3703
3704 /* PREFIX_VEX_0F2F */
3705 {
3706 { "vcomisX", { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
3707 { Bad_Opcode },
3708 { "vcomisX", { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
3709 },
3710
3711 /* PREFIX_VEX_0F41_L_1_M_1_W_0 */
3712 {
3713 { "kandw", { MaskG, MaskVex, MaskE }, 0 },
3714 { Bad_Opcode },
3715 { "kandb", { MaskG, MaskVex, MaskE }, 0 },
3716 },
3717
3718 /* PREFIX_VEX_0F41_L_1_M_1_W_1 */
3719 {
3720 { "kandq", { MaskG, MaskVex, MaskE }, 0 },
3721 { Bad_Opcode },
3722 { "kandd", { MaskG, MaskVex, MaskE }, 0 },
3723 },
3724
3725 /* PREFIX_VEX_0F42_L_1_M_1_W_0 */
3726 {
3727 { "kandnw", { MaskG, MaskVex, MaskE }, 0 },
3728 { Bad_Opcode },
3729 { "kandnb", { MaskG, MaskVex, MaskE }, 0 },
3730 },
3731
3732 /* PREFIX_VEX_0F42_L_1_M_1_W_1 */
3733 {
3734 { "kandnq", { MaskG, MaskVex, MaskE }, 0 },
3735 { Bad_Opcode },
3736 { "kandnd", { MaskG, MaskVex, MaskE }, 0 },
3737 },
3738
3739 /* PREFIX_VEX_0F44_L_0_M_1_W_0 */
3740 {
3741 { "knotw", { MaskG, MaskE }, 0 },
3742 { Bad_Opcode },
3743 { "knotb", { MaskG, MaskE }, 0 },
3744 },
3745
3746 /* PREFIX_VEX_0F44_L_0_M_1_W_1 */
3747 {
3748 { "knotq", { MaskG, MaskE }, 0 },
3749 { Bad_Opcode },
3750 { "knotd", { MaskG, MaskE }, 0 },
3751 },
3752
3753 /* PREFIX_VEX_0F45_L_1_M_1_W_0 */
3754 {
3755 { "korw", { MaskG, MaskVex, MaskE }, 0 },
3756 { Bad_Opcode },
3757 { "korb", { MaskG, MaskVex, MaskE }, 0 },
3758 },
3759
3760 /* PREFIX_VEX_0F45_L_1_M_1_W_1 */
3761 {
3762 { "korq", { MaskG, MaskVex, MaskE }, 0 },
3763 { Bad_Opcode },
3764 { "kord", { MaskG, MaskVex, MaskE }, 0 },
3765 },
3766
3767 /* PREFIX_VEX_0F46_L_1_M_1_W_0 */
3768 {
3769 { "kxnorw", { MaskG, MaskVex, MaskE }, 0 },
3770 { Bad_Opcode },
3771 { "kxnorb", { MaskG, MaskVex, MaskE }, 0 },
3772 },
3773
3774 /* PREFIX_VEX_0F46_L_1_M_1_W_1 */
3775 {
3776 { "kxnorq", { MaskG, MaskVex, MaskE }, 0 },
3777 { Bad_Opcode },
3778 { "kxnord", { MaskG, MaskVex, MaskE }, 0 },
3779 },
3780
3781 /* PREFIX_VEX_0F47_L_1_M_1_W_0 */
3782 {
3783 { "kxorw", { MaskG, MaskVex, MaskE }, 0 },
3784 { Bad_Opcode },
3785 { "kxorb", { MaskG, MaskVex, MaskE }, 0 },
3786 },
3787
3788 /* PREFIX_VEX_0F47_L_1_M_1_W_1 */
3789 {
3790 { "kxorq", { MaskG, MaskVex, MaskE }, 0 },
3791 { Bad_Opcode },
3792 { "kxord", { MaskG, MaskVex, MaskE }, 0 },
3793 },
3794
3795 /* PREFIX_VEX_0F4A_L_1_M_1_W_0 */
3796 {
3797 { "kaddw", { MaskG, MaskVex, MaskE }, 0 },
3798 { Bad_Opcode },
3799 { "kaddb", { MaskG, MaskVex, MaskE }, 0 },
3800 },
3801
3802 /* PREFIX_VEX_0F4A_L_1_M_1_W_1 */
3803 {
3804 { "kaddq", { MaskG, MaskVex, MaskE }, 0 },
3805 { Bad_Opcode },
3806 { "kaddd", { MaskG, MaskVex, MaskE }, 0 },
3807 },
3808
3809 /* PREFIX_VEX_0F4B_L_1_M_1_W_0 */
3810 {
3811 { "kunpckwd", { MaskG, MaskVex, MaskE }, 0 },
3812 { Bad_Opcode },
3813 { "kunpckbw", { MaskG, MaskVex, MaskE }, 0 },
3814 },
3815
3816 /* PREFIX_VEX_0F4B_L_1_M_1_W_1 */
3817 {
3818 { "kunpckdq", { MaskG, MaskVex, MaskE }, 0 },
3819 },
3820
3821 /* PREFIX_VEX_0F51 */
3822 {
3823 { "vsqrtps", { XM, EXx }, 0 },
3824 { "vsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3825 { "vsqrtpd", { XM, EXx }, 0 },
3826 { "vsqrtsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3827 },
3828
3829 /* PREFIX_VEX_0F52 */
3830 {
3831 { "vrsqrtps", { XM, EXx }, 0 },
3832 { "vrsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3833 },
3834
3835 /* PREFIX_VEX_0F53 */
3836 {
3837 { "vrcpps", { XM, EXx }, 0 },
3838 { "vrcpss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3839 },
3840
3841 /* PREFIX_VEX_0F58 */
3842 {
3843 { "vaddps", { XM, Vex, EXx }, 0 },
3844 { "vaddss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3845 { "vaddpd", { XM, Vex, EXx }, 0 },
3846 { "vaddsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3847 },
3848
3849 /* PREFIX_VEX_0F59 */
3850 {
3851 { "vmulps", { XM, Vex, EXx }, 0 },
3852 { "vmulss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3853 { "vmulpd", { XM, Vex, EXx }, 0 },
3854 { "vmulsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3855 },
3856
3857 /* PREFIX_VEX_0F5A */
3858 {
3859 { "vcvtps2pd", { XM, EXxmmq }, 0 },
3860 { "vcvtss2sd", { XMScalar, VexScalar, EXxmm_md }, 0 },
3861 { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
3862 { "vcvtsd2ss", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3863 },
3864
3865 /* PREFIX_VEX_0F5B */
3866 {
3867 { "vcvtdq2ps", { XM, EXx }, 0 },
3868 { "vcvttps2dq", { XM, EXx }, 0 },
3869 { "vcvtps2dq", { XM, EXx }, 0 },
3870 },
3871
3872 /* PREFIX_VEX_0F5C */
3873 {
3874 { "vsubps", { XM, Vex, EXx }, 0 },
3875 { "vsubss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3876 { "vsubpd", { XM, Vex, EXx }, 0 },
3877 { "vsubsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3878 },
3879
3880 /* PREFIX_VEX_0F5D */
3881 {
3882 { "vminps", { XM, Vex, EXx }, 0 },
3883 { "vminss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3884 { "vminpd", { XM, Vex, EXx }, 0 },
3885 { "vminsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3886 },
3887
3888 /* PREFIX_VEX_0F5E */
3889 {
3890 { "vdivps", { XM, Vex, EXx }, 0 },
3891 { "vdivss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3892 { "vdivpd", { XM, Vex, EXx }, 0 },
3893 { "vdivsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3894 },
3895
3896 /* PREFIX_VEX_0F5F */
3897 {
3898 { "vmaxps", { XM, Vex, EXx }, 0 },
3899 { "vmaxss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3900 { "vmaxpd", { XM, Vex, EXx }, 0 },
3901 { "vmaxsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3902 },
3903
3904 /* PREFIX_VEX_0F6F */
3905 {
3906 { Bad_Opcode },
3907 { "vmovdqu", { XM, EXx }, 0 },
3908 { "vmovdqa", { XM, EXx }, 0 },
3909 },
3910
3911 /* PREFIX_VEX_0F70 */
3912 {
3913 { Bad_Opcode },
3914 { "vpshufhw", { XM, EXx, Ib }, 0 },
3915 { "vpshufd", { XM, EXx, Ib }, 0 },
3916 { "vpshuflw", { XM, EXx, Ib }, 0 },
3917 },
3918
3919 /* PREFIX_VEX_0F7C */
3920 {
3921 { Bad_Opcode },
3922 { Bad_Opcode },
3923 { "vhaddpd", { XM, Vex, EXx }, 0 },
3924 { "vhaddps", { XM, Vex, EXx }, 0 },
3925 },
3926
3927 /* PREFIX_VEX_0F7D */
3928 {
3929 { Bad_Opcode },
3930 { Bad_Opcode },
3931 { "vhsubpd", { XM, Vex, EXx }, 0 },
3932 { "vhsubps", { XM, Vex, EXx }, 0 },
3933 },
3934
3935 /* PREFIX_VEX_0F7E */
3936 {
3937 { Bad_Opcode },
3938 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
3939 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
3940 },
3941
3942 /* PREFIX_VEX_0F7F */
3943 {
3944 { Bad_Opcode },
3945 { "vmovdqu", { EXxS, XM }, 0 },
3946 { "vmovdqa", { EXxS, XM }, 0 },
3947 },
3948
3949 /* PREFIX_VEX_0F90_L_0_W_0 */
3950 {
3951 { "kmovw", { MaskG, MaskE }, 0 },
3952 { Bad_Opcode },
3953 { "kmovb", { MaskG, MaskBDE }, 0 },
3954 },
3955
3956 /* PREFIX_VEX_0F90_L_0_W_1 */
3957 {
3958 { "kmovq", { MaskG, MaskE }, 0 },
3959 { Bad_Opcode },
3960 { "kmovd", { MaskG, MaskBDE }, 0 },
3961 },
3962
3963 /* PREFIX_VEX_0F91_L_0_M_0_W_0 */
3964 {
3965 { "kmovw", { Ew, MaskG }, 0 },
3966 { Bad_Opcode },
3967 { "kmovb", { Eb, MaskG }, 0 },
3968 },
3969
3970 /* PREFIX_VEX_0F91_L_0_M_0_W_1 */
3971 {
3972 { "kmovq", { Eq, MaskG }, 0 },
3973 { Bad_Opcode },
3974 { "kmovd", { Ed, MaskG }, 0 },
3975 },
3976
3977 /* PREFIX_VEX_0F92_L_0_M_1_W_0 */
3978 {
3979 { "kmovw", { MaskG, Edq }, 0 },
3980 { Bad_Opcode },
3981 { "kmovb", { MaskG, Edq }, 0 },
3982 { "kmovd", { MaskG, Edq }, 0 },
3983 },
3984
3985 /* PREFIX_VEX_0F92_L_0_M_1_W_1 */
3986 {
3987 { Bad_Opcode },
3988 { Bad_Opcode },
3989 { Bad_Opcode },
3990 { "kmovK", { MaskG, Edq }, 0 },
3991 },
3992
3993 /* PREFIX_VEX_0F93_L_0_M_1_W_0 */
3994 {
3995 { "kmovw", { Gdq, MaskE }, 0 },
3996 { Bad_Opcode },
3997 { "kmovb", { Gdq, MaskE }, 0 },
3998 { "kmovd", { Gdq, MaskE }, 0 },
3999 },
4000
4001 /* PREFIX_VEX_0F93_L_0_M_1_W_1 */
4002 {
4003 { Bad_Opcode },
4004 { Bad_Opcode },
4005 { Bad_Opcode },
4006 { "kmovK", { Gdq, MaskE }, 0 },
4007 },
4008
4009 /* PREFIX_VEX_0F98_L_0_M_1_W_0 */
4010 {
4011 { "kortestw", { MaskG, MaskE }, 0 },
4012 { Bad_Opcode },
4013 { "kortestb", { MaskG, MaskE }, 0 },
4014 },
4015
4016 /* PREFIX_VEX_0F98_L_0_M_1_W_1 */
4017 {
4018 { "kortestq", { MaskG, MaskE }, 0 },
4019 { Bad_Opcode },
4020 { "kortestd", { MaskG, MaskE }, 0 },
4021 },
4022
4023 /* PREFIX_VEX_0F99_L_0_M_1_W_0 */
4024 {
4025 { "ktestw", { MaskG, MaskE }, 0 },
4026 { Bad_Opcode },
4027 { "ktestb", { MaskG, MaskE }, 0 },
4028 },
4029
4030 /* PREFIX_VEX_0F99_L_0_M_1_W_1 */
4031 {
4032 { "ktestq", { MaskG, MaskE }, 0 },
4033 { Bad_Opcode },
4034 { "ktestd", { MaskG, MaskE }, 0 },
4035 },
4036
4037 /* PREFIX_VEX_0FC2 */
4038 {
4039 { "vcmpps", { XM, Vex, EXx, CMP }, 0 },
4040 { "vcmpss", { XMScalar, VexScalar, EXxmm_md, CMP }, 0 },
4041 { "vcmppd", { XM, Vex, EXx, CMP }, 0 },
4042 { "vcmpsd", { XMScalar, VexScalar, EXxmm_mq, CMP }, 0 },
4043 },
4044
4045 /* PREFIX_VEX_0FD0 */
4046 {
4047 { Bad_Opcode },
4048 { Bad_Opcode },
4049 { "vaddsubpd", { XM, Vex, EXx }, 0 },
4050 { "vaddsubps", { XM, Vex, EXx }, 0 },
4051 },
4052
4053 /* PREFIX_VEX_0FE6 */
4054 {
4055 { Bad_Opcode },
4056 { "vcvtdq2pd", { XM, EXxmmq }, 0 },
4057 { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
4058 { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
4059 },
4060
4061 /* PREFIX_VEX_0FF0 */
4062 {
4063 { Bad_Opcode },
4064 { Bad_Opcode },
4065 { Bad_Opcode },
4066 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
4067 },
4068
4069 /* PREFIX_VEX_0F3849_X86_64 */
4070 {
4071 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) },
4072 { Bad_Opcode },
4073 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) },
4074 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) },
4075 },
4076
4077 /* PREFIX_VEX_0F384B_X86_64 */
4078 {
4079 { Bad_Opcode },
4080 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) },
4081 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) },
4082 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) },
4083 },
4084
4085 /* PREFIX_VEX_0F385C_X86_64 */
4086 {
4087 { Bad_Opcode },
4088 { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) },
4089 { Bad_Opcode },
4090 },
4091
4092 /* PREFIX_VEX_0F385E_X86_64 */
4093 {
4094 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) },
4095 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) },
4096 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) },
4097 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) },
4098 },
4099
4100 /* PREFIX_VEX_0F38F5_L_0 */
4101 {
4102 { "bzhiS", { Gdq, Edq, VexGdq }, 0 },
4103 { "pextS", { Gdq, VexGdq, Edq }, 0 },
4104 { Bad_Opcode },
4105 { "pdepS", { Gdq, VexGdq, Edq }, 0 },
4106 },
4107
4108 /* PREFIX_VEX_0F38F6_L_0 */
4109 {
4110 { Bad_Opcode },
4111 { Bad_Opcode },
4112 { Bad_Opcode },
4113 { "mulxS", { Gdq, VexGdq, Edq }, 0 },
4114 },
4115
4116 /* PREFIX_VEX_0F38F7_L_0 */
4117 {
4118 { "bextrS", { Gdq, Edq, VexGdq }, 0 },
4119 { "sarxS", { Gdq, Edq, VexGdq }, 0 },
4120 { "shlxS", { Gdq, Edq, VexGdq }, 0 },
4121 { "shrxS", { Gdq, Edq, VexGdq }, 0 },
4122 },
4123
4124 /* PREFIX_VEX_0F3AF0_L_0 */
4125 {
4126 { Bad_Opcode },
4127 { Bad_Opcode },
4128 { Bad_Opcode },
4129 { "rorxS", { Gdq, Edq, Ib }, 0 },
4130 },
4131
4132 #include "i386-dis-evex-prefix.h"
4133 };
4134
4135 static const struct dis386 x86_64_table[][2] = {
4136 /* X86_64_06 */
4137 {
4138 { "pushP", { es }, 0 },
4139 },
4140
4141 /* X86_64_07 */
4142 {
4143 { "popP", { es }, 0 },
4144 },
4145
4146 /* X86_64_0E */
4147 {
4148 { "pushP", { cs }, 0 },
4149 },
4150
4151 /* X86_64_16 */
4152 {
4153 { "pushP", { ss }, 0 },
4154 },
4155
4156 /* X86_64_17 */
4157 {
4158 { "popP", { ss }, 0 },
4159 },
4160
4161 /* X86_64_1E */
4162 {
4163 { "pushP", { ds }, 0 },
4164 },
4165
4166 /* X86_64_1F */
4167 {
4168 { "popP", { ds }, 0 },
4169 },
4170
4171 /* X86_64_27 */
4172 {
4173 { "daa", { XX }, 0 },
4174 },
4175
4176 /* X86_64_2F */
4177 {
4178 { "das", { XX }, 0 },
4179 },
4180
4181 /* X86_64_37 */
4182 {
4183 { "aaa", { XX }, 0 },
4184 },
4185
4186 /* X86_64_3F */
4187 {
4188 { "aas", { XX }, 0 },
4189 },
4190
4191 /* X86_64_60 */
4192 {
4193 { "pushaP", { XX }, 0 },
4194 },
4195
4196 /* X86_64_61 */
4197 {
4198 { "popaP", { XX }, 0 },
4199 },
4200
4201 /* X86_64_62 */
4202 {
4203 { MOD_TABLE (MOD_62_32BIT) },
4204 { EVEX_TABLE (EVEX_0F) },
4205 },
4206
4207 /* X86_64_63 */
4208 {
4209 { "arpl", { Ew, Gw }, 0 },
4210 { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4211 },
4212
4213 /* X86_64_6D */
4214 {
4215 { "ins{R|}", { Yzr, indirDX }, 0 },
4216 { "ins{G|}", { Yzr, indirDX }, 0 },
4217 },
4218
4219 /* X86_64_6F */
4220 {
4221 { "outs{R|}", { indirDXr, Xz }, 0 },
4222 { "outs{G|}", { indirDXr, Xz }, 0 },
4223 },
4224
4225 /* X86_64_82 */
4226 {
4227 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
4228 { REG_TABLE (REG_80) },
4229 },
4230
4231 /* X86_64_9A */
4232 {
4233 { "{l|}call{P|}", { Ap }, 0 },
4234 },
4235
4236 /* X86_64_C2 */
4237 {
4238 { "retP", { Iw, BND }, 0 },
4239 { "ret@", { Iw, BND }, 0 },
4240 },
4241
4242 /* X86_64_C3 */
4243 {
4244 { "retP", { BND }, 0 },
4245 { "ret@", { BND }, 0 },
4246 },
4247
4248 /* X86_64_C4 */
4249 {
4250 { MOD_TABLE (MOD_C4_32BIT) },
4251 { VEX_C4_TABLE (VEX_0F) },
4252 },
4253
4254 /* X86_64_C5 */
4255 {
4256 { MOD_TABLE (MOD_C5_32BIT) },
4257 { VEX_C5_TABLE (VEX_0F) },
4258 },
4259
4260 /* X86_64_CE */
4261 {
4262 { "into", { XX }, 0 },
4263 },
4264
4265 /* X86_64_D4 */
4266 {
4267 { "aam", { Ib }, 0 },
4268 },
4269
4270 /* X86_64_D5 */
4271 {
4272 { "aad", { Ib }, 0 },
4273 },
4274
4275 /* X86_64_E8 */
4276 {
4277 { "callP", { Jv, BND }, 0 },
4278 { "call@", { Jv, BND }, 0 }
4279 },
4280
4281 /* X86_64_E9 */
4282 {
4283 { "jmpP", { Jv, BND }, 0 },
4284 { "jmp@", { Jv, BND }, 0 }
4285 },
4286
4287 /* X86_64_EA */
4288 {
4289 { "{l|}jmp{P|}", { Ap }, 0 },
4290 },
4291
4292 /* X86_64_0F01_REG_0 */
4293 {
4294 { "sgdt{Q|Q}", { M }, 0 },
4295 { "sgdt", { M }, 0 },
4296 },
4297
4298 /* X86_64_0F01_REG_1 */
4299 {
4300 { "sidt{Q|Q}", { M }, 0 },
4301 { "sidt", { M }, 0 },
4302 },
4303
4304 /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4305 {
4306 { Bad_Opcode },
4307 { "seamret", { Skip_MODRM }, 0 },
4308 },
4309
4310 /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4311 {
4312 { Bad_Opcode },
4313 { "seamops", { Skip_MODRM }, 0 },
4314 },
4315
4316 /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4317 {
4318 { Bad_Opcode },
4319 { "seamcall", { Skip_MODRM }, 0 },
4320 },
4321
4322 /* X86_64_0F01_REG_2 */
4323 {
4324 { "lgdt{Q|Q}", { M }, 0 },
4325 { "lgdt", { M }, 0 },
4326 },
4327
4328 /* X86_64_0F01_REG_3 */
4329 {
4330 { "lidt{Q|Q}", { M }, 0 },
4331 { "lidt", { M }, 0 },
4332 },
4333
4334 {
4335 /* X86_64_0F24 */
4336 { "movZ", { Em, Td }, 0 },
4337 },
4338
4339 {
4340 /* X86_64_0F26 */
4341 { "movZ", { Td, Em }, 0 },
4342 },
4343
4344 /* X86_64_VEX_0F3849 */
4345 {
4346 { Bad_Opcode },
4347 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) },
4348 },
4349
4350 /* X86_64_VEX_0F384B */
4351 {
4352 { Bad_Opcode },
4353 { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) },
4354 },
4355
4356 /* X86_64_VEX_0F385C */
4357 {
4358 { Bad_Opcode },
4359 { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) },
4360 },
4361
4362 /* X86_64_VEX_0F385E */
4363 {
4364 { Bad_Opcode },
4365 { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
4366 },
4367
4368 /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4369 {
4370 { Bad_Opcode },
4371 { "uiret", { Skip_MODRM }, 0 },
4372 },
4373
4374 /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4375 {
4376 { Bad_Opcode },
4377 { "testui", { Skip_MODRM }, 0 },
4378 },
4379
4380 /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4381 {
4382 { Bad_Opcode },
4383 { "clui", { Skip_MODRM }, 0 },
4384 },
4385
4386 /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4387 {
4388 { Bad_Opcode },
4389 { "stui", { Skip_MODRM }, 0 },
4390 },
4391
4392 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
4393 {
4394 { Bad_Opcode },
4395 { "rmpadjust", { Skip_MODRM }, 0 },
4396 },
4397
4398 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
4399 {
4400 { Bad_Opcode },
4401 { "rmpupdate", { Skip_MODRM }, 0 },
4402 },
4403
4404 /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
4405 {
4406 { Bad_Opcode },
4407 { "psmash", { Skip_MODRM }, 0 },
4408 },
4409
4410 /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4411 {
4412 { Bad_Opcode },
4413 { "senduipi", { Eq }, 0 },
4414 },
4415 };
4416
4417 static const struct dis386 three_byte_table[][256] = {
4418
4419 /* THREE_BYTE_0F38 */
4420 {
4421 /* 00 */
4422 { "pshufb", { MX, EM }, PREFIX_OPCODE },
4423 { "phaddw", { MX, EM }, PREFIX_OPCODE },
4424 { "phaddd", { MX, EM }, PREFIX_OPCODE },
4425 { "phaddsw", { MX, EM }, PREFIX_OPCODE },
4426 { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
4427 { "phsubw", { MX, EM }, PREFIX_OPCODE },
4428 { "phsubd", { MX, EM }, PREFIX_OPCODE },
4429 { "phsubsw", { MX, EM }, PREFIX_OPCODE },
4430 /* 08 */
4431 { "psignb", { MX, EM }, PREFIX_OPCODE },
4432 { "psignw", { MX, EM }, PREFIX_OPCODE },
4433 { "psignd", { MX, EM }, PREFIX_OPCODE },
4434 { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
4435 { Bad_Opcode },
4436 { Bad_Opcode },
4437 { Bad_Opcode },
4438 { Bad_Opcode },
4439 /* 10 */
4440 { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4441 { Bad_Opcode },
4442 { Bad_Opcode },
4443 { Bad_Opcode },
4444 { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4445 { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4446 { Bad_Opcode },
4447 { "ptest", { XM, EXx }, PREFIX_DATA },
4448 /* 18 */
4449 { Bad_Opcode },
4450 { Bad_Opcode },
4451 { Bad_Opcode },
4452 { Bad_Opcode },
4453 { "pabsb", { MX, EM }, PREFIX_OPCODE },
4454 { "pabsw", { MX, EM }, PREFIX_OPCODE },
4455 { "pabsd", { MX, EM }, PREFIX_OPCODE },
4456 { Bad_Opcode },
4457 /* 20 */
4458 { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4459 { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4460 { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4461 { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4462 { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4463 { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4464 { Bad_Opcode },
4465 { Bad_Opcode },
4466 /* 28 */
4467 { "pmuldq", { XM, EXx }, PREFIX_DATA },
4468 { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4469 { MOD_TABLE (MOD_0F382A) },
4470 { "packusdw", { XM, EXx }, PREFIX_DATA },
4471 { Bad_Opcode },
4472 { Bad_Opcode },
4473 { Bad_Opcode },
4474 { Bad_Opcode },
4475 /* 30 */
4476 { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4477 { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4478 { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4479 { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4480 { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4481 { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4482 { Bad_Opcode },
4483 { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4484 /* 38 */
4485 { "pminsb", { XM, EXx }, PREFIX_DATA },
4486 { "pminsd", { XM, EXx }, PREFIX_DATA },
4487 { "pminuw", { XM, EXx }, PREFIX_DATA },
4488 { "pminud", { XM, EXx }, PREFIX_DATA },
4489 { "pmaxsb", { XM, EXx }, PREFIX_DATA },
4490 { "pmaxsd", { XM, EXx }, PREFIX_DATA },
4491 { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4492 { "pmaxud", { XM, EXx }, PREFIX_DATA },
4493 /* 40 */
4494 { "pmulld", { XM, EXx }, PREFIX_DATA },
4495 { "phminposuw", { XM, EXx }, PREFIX_DATA },
4496 { Bad_Opcode },
4497 { Bad_Opcode },
4498 { Bad_Opcode },
4499 { Bad_Opcode },
4500 { Bad_Opcode },
4501 { Bad_Opcode },
4502 /* 48 */
4503 { Bad_Opcode },
4504 { Bad_Opcode },
4505 { Bad_Opcode },
4506 { Bad_Opcode },
4507 { Bad_Opcode },
4508 { Bad_Opcode },
4509 { Bad_Opcode },
4510 { Bad_Opcode },
4511 /* 50 */
4512 { Bad_Opcode },
4513 { Bad_Opcode },
4514 { Bad_Opcode },
4515 { Bad_Opcode },
4516 { Bad_Opcode },
4517 { Bad_Opcode },
4518 { Bad_Opcode },
4519 { Bad_Opcode },
4520 /* 58 */
4521 { Bad_Opcode },
4522 { Bad_Opcode },
4523 { Bad_Opcode },
4524 { Bad_Opcode },
4525 { Bad_Opcode },
4526 { Bad_Opcode },
4527 { Bad_Opcode },
4528 { Bad_Opcode },
4529 /* 60 */
4530 { Bad_Opcode },
4531 { Bad_Opcode },
4532 { Bad_Opcode },
4533 { Bad_Opcode },
4534 { Bad_Opcode },
4535 { Bad_Opcode },
4536 { Bad_Opcode },
4537 { Bad_Opcode },
4538 /* 68 */
4539 { Bad_Opcode },
4540 { Bad_Opcode },
4541 { Bad_Opcode },
4542 { Bad_Opcode },
4543 { Bad_Opcode },
4544 { Bad_Opcode },
4545 { Bad_Opcode },
4546 { Bad_Opcode },
4547 /* 70 */
4548 { Bad_Opcode },
4549 { Bad_Opcode },
4550 { Bad_Opcode },
4551 { Bad_Opcode },
4552 { Bad_Opcode },
4553 { Bad_Opcode },
4554 { Bad_Opcode },
4555 { Bad_Opcode },
4556 /* 78 */
4557 { Bad_Opcode },
4558 { Bad_Opcode },
4559 { Bad_Opcode },
4560 { Bad_Opcode },
4561 { Bad_Opcode },
4562 { Bad_Opcode },
4563 { Bad_Opcode },
4564 { Bad_Opcode },
4565 /* 80 */
4566 { "invept", { Gm, Mo }, PREFIX_DATA },
4567 { "invvpid", { Gm, Mo }, PREFIX_DATA },
4568 { "invpcid", { Gm, M }, PREFIX_DATA },
4569 { Bad_Opcode },
4570 { Bad_Opcode },
4571 { Bad_Opcode },
4572 { Bad_Opcode },
4573 { Bad_Opcode },
4574 /* 88 */
4575 { Bad_Opcode },
4576 { Bad_Opcode },
4577 { Bad_Opcode },
4578 { Bad_Opcode },
4579 { Bad_Opcode },
4580 { Bad_Opcode },
4581 { Bad_Opcode },
4582 { Bad_Opcode },
4583 /* 90 */
4584 { Bad_Opcode },
4585 { Bad_Opcode },
4586 { Bad_Opcode },
4587 { Bad_Opcode },
4588 { Bad_Opcode },
4589 { Bad_Opcode },
4590 { Bad_Opcode },
4591 { Bad_Opcode },
4592 /* 98 */
4593 { Bad_Opcode },
4594 { Bad_Opcode },
4595 { Bad_Opcode },
4596 { Bad_Opcode },
4597 { Bad_Opcode },
4598 { Bad_Opcode },
4599 { Bad_Opcode },
4600 { Bad_Opcode },
4601 /* a0 */
4602 { Bad_Opcode },
4603 { Bad_Opcode },
4604 { Bad_Opcode },
4605 { Bad_Opcode },
4606 { Bad_Opcode },
4607 { Bad_Opcode },
4608 { Bad_Opcode },
4609 { Bad_Opcode },
4610 /* a8 */
4611 { Bad_Opcode },
4612 { Bad_Opcode },
4613 { Bad_Opcode },
4614 { Bad_Opcode },
4615 { Bad_Opcode },
4616 { Bad_Opcode },
4617 { Bad_Opcode },
4618 { Bad_Opcode },
4619 /* b0 */
4620 { Bad_Opcode },
4621 { Bad_Opcode },
4622 { Bad_Opcode },
4623 { Bad_Opcode },
4624 { Bad_Opcode },
4625 { Bad_Opcode },
4626 { Bad_Opcode },
4627 { Bad_Opcode },
4628 /* b8 */
4629 { Bad_Opcode },
4630 { Bad_Opcode },
4631 { Bad_Opcode },
4632 { Bad_Opcode },
4633 { Bad_Opcode },
4634 { Bad_Opcode },
4635 { Bad_Opcode },
4636 { Bad_Opcode },
4637 /* c0 */
4638 { Bad_Opcode },
4639 { Bad_Opcode },
4640 { Bad_Opcode },
4641 { Bad_Opcode },
4642 { Bad_Opcode },
4643 { Bad_Opcode },
4644 { Bad_Opcode },
4645 { Bad_Opcode },
4646 /* c8 */
4647 { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4648 { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4649 { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4650 { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4651 { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4652 { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4653 { Bad_Opcode },
4654 { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
4655 /* d0 */
4656 { Bad_Opcode },
4657 { Bad_Opcode },
4658 { Bad_Opcode },
4659 { Bad_Opcode },
4660 { Bad_Opcode },
4661 { Bad_Opcode },
4662 { Bad_Opcode },
4663 { Bad_Opcode },
4664 /* d8 */
4665 { PREFIX_TABLE (PREFIX_0F38D8) },
4666 { Bad_Opcode },
4667 { Bad_Opcode },
4668 { "aesimc", { XM, EXx }, PREFIX_DATA },
4669 { PREFIX_TABLE (PREFIX_0F38DC) },
4670 { PREFIX_TABLE (PREFIX_0F38DD) },
4671 { PREFIX_TABLE (PREFIX_0F38DE) },
4672 { PREFIX_TABLE (PREFIX_0F38DF) },
4673 /* e0 */
4674 { Bad_Opcode },
4675 { Bad_Opcode },
4676 { Bad_Opcode },
4677 { Bad_Opcode },
4678 { Bad_Opcode },
4679 { Bad_Opcode },
4680 { Bad_Opcode },
4681 { Bad_Opcode },
4682 /* e8 */
4683 { Bad_Opcode },
4684 { Bad_Opcode },
4685 { Bad_Opcode },
4686 { Bad_Opcode },
4687 { Bad_Opcode },
4688 { Bad_Opcode },
4689 { Bad_Opcode },
4690 { Bad_Opcode },
4691 /* f0 */
4692 { PREFIX_TABLE (PREFIX_0F38F0) },
4693 { PREFIX_TABLE (PREFIX_0F38F1) },
4694 { Bad_Opcode },
4695 { Bad_Opcode },
4696 { Bad_Opcode },
4697 { MOD_TABLE (MOD_0F38F5) },
4698 { PREFIX_TABLE (PREFIX_0F38F6) },
4699 { Bad_Opcode },
4700 /* f8 */
4701 { PREFIX_TABLE (PREFIX_0F38F8) },
4702 { MOD_TABLE (MOD_0F38F9) },
4703 { PREFIX_TABLE (PREFIX_0F38FA) },
4704 { PREFIX_TABLE (PREFIX_0F38FB) },
4705 { Bad_Opcode },
4706 { Bad_Opcode },
4707 { Bad_Opcode },
4708 { Bad_Opcode },
4709 },
4710 /* THREE_BYTE_0F3A */
4711 {
4712 /* 00 */
4713 { Bad_Opcode },
4714 { Bad_Opcode },
4715 { Bad_Opcode },
4716 { Bad_Opcode },
4717 { Bad_Opcode },
4718 { Bad_Opcode },
4719 { Bad_Opcode },
4720 { Bad_Opcode },
4721 /* 08 */
4722 { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
4723 { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
4724 { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
4725 { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
4726 { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
4727 { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
4728 { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
4729 { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
4730 /* 10 */
4731 { Bad_Opcode },
4732 { Bad_Opcode },
4733 { Bad_Opcode },
4734 { Bad_Opcode },
4735 { "pextrb", { Edqb, XM, Ib }, PREFIX_DATA },
4736 { "pextrw", { Edqw, XM, Ib }, PREFIX_DATA },
4737 { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
4738 { "extractps", { Edqd, XM, Ib }, PREFIX_DATA },
4739 /* 18 */
4740 { Bad_Opcode },
4741 { Bad_Opcode },
4742 { Bad_Opcode },
4743 { Bad_Opcode },
4744 { Bad_Opcode },
4745 { Bad_Opcode },
4746 { Bad_Opcode },
4747 { Bad_Opcode },
4748 /* 20 */
4749 { "pinsrb", { XM, Edqb, Ib }, PREFIX_DATA },
4750 { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
4751 { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
4752 { Bad_Opcode },
4753 { Bad_Opcode },
4754 { Bad_Opcode },
4755 { Bad_Opcode },
4756 { Bad_Opcode },
4757 /* 28 */
4758 { Bad_Opcode },
4759 { Bad_Opcode },
4760 { Bad_Opcode },
4761 { Bad_Opcode },
4762 { Bad_Opcode },
4763 { Bad_Opcode },
4764 { Bad_Opcode },
4765 { Bad_Opcode },
4766 /* 30 */
4767 { Bad_Opcode },
4768 { Bad_Opcode },
4769 { Bad_Opcode },
4770 { Bad_Opcode },
4771 { Bad_Opcode },
4772 { Bad_Opcode },
4773 { Bad_Opcode },
4774 { Bad_Opcode },
4775 /* 38 */
4776 { Bad_Opcode },
4777 { Bad_Opcode },
4778 { Bad_Opcode },
4779 { Bad_Opcode },
4780 { Bad_Opcode },
4781 { Bad_Opcode },
4782 { Bad_Opcode },
4783 { Bad_Opcode },
4784 /* 40 */
4785 { "dpps", { XM, EXx, Ib }, PREFIX_DATA },
4786 { "dppd", { XM, EXx, Ib }, PREFIX_DATA },
4787 { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
4788 { Bad_Opcode },
4789 { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
4790 { Bad_Opcode },
4791 { Bad_Opcode },
4792 { Bad_Opcode },
4793 /* 48 */
4794 { Bad_Opcode },
4795 { Bad_Opcode },
4796 { Bad_Opcode },
4797 { Bad_Opcode },
4798 { Bad_Opcode },
4799 { Bad_Opcode },
4800 { Bad_Opcode },
4801 { Bad_Opcode },
4802 /* 50 */
4803 { Bad_Opcode },
4804 { Bad_Opcode },
4805 { Bad_Opcode },
4806 { Bad_Opcode },
4807 { Bad_Opcode },
4808 { Bad_Opcode },
4809 { Bad_Opcode },
4810 { Bad_Opcode },
4811 /* 58 */
4812 { Bad_Opcode },
4813 { Bad_Opcode },
4814 { Bad_Opcode },
4815 { Bad_Opcode },
4816 { Bad_Opcode },
4817 { Bad_Opcode },
4818 { Bad_Opcode },
4819 { Bad_Opcode },
4820 /* 60 */
4821 { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4822 { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4823 { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
4824 { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
4825 { Bad_Opcode },
4826 { Bad_Opcode },
4827 { Bad_Opcode },
4828 { Bad_Opcode },
4829 /* 68 */
4830 { Bad_Opcode },
4831 { Bad_Opcode },
4832 { Bad_Opcode },
4833 { Bad_Opcode },
4834 { Bad_Opcode },
4835 { Bad_Opcode },
4836 { Bad_Opcode },
4837 { Bad_Opcode },
4838 /* 70 */
4839 { Bad_Opcode },
4840 { Bad_Opcode },
4841 { Bad_Opcode },
4842 { Bad_Opcode },
4843 { Bad_Opcode },
4844 { Bad_Opcode },
4845 { Bad_Opcode },
4846 { Bad_Opcode },
4847 /* 78 */
4848 { Bad_Opcode },
4849 { Bad_Opcode },
4850 { Bad_Opcode },
4851 { Bad_Opcode },
4852 { Bad_Opcode },
4853 { Bad_Opcode },
4854 { Bad_Opcode },
4855 { Bad_Opcode },
4856 /* 80 */
4857 { Bad_Opcode },
4858 { Bad_Opcode },
4859 { Bad_Opcode },
4860 { Bad_Opcode },
4861 { Bad_Opcode },
4862 { Bad_Opcode },
4863 { Bad_Opcode },
4864 { Bad_Opcode },
4865 /* 88 */
4866 { Bad_Opcode },
4867 { Bad_Opcode },
4868 { Bad_Opcode },
4869 { Bad_Opcode },
4870 { Bad_Opcode },
4871 { Bad_Opcode },
4872 { Bad_Opcode },
4873 { Bad_Opcode },
4874 /* 90 */
4875 { Bad_Opcode },
4876 { Bad_Opcode },
4877 { Bad_Opcode },
4878 { Bad_Opcode },
4879 { Bad_Opcode },
4880 { Bad_Opcode },
4881 { Bad_Opcode },
4882 { Bad_Opcode },
4883 /* 98 */
4884 { Bad_Opcode },
4885 { Bad_Opcode },
4886 { Bad_Opcode },
4887 { Bad_Opcode },
4888 { Bad_Opcode },
4889 { Bad_Opcode },
4890 { Bad_Opcode },
4891 { Bad_Opcode },
4892 /* a0 */
4893 { Bad_Opcode },
4894 { Bad_Opcode },
4895 { Bad_Opcode },
4896 { Bad_Opcode },
4897 { Bad_Opcode },
4898 { Bad_Opcode },
4899 { Bad_Opcode },
4900 { Bad_Opcode },
4901 /* a8 */
4902 { Bad_Opcode },
4903 { Bad_Opcode },
4904 { Bad_Opcode },
4905 { Bad_Opcode },
4906 { Bad_Opcode },
4907 { Bad_Opcode },
4908 { Bad_Opcode },
4909 { Bad_Opcode },
4910 /* b0 */
4911 { Bad_Opcode },
4912 { Bad_Opcode },
4913 { Bad_Opcode },
4914 { Bad_Opcode },
4915 { Bad_Opcode },
4916 { Bad_Opcode },
4917 { Bad_Opcode },
4918 { Bad_Opcode },
4919 /* b8 */
4920 { Bad_Opcode },
4921 { Bad_Opcode },
4922 { Bad_Opcode },
4923 { Bad_Opcode },
4924 { Bad_Opcode },
4925 { Bad_Opcode },
4926 { Bad_Opcode },
4927 { Bad_Opcode },
4928 /* c0 */
4929 { Bad_Opcode },
4930 { Bad_Opcode },
4931 { Bad_Opcode },
4932 { Bad_Opcode },
4933 { Bad_Opcode },
4934 { Bad_Opcode },
4935 { Bad_Opcode },
4936 { Bad_Opcode },
4937 /* c8 */
4938 { Bad_Opcode },
4939 { Bad_Opcode },
4940 { Bad_Opcode },
4941 { Bad_Opcode },
4942 { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4943 { Bad_Opcode },
4944 { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4945 { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4946 /* d0 */
4947 { Bad_Opcode },
4948 { Bad_Opcode },
4949 { Bad_Opcode },
4950 { Bad_Opcode },
4951 { Bad_Opcode },
4952 { Bad_Opcode },
4953 { Bad_Opcode },
4954 { Bad_Opcode },
4955 /* d8 */
4956 { Bad_Opcode },
4957 { Bad_Opcode },
4958 { Bad_Opcode },
4959 { Bad_Opcode },
4960 { Bad_Opcode },
4961 { Bad_Opcode },
4962 { Bad_Opcode },
4963 { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
4964 /* e0 */
4965 { Bad_Opcode },
4966 { Bad_Opcode },
4967 { Bad_Opcode },
4968 { Bad_Opcode },
4969 { Bad_Opcode },
4970 { Bad_Opcode },
4971 { Bad_Opcode },
4972 { Bad_Opcode },
4973 /* e8 */
4974 { Bad_Opcode },
4975 { Bad_Opcode },
4976 { Bad_Opcode },
4977 { Bad_Opcode },
4978 { Bad_Opcode },
4979 { Bad_Opcode },
4980 { Bad_Opcode },
4981 { Bad_Opcode },
4982 /* f0 */
4983 { PREFIX_TABLE (PREFIX_0F3A0F) },
4984 { Bad_Opcode },
4985 { Bad_Opcode },
4986 { Bad_Opcode },
4987 { Bad_Opcode },
4988 { Bad_Opcode },
4989 { Bad_Opcode },
4990 { Bad_Opcode },
4991 /* f8 */
4992 { Bad_Opcode },
4993 { Bad_Opcode },
4994 { Bad_Opcode },
4995 { Bad_Opcode },
4996 { Bad_Opcode },
4997 { Bad_Opcode },
4998 { Bad_Opcode },
4999 { Bad_Opcode },
5000 },
5001 };
5002
5003 static const struct dis386 xop_table[][256] = {
5004 /* XOP_08 */
5005 {
5006 /* 00 */
5007 { Bad_Opcode },
5008 { Bad_Opcode },
5009 { Bad_Opcode },
5010 { Bad_Opcode },
5011 { Bad_Opcode },
5012 { Bad_Opcode },
5013 { Bad_Opcode },
5014 { Bad_Opcode },
5015 /* 08 */
5016 { Bad_Opcode },
5017 { Bad_Opcode },
5018 { Bad_Opcode },
5019 { Bad_Opcode },
5020 { Bad_Opcode },
5021 { Bad_Opcode },
5022 { Bad_Opcode },
5023 { Bad_Opcode },
5024 /* 10 */
5025 { Bad_Opcode },
5026 { Bad_Opcode },
5027 { Bad_Opcode },
5028 { Bad_Opcode },
5029 { Bad_Opcode },
5030 { Bad_Opcode },
5031 { Bad_Opcode },
5032 { Bad_Opcode },
5033 /* 18 */
5034 { Bad_Opcode },
5035 { Bad_Opcode },
5036 { Bad_Opcode },
5037 { Bad_Opcode },
5038 { Bad_Opcode },
5039 { Bad_Opcode },
5040 { Bad_Opcode },
5041 { Bad_Opcode },
5042 /* 20 */
5043 { Bad_Opcode },
5044 { Bad_Opcode },
5045 { Bad_Opcode },
5046 { Bad_Opcode },
5047 { Bad_Opcode },
5048 { Bad_Opcode },
5049 { Bad_Opcode },
5050 { Bad_Opcode },
5051 /* 28 */
5052 { Bad_Opcode },
5053 { Bad_Opcode },
5054 { Bad_Opcode },
5055 { Bad_Opcode },
5056 { Bad_Opcode },
5057 { Bad_Opcode },
5058 { Bad_Opcode },
5059 { Bad_Opcode },
5060 /* 30 */
5061 { Bad_Opcode },
5062 { Bad_Opcode },
5063 { Bad_Opcode },
5064 { Bad_Opcode },
5065 { Bad_Opcode },
5066 { Bad_Opcode },
5067 { Bad_Opcode },
5068 { Bad_Opcode },
5069 /* 38 */
5070 { Bad_Opcode },
5071 { Bad_Opcode },
5072 { Bad_Opcode },
5073 { Bad_Opcode },
5074 { Bad_Opcode },
5075 { Bad_Opcode },
5076 { Bad_Opcode },
5077 { Bad_Opcode },
5078 /* 40 */
5079 { Bad_Opcode },
5080 { Bad_Opcode },
5081 { Bad_Opcode },
5082 { Bad_Opcode },
5083 { Bad_Opcode },
5084 { Bad_Opcode },
5085 { Bad_Opcode },
5086 { Bad_Opcode },
5087 /* 48 */
5088 { Bad_Opcode },
5089 { Bad_Opcode },
5090 { Bad_Opcode },
5091 { Bad_Opcode },
5092 { Bad_Opcode },
5093 { Bad_Opcode },
5094 { Bad_Opcode },
5095 { Bad_Opcode },
5096 /* 50 */
5097 { Bad_Opcode },
5098 { Bad_Opcode },
5099 { Bad_Opcode },
5100 { Bad_Opcode },
5101 { Bad_Opcode },
5102 { Bad_Opcode },
5103 { Bad_Opcode },
5104 { Bad_Opcode },
5105 /* 58 */
5106 { Bad_Opcode },
5107 { Bad_Opcode },
5108 { Bad_Opcode },
5109 { Bad_Opcode },
5110 { Bad_Opcode },
5111 { Bad_Opcode },
5112 { Bad_Opcode },
5113 { Bad_Opcode },
5114 /* 60 */
5115 { Bad_Opcode },
5116 { Bad_Opcode },
5117 { Bad_Opcode },
5118 { Bad_Opcode },
5119 { Bad_Opcode },
5120 { Bad_Opcode },
5121 { Bad_Opcode },
5122 { Bad_Opcode },
5123 /* 68 */
5124 { Bad_Opcode },
5125 { Bad_Opcode },
5126 { Bad_Opcode },
5127 { Bad_Opcode },
5128 { Bad_Opcode },
5129 { Bad_Opcode },
5130 { Bad_Opcode },
5131 { Bad_Opcode },
5132 /* 70 */
5133 { Bad_Opcode },
5134 { Bad_Opcode },
5135 { Bad_Opcode },
5136 { Bad_Opcode },
5137 { Bad_Opcode },
5138 { Bad_Opcode },
5139 { Bad_Opcode },
5140 { Bad_Opcode },
5141 /* 78 */
5142 { Bad_Opcode },
5143 { Bad_Opcode },
5144 { Bad_Opcode },
5145 { Bad_Opcode },
5146 { Bad_Opcode },
5147 { Bad_Opcode },
5148 { Bad_Opcode },
5149 { Bad_Opcode },
5150 /* 80 */
5151 { Bad_Opcode },
5152 { Bad_Opcode },
5153 { Bad_Opcode },
5154 { Bad_Opcode },
5155 { Bad_Opcode },
5156 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
5157 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
5158 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
5159 /* 88 */
5160 { Bad_Opcode },
5161 { Bad_Opcode },
5162 { Bad_Opcode },
5163 { Bad_Opcode },
5164 { Bad_Opcode },
5165 { Bad_Opcode },
5166 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
5167 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
5168 /* 90 */
5169 { Bad_Opcode },
5170 { Bad_Opcode },
5171 { Bad_Opcode },
5172 { Bad_Opcode },
5173 { Bad_Opcode },
5174 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
5175 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
5176 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
5177 /* 98 */
5178 { Bad_Opcode },
5179 { Bad_Opcode },
5180 { Bad_Opcode },
5181 { Bad_Opcode },
5182 { Bad_Opcode },
5183 { Bad_Opcode },
5184 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
5185 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
5186 /* a0 */
5187 { Bad_Opcode },
5188 { Bad_Opcode },
5189 { "vpcmov", { XM, Vex, EXx, XMVexI4 }, 0 },
5190 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
5191 { Bad_Opcode },
5192 { Bad_Opcode },
5193 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
5194 { Bad_Opcode },
5195 /* a8 */
5196 { Bad_Opcode },
5197 { Bad_Opcode },
5198 { Bad_Opcode },
5199 { Bad_Opcode },
5200 { Bad_Opcode },
5201 { Bad_Opcode },
5202 { Bad_Opcode },
5203 { Bad_Opcode },
5204 /* b0 */
5205 { Bad_Opcode },
5206 { Bad_Opcode },
5207 { Bad_Opcode },
5208 { Bad_Opcode },
5209 { Bad_Opcode },
5210 { Bad_Opcode },
5211 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
5212 { Bad_Opcode },
5213 /* b8 */
5214 { Bad_Opcode },
5215 { Bad_Opcode },
5216 { Bad_Opcode },
5217 { Bad_Opcode },
5218 { Bad_Opcode },
5219 { Bad_Opcode },
5220 { Bad_Opcode },
5221 { Bad_Opcode },
5222 /* c0 */
5223 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
5224 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
5225 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
5226 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
5227 { Bad_Opcode },
5228 { Bad_Opcode },
5229 { Bad_Opcode },
5230 { Bad_Opcode },
5231 /* c8 */
5232 { Bad_Opcode },
5233 { Bad_Opcode },
5234 { Bad_Opcode },
5235 { Bad_Opcode },
5236 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
5237 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
5238 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
5239 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
5240 /* d0 */
5241 { Bad_Opcode },
5242 { Bad_Opcode },
5243 { Bad_Opcode },
5244 { Bad_Opcode },
5245 { Bad_Opcode },
5246 { Bad_Opcode },
5247 { Bad_Opcode },
5248 { Bad_Opcode },
5249 /* d8 */
5250 { Bad_Opcode },
5251 { Bad_Opcode },
5252 { Bad_Opcode },
5253 { Bad_Opcode },
5254 { Bad_Opcode },
5255 { Bad_Opcode },
5256 { Bad_Opcode },
5257 { Bad_Opcode },
5258 /* e0 */
5259 { Bad_Opcode },
5260 { Bad_Opcode },
5261 { Bad_Opcode },
5262 { Bad_Opcode },
5263 { Bad_Opcode },
5264 { Bad_Opcode },
5265 { Bad_Opcode },
5266 { Bad_Opcode },
5267 /* e8 */
5268 { Bad_Opcode },
5269 { Bad_Opcode },
5270 { Bad_Opcode },
5271 { Bad_Opcode },
5272 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
5273 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
5274 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
5275 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
5276 /* f0 */
5277 { Bad_Opcode },
5278 { Bad_Opcode },
5279 { Bad_Opcode },
5280 { Bad_Opcode },
5281 { Bad_Opcode },
5282 { Bad_Opcode },
5283 { Bad_Opcode },
5284 { Bad_Opcode },
5285 /* f8 */
5286 { Bad_Opcode },
5287 { Bad_Opcode },
5288 { Bad_Opcode },
5289 { Bad_Opcode },
5290 { Bad_Opcode },
5291 { Bad_Opcode },
5292 { Bad_Opcode },
5293 { Bad_Opcode },
5294 },
5295 /* XOP_09 */
5296 {
5297 /* 00 */
5298 { Bad_Opcode },
5299 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
5300 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
5301 { Bad_Opcode },
5302 { Bad_Opcode },
5303 { Bad_Opcode },
5304 { Bad_Opcode },
5305 { Bad_Opcode },
5306 /* 08 */
5307 { Bad_Opcode },
5308 { Bad_Opcode },
5309 { Bad_Opcode },
5310 { Bad_Opcode },
5311 { Bad_Opcode },
5312 { Bad_Opcode },
5313 { Bad_Opcode },
5314 { Bad_Opcode },
5315 /* 10 */
5316 { Bad_Opcode },
5317 { Bad_Opcode },
5318 { MOD_TABLE (MOD_VEX_0FXOP_09_12) },
5319 { Bad_Opcode },
5320 { Bad_Opcode },
5321 { Bad_Opcode },
5322 { Bad_Opcode },
5323 { Bad_Opcode },
5324 /* 18 */
5325 { Bad_Opcode },
5326 { Bad_Opcode },
5327 { Bad_Opcode },
5328 { Bad_Opcode },
5329 { Bad_Opcode },
5330 { Bad_Opcode },
5331 { Bad_Opcode },
5332 { Bad_Opcode },
5333 /* 20 */
5334 { Bad_Opcode },
5335 { Bad_Opcode },
5336 { Bad_Opcode },
5337 { Bad_Opcode },
5338 { Bad_Opcode },
5339 { Bad_Opcode },
5340 { Bad_Opcode },
5341 { Bad_Opcode },
5342 /* 28 */
5343 { Bad_Opcode },
5344 { Bad_Opcode },
5345 { Bad_Opcode },
5346 { Bad_Opcode },
5347 { Bad_Opcode },
5348 { Bad_Opcode },
5349 { Bad_Opcode },
5350 { Bad_Opcode },
5351 /* 30 */
5352 { Bad_Opcode },
5353 { Bad_Opcode },
5354 { Bad_Opcode },
5355 { Bad_Opcode },
5356 { Bad_Opcode },
5357 { Bad_Opcode },
5358 { Bad_Opcode },
5359 { Bad_Opcode },
5360 /* 38 */
5361 { Bad_Opcode },
5362 { Bad_Opcode },
5363 { Bad_Opcode },
5364 { Bad_Opcode },
5365 { Bad_Opcode },
5366 { Bad_Opcode },
5367 { Bad_Opcode },
5368 { Bad_Opcode },
5369 /* 40 */
5370 { Bad_Opcode },
5371 { Bad_Opcode },
5372 { Bad_Opcode },
5373 { Bad_Opcode },
5374 { Bad_Opcode },
5375 { Bad_Opcode },
5376 { Bad_Opcode },
5377 { Bad_Opcode },
5378 /* 48 */
5379 { Bad_Opcode },
5380 { Bad_Opcode },
5381 { Bad_Opcode },
5382 { Bad_Opcode },
5383 { Bad_Opcode },
5384 { Bad_Opcode },
5385 { Bad_Opcode },
5386 { Bad_Opcode },
5387 /* 50 */
5388 { Bad_Opcode },
5389 { Bad_Opcode },
5390 { Bad_Opcode },
5391 { Bad_Opcode },
5392 { Bad_Opcode },
5393 { Bad_Opcode },
5394 { Bad_Opcode },
5395 { Bad_Opcode },
5396 /* 58 */
5397 { Bad_Opcode },
5398 { Bad_Opcode },
5399 { Bad_Opcode },
5400 { Bad_Opcode },
5401 { Bad_Opcode },
5402 { Bad_Opcode },
5403 { Bad_Opcode },
5404 { Bad_Opcode },
5405 /* 60 */
5406 { Bad_Opcode },
5407 { Bad_Opcode },
5408 { Bad_Opcode },
5409 { Bad_Opcode },
5410 { Bad_Opcode },
5411 { Bad_Opcode },
5412 { Bad_Opcode },
5413 { Bad_Opcode },
5414 /* 68 */
5415 { Bad_Opcode },
5416 { Bad_Opcode },
5417 { Bad_Opcode },
5418 { Bad_Opcode },
5419 { Bad_Opcode },
5420 { Bad_Opcode },
5421 { Bad_Opcode },
5422 { Bad_Opcode },
5423 /* 70 */
5424 { Bad_Opcode },
5425 { Bad_Opcode },
5426 { Bad_Opcode },
5427 { Bad_Opcode },
5428 { Bad_Opcode },
5429 { Bad_Opcode },
5430 { Bad_Opcode },
5431 { Bad_Opcode },
5432 /* 78 */
5433 { Bad_Opcode },
5434 { Bad_Opcode },
5435 { Bad_Opcode },
5436 { Bad_Opcode },
5437 { Bad_Opcode },
5438 { Bad_Opcode },
5439 { Bad_Opcode },
5440 { Bad_Opcode },
5441 /* 80 */
5442 { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
5443 { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
5444 { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
5445 { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
5446 { Bad_Opcode },
5447 { Bad_Opcode },
5448 { Bad_Opcode },
5449 { Bad_Opcode },
5450 /* 88 */
5451 { Bad_Opcode },
5452 { Bad_Opcode },
5453 { Bad_Opcode },
5454 { Bad_Opcode },
5455 { Bad_Opcode },
5456 { Bad_Opcode },
5457 { Bad_Opcode },
5458 { Bad_Opcode },
5459 /* 90 */
5460 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
5461 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
5462 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
5463 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
5464 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
5465 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
5466 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
5467 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
5468 /* 98 */
5469 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
5470 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
5471 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
5472 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
5473 { Bad_Opcode },
5474 { Bad_Opcode },
5475 { Bad_Opcode },
5476 { Bad_Opcode },
5477 /* a0 */
5478 { Bad_Opcode },
5479 { Bad_Opcode },
5480 { Bad_Opcode },
5481 { Bad_Opcode },
5482 { Bad_Opcode },
5483 { Bad_Opcode },
5484 { Bad_Opcode },
5485 { Bad_Opcode },
5486 /* a8 */
5487 { Bad_Opcode },
5488 { Bad_Opcode },
5489 { Bad_Opcode },
5490 { Bad_Opcode },
5491 { Bad_Opcode },
5492 { Bad_Opcode },
5493 { Bad_Opcode },
5494 { Bad_Opcode },
5495 /* b0 */
5496 { Bad_Opcode },
5497 { Bad_Opcode },
5498 { Bad_Opcode },
5499 { Bad_Opcode },
5500 { Bad_Opcode },
5501 { Bad_Opcode },
5502 { Bad_Opcode },
5503 { Bad_Opcode },
5504 /* b8 */
5505 { Bad_Opcode },
5506 { Bad_Opcode },
5507 { Bad_Opcode },
5508 { Bad_Opcode },
5509 { Bad_Opcode },
5510 { Bad_Opcode },
5511 { Bad_Opcode },
5512 { Bad_Opcode },
5513 /* c0 */
5514 { Bad_Opcode },
5515 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
5516 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
5517 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
5518 { Bad_Opcode },
5519 { Bad_Opcode },
5520 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
5521 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
5522 /* c8 */
5523 { Bad_Opcode },
5524 { Bad_Opcode },
5525 { Bad_Opcode },
5526 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
5527 { Bad_Opcode },
5528 { Bad_Opcode },
5529 { Bad_Opcode },
5530 { Bad_Opcode },
5531 /* d0 */
5532 { Bad_Opcode },
5533 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
5534 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
5535 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
5536 { Bad_Opcode },
5537 { Bad_Opcode },
5538 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
5539 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
5540 /* d8 */
5541 { Bad_Opcode },
5542 { Bad_Opcode },
5543 { Bad_Opcode },
5544 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
5545 { Bad_Opcode },
5546 { Bad_Opcode },
5547 { Bad_Opcode },
5548 { Bad_Opcode },
5549 /* e0 */
5550 { Bad_Opcode },
5551 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
5552 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
5553 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
5554 { Bad_Opcode },
5555 { Bad_Opcode },
5556 { Bad_Opcode },
5557 { Bad_Opcode },
5558 /* e8 */
5559 { Bad_Opcode },
5560 { Bad_Opcode },
5561 { Bad_Opcode },
5562 { Bad_Opcode },
5563 { Bad_Opcode },
5564 { Bad_Opcode },
5565 { Bad_Opcode },
5566 { Bad_Opcode },
5567 /* f0 */
5568 { Bad_Opcode },
5569 { Bad_Opcode },
5570 { Bad_Opcode },
5571 { Bad_Opcode },
5572 { Bad_Opcode },
5573 { Bad_Opcode },
5574 { Bad_Opcode },
5575 { Bad_Opcode },
5576 /* f8 */
5577 { Bad_Opcode },
5578 { Bad_Opcode },
5579 { Bad_Opcode },
5580 { Bad_Opcode },
5581 { Bad_Opcode },
5582 { Bad_Opcode },
5583 { Bad_Opcode },
5584 { Bad_Opcode },
5585 },
5586 /* XOP_0A */
5587 {
5588 /* 00 */
5589 { Bad_Opcode },
5590 { Bad_Opcode },
5591 { Bad_Opcode },
5592 { Bad_Opcode },
5593 { Bad_Opcode },
5594 { Bad_Opcode },
5595 { Bad_Opcode },
5596 { Bad_Opcode },
5597 /* 08 */
5598 { Bad_Opcode },
5599 { Bad_Opcode },
5600 { Bad_Opcode },
5601 { Bad_Opcode },
5602 { Bad_Opcode },
5603 { Bad_Opcode },
5604 { Bad_Opcode },
5605 { Bad_Opcode },
5606 /* 10 */
5607 { "bextrS", { Gdq, Edq, Id }, 0 },
5608 { Bad_Opcode },
5609 { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
5610 { Bad_Opcode },
5611 { Bad_Opcode },
5612 { Bad_Opcode },
5613 { Bad_Opcode },
5614 { Bad_Opcode },
5615 /* 18 */
5616 { Bad_Opcode },
5617 { Bad_Opcode },
5618 { Bad_Opcode },
5619 { Bad_Opcode },
5620 { Bad_Opcode },
5621 { Bad_Opcode },
5622 { Bad_Opcode },
5623 { Bad_Opcode },
5624 /* 20 */
5625 { Bad_Opcode },
5626 { Bad_Opcode },
5627 { Bad_Opcode },
5628 { Bad_Opcode },
5629 { Bad_Opcode },
5630 { Bad_Opcode },
5631 { Bad_Opcode },
5632 { Bad_Opcode },
5633 /* 28 */
5634 { Bad_Opcode },
5635 { Bad_Opcode },
5636 { Bad_Opcode },
5637 { Bad_Opcode },
5638 { Bad_Opcode },
5639 { Bad_Opcode },
5640 { Bad_Opcode },
5641 { Bad_Opcode },
5642 /* 30 */
5643 { Bad_Opcode },
5644 { Bad_Opcode },
5645 { Bad_Opcode },
5646 { Bad_Opcode },
5647 { Bad_Opcode },
5648 { Bad_Opcode },
5649 { Bad_Opcode },
5650 { Bad_Opcode },
5651 /* 38 */
5652 { Bad_Opcode },
5653 { Bad_Opcode },
5654 { Bad_Opcode },
5655 { Bad_Opcode },
5656 { Bad_Opcode },
5657 { Bad_Opcode },
5658 { Bad_Opcode },
5659 { Bad_Opcode },
5660 /* 40 */
5661 { Bad_Opcode },
5662 { Bad_Opcode },
5663 { Bad_Opcode },
5664 { Bad_Opcode },
5665 { Bad_Opcode },
5666 { Bad_Opcode },
5667 { Bad_Opcode },
5668 { Bad_Opcode },
5669 /* 48 */
5670 { Bad_Opcode },
5671 { Bad_Opcode },
5672 { Bad_Opcode },
5673 { Bad_Opcode },
5674 { Bad_Opcode },
5675 { Bad_Opcode },
5676 { Bad_Opcode },
5677 { Bad_Opcode },
5678 /* 50 */
5679 { Bad_Opcode },
5680 { Bad_Opcode },
5681 { Bad_Opcode },
5682 { Bad_Opcode },
5683 { Bad_Opcode },
5684 { Bad_Opcode },
5685 { Bad_Opcode },
5686 { Bad_Opcode },
5687 /* 58 */
5688 { Bad_Opcode },
5689 { Bad_Opcode },
5690 { Bad_Opcode },
5691 { Bad_Opcode },
5692 { Bad_Opcode },
5693 { Bad_Opcode },
5694 { Bad_Opcode },
5695 { Bad_Opcode },
5696 /* 60 */
5697 { Bad_Opcode },
5698 { Bad_Opcode },
5699 { Bad_Opcode },
5700 { Bad_Opcode },
5701 { Bad_Opcode },
5702 { Bad_Opcode },
5703 { Bad_Opcode },
5704 { Bad_Opcode },
5705 /* 68 */
5706 { Bad_Opcode },
5707 { Bad_Opcode },
5708 { Bad_Opcode },
5709 { Bad_Opcode },
5710 { Bad_Opcode },
5711 { Bad_Opcode },
5712 { Bad_Opcode },
5713 { Bad_Opcode },
5714 /* 70 */
5715 { Bad_Opcode },
5716 { Bad_Opcode },
5717 { Bad_Opcode },
5718 { Bad_Opcode },
5719 { Bad_Opcode },
5720 { Bad_Opcode },
5721 { Bad_Opcode },
5722 { Bad_Opcode },
5723 /* 78 */
5724 { Bad_Opcode },
5725 { Bad_Opcode },
5726 { Bad_Opcode },
5727 { Bad_Opcode },
5728 { Bad_Opcode },
5729 { Bad_Opcode },
5730 { Bad_Opcode },
5731 { Bad_Opcode },
5732 /* 80 */
5733 { Bad_Opcode },
5734 { Bad_Opcode },
5735 { Bad_Opcode },
5736 { Bad_Opcode },
5737 { Bad_Opcode },
5738 { Bad_Opcode },
5739 { Bad_Opcode },
5740 { Bad_Opcode },
5741 /* 88 */
5742 { Bad_Opcode },
5743 { Bad_Opcode },
5744 { Bad_Opcode },
5745 { Bad_Opcode },
5746 { Bad_Opcode },
5747 { Bad_Opcode },
5748 { Bad_Opcode },
5749 { Bad_Opcode },
5750 /* 90 */
5751 { Bad_Opcode },
5752 { Bad_Opcode },
5753 { Bad_Opcode },
5754 { Bad_Opcode },
5755 { Bad_Opcode },
5756 { Bad_Opcode },
5757 { Bad_Opcode },
5758 { Bad_Opcode },
5759 /* 98 */
5760 { Bad_Opcode },
5761 { Bad_Opcode },
5762 { Bad_Opcode },
5763 { Bad_Opcode },
5764 { Bad_Opcode },
5765 { Bad_Opcode },
5766 { Bad_Opcode },
5767 { Bad_Opcode },
5768 /* a0 */
5769 { Bad_Opcode },
5770 { Bad_Opcode },
5771 { Bad_Opcode },
5772 { Bad_Opcode },
5773 { Bad_Opcode },
5774 { Bad_Opcode },
5775 { Bad_Opcode },
5776 { Bad_Opcode },
5777 /* a8 */
5778 { Bad_Opcode },
5779 { Bad_Opcode },
5780 { Bad_Opcode },
5781 { Bad_Opcode },
5782 { Bad_Opcode },
5783 { Bad_Opcode },
5784 { Bad_Opcode },
5785 { Bad_Opcode },
5786 /* b0 */
5787 { Bad_Opcode },
5788 { Bad_Opcode },
5789 { Bad_Opcode },
5790 { Bad_Opcode },
5791 { Bad_Opcode },
5792 { Bad_Opcode },
5793 { Bad_Opcode },
5794 { Bad_Opcode },
5795 /* b8 */
5796 { Bad_Opcode },
5797 { Bad_Opcode },
5798 { Bad_Opcode },
5799 { Bad_Opcode },
5800 { Bad_Opcode },
5801 { Bad_Opcode },
5802 { Bad_Opcode },
5803 { Bad_Opcode },
5804 /* c0 */
5805 { Bad_Opcode },
5806 { Bad_Opcode },
5807 { Bad_Opcode },
5808 { Bad_Opcode },
5809 { Bad_Opcode },
5810 { Bad_Opcode },
5811 { Bad_Opcode },
5812 { Bad_Opcode },
5813 /* c8 */
5814 { Bad_Opcode },
5815 { Bad_Opcode },
5816 { Bad_Opcode },
5817 { Bad_Opcode },
5818 { Bad_Opcode },
5819 { Bad_Opcode },
5820 { Bad_Opcode },
5821 { Bad_Opcode },
5822 /* d0 */
5823 { Bad_Opcode },
5824 { Bad_Opcode },
5825 { Bad_Opcode },
5826 { Bad_Opcode },
5827 { Bad_Opcode },
5828 { Bad_Opcode },
5829 { Bad_Opcode },
5830 { Bad_Opcode },
5831 /* d8 */
5832 { Bad_Opcode },
5833 { Bad_Opcode },
5834 { Bad_Opcode },
5835 { Bad_Opcode },
5836 { Bad_Opcode },
5837 { Bad_Opcode },
5838 { Bad_Opcode },
5839 { Bad_Opcode },
5840 /* e0 */
5841 { Bad_Opcode },
5842 { Bad_Opcode },
5843 { Bad_Opcode },
5844 { Bad_Opcode },
5845 { Bad_Opcode },
5846 { Bad_Opcode },
5847 { Bad_Opcode },
5848 { Bad_Opcode },
5849 /* e8 */
5850 { Bad_Opcode },
5851 { Bad_Opcode },
5852 { Bad_Opcode },
5853 { Bad_Opcode },
5854 { Bad_Opcode },
5855 { Bad_Opcode },
5856 { Bad_Opcode },
5857 { Bad_Opcode },
5858 /* f0 */
5859 { Bad_Opcode },
5860 { Bad_Opcode },
5861 { Bad_Opcode },
5862 { Bad_Opcode },
5863 { Bad_Opcode },
5864 { Bad_Opcode },
5865 { Bad_Opcode },
5866 { Bad_Opcode },
5867 /* f8 */
5868 { Bad_Opcode },
5869 { Bad_Opcode },
5870 { Bad_Opcode },
5871 { Bad_Opcode },
5872 { Bad_Opcode },
5873 { Bad_Opcode },
5874 { Bad_Opcode },
5875 { Bad_Opcode },
5876 },
5877 };
5878
5879 static const struct dis386 vex_table[][256] = {
5880 /* VEX_0F */
5881 {
5882 /* 00 */
5883 { Bad_Opcode },
5884 { Bad_Opcode },
5885 { Bad_Opcode },
5886 { Bad_Opcode },
5887 { Bad_Opcode },
5888 { Bad_Opcode },
5889 { Bad_Opcode },
5890 { Bad_Opcode },
5891 /* 08 */
5892 { Bad_Opcode },
5893 { Bad_Opcode },
5894 { Bad_Opcode },
5895 { Bad_Opcode },
5896 { Bad_Opcode },
5897 { Bad_Opcode },
5898 { Bad_Opcode },
5899 { Bad_Opcode },
5900 /* 10 */
5901 { PREFIX_TABLE (PREFIX_VEX_0F10) },
5902 { PREFIX_TABLE (PREFIX_VEX_0F11) },
5903 { PREFIX_TABLE (PREFIX_VEX_0F12) },
5904 { MOD_TABLE (MOD_VEX_0F13) },
5905 { "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5906 { "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5907 { PREFIX_TABLE (PREFIX_VEX_0F16) },
5908 { MOD_TABLE (MOD_VEX_0F17) },
5909 /* 18 */
5910 { Bad_Opcode },
5911 { Bad_Opcode },
5912 { Bad_Opcode },
5913 { Bad_Opcode },
5914 { Bad_Opcode },
5915 { Bad_Opcode },
5916 { Bad_Opcode },
5917 { Bad_Opcode },
5918 /* 20 */
5919 { Bad_Opcode },
5920 { Bad_Opcode },
5921 { Bad_Opcode },
5922 { Bad_Opcode },
5923 { Bad_Opcode },
5924 { Bad_Opcode },
5925 { Bad_Opcode },
5926 { Bad_Opcode },
5927 /* 28 */
5928 { "vmovapX", { XM, EXx }, PREFIX_OPCODE },
5929 { "vmovapX", { EXxS, XM }, PREFIX_OPCODE },
5930 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
5931 { MOD_TABLE (MOD_VEX_0F2B) },
5932 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
5933 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
5934 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
5935 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
5936 /* 30 */
5937 { Bad_Opcode },
5938 { Bad_Opcode },
5939 { Bad_Opcode },
5940 { Bad_Opcode },
5941 { Bad_Opcode },
5942 { Bad_Opcode },
5943 { Bad_Opcode },
5944 { Bad_Opcode },
5945 /* 38 */
5946 { Bad_Opcode },
5947 { Bad_Opcode },
5948 { Bad_Opcode },
5949 { Bad_Opcode },
5950 { Bad_Opcode },
5951 { Bad_Opcode },
5952 { Bad_Opcode },
5953 { Bad_Opcode },
5954 /* 40 */
5955 { Bad_Opcode },
5956 { VEX_LEN_TABLE (VEX_LEN_0F41) },
5957 { VEX_LEN_TABLE (VEX_LEN_0F42) },
5958 { Bad_Opcode },
5959 { VEX_LEN_TABLE (VEX_LEN_0F44) },
5960 { VEX_LEN_TABLE (VEX_LEN_0F45) },
5961 { VEX_LEN_TABLE (VEX_LEN_0F46) },
5962 { VEX_LEN_TABLE (VEX_LEN_0F47) },
5963 /* 48 */
5964 { Bad_Opcode },
5965 { Bad_Opcode },
5966 { VEX_LEN_TABLE (VEX_LEN_0F4A) },
5967 { VEX_LEN_TABLE (VEX_LEN_0F4B) },
5968 { Bad_Opcode },
5969 { Bad_Opcode },
5970 { Bad_Opcode },
5971 { Bad_Opcode },
5972 /* 50 */
5973 { MOD_TABLE (MOD_VEX_0F50) },
5974 { PREFIX_TABLE (PREFIX_VEX_0F51) },
5975 { PREFIX_TABLE (PREFIX_VEX_0F52) },
5976 { PREFIX_TABLE (PREFIX_VEX_0F53) },
5977 { "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5978 { "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5979 { "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5980 { "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5981 /* 58 */
5982 { PREFIX_TABLE (PREFIX_VEX_0F58) },
5983 { PREFIX_TABLE (PREFIX_VEX_0F59) },
5984 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
5985 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
5986 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
5987 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
5988 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
5989 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
5990 /* 60 */
5991 { "vpunpcklbw", { XM, Vex, EXx }, PREFIX_DATA },
5992 { "vpunpcklwd", { XM, Vex, EXx }, PREFIX_DATA },
5993 { "vpunpckldq", { XM, Vex, EXx }, PREFIX_DATA },
5994 { "vpacksswb", { XM, Vex, EXx }, PREFIX_DATA },
5995 { "vpcmpgtb", { XM, Vex, EXx }, PREFIX_DATA },
5996 { "vpcmpgtw", { XM, Vex, EXx }, PREFIX_DATA },
5997 { "vpcmpgtd", { XM, Vex, EXx }, PREFIX_DATA },
5998 { "vpackuswb", { XM, Vex, EXx }, PREFIX_DATA },
5999 /* 68 */
6000 { "vpunpckhbw", { XM, Vex, EXx }, PREFIX_DATA },
6001 { "vpunpckhwd", { XM, Vex, EXx }, PREFIX_DATA },
6002 { "vpunpckhdq", { XM, Vex, EXx }, PREFIX_DATA },
6003 { "vpackssdw", { XM, Vex, EXx }, PREFIX_DATA },
6004 { "vpunpcklqdq", { XM, Vex, EXx }, PREFIX_DATA },
6005 { "vpunpckhqdq", { XM, Vex, EXx }, PREFIX_DATA },
6006 { VEX_LEN_TABLE (VEX_LEN_0F6E) },
6007 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
6008 /* 70 */
6009 { PREFIX_TABLE (PREFIX_VEX_0F70) },
6010 { MOD_TABLE (MOD_VEX_0F71) },
6011 { MOD_TABLE (MOD_VEX_0F72) },
6012 { MOD_TABLE (MOD_VEX_0F73) },
6013 { "vpcmpeqb", { XM, Vex, EXx }, PREFIX_DATA },
6014 { "vpcmpeqw", { XM, Vex, EXx }, PREFIX_DATA },
6015 { "vpcmpeqd", { XM, Vex, EXx }, PREFIX_DATA },
6016 { VEX_LEN_TABLE (VEX_LEN_0F77) },
6017 /* 78 */
6018 { Bad_Opcode },
6019 { Bad_Opcode },
6020 { Bad_Opcode },
6021 { Bad_Opcode },
6022 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
6023 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
6024 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
6025 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
6026 /* 80 */
6027 { Bad_Opcode },
6028 { Bad_Opcode },
6029 { Bad_Opcode },
6030 { Bad_Opcode },
6031 { Bad_Opcode },
6032 { Bad_Opcode },
6033 { Bad_Opcode },
6034 { Bad_Opcode },
6035 /* 88 */
6036 { Bad_Opcode },
6037 { Bad_Opcode },
6038 { Bad_Opcode },
6039 { Bad_Opcode },
6040 { Bad_Opcode },
6041 { Bad_Opcode },
6042 { Bad_Opcode },
6043 { Bad_Opcode },
6044 /* 90 */
6045 { VEX_LEN_TABLE (VEX_LEN_0F90) },
6046 { VEX_LEN_TABLE (VEX_LEN_0F91) },
6047 { VEX_LEN_TABLE (VEX_LEN_0F92) },
6048 { VEX_LEN_TABLE (VEX_LEN_0F93) },
6049 { Bad_Opcode },
6050 { Bad_Opcode },
6051 { Bad_Opcode },
6052 { Bad_Opcode },
6053 /* 98 */
6054 { VEX_LEN_TABLE (VEX_LEN_0F98) },
6055 { VEX_LEN_TABLE (VEX_LEN_0F99) },
6056 { Bad_Opcode },
6057 { Bad_Opcode },
6058 { Bad_Opcode },
6059 { Bad_Opcode },
6060 { Bad_Opcode },
6061 { Bad_Opcode },
6062 /* a0 */
6063 { Bad_Opcode },
6064 { Bad_Opcode },
6065 { Bad_Opcode },
6066 { Bad_Opcode },
6067 { Bad_Opcode },
6068 { Bad_Opcode },
6069 { Bad_Opcode },
6070 { Bad_Opcode },
6071 /* a8 */
6072 { Bad_Opcode },
6073 { Bad_Opcode },
6074 { Bad_Opcode },
6075 { Bad_Opcode },
6076 { Bad_Opcode },
6077 { Bad_Opcode },
6078 { REG_TABLE (REG_VEX_0FAE) },
6079 { Bad_Opcode },
6080 /* b0 */
6081 { Bad_Opcode },
6082 { Bad_Opcode },
6083 { Bad_Opcode },
6084 { Bad_Opcode },
6085 { Bad_Opcode },
6086 { Bad_Opcode },
6087 { Bad_Opcode },
6088 { Bad_Opcode },
6089 /* b8 */
6090 { Bad_Opcode },
6091 { Bad_Opcode },
6092 { Bad_Opcode },
6093 { Bad_Opcode },
6094 { Bad_Opcode },
6095 { Bad_Opcode },
6096 { Bad_Opcode },
6097 { Bad_Opcode },
6098 /* c0 */
6099 { Bad_Opcode },
6100 { Bad_Opcode },
6101 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
6102 { Bad_Opcode },
6103 { VEX_LEN_TABLE (VEX_LEN_0FC4) },
6104 { VEX_LEN_TABLE (VEX_LEN_0FC5) },
6105 { "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
6106 { Bad_Opcode },
6107 /* c8 */
6108 { Bad_Opcode },
6109 { Bad_Opcode },
6110 { Bad_Opcode },
6111 { Bad_Opcode },
6112 { Bad_Opcode },
6113 { Bad_Opcode },
6114 { Bad_Opcode },
6115 { Bad_Opcode },
6116 /* d0 */
6117 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
6118 { "vpsrlw", { XM, Vex, EXxmm }, PREFIX_DATA },
6119 { "vpsrld", { XM, Vex, EXxmm }, PREFIX_DATA },
6120 { "vpsrlq", { XM, Vex, EXxmm }, PREFIX_DATA },
6121 { "vpaddq", { XM, Vex, EXx }, PREFIX_DATA },
6122 { "vpmullw", { XM, Vex, EXx }, PREFIX_DATA },
6123 { VEX_LEN_TABLE (VEX_LEN_0FD6) },
6124 { MOD_TABLE (MOD_VEX_0FD7) },
6125 /* d8 */
6126 { "vpsubusb", { XM, Vex, EXx }, PREFIX_DATA },
6127 { "vpsubusw", { XM, Vex, EXx }, PREFIX_DATA },
6128 { "vpminub", { XM, Vex, EXx }, PREFIX_DATA },
6129 { "vpand", { XM, Vex, EXx }, PREFIX_DATA },
6130 { "vpaddusb", { XM, Vex, EXx }, PREFIX_DATA },
6131 { "vpaddusw", { XM, Vex, EXx }, PREFIX_DATA },
6132 { "vpmaxub", { XM, Vex, EXx }, PREFIX_DATA },
6133 { "vpandn", { XM, Vex, EXx }, PREFIX_DATA },
6134 /* e0 */
6135 { "vpavgb", { XM, Vex, EXx }, PREFIX_DATA },
6136 { "vpsraw", { XM, Vex, EXxmm }, PREFIX_DATA },
6137 { "vpsrad", { XM, Vex, EXxmm }, PREFIX_DATA },
6138 { "vpavgw", { XM, Vex, EXx }, PREFIX_DATA },
6139 { "vpmulhuw", { XM, Vex, EXx }, PREFIX_DATA },
6140 { "vpmulhw", { XM, Vex, EXx }, PREFIX_DATA },
6141 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
6142 { MOD_TABLE (MOD_VEX_0FE7) },
6143 /* e8 */
6144 { "vpsubsb", { XM, Vex, EXx }, PREFIX_DATA },
6145 { "vpsubsw", { XM, Vex, EXx }, PREFIX_DATA },
6146 { "vpminsw", { XM, Vex, EXx }, PREFIX_DATA },
6147 { "vpor", { XM, Vex, EXx }, PREFIX_DATA },
6148 { "vpaddsb", { XM, Vex, EXx }, PREFIX_DATA },
6149 { "vpaddsw", { XM, Vex, EXx }, PREFIX_DATA },
6150 { "vpmaxsw", { XM, Vex, EXx }, PREFIX_DATA },
6151 { "vpxor", { XM, Vex, EXx }, PREFIX_DATA },
6152 /* f0 */
6153 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
6154 { "vpsllw", { XM, Vex, EXxmm }, PREFIX_DATA },
6155 { "vpslld", { XM, Vex, EXxmm }, PREFIX_DATA },
6156 { "vpsllq", { XM, Vex, EXxmm }, PREFIX_DATA },
6157 { "vpmuludq", { XM, Vex, EXx }, PREFIX_DATA },
6158 { "vpmaddwd", { XM, Vex, EXx }, PREFIX_DATA },
6159 { "vpsadbw", { XM, Vex, EXx }, PREFIX_DATA },
6160 { VEX_LEN_TABLE (VEX_LEN_0FF7) },
6161 /* f8 */
6162 { "vpsubb", { XM, Vex, EXx }, PREFIX_DATA },
6163 { "vpsubw", { XM, Vex, EXx }, PREFIX_DATA },
6164 { "vpsubd", { XM, Vex, EXx }, PREFIX_DATA },
6165 { "vpsubq", { XM, Vex, EXx }, PREFIX_DATA },
6166 { "vpaddb", { XM, Vex, EXx }, PREFIX_DATA },
6167 { "vpaddw", { XM, Vex, EXx }, PREFIX_DATA },
6168 { "vpaddd", { XM, Vex, EXx }, PREFIX_DATA },
6169 { Bad_Opcode },
6170 },
6171 /* VEX_0F38 */
6172 {
6173 /* 00 */
6174 { "vpshufb", { XM, Vex, EXx }, PREFIX_DATA },
6175 { "vphaddw", { XM, Vex, EXx }, PREFIX_DATA },
6176 { "vphaddd", { XM, Vex, EXx }, PREFIX_DATA },
6177 { "vphaddsw", { XM, Vex, EXx }, PREFIX_DATA },
6178 { "vpmaddubsw", { XM, Vex, EXx }, PREFIX_DATA },
6179 { "vphsubw", { XM, Vex, EXx }, PREFIX_DATA },
6180 { "vphsubd", { XM, Vex, EXx }, PREFIX_DATA },
6181 { "vphsubsw", { XM, Vex, EXx }, PREFIX_DATA },
6182 /* 08 */
6183 { "vpsignb", { XM, Vex, EXx }, PREFIX_DATA },
6184 { "vpsignw", { XM, Vex, EXx }, PREFIX_DATA },
6185 { "vpsignd", { XM, Vex, EXx }, PREFIX_DATA },
6186 { "vpmulhrsw", { XM, Vex, EXx }, PREFIX_DATA },
6187 { VEX_W_TABLE (VEX_W_0F380C) },
6188 { VEX_W_TABLE (VEX_W_0F380D) },
6189 { VEX_W_TABLE (VEX_W_0F380E) },
6190 { VEX_W_TABLE (VEX_W_0F380F) },
6191 /* 10 */
6192 { Bad_Opcode },
6193 { Bad_Opcode },
6194 { Bad_Opcode },
6195 { VEX_W_TABLE (VEX_W_0F3813) },
6196 { Bad_Opcode },
6197 { Bad_Opcode },
6198 { VEX_LEN_TABLE (VEX_LEN_0F3816) },
6199 { "vptest", { XM, EXx }, PREFIX_DATA },
6200 /* 18 */
6201 { VEX_W_TABLE (VEX_W_0F3818) },
6202 { VEX_LEN_TABLE (VEX_LEN_0F3819) },
6203 { MOD_TABLE (MOD_VEX_0F381A) },
6204 { Bad_Opcode },
6205 { "vpabsb", { XM, EXx }, PREFIX_DATA },
6206 { "vpabsw", { XM, EXx }, PREFIX_DATA },
6207 { "vpabsd", { XM, EXx }, PREFIX_DATA },
6208 { Bad_Opcode },
6209 /* 20 */
6210 { "vpmovsxbw", { XM, EXxmmq }, PREFIX_DATA },
6211 { "vpmovsxbd", { XM, EXxmmqd }, PREFIX_DATA },
6212 { "vpmovsxbq", { XM, EXxmmdw }, PREFIX_DATA },
6213 { "vpmovsxwd", { XM, EXxmmq }, PREFIX_DATA },
6214 { "vpmovsxwq", { XM, EXxmmqd }, PREFIX_DATA },
6215 { "vpmovsxdq", { XM, EXxmmq }, PREFIX_DATA },
6216 { Bad_Opcode },
6217 { Bad_Opcode },
6218 /* 28 */
6219 { "vpmuldq", { XM, Vex, EXx }, PREFIX_DATA },
6220 { "vpcmpeqq", { XM, Vex, EXx }, PREFIX_DATA },
6221 { MOD_TABLE (MOD_VEX_0F382A) },
6222 { "vpackusdw", { XM, Vex, EXx }, PREFIX_DATA },
6223 { MOD_TABLE (MOD_VEX_0F382C) },
6224 { MOD_TABLE (MOD_VEX_0F382D) },
6225 { MOD_TABLE (MOD_VEX_0F382E) },
6226 { MOD_TABLE (MOD_VEX_0F382F) },
6227 /* 30 */
6228 { "vpmovzxbw", { XM, EXxmmq }, PREFIX_DATA },
6229 { "vpmovzxbd", { XM, EXxmmqd }, PREFIX_DATA },
6230 { "vpmovzxbq", { XM, EXxmmdw }, PREFIX_DATA },
6231 { "vpmovzxwd", { XM, EXxmmq }, PREFIX_DATA },
6232 { "vpmovzxwq", { XM, EXxmmqd }, PREFIX_DATA },
6233 { "vpmovzxdq", { XM, EXxmmq }, PREFIX_DATA },
6234 { VEX_LEN_TABLE (VEX_LEN_0F3836) },
6235 { "vpcmpgtq", { XM, Vex, EXx }, PREFIX_DATA },
6236 /* 38 */
6237 { "vpminsb", { XM, Vex, EXx }, PREFIX_DATA },
6238 { "vpminsd", { XM, Vex, EXx }, PREFIX_DATA },
6239 { "vpminuw", { XM, Vex, EXx }, PREFIX_DATA },
6240 { "vpminud", { XM, Vex, EXx }, PREFIX_DATA },
6241 { "vpmaxsb", { XM, Vex, EXx }, PREFIX_DATA },
6242 { "vpmaxsd", { XM, Vex, EXx }, PREFIX_DATA },
6243 { "vpmaxuw", { XM, Vex, EXx }, PREFIX_DATA },
6244 { "vpmaxud", { XM, Vex, EXx }, PREFIX_DATA },
6245 /* 40 */
6246 { "vpmulld", { XM, Vex, EXx }, PREFIX_DATA },
6247 { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6248 { Bad_Opcode },
6249 { Bad_Opcode },
6250 { Bad_Opcode },
6251 { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6252 { VEX_W_TABLE (VEX_W_0F3846) },
6253 { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6254 /* 48 */
6255 { Bad_Opcode },
6256 { X86_64_TABLE (X86_64_VEX_0F3849) },
6257 { Bad_Opcode },
6258 { X86_64_TABLE (X86_64_VEX_0F384B) },
6259 { Bad_Opcode },
6260 { Bad_Opcode },
6261 { Bad_Opcode },
6262 { Bad_Opcode },
6263 /* 50 */
6264 { VEX_W_TABLE (VEX_W_0F3850) },
6265 { VEX_W_TABLE (VEX_W_0F3851) },
6266 { VEX_W_TABLE (VEX_W_0F3852) },
6267 { VEX_W_TABLE (VEX_W_0F3853) },
6268 { Bad_Opcode },
6269 { Bad_Opcode },
6270 { Bad_Opcode },
6271 { Bad_Opcode },
6272 /* 58 */
6273 { VEX_W_TABLE (VEX_W_0F3858) },
6274 { VEX_W_TABLE (VEX_W_0F3859) },
6275 { MOD_TABLE (MOD_VEX_0F385A) },
6276 { Bad_Opcode },
6277 { X86_64_TABLE (X86_64_VEX_0F385C) },
6278 { Bad_Opcode },
6279 { X86_64_TABLE (X86_64_VEX_0F385E) },
6280 { Bad_Opcode },
6281 /* 60 */
6282 { Bad_Opcode },
6283 { Bad_Opcode },
6284 { Bad_Opcode },
6285 { Bad_Opcode },
6286 { Bad_Opcode },
6287 { Bad_Opcode },
6288 { Bad_Opcode },
6289 { Bad_Opcode },
6290 /* 68 */
6291 { Bad_Opcode },
6292 { Bad_Opcode },
6293 { Bad_Opcode },
6294 { Bad_Opcode },
6295 { Bad_Opcode },
6296 { Bad_Opcode },
6297 { Bad_Opcode },
6298 { Bad_Opcode },
6299 /* 70 */
6300 { Bad_Opcode },
6301 { Bad_Opcode },
6302 { Bad_Opcode },
6303 { Bad_Opcode },
6304 { Bad_Opcode },
6305 { Bad_Opcode },
6306 { Bad_Opcode },
6307 { Bad_Opcode },
6308 /* 78 */
6309 { VEX_W_TABLE (VEX_W_0F3878) },
6310 { VEX_W_TABLE (VEX_W_0F3879) },
6311 { Bad_Opcode },
6312 { Bad_Opcode },
6313 { Bad_Opcode },
6314 { Bad_Opcode },
6315 { Bad_Opcode },
6316 { Bad_Opcode },
6317 /* 80 */
6318 { Bad_Opcode },
6319 { Bad_Opcode },
6320 { Bad_Opcode },
6321 { Bad_Opcode },
6322 { Bad_Opcode },
6323 { Bad_Opcode },
6324 { Bad_Opcode },
6325 { Bad_Opcode },
6326 /* 88 */
6327 { Bad_Opcode },
6328 { Bad_Opcode },
6329 { Bad_Opcode },
6330 { Bad_Opcode },
6331 { MOD_TABLE (MOD_VEX_0F388C) },
6332 { Bad_Opcode },
6333 { MOD_TABLE (MOD_VEX_0F388E) },
6334 { Bad_Opcode },
6335 /* 90 */
6336 { "vpgatherd%DQ", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA },
6337 { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6338 { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA },
6339 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6340 { Bad_Opcode },
6341 { Bad_Opcode },
6342 { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6343 { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6344 /* 98 */
6345 { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6346 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6347 { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6348 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6349 { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6350 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6351 { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6352 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6353 /* a0 */
6354 { Bad_Opcode },
6355 { Bad_Opcode },
6356 { Bad_Opcode },
6357 { Bad_Opcode },
6358 { Bad_Opcode },
6359 { Bad_Opcode },
6360 { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6361 { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6362 /* a8 */
6363 { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6364 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6365 { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6366 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6367 { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6368 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6369 { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6370 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6371 /* b0 */
6372 { Bad_Opcode },
6373 { Bad_Opcode },
6374 { Bad_Opcode },
6375 { Bad_Opcode },
6376 { Bad_Opcode },
6377 { Bad_Opcode },
6378 { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6379 { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6380 /* b8 */
6381 { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6382 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6383 { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6384 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6385 { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6386 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6387 { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6388 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6389 /* c0 */
6390 { Bad_Opcode },
6391 { Bad_Opcode },
6392 { Bad_Opcode },
6393 { Bad_Opcode },
6394 { Bad_Opcode },
6395 { Bad_Opcode },
6396 { Bad_Opcode },
6397 { Bad_Opcode },
6398 /* c8 */
6399 { Bad_Opcode },
6400 { Bad_Opcode },
6401 { Bad_Opcode },
6402 { Bad_Opcode },
6403 { Bad_Opcode },
6404 { Bad_Opcode },
6405 { Bad_Opcode },
6406 { VEX_W_TABLE (VEX_W_0F38CF) },
6407 /* d0 */
6408 { Bad_Opcode },
6409 { Bad_Opcode },
6410 { Bad_Opcode },
6411 { Bad_Opcode },
6412 { Bad_Opcode },
6413 { Bad_Opcode },
6414 { Bad_Opcode },
6415 { Bad_Opcode },
6416 /* d8 */
6417 { Bad_Opcode },
6418 { Bad_Opcode },
6419 { Bad_Opcode },
6420 { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6421 { "vaesenc", { XM, Vex, EXx }, PREFIX_DATA },
6422 { "vaesenclast", { XM, Vex, EXx }, PREFIX_DATA },
6423 { "vaesdec", { XM, Vex, EXx }, PREFIX_DATA },
6424 { "vaesdeclast", { XM, Vex, EXx }, PREFIX_DATA },
6425 /* e0 */
6426 { Bad_Opcode },
6427 { Bad_Opcode },
6428 { Bad_Opcode },
6429 { Bad_Opcode },
6430 { Bad_Opcode },
6431 { Bad_Opcode },
6432 { Bad_Opcode },
6433 { Bad_Opcode },
6434 /* e8 */
6435 { Bad_Opcode },
6436 { Bad_Opcode },
6437 { Bad_Opcode },
6438 { Bad_Opcode },
6439 { Bad_Opcode },
6440 { Bad_Opcode },
6441 { Bad_Opcode },
6442 { Bad_Opcode },
6443 /* f0 */
6444 { Bad_Opcode },
6445 { Bad_Opcode },
6446 { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
6447 { VEX_LEN_TABLE (VEX_LEN_0F38F3) },
6448 { Bad_Opcode },
6449 { VEX_LEN_TABLE (VEX_LEN_0F38F5) },
6450 { VEX_LEN_TABLE (VEX_LEN_0F38F6) },
6451 { VEX_LEN_TABLE (VEX_LEN_0F38F7) },
6452 /* f8 */
6453 { Bad_Opcode },
6454 { Bad_Opcode },
6455 { Bad_Opcode },
6456 { Bad_Opcode },
6457 { Bad_Opcode },
6458 { Bad_Opcode },
6459 { Bad_Opcode },
6460 { Bad_Opcode },
6461 },
6462 /* VEX_0F3A */
6463 {
6464 /* 00 */
6465 { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6466 { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6467 { VEX_W_TABLE (VEX_W_0F3A02) },
6468 { Bad_Opcode },
6469 { VEX_W_TABLE (VEX_W_0F3A04) },
6470 { VEX_W_TABLE (VEX_W_0F3A05) },
6471 { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6472 { Bad_Opcode },
6473 /* 08 */
6474 { "vroundps", { XM, EXx, Ib }, PREFIX_DATA },
6475 { "vroundpd", { XM, EXx, Ib }, PREFIX_DATA },
6476 { "vroundss", { XMScalar, VexScalar, EXxmm_md, Ib }, PREFIX_DATA },
6477 { "vroundsd", { XMScalar, VexScalar, EXxmm_mq, Ib }, PREFIX_DATA },
6478 { "vblendps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6479 { "vblendpd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6480 { "vpblendw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6481 { "vpalignr", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6482 /* 10 */
6483 { Bad_Opcode },
6484 { Bad_Opcode },
6485 { Bad_Opcode },
6486 { Bad_Opcode },
6487 { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6488 { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6489 { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6490 { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6491 /* 18 */
6492 { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6493 { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6494 { Bad_Opcode },
6495 { Bad_Opcode },
6496 { Bad_Opcode },
6497 { VEX_W_TABLE (VEX_W_0F3A1D) },
6498 { Bad_Opcode },
6499 { Bad_Opcode },
6500 /* 20 */
6501 { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6502 { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6503 { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6504 { Bad_Opcode },
6505 { Bad_Opcode },
6506 { Bad_Opcode },
6507 { Bad_Opcode },
6508 { Bad_Opcode },
6509 /* 28 */
6510 { Bad_Opcode },
6511 { Bad_Opcode },
6512 { Bad_Opcode },
6513 { Bad_Opcode },
6514 { Bad_Opcode },
6515 { Bad_Opcode },
6516 { Bad_Opcode },
6517 { Bad_Opcode },
6518 /* 30 */
6519 { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6520 { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6521 { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6522 { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6523 { Bad_Opcode },
6524 { Bad_Opcode },
6525 { Bad_Opcode },
6526 { Bad_Opcode },
6527 /* 38 */
6528 { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6529 { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6530 { Bad_Opcode },
6531 { Bad_Opcode },
6532 { Bad_Opcode },
6533 { Bad_Opcode },
6534 { Bad_Opcode },
6535 { Bad_Opcode },
6536 /* 40 */
6537 { "vdpps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6538 { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6539 { "vmpsadbw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6540 { Bad_Opcode },
6541 { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6542 { Bad_Opcode },
6543 { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6544 { Bad_Opcode },
6545 /* 48 */
6546 { "vpermil2ps", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6547 { "vpermil2pd", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6548 { VEX_W_TABLE (VEX_W_0F3A4A) },
6549 { VEX_W_TABLE (VEX_W_0F3A4B) },
6550 { VEX_W_TABLE (VEX_W_0F3A4C) },
6551 { Bad_Opcode },
6552 { Bad_Opcode },
6553 { Bad_Opcode },
6554 /* 50 */
6555 { Bad_Opcode },
6556 { Bad_Opcode },
6557 { Bad_Opcode },
6558 { Bad_Opcode },
6559 { Bad_Opcode },
6560 { Bad_Opcode },
6561 { Bad_Opcode },
6562 { Bad_Opcode },
6563 /* 58 */
6564 { Bad_Opcode },
6565 { Bad_Opcode },
6566 { Bad_Opcode },
6567 { Bad_Opcode },
6568 { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6569 { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6570 { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6571 { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6572 /* 60 */
6573 { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6574 { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6575 { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6576 { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6577 { Bad_Opcode },
6578 { Bad_Opcode },
6579 { Bad_Opcode },
6580 { Bad_Opcode },
6581 /* 68 */
6582 { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6583 { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6584 { "vfmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6585 { "vfmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6586 { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6587 { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6588 { "vfmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6589 { "vfmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6590 /* 70 */
6591 { Bad_Opcode },
6592 { Bad_Opcode },
6593 { Bad_Opcode },
6594 { Bad_Opcode },
6595 { Bad_Opcode },
6596 { Bad_Opcode },
6597 { Bad_Opcode },
6598 { Bad_Opcode },
6599 /* 78 */
6600 { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6601 { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6602 { "vfnmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6603 { "vfnmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6604 { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6605 { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6606 { "vfnmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6607 { "vfnmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6608 /* 80 */
6609 { Bad_Opcode },
6610 { Bad_Opcode },
6611 { Bad_Opcode },
6612 { Bad_Opcode },
6613 { Bad_Opcode },
6614 { Bad_Opcode },
6615 { Bad_Opcode },
6616 { Bad_Opcode },
6617 /* 88 */
6618 { Bad_Opcode },
6619 { Bad_Opcode },
6620 { Bad_Opcode },
6621 { Bad_Opcode },
6622 { Bad_Opcode },
6623 { Bad_Opcode },
6624 { Bad_Opcode },
6625 { Bad_Opcode },
6626 /* 90 */
6627 { Bad_Opcode },
6628 { Bad_Opcode },
6629 { Bad_Opcode },
6630 { Bad_Opcode },
6631 { Bad_Opcode },
6632 { Bad_Opcode },
6633 { Bad_Opcode },
6634 { Bad_Opcode },
6635 /* 98 */
6636 { Bad_Opcode },
6637 { Bad_Opcode },
6638 { Bad_Opcode },
6639 { Bad_Opcode },
6640 { Bad_Opcode },
6641 { Bad_Opcode },
6642 { Bad_Opcode },
6643 { Bad_Opcode },
6644 /* a0 */
6645 { Bad_Opcode },
6646 { Bad_Opcode },
6647 { Bad_Opcode },
6648 { Bad_Opcode },
6649 { Bad_Opcode },
6650 { Bad_Opcode },
6651 { Bad_Opcode },
6652 { Bad_Opcode },
6653 /* a8 */
6654 { Bad_Opcode },
6655 { Bad_Opcode },
6656 { Bad_Opcode },
6657 { Bad_Opcode },
6658 { Bad_Opcode },
6659 { Bad_Opcode },
6660 { Bad_Opcode },
6661 { Bad_Opcode },
6662 /* b0 */
6663 { Bad_Opcode },
6664 { Bad_Opcode },
6665 { Bad_Opcode },
6666 { Bad_Opcode },
6667 { Bad_Opcode },
6668 { Bad_Opcode },
6669 { Bad_Opcode },
6670 { Bad_Opcode },
6671 /* b8 */
6672 { Bad_Opcode },
6673 { Bad_Opcode },
6674 { Bad_Opcode },
6675 { Bad_Opcode },
6676 { Bad_Opcode },
6677 { Bad_Opcode },
6678 { Bad_Opcode },
6679 { Bad_Opcode },
6680 /* c0 */
6681 { Bad_Opcode },
6682 { Bad_Opcode },
6683 { Bad_Opcode },
6684 { Bad_Opcode },
6685 { Bad_Opcode },
6686 { Bad_Opcode },
6687 { Bad_Opcode },
6688 { Bad_Opcode },
6689 /* c8 */
6690 { Bad_Opcode },
6691 { Bad_Opcode },
6692 { Bad_Opcode },
6693 { Bad_Opcode },
6694 { Bad_Opcode },
6695 { Bad_Opcode },
6696 { VEX_W_TABLE (VEX_W_0F3ACE) },
6697 { VEX_W_TABLE (VEX_W_0F3ACF) },
6698 /* d0 */
6699 { Bad_Opcode },
6700 { Bad_Opcode },
6701 { Bad_Opcode },
6702 { Bad_Opcode },
6703 { Bad_Opcode },
6704 { Bad_Opcode },
6705 { Bad_Opcode },
6706 { Bad_Opcode },
6707 /* d8 */
6708 { Bad_Opcode },
6709 { Bad_Opcode },
6710 { Bad_Opcode },
6711 { Bad_Opcode },
6712 { Bad_Opcode },
6713 { Bad_Opcode },
6714 { Bad_Opcode },
6715 { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
6716 /* e0 */
6717 { Bad_Opcode },
6718 { Bad_Opcode },
6719 { Bad_Opcode },
6720 { Bad_Opcode },
6721 { Bad_Opcode },
6722 { Bad_Opcode },
6723 { Bad_Opcode },
6724 { Bad_Opcode },
6725 /* e8 */
6726 { Bad_Opcode },
6727 { Bad_Opcode },
6728 { Bad_Opcode },
6729 { Bad_Opcode },
6730 { Bad_Opcode },
6731 { Bad_Opcode },
6732 { Bad_Opcode },
6733 { Bad_Opcode },
6734 /* f0 */
6735 { VEX_LEN_TABLE (VEX_LEN_0F3AF0) },
6736 { Bad_Opcode },
6737 { Bad_Opcode },
6738 { Bad_Opcode },
6739 { Bad_Opcode },
6740 { Bad_Opcode },
6741 { Bad_Opcode },
6742 { Bad_Opcode },
6743 /* f8 */
6744 { Bad_Opcode },
6745 { Bad_Opcode },
6746 { Bad_Opcode },
6747 { Bad_Opcode },
6748 { Bad_Opcode },
6749 { Bad_Opcode },
6750 { Bad_Opcode },
6751 { Bad_Opcode },
6752 },
6753 };
6754
6755 #include "i386-dis-evex.h"
6756
6757 static const struct dis386 vex_len_table[][2] = {
6758 /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
6759 {
6760 { "vmovlpX", { XM, Vex, EXq }, 0 },
6761 },
6762
6763 /* VEX_LEN_0F12_P_0_M_1 */
6764 {
6765 { "vmovhlps", { XM, Vex, EXq }, 0 },
6766 },
6767
6768 /* VEX_LEN_0F13_M_0 */
6769 {
6770 { "vmovlpX", { EXq, XM }, PREFIX_OPCODE },
6771 },
6772
6773 /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
6774 {
6775 { "vmovhpX", { XM, Vex, EXq }, 0 },
6776 },
6777
6778 /* VEX_LEN_0F16_P_0_M_1 */
6779 {
6780 { "vmovlhps", { XM, Vex, EXq }, 0 },
6781 },
6782
6783 /* VEX_LEN_0F17_M_0 */
6784 {
6785 { "vmovhpX", { EXq, XM }, PREFIX_OPCODE },
6786 },
6787
6788 /* VEX_LEN_0F41 */
6789 {
6790 { Bad_Opcode },
6791 { MOD_TABLE (MOD_VEX_0F41_L_1) },
6792 },
6793
6794 /* VEX_LEN_0F42 */
6795 {
6796 { Bad_Opcode },
6797 { MOD_TABLE (MOD_VEX_0F42_L_1) },
6798 },
6799
6800 /* VEX_LEN_0F44 */
6801 {
6802 { MOD_TABLE (MOD_VEX_0F44_L_0) },
6803 },
6804
6805 /* VEX_LEN_0F45 */
6806 {
6807 { Bad_Opcode },
6808 { MOD_TABLE (MOD_VEX_0F45_L_1) },
6809 },
6810
6811 /* VEX_LEN_0F46 */
6812 {
6813 { Bad_Opcode },
6814 { MOD_TABLE (MOD_VEX_0F46_L_1) },
6815 },
6816
6817 /* VEX_LEN_0F47 */
6818 {
6819 { Bad_Opcode },
6820 { MOD_TABLE (MOD_VEX_0F47_L_1) },
6821 },
6822
6823 /* VEX_LEN_0F4A */
6824 {
6825 { Bad_Opcode },
6826 { MOD_TABLE (MOD_VEX_0F4A_L_1) },
6827 },
6828
6829 /* VEX_LEN_0F4B */
6830 {
6831 { Bad_Opcode },
6832 { MOD_TABLE (MOD_VEX_0F4B_L_1) },
6833 },
6834
6835 /* VEX_LEN_0F6E */
6836 {
6837 { "vmovK", { XMScalar, Edq }, PREFIX_DATA },
6838 },
6839
6840 /* VEX_LEN_0F77 */
6841 {
6842 { "vzeroupper", { XX }, 0 },
6843 { "vzeroall", { XX }, 0 },
6844 },
6845
6846 /* VEX_LEN_0F7E_P_1 */
6847 {
6848 { "vmovq", { XMScalar, EXxmm_mq }, 0 },
6849 },
6850
6851 /* VEX_LEN_0F7E_P_2 */
6852 {
6853 { "vmovK", { Edq, XMScalar }, 0 },
6854 },
6855
6856 /* VEX_LEN_0F90 */
6857 {
6858 { VEX_W_TABLE (VEX_W_0F90_L_0) },
6859 },
6860
6861 /* VEX_LEN_0F91 */
6862 {
6863 { MOD_TABLE (MOD_VEX_0F91_L_0) },
6864 },
6865
6866 /* VEX_LEN_0F92 */
6867 {
6868 { MOD_TABLE (MOD_VEX_0F92_L_0) },
6869 },
6870
6871 /* VEX_LEN_0F93 */
6872 {
6873 { MOD_TABLE (MOD_VEX_0F93_L_0) },
6874 },
6875
6876 /* VEX_LEN_0F98 */
6877 {
6878 { MOD_TABLE (MOD_VEX_0F98_L_0) },
6879 },
6880
6881 /* VEX_LEN_0F99 */
6882 {
6883 { MOD_TABLE (MOD_VEX_0F99_L_0) },
6884 },
6885
6886 /* VEX_LEN_0FAE_R_2_M_0 */
6887 {
6888 { "vldmxcsr", { Md }, 0 },
6889 },
6890
6891 /* VEX_LEN_0FAE_R_3_M_0 */
6892 {
6893 { "vstmxcsr", { Md }, 0 },
6894 },
6895
6896 /* VEX_LEN_0FC4 */
6897 {
6898 { "vpinsrw", { XM, Vex, Edqw, Ib }, PREFIX_DATA },
6899 },
6900
6901 /* VEX_LEN_0FC5 */
6902 {
6903 { "vpextrw", { Gdq, XS, Ib }, PREFIX_DATA },
6904 },
6905
6906 /* VEX_LEN_0FD6 */
6907 {
6908 { "vmovq", { EXqS, XMScalar }, PREFIX_DATA },
6909 },
6910
6911 /* VEX_LEN_0FF7 */
6912 {
6913 { "vmaskmovdqu", { XM, XS }, PREFIX_DATA },
6914 },
6915
6916 /* VEX_LEN_0F3816 */
6917 {
6918 { Bad_Opcode },
6919 { VEX_W_TABLE (VEX_W_0F3816_L_1) },
6920 },
6921
6922 /* VEX_LEN_0F3819 */
6923 {
6924 { Bad_Opcode },
6925 { VEX_W_TABLE (VEX_W_0F3819_L_1) },
6926 },
6927
6928 /* VEX_LEN_0F381A_M_0 */
6929 {
6930 { Bad_Opcode },
6931 { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1) },
6932 },
6933
6934 /* VEX_LEN_0F3836 */
6935 {
6936 { Bad_Opcode },
6937 { VEX_W_TABLE (VEX_W_0F3836) },
6938 },
6939
6940 /* VEX_LEN_0F3841 */
6941 {
6942 { "vphminposuw", { XM, EXx }, PREFIX_DATA },
6943 },
6944
6945 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
6946 {
6947 { "ldtilecfg", { M }, 0 },
6948 },
6949
6950 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
6951 {
6952 { "tilerelease", { Skip_MODRM }, 0 },
6953 },
6954
6955 /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
6956 {
6957 { "sttilecfg", { M }, 0 },
6958 },
6959
6960 /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
6961 {
6962 { "tilezero", { TMM, Skip_MODRM }, 0 },
6963 },
6964
6965 /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
6966 {
6967 { "tilestored", { MVexSIBMEM, TMM }, 0 },
6968 },
6969 /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
6970 {
6971 { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
6972 },
6973
6974 /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
6975 {
6976 { "tileloadd", { TMM, MVexSIBMEM }, 0 },
6977 },
6978
6979 /* VEX_LEN_0F385A_M_0 */
6980 {
6981 { Bad_Opcode },
6982 { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0) },
6983 },
6984
6985 /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
6986 {
6987 { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
6988 },
6989
6990 /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
6991 {
6992 { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
6993 },
6994
6995 /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
6996 {
6997 { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 },
6998 },
6999
7000 /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
7001 {
7002 { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 },
7003 },
7004
7005 /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
7006 {
7007 { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 },
7008 },
7009
7010 /* VEX_LEN_0F38DB */
7011 {
7012 { "vaesimc", { XM, EXx }, PREFIX_DATA },
7013 },
7014
7015 /* VEX_LEN_0F38F2 */
7016 {
7017 { "andnS", { Gdq, VexGdq, Edq }, PREFIX_OPCODE },
7018 },
7019
7020 /* VEX_LEN_0F38F3 */
7021 {
7022 { REG_TABLE(REG_VEX_0F38F3_L_0) },
7023 },
7024
7025 /* VEX_LEN_0F38F5 */
7026 {
7027 { PREFIX_TABLE(PREFIX_VEX_0F38F5_L_0) },
7028 },
7029
7030 /* VEX_LEN_0F38F6 */
7031 {
7032 { PREFIX_TABLE(PREFIX_VEX_0F38F6_L_0) },
7033 },
7034
7035 /* VEX_LEN_0F38F7 */
7036 {
7037 { PREFIX_TABLE(PREFIX_VEX_0F38F7_L_0) },
7038 },
7039
7040 /* VEX_LEN_0F3A00 */
7041 {
7042 { Bad_Opcode },
7043 { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
7044 },
7045
7046 /* VEX_LEN_0F3A01 */
7047 {
7048 { Bad_Opcode },
7049 { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
7050 },
7051
7052 /* VEX_LEN_0F3A06 */
7053 {
7054 { Bad_Opcode },
7055 { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
7056 },
7057
7058 /* VEX_LEN_0F3A14 */
7059 {
7060 { "vpextrb", { Edqb, XM, Ib }, PREFIX_DATA },
7061 },
7062
7063 /* VEX_LEN_0F3A15 */
7064 {
7065 { "vpextrw", { Edqw, XM, Ib }, PREFIX_DATA },
7066 },
7067
7068 /* VEX_LEN_0F3A16 */
7069 {
7070 { "vpextrK", { Edq, XM, Ib }, PREFIX_DATA },
7071 },
7072
7073 /* VEX_LEN_0F3A17 */
7074 {
7075 { "vextractps", { Edqd, XM, Ib }, PREFIX_DATA },
7076 },
7077
7078 /* VEX_LEN_0F3A18 */
7079 {
7080 { Bad_Opcode },
7081 { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
7082 },
7083
7084 /* VEX_LEN_0F3A19 */
7085 {
7086 { Bad_Opcode },
7087 { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
7088 },
7089
7090 /* VEX_LEN_0F3A20 */
7091 {
7092 { "vpinsrb", { XM, Vex, Edqb, Ib }, PREFIX_DATA },
7093 },
7094
7095 /* VEX_LEN_0F3A21 */
7096 {
7097 { "vinsertps", { XM, Vex, EXd, Ib }, PREFIX_DATA },
7098 },
7099
7100 /* VEX_LEN_0F3A22 */
7101 {
7102 { "vpinsrK", { XM, Vex, Edq, Ib }, PREFIX_DATA },
7103 },
7104
7105 /* VEX_LEN_0F3A30 */
7106 {
7107 { MOD_TABLE (MOD_VEX_0F3A30_L_0) },
7108 },
7109
7110 /* VEX_LEN_0F3A31 */
7111 {
7112 { MOD_TABLE (MOD_VEX_0F3A31_L_0) },
7113 },
7114
7115 /* VEX_LEN_0F3A32 */
7116 {
7117 { MOD_TABLE (MOD_VEX_0F3A32_L_0) },
7118 },
7119
7120 /* VEX_LEN_0F3A33 */
7121 {
7122 { MOD_TABLE (MOD_VEX_0F3A33_L_0) },
7123 },
7124
7125 /* VEX_LEN_0F3A38 */
7126 {
7127 { Bad_Opcode },
7128 { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7129 },
7130
7131 /* VEX_LEN_0F3A39 */
7132 {
7133 { Bad_Opcode },
7134 { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7135 },
7136
7137 /* VEX_LEN_0F3A41 */
7138 {
7139 { "vdppd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7140 },
7141
7142 /* VEX_LEN_0F3A46 */
7143 {
7144 { Bad_Opcode },
7145 { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7146 },
7147
7148 /* VEX_LEN_0F3A60 */
7149 {
7150 { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7151 },
7152
7153 /* VEX_LEN_0F3A61 */
7154 {
7155 { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7156 },
7157
7158 /* VEX_LEN_0F3A62 */
7159 {
7160 { "vpcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
7161 },
7162
7163 /* VEX_LEN_0F3A63 */
7164 {
7165 { "vpcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
7166 },
7167
7168 /* VEX_LEN_0F3ADF */
7169 {
7170 { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7171 },
7172
7173 /* VEX_LEN_0F3AF0 */
7174 {
7175 { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) },
7176 },
7177
7178 /* VEX_LEN_0FXOP_08_85 */
7179 {
7180 { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
7181 },
7182
7183 /* VEX_LEN_0FXOP_08_86 */
7184 {
7185 { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
7186 },
7187
7188 /* VEX_LEN_0FXOP_08_87 */
7189 {
7190 { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
7191 },
7192
7193 /* VEX_LEN_0FXOP_08_8E */
7194 {
7195 { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
7196 },
7197
7198 /* VEX_LEN_0FXOP_08_8F */
7199 {
7200 { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
7201 },
7202
7203 /* VEX_LEN_0FXOP_08_95 */
7204 {
7205 { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
7206 },
7207
7208 /* VEX_LEN_0FXOP_08_96 */
7209 {
7210 { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
7211 },
7212
7213 /* VEX_LEN_0FXOP_08_97 */
7214 {
7215 { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
7216 },
7217
7218 /* VEX_LEN_0FXOP_08_9E */
7219 {
7220 { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
7221 },
7222
7223 /* VEX_LEN_0FXOP_08_9F */
7224 {
7225 { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
7226 },
7227
7228 /* VEX_LEN_0FXOP_08_A3 */
7229 {
7230 { "vpperm", { XM, Vex, EXx, XMVexI4 }, 0 },
7231 },
7232
7233 /* VEX_LEN_0FXOP_08_A6 */
7234 {
7235 { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
7236 },
7237
7238 /* VEX_LEN_0FXOP_08_B6 */
7239 {
7240 { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
7241 },
7242
7243 /* VEX_LEN_0FXOP_08_C0 */
7244 {
7245 { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
7246 },
7247
7248 /* VEX_LEN_0FXOP_08_C1 */
7249 {
7250 { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
7251 },
7252
7253 /* VEX_LEN_0FXOP_08_C2 */
7254 {
7255 { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
7256 },
7257
7258 /* VEX_LEN_0FXOP_08_C3 */
7259 {
7260 { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
7261 },
7262
7263 /* VEX_LEN_0FXOP_08_CC */
7264 {
7265 { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
7266 },
7267
7268 /* VEX_LEN_0FXOP_08_CD */
7269 {
7270 { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
7271 },
7272
7273 /* VEX_LEN_0FXOP_08_CE */
7274 {
7275 { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
7276 },
7277
7278 /* VEX_LEN_0FXOP_08_CF */
7279 {
7280 { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
7281 },
7282
7283 /* VEX_LEN_0FXOP_08_EC */
7284 {
7285 { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
7286 },
7287
7288 /* VEX_LEN_0FXOP_08_ED */
7289 {
7290 { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
7291 },
7292
7293 /* VEX_LEN_0FXOP_08_EE */
7294 {
7295 { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
7296 },
7297
7298 /* VEX_LEN_0FXOP_08_EF */
7299 {
7300 { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
7301 },
7302
7303 /* VEX_LEN_0FXOP_09_01 */
7304 {
7305 { REG_TABLE (REG_0FXOP_09_01_L_0) },
7306 },
7307
7308 /* VEX_LEN_0FXOP_09_02 */
7309 {
7310 { REG_TABLE (REG_0FXOP_09_02_L_0) },
7311 },
7312
7313 /* VEX_LEN_0FXOP_09_12_M_1 */
7314 {
7315 { REG_TABLE (REG_0FXOP_09_12_M_1_L_0) },
7316 },
7317
7318 /* VEX_LEN_0FXOP_09_82_W_0 */
7319 {
7320 { "vfrczss", { XM, EXd }, 0 },
7321 },
7322
7323 /* VEX_LEN_0FXOP_09_83_W_0 */
7324 {
7325 { "vfrczsd", { XM, EXq }, 0 },
7326 },
7327
7328 /* VEX_LEN_0FXOP_09_90 */
7329 {
7330 { "vprotb", { XM, EXx, VexW }, 0 },
7331 },
7332
7333 /* VEX_LEN_0FXOP_09_91 */
7334 {
7335 { "vprotw", { XM, EXx, VexW }, 0 },
7336 },
7337
7338 /* VEX_LEN_0FXOP_09_92 */
7339 {
7340 { "vprotd", { XM, EXx, VexW }, 0 },
7341 },
7342
7343 /* VEX_LEN_0FXOP_09_93 */
7344 {
7345 { "vprotq", { XM, EXx, VexW }, 0 },
7346 },
7347
7348 /* VEX_LEN_0FXOP_09_94 */
7349 {
7350 { "vpshlb", { XM, EXx, VexW }, 0 },
7351 },
7352
7353 /* VEX_LEN_0FXOP_09_95 */
7354 {
7355 { "vpshlw", { XM, EXx, VexW }, 0 },
7356 },
7357
7358 /* VEX_LEN_0FXOP_09_96 */
7359 {
7360 { "vpshld", { XM, EXx, VexW }, 0 },
7361 },
7362
7363 /* VEX_LEN_0FXOP_09_97 */
7364 {
7365 { "vpshlq", { XM, EXx, VexW }, 0 },
7366 },
7367
7368 /* VEX_LEN_0FXOP_09_98 */
7369 {
7370 { "vpshab", { XM, EXx, VexW }, 0 },
7371 },
7372
7373 /* VEX_LEN_0FXOP_09_99 */
7374 {
7375 { "vpshaw", { XM, EXx, VexW }, 0 },
7376 },
7377
7378 /* VEX_LEN_0FXOP_09_9A */
7379 {
7380 { "vpshad", { XM, EXx, VexW }, 0 },
7381 },
7382
7383 /* VEX_LEN_0FXOP_09_9B */
7384 {
7385 { "vpshaq", { XM, EXx, VexW }, 0 },
7386 },
7387
7388 /* VEX_LEN_0FXOP_09_C1 */
7389 {
7390 { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
7391 },
7392
7393 /* VEX_LEN_0FXOP_09_C2 */
7394 {
7395 { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
7396 },
7397
7398 /* VEX_LEN_0FXOP_09_C3 */
7399 {
7400 { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
7401 },
7402
7403 /* VEX_LEN_0FXOP_09_C6 */
7404 {
7405 { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
7406 },
7407
7408 /* VEX_LEN_0FXOP_09_C7 */
7409 {
7410 { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
7411 },
7412
7413 /* VEX_LEN_0FXOP_09_CB */
7414 {
7415 { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
7416 },
7417
7418 /* VEX_LEN_0FXOP_09_D1 */
7419 {
7420 { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
7421 },
7422
7423 /* VEX_LEN_0FXOP_09_D2 */
7424 {
7425 { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
7426 },
7427
7428 /* VEX_LEN_0FXOP_09_D3 */
7429 {
7430 { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
7431 },
7432
7433 /* VEX_LEN_0FXOP_09_D6 */
7434 {
7435 { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
7436 },
7437
7438 /* VEX_LEN_0FXOP_09_D7 */
7439 {
7440 { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
7441 },
7442
7443 /* VEX_LEN_0FXOP_09_DB */
7444 {
7445 { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
7446 },
7447
7448 /* VEX_LEN_0FXOP_09_E1 */
7449 {
7450 { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
7451 },
7452
7453 /* VEX_LEN_0FXOP_09_E2 */
7454 {
7455 { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
7456 },
7457
7458 /* VEX_LEN_0FXOP_09_E3 */
7459 {
7460 { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
7461 },
7462
7463 /* VEX_LEN_0FXOP_0A_12 */
7464 {
7465 { REG_TABLE (REG_0FXOP_0A_12_L_0) },
7466 },
7467 };
7468
7469 #include "i386-dis-evex-len.h"
7470
7471 static const struct dis386 vex_w_table[][2] = {
7472 {
7473 /* VEX_W_0F41_L_1_M_1 */
7474 { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_0) },
7475 { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_1) },
7476 },
7477 {
7478 /* VEX_W_0F42_L_1_M_1 */
7479 { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_0) },
7480 { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_1) },
7481 },
7482 {
7483 /* VEX_W_0F44_L_0_M_1 */
7484 { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_0) },
7485 { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_1) },
7486 },
7487 {
7488 /* VEX_W_0F45_L_1_M_1 */
7489 { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_0) },
7490 { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_1) },
7491 },
7492 {
7493 /* VEX_W_0F46_L_1_M_1 */
7494 { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_0) },
7495 { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_1) },
7496 },
7497 {
7498 /* VEX_W_0F47_L_1_M_1 */
7499 { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_0) },
7500 { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_1) },
7501 },
7502 {
7503 /* VEX_W_0F4A_L_1_M_1 */
7504 { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_0) },
7505 { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_1) },
7506 },
7507 {
7508 /* VEX_W_0F4B_L_1_M_1 */
7509 { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_0) },
7510 { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_1) },
7511 },
7512 {
7513 /* VEX_W_0F90_L_0 */
7514 { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_0) },
7515 { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_1) },
7516 },
7517 {
7518 /* VEX_W_0F91_L_0_M_0 */
7519 { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_0) },
7520 { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_1) },
7521 },
7522 {
7523 /* VEX_W_0F92_L_0_M_1 */
7524 { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_0) },
7525 { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_1) },
7526 },
7527 {
7528 /* VEX_W_0F93_L_0_M_1 */
7529 { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_0) },
7530 { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_1) },
7531 },
7532 {
7533 /* VEX_W_0F98_L_0_M_1 */
7534 { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_0) },
7535 { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_1) },
7536 },
7537 {
7538 /* VEX_W_0F99_L_0_M_1 */
7539 { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_0) },
7540 { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_1) },
7541 },
7542 {
7543 /* VEX_W_0F380C */
7544 { "vpermilps", { XM, Vex, EXx }, PREFIX_DATA },
7545 },
7546 {
7547 /* VEX_W_0F380D */
7548 { "vpermilpd", { XM, Vex, EXx }, PREFIX_DATA },
7549 },
7550 {
7551 /* VEX_W_0F380E */
7552 { "vtestps", { XM, EXx }, PREFIX_DATA },
7553 },
7554 {
7555 /* VEX_W_0F380F */
7556 { "vtestpd", { XM, EXx }, PREFIX_DATA },
7557 },
7558 {
7559 /* VEX_W_0F3813 */
7560 { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
7561 },
7562 {
7563 /* VEX_W_0F3816_L_1 */
7564 { "vpermps", { XM, Vex, EXx }, PREFIX_DATA },
7565 },
7566 {
7567 /* VEX_W_0F3818 */
7568 { "vbroadcastss", { XM, EXxmm_md }, PREFIX_DATA },
7569 },
7570 {
7571 /* VEX_W_0F3819_L_1 */
7572 { "vbroadcastsd", { XM, EXxmm_mq }, PREFIX_DATA },
7573 },
7574 {
7575 /* VEX_W_0F381A_M_0_L_1 */
7576 { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
7577 },
7578 {
7579 /* VEX_W_0F382C_M_0 */
7580 { "vmaskmovps", { XM, Vex, Mx }, PREFIX_DATA },
7581 },
7582 {
7583 /* VEX_W_0F382D_M_0 */
7584 { "vmaskmovpd", { XM, Vex, Mx }, PREFIX_DATA },
7585 },
7586 {
7587 /* VEX_W_0F382E_M_0 */
7588 { "vmaskmovps", { Mx, Vex, XM }, PREFIX_DATA },
7589 },
7590 {
7591 /* VEX_W_0F382F_M_0 */
7592 { "vmaskmovpd", { Mx, Vex, XM }, PREFIX_DATA },
7593 },
7594 {
7595 /* VEX_W_0F3836 */
7596 { "vpermd", { XM, Vex, EXx }, PREFIX_DATA },
7597 },
7598 {
7599 /* VEX_W_0F3846 */
7600 { "vpsravd", { XM, Vex, EXx }, PREFIX_DATA },
7601 },
7602 {
7603 /* VEX_W_0F3849_X86_64_P_0 */
7604 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) },
7605 },
7606 {
7607 /* VEX_W_0F3849_X86_64_P_2 */
7608 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) },
7609 },
7610 {
7611 /* VEX_W_0F3849_X86_64_P_3 */
7612 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) },
7613 },
7614 {
7615 /* VEX_W_0F384B_X86_64_P_1 */
7616 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) },
7617 },
7618 {
7619 /* VEX_W_0F384B_X86_64_P_2 */
7620 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) },
7621 },
7622 {
7623 /* VEX_W_0F384B_X86_64_P_3 */
7624 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) },
7625 },
7626 {
7627 /* VEX_W_0F3850 */
7628 { "%XV vpdpbusd", { XM, Vex, EXx }, 0 },
7629 },
7630 {
7631 /* VEX_W_0F3851 */
7632 { "%XV vpdpbusds", { XM, Vex, EXx }, 0 },
7633 },
7634 {
7635 /* VEX_W_0F3852 */
7636 { "%XV vpdpwssd", { XM, Vex, EXx }, 0 },
7637 },
7638 {
7639 /* VEX_W_0F3853 */
7640 { "%XV vpdpwssds", { XM, Vex, EXx }, 0 },
7641 },
7642 {
7643 /* VEX_W_0F3858 */
7644 { "vpbroadcastd", { XM, EXxmm_md }, PREFIX_DATA },
7645 },
7646 {
7647 /* VEX_W_0F3859 */
7648 { "vpbroadcastq", { XM, EXxmm_mq }, PREFIX_DATA },
7649 },
7650 {
7651 /* VEX_W_0F385A_M_0_L_0 */
7652 { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
7653 },
7654 {
7655 /* VEX_W_0F385C_X86_64_P_1 */
7656 { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) },
7657 },
7658 {
7659 /* VEX_W_0F385E_X86_64_P_0 */
7660 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) },
7661 },
7662 {
7663 /* VEX_W_0F385E_X86_64_P_1 */
7664 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) },
7665 },
7666 {
7667 /* VEX_W_0F385E_X86_64_P_2 */
7668 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) },
7669 },
7670 {
7671 /* VEX_W_0F385E_X86_64_P_3 */
7672 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) },
7673 },
7674 {
7675 /* VEX_W_0F3878 */
7676 { "vpbroadcastb", { XM, EXxmm_mb }, PREFIX_DATA },
7677 },
7678 {
7679 /* VEX_W_0F3879 */
7680 { "vpbroadcastw", { XM, EXxmm_mw }, PREFIX_DATA },
7681 },
7682 {
7683 /* VEX_W_0F38CF */
7684 { "vgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
7685 },
7686 {
7687 /* VEX_W_0F3A00_L_1 */
7688 { Bad_Opcode },
7689 { "vpermq", { XM, EXx, Ib }, PREFIX_DATA },
7690 },
7691 {
7692 /* VEX_W_0F3A01_L_1 */
7693 { Bad_Opcode },
7694 { "vpermpd", { XM, EXx, Ib }, PREFIX_DATA },
7695 },
7696 {
7697 /* VEX_W_0F3A02 */
7698 { "vpblendd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7699 },
7700 {
7701 /* VEX_W_0F3A04 */
7702 { "vpermilps", { XM, EXx, Ib }, PREFIX_DATA },
7703 },
7704 {
7705 /* VEX_W_0F3A05 */
7706 { "vpermilpd", { XM, EXx, Ib }, PREFIX_DATA },
7707 },
7708 {
7709 /* VEX_W_0F3A06_L_1 */
7710 { "vperm2f128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7711 },
7712 {
7713 /* VEX_W_0F3A18_L_1 */
7714 { "vinsertf128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7715 },
7716 {
7717 /* VEX_W_0F3A19_L_1 */
7718 { "vextractf128", { EXxmm, XM, Ib }, PREFIX_DATA },
7719 },
7720 {
7721 /* VEX_W_0F3A1D */
7722 { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
7723 },
7724 {
7725 /* VEX_W_0F3A38_L_1 */
7726 { "vinserti128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7727 },
7728 {
7729 /* VEX_W_0F3A39_L_1 */
7730 { "vextracti128", { EXxmm, XM, Ib }, PREFIX_DATA },
7731 },
7732 {
7733 /* VEX_W_0F3A46_L_1 */
7734 { "vperm2i128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7735 },
7736 {
7737 /* VEX_W_0F3A4A */
7738 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7739 },
7740 {
7741 /* VEX_W_0F3A4B */
7742 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7743 },
7744 {
7745 /* VEX_W_0F3A4C */
7746 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7747 },
7748 {
7749 /* VEX_W_0F3ACE */
7750 { Bad_Opcode },
7751 { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7752 },
7753 {
7754 /* VEX_W_0F3ACF */
7755 { Bad_Opcode },
7756 { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7757 },
7758 /* VEX_W_0FXOP_08_85_L_0 */
7759 {
7760 { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 },
7761 },
7762 /* VEX_W_0FXOP_08_86_L_0 */
7763 {
7764 { "vpmacsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7765 },
7766 /* VEX_W_0FXOP_08_87_L_0 */
7767 {
7768 { "vpmacssdql", { XM, Vex, EXx, XMVexI4 }, 0 },
7769 },
7770 /* VEX_W_0FXOP_08_8E_L_0 */
7771 {
7772 { "vpmacssdd", { XM, Vex, EXx, XMVexI4 }, 0 },
7773 },
7774 /* VEX_W_0FXOP_08_8F_L_0 */
7775 {
7776 { "vpmacssdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
7777 },
7778 /* VEX_W_0FXOP_08_95_L_0 */
7779 {
7780 { "vpmacsww", { XM, Vex, EXx, XMVexI4 }, 0 },
7781 },
7782 /* VEX_W_0FXOP_08_96_L_0 */
7783 {
7784 { "vpmacswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7785 },
7786 /* VEX_W_0FXOP_08_97_L_0 */
7787 {
7788 { "vpmacsdql", { XM, Vex, EXx, XMVexI4 }, 0 },
7789 },
7790 /* VEX_W_0FXOP_08_9E_L_0 */
7791 {
7792 { "vpmacsdd", { XM, Vex, EXx, XMVexI4 }, 0 },
7793 },
7794 /* VEX_W_0FXOP_08_9F_L_0 */
7795 {
7796 { "vpmacsdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
7797 },
7798 /* VEX_W_0FXOP_08_A6_L_0 */
7799 {
7800 { "vpmadcsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7801 },
7802 /* VEX_W_0FXOP_08_B6_L_0 */
7803 {
7804 { "vpmadcswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7805 },
7806 /* VEX_W_0FXOP_08_C0_L_0 */
7807 {
7808 { "vprotb", { XM, EXx, Ib }, 0 },
7809 },
7810 /* VEX_W_0FXOP_08_C1_L_0 */
7811 {
7812 { "vprotw", { XM, EXx, Ib }, 0 },
7813 },
7814 /* VEX_W_0FXOP_08_C2_L_0 */
7815 {
7816 { "vprotd", { XM, EXx, Ib }, 0 },
7817 },
7818 /* VEX_W_0FXOP_08_C3_L_0 */
7819 {
7820 { "vprotq", { XM, EXx, Ib }, 0 },
7821 },
7822 /* VEX_W_0FXOP_08_CC_L_0 */
7823 {
7824 { "vpcomb", { XM, Vex, EXx, VPCOM }, 0 },
7825 },
7826 /* VEX_W_0FXOP_08_CD_L_0 */
7827 {
7828 { "vpcomw", { XM, Vex, EXx, VPCOM }, 0 },
7829 },
7830 /* VEX_W_0FXOP_08_CE_L_0 */
7831 {
7832 { "vpcomd", { XM, Vex, EXx, VPCOM }, 0 },
7833 },
7834 /* VEX_W_0FXOP_08_CF_L_0 */
7835 {
7836 { "vpcomq", { XM, Vex, EXx, VPCOM }, 0 },
7837 },
7838 /* VEX_W_0FXOP_08_EC_L_0 */
7839 {
7840 { "vpcomub", { XM, Vex, EXx, VPCOM }, 0 },
7841 },
7842 /* VEX_W_0FXOP_08_ED_L_0 */
7843 {
7844 { "vpcomuw", { XM, Vex, EXx, VPCOM }, 0 },
7845 },
7846 /* VEX_W_0FXOP_08_EE_L_0 */
7847 {
7848 { "vpcomud", { XM, Vex, EXx, VPCOM }, 0 },
7849 },
7850 /* VEX_W_0FXOP_08_EF_L_0 */
7851 {
7852 { "vpcomuq", { XM, Vex, EXx, VPCOM }, 0 },
7853 },
7854 /* VEX_W_0FXOP_09_80 */
7855 {
7856 { "vfrczps", { XM, EXx }, 0 },
7857 },
7858 /* VEX_W_0FXOP_09_81 */
7859 {
7860 { "vfrczpd", { XM, EXx }, 0 },
7861 },
7862 /* VEX_W_0FXOP_09_82 */
7863 {
7864 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
7865 },
7866 /* VEX_W_0FXOP_09_83 */
7867 {
7868 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
7869 },
7870 /* VEX_W_0FXOP_09_C1_L_0 */
7871 {
7872 { "vphaddbw", { XM, EXxmm }, 0 },
7873 },
7874 /* VEX_W_0FXOP_09_C2_L_0 */
7875 {
7876 { "vphaddbd", { XM, EXxmm }, 0 },
7877 },
7878 /* VEX_W_0FXOP_09_C3_L_0 */
7879 {
7880 { "vphaddbq", { XM, EXxmm }, 0 },
7881 },
7882 /* VEX_W_0FXOP_09_C6_L_0 */
7883 {
7884 { "vphaddwd", { XM, EXxmm }, 0 },
7885 },
7886 /* VEX_W_0FXOP_09_C7_L_0 */
7887 {
7888 { "vphaddwq", { XM, EXxmm }, 0 },
7889 },
7890 /* VEX_W_0FXOP_09_CB_L_0 */
7891 {
7892 { "vphadddq", { XM, EXxmm }, 0 },
7893 },
7894 /* VEX_W_0FXOP_09_D1_L_0 */
7895 {
7896 { "vphaddubw", { XM, EXxmm }, 0 },
7897 },
7898 /* VEX_W_0FXOP_09_D2_L_0 */
7899 {
7900 { "vphaddubd", { XM, EXxmm }, 0 },
7901 },
7902 /* VEX_W_0FXOP_09_D3_L_0 */
7903 {
7904 { "vphaddubq", { XM, EXxmm }, 0 },
7905 },
7906 /* VEX_W_0FXOP_09_D6_L_0 */
7907 {
7908 { "vphadduwd", { XM, EXxmm }, 0 },
7909 },
7910 /* VEX_W_0FXOP_09_D7_L_0 */
7911 {
7912 { "vphadduwq", { XM, EXxmm }, 0 },
7913 },
7914 /* VEX_W_0FXOP_09_DB_L_0 */
7915 {
7916 { "vphaddudq", { XM, EXxmm }, 0 },
7917 },
7918 /* VEX_W_0FXOP_09_E1_L_0 */
7919 {
7920 { "vphsubbw", { XM, EXxmm }, 0 },
7921 },
7922 /* VEX_W_0FXOP_09_E2_L_0 */
7923 {
7924 { "vphsubwd", { XM, EXxmm }, 0 },
7925 },
7926 /* VEX_W_0FXOP_09_E3_L_0 */
7927 {
7928 { "vphsubdq", { XM, EXxmm }, 0 },
7929 },
7930
7931 #include "i386-dis-evex-w.h"
7932 };
7933
7934 static const struct dis386 mod_table[][2] = {
7935 {
7936 /* MOD_8D */
7937 { "leaS", { Gv, M }, 0 },
7938 },
7939 {
7940 /* MOD_C6_REG_7 */
7941 { Bad_Opcode },
7942 { RM_TABLE (RM_C6_REG_7) },
7943 },
7944 {
7945 /* MOD_C7_REG_7 */
7946 { Bad_Opcode },
7947 { RM_TABLE (RM_C7_REG_7) },
7948 },
7949 {
7950 /* MOD_FF_REG_3 */
7951 { "{l|}call^", { indirEp }, 0 },
7952 },
7953 {
7954 /* MOD_FF_REG_5 */
7955 { "{l|}jmp^", { indirEp }, 0 },
7956 },
7957 {
7958 /* MOD_0F01_REG_0 */
7959 { X86_64_TABLE (X86_64_0F01_REG_0) },
7960 { RM_TABLE (RM_0F01_REG_0) },
7961 },
7962 {
7963 /* MOD_0F01_REG_1 */
7964 { X86_64_TABLE (X86_64_0F01_REG_1) },
7965 { RM_TABLE (RM_0F01_REG_1) },
7966 },
7967 {
7968 /* MOD_0F01_REG_2 */
7969 { X86_64_TABLE (X86_64_0F01_REG_2) },
7970 { RM_TABLE (RM_0F01_REG_2) },
7971 },
7972 {
7973 /* MOD_0F01_REG_3 */
7974 { X86_64_TABLE (X86_64_0F01_REG_3) },
7975 { RM_TABLE (RM_0F01_REG_3) },
7976 },
7977 {
7978 /* MOD_0F01_REG_5 */
7979 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
7980 { RM_TABLE (RM_0F01_REG_5_MOD_3) },
7981 },
7982 {
7983 /* MOD_0F01_REG_7 */
7984 { "invlpg", { Mb }, 0 },
7985 { RM_TABLE (RM_0F01_REG_7_MOD_3) },
7986 },
7987 {
7988 /* MOD_0F12_PREFIX_0 */
7989 { "movlpX", { XM, EXq }, 0 },
7990 { "movhlps", { XM, EXq }, 0 },
7991 },
7992 {
7993 /* MOD_0F12_PREFIX_2 */
7994 { "movlpX", { XM, EXq }, 0 },
7995 },
7996 {
7997 /* MOD_0F13 */
7998 { "movlpX", { EXq, XM }, PREFIX_OPCODE },
7999 },
8000 {
8001 /* MOD_0F16_PREFIX_0 */
8002 { "movhpX", { XM, EXq }, 0 },
8003 { "movlhps", { XM, EXq }, 0 },
8004 },
8005 {
8006 /* MOD_0F16_PREFIX_2 */
8007 { "movhpX", { XM, EXq }, 0 },
8008 },
8009 {
8010 /* MOD_0F17 */
8011 { "movhpX", { EXq, XM }, PREFIX_OPCODE },
8012 },
8013 {
8014 /* MOD_0F18_REG_0 */
8015 { "prefetchnta", { Mb }, 0 },
8016 { "nopQ", { Ev }, 0 },
8017 },
8018 {
8019 /* MOD_0F18_REG_1 */
8020 { "prefetcht0", { Mb }, 0 },
8021 { "nopQ", { Ev }, 0 },
8022 },
8023 {
8024 /* MOD_0F18_REG_2 */
8025 { "prefetcht1", { Mb }, 0 },
8026 { "nopQ", { Ev }, 0 },
8027 },
8028 {
8029 /* MOD_0F18_REG_3 */
8030 { "prefetcht2", { Mb }, 0 },
8031 { "nopQ", { Ev }, 0 },
8032 },
8033 {
8034 /* MOD_0F1A_PREFIX_0 */
8035 { "bndldx", { Gbnd, Mv_bnd }, 0 },
8036 { "nopQ", { Ev }, 0 },
8037 },
8038 {
8039 /* MOD_0F1B_PREFIX_0 */
8040 { "bndstx", { Mv_bnd, Gbnd }, 0 },
8041 { "nopQ", { Ev }, 0 },
8042 },
8043 {
8044 /* MOD_0F1B_PREFIX_1 */
8045 { "bndmk", { Gbnd, Mv_bnd }, 0 },
8046 { "nopQ", { Ev }, PREFIX_IGNORED },
8047 },
8048 {
8049 /* MOD_0F1C_PREFIX_0 */
8050 { REG_TABLE (REG_0F1C_P_0_MOD_0) },
8051 { "nopQ", { Ev }, 0 },
8052 },
8053 {
8054 /* MOD_0F1E_PREFIX_1 */
8055 { "nopQ", { Ev }, PREFIX_IGNORED },
8056 { REG_TABLE (REG_0F1E_P_1_MOD_3) },
8057 },
8058 {
8059 /* MOD_0F2B_PREFIX_0 */
8060 {"movntps", { Mx, XM }, PREFIX_OPCODE },
8061 },
8062 {
8063 /* MOD_0F2B_PREFIX_1 */
8064 {"movntss", { Md, XM }, PREFIX_OPCODE },
8065 },
8066 {
8067 /* MOD_0F2B_PREFIX_2 */
8068 {"movntpd", { Mx, XM }, PREFIX_OPCODE },
8069 },
8070 {
8071 /* MOD_0F2B_PREFIX_3 */
8072 {"movntsd", { Mq, XM }, PREFIX_OPCODE },
8073 },
8074 {
8075 /* MOD_0F50 */
8076 { Bad_Opcode },
8077 { "movmskpX", { Gdq, XS }, PREFIX_OPCODE },
8078 },
8079 {
8080 /* MOD_0F71 */
8081 { Bad_Opcode },
8082 { REG_TABLE (REG_0F71_MOD_0) },
8083 },
8084 {
8085 /* MOD_0F72 */
8086 { Bad_Opcode },
8087 { REG_TABLE (REG_0F72_MOD_0) },
8088 },
8089 {
8090 /* MOD_0F73 */
8091 { Bad_Opcode },
8092 { REG_TABLE (REG_0F73_MOD_0) },
8093 },
8094 {
8095 /* MOD_0FAE_REG_0 */
8096 { "fxsave", { FXSAVE }, 0 },
8097 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8098 },
8099 {
8100 /* MOD_0FAE_REG_1 */
8101 { "fxrstor", { FXSAVE }, 0 },
8102 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8103 },
8104 {
8105 /* MOD_0FAE_REG_2 */
8106 { "ldmxcsr", { Md }, 0 },
8107 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8108 },
8109 {
8110 /* MOD_0FAE_REG_3 */
8111 { "stmxcsr", { Md }, 0 },
8112 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8113 },
8114 {
8115 /* MOD_0FAE_REG_4 */
8116 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8117 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8118 },
8119 {
8120 /* MOD_0FAE_REG_5 */
8121 { "xrstor", { FXSAVE }, PREFIX_OPCODE },
8122 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8123 },
8124 {
8125 /* MOD_0FAE_REG_6 */
8126 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8127 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8128 },
8129 {
8130 /* MOD_0FAE_REG_7 */
8131 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8132 { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8133 },
8134 {
8135 /* MOD_0FB2 */
8136 { "lssS", { Gv, Mp }, 0 },
8137 },
8138 {
8139 /* MOD_0FB4 */
8140 { "lfsS", { Gv, Mp }, 0 },
8141 },
8142 {
8143 /* MOD_0FB5 */
8144 { "lgsS", { Gv, Mp }, 0 },
8145 },
8146 {
8147 /* MOD_0FC3 */
8148 { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
8149 },
8150 {
8151 /* MOD_0FC7_REG_3 */
8152 { "xrstors", { FXSAVE }, 0 },
8153 },
8154 {
8155 /* MOD_0FC7_REG_4 */
8156 { "xsavec", { FXSAVE }, 0 },
8157 },
8158 {
8159 /* MOD_0FC7_REG_5 */
8160 { "xsaves", { FXSAVE }, 0 },
8161 },
8162 {
8163 /* MOD_0FC7_REG_6 */
8164 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8165 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8166 },
8167 {
8168 /* MOD_0FC7_REG_7 */
8169 { "vmptrst", { Mq }, 0 },
8170 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8171 },
8172 {
8173 /* MOD_0FD7 */
8174 { Bad_Opcode },
8175 { "pmovmskb", { Gdq, MS }, 0 },
8176 },
8177 {
8178 /* MOD_0FE7_PREFIX_2 */
8179 { "movntdq", { Mx, XM }, 0 },
8180 },
8181 {
8182 /* MOD_0FF0_PREFIX_3 */
8183 { "lddqu", { XM, M }, 0 },
8184 },
8185 {
8186 /* MOD_0F382A */
8187 { "movntdqa", { XM, Mx }, PREFIX_DATA },
8188 },
8189 {
8190 /* MOD_0F38DC_PREFIX_1 */
8191 { "aesenc128kl", { XM, M }, 0 },
8192 { "loadiwkey", { XM, EXx }, 0 },
8193 },
8194 {
8195 /* MOD_0F38DD_PREFIX_1 */
8196 { "aesdec128kl", { XM, M }, 0 },
8197 },
8198 {
8199 /* MOD_0F38DE_PREFIX_1 */
8200 { "aesenc256kl", { XM, M }, 0 },
8201 },
8202 {
8203 /* MOD_0F38DF_PREFIX_1 */
8204 { "aesdec256kl", { XM, M }, 0 },
8205 },
8206 {
8207 /* MOD_0F38F5 */
8208 { "wrussK", { M, Gdq }, PREFIX_DATA },
8209 },
8210 {
8211 /* MOD_0F38F6_PREFIX_0 */
8212 { "wrssK", { M, Gdq }, PREFIX_OPCODE },
8213 },
8214 {
8215 /* MOD_0F38F8_PREFIX_1 */
8216 { "enqcmds", { Gva, M }, PREFIX_OPCODE },
8217 },
8218 {
8219 /* MOD_0F38F8_PREFIX_2 */
8220 { "movdir64b", { Gva, M }, PREFIX_OPCODE },
8221 },
8222 {
8223 /* MOD_0F38F8_PREFIX_3 */
8224 { "enqcmd", { Gva, M }, PREFIX_OPCODE },
8225 },
8226 {
8227 /* MOD_0F38F9 */
8228 { "movdiri", { Edq, Gdq }, PREFIX_OPCODE },
8229 },
8230 {
8231 /* MOD_0F38FA_PREFIX_1 */
8232 { Bad_Opcode },
8233 { "encodekey128", { Gd, Ed }, 0 },
8234 },
8235 {
8236 /* MOD_0F38FB_PREFIX_1 */
8237 { Bad_Opcode },
8238 { "encodekey256", { Gd, Ed }, 0 },
8239 },
8240 {
8241 /* MOD_0F3A0F_PREFIX_1 */
8242 { Bad_Opcode },
8243 { REG_TABLE (REG_0F3A0F_PREFIX_1_MOD_3) },
8244 },
8245 {
8246 /* MOD_62_32BIT */
8247 { "bound{S|}", { Gv, Ma }, 0 },
8248 { EVEX_TABLE (EVEX_0F) },
8249 },
8250 {
8251 /* MOD_C4_32BIT */
8252 { "lesS", { Gv, Mp }, 0 },
8253 { VEX_C4_TABLE (VEX_0F) },
8254 },
8255 {
8256 /* MOD_C5_32BIT */
8257 { "ldsS", { Gv, Mp }, 0 },
8258 { VEX_C5_TABLE (VEX_0F) },
8259 },
8260 {
8261 /* MOD_VEX_0F12_PREFIX_0 */
8262 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
8263 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
8264 },
8265 {
8266 /* MOD_VEX_0F12_PREFIX_2 */
8267 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
8268 },
8269 {
8270 /* MOD_VEX_0F13 */
8271 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
8272 },
8273 {
8274 /* MOD_VEX_0F16_PREFIX_0 */
8275 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
8276 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
8277 },
8278 {
8279 /* MOD_VEX_0F16_PREFIX_2 */
8280 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
8281 },
8282 {
8283 /* MOD_VEX_0F17 */
8284 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
8285 },
8286 {
8287 /* MOD_VEX_0F2B */
8288 { "vmovntpX", { Mx, XM }, PREFIX_OPCODE },
8289 },
8290 {
8291 /* MOD_VEX_0F41_L_1 */
8292 { Bad_Opcode },
8293 { VEX_W_TABLE (VEX_W_0F41_L_1_M_1) },
8294 },
8295 {
8296 /* MOD_VEX_0F42_L_1 */
8297 { Bad_Opcode },
8298 { VEX_W_TABLE (VEX_W_0F42_L_1_M_1) },
8299 },
8300 {
8301 /* MOD_VEX_0F44_L_0 */
8302 { Bad_Opcode },
8303 { VEX_W_TABLE (VEX_W_0F44_L_0_M_1) },
8304 },
8305 {
8306 /* MOD_VEX_0F45_L_1 */
8307 { Bad_Opcode },
8308 { VEX_W_TABLE (VEX_W_0F45_L_1_M_1) },
8309 },
8310 {
8311 /* MOD_VEX_0F46_L_1 */
8312 { Bad_Opcode },
8313 { VEX_W_TABLE (VEX_W_0F46_L_1_M_1) },
8314 },
8315 {
8316 /* MOD_VEX_0F47_L_1 */
8317 { Bad_Opcode },
8318 { VEX_W_TABLE (VEX_W_0F47_L_1_M_1) },
8319 },
8320 {
8321 /* MOD_VEX_0F4A_L_1 */
8322 { Bad_Opcode },
8323 { VEX_W_TABLE (VEX_W_0F4A_L_1_M_1) },
8324 },
8325 {
8326 /* MOD_VEX_0F4B_L_1 */
8327 { Bad_Opcode },
8328 { VEX_W_TABLE (VEX_W_0F4B_L_1_M_1) },
8329 },
8330 {
8331 /* MOD_VEX_0F50 */
8332 { Bad_Opcode },
8333 { "vmovmskpX", { Gdq, XS }, PREFIX_OPCODE },
8334 },
8335 {
8336 /* MOD_VEX_0F71 */
8337 { Bad_Opcode },
8338 { REG_TABLE (REG_VEX_0F71_M_0) },
8339 },
8340 {
8341 /* MOD_VEX_0F72 */
8342 { Bad_Opcode },
8343 { REG_TABLE (REG_VEX_0F72_M_0) },
8344 },
8345 {
8346 /* MOD_VEX_0F73 */
8347 { Bad_Opcode },
8348 { REG_TABLE (REG_VEX_0F73_M_0) },
8349 },
8350 {
8351 /* MOD_VEX_0F91_L_0 */
8352 { VEX_W_TABLE (VEX_W_0F91_L_0_M_0) },
8353 },
8354 {
8355 /* MOD_VEX_0F92_L_0 */
8356 { Bad_Opcode },
8357 { VEX_W_TABLE (VEX_W_0F92_L_0_M_1) },
8358 },
8359 {
8360 /* MOD_VEX_0F93_L_0 */
8361 { Bad_Opcode },
8362 { VEX_W_TABLE (VEX_W_0F93_L_0_M_1) },
8363 },
8364 {
8365 /* MOD_VEX_0F98_L_0 */
8366 { Bad_Opcode },
8367 { VEX_W_TABLE (VEX_W_0F98_L_0_M_1) },
8368 },
8369 {
8370 /* MOD_VEX_0F99_L_0 */
8371 { Bad_Opcode },
8372 { VEX_W_TABLE (VEX_W_0F99_L_0_M_1) },
8373 },
8374 {
8375 /* MOD_VEX_0FAE_REG_2 */
8376 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
8377 },
8378 {
8379 /* MOD_VEX_0FAE_REG_3 */
8380 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
8381 },
8382 {
8383 /* MOD_VEX_0FD7 */
8384 { Bad_Opcode },
8385 { "vpmovmskb", { Gdq, XS }, PREFIX_DATA },
8386 },
8387 {
8388 /* MOD_VEX_0FE7 */
8389 { "vmovntdq", { Mx, XM }, PREFIX_DATA },
8390 },
8391 {
8392 /* MOD_VEX_0FF0_PREFIX_3 */
8393 { "vlddqu", { XM, M }, 0 },
8394 },
8395 {
8396 /* MOD_VEX_0F381A */
8397 { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0) },
8398 },
8399 {
8400 /* MOD_VEX_0F382A */
8401 { "vmovntdqa", { XM, Mx }, PREFIX_DATA },
8402 },
8403 {
8404 /* MOD_VEX_0F382C */
8405 { VEX_W_TABLE (VEX_W_0F382C_M_0) },
8406 },
8407 {
8408 /* MOD_VEX_0F382D */
8409 { VEX_W_TABLE (VEX_W_0F382D_M_0) },
8410 },
8411 {
8412 /* MOD_VEX_0F382E */
8413 { VEX_W_TABLE (VEX_W_0F382E_M_0) },
8414 },
8415 {
8416 /* MOD_VEX_0F382F */
8417 { VEX_W_TABLE (VEX_W_0F382F_M_0) },
8418 },
8419 {
8420 /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
8421 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) },
8422 { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) },
8423 },
8424 {
8425 /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
8426 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) },
8427 },
8428 {
8429 /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
8430 { Bad_Opcode },
8431 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) },
8432 },
8433 {
8434 /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
8435 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) },
8436 },
8437 {
8438 /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
8439 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) },
8440 },
8441 {
8442 /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
8443 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) },
8444 },
8445 {
8446 /* MOD_VEX_0F385A */
8447 { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0) },
8448 },
8449 {
8450 /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
8451 { Bad_Opcode },
8452 { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) },
8453 },
8454 {
8455 /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
8456 { Bad_Opcode },
8457 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) },
8458 },
8459 {
8460 /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
8461 { Bad_Opcode },
8462 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) },
8463 },
8464 {
8465 /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
8466 { Bad_Opcode },
8467 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) },
8468 },
8469 {
8470 /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
8471 { Bad_Opcode },
8472 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) },
8473 },
8474 {
8475 /* MOD_VEX_0F388C */
8476 { "vpmaskmov%DQ", { XM, Vex, Mx }, PREFIX_DATA },
8477 },
8478 {
8479 /* MOD_VEX_0F388E */
8480 { "vpmaskmov%DQ", { Mx, Vex, XM }, PREFIX_DATA },
8481 },
8482 {
8483 /* MOD_VEX_0F3A30_L_0 */
8484 { Bad_Opcode },
8485 { "kshiftr%BW", { MaskG, MaskE, Ib }, PREFIX_DATA },
8486 },
8487 {
8488 /* MOD_VEX_0F3A31_L_0 */
8489 { Bad_Opcode },
8490 { "kshiftr%DQ", { MaskG, MaskE, Ib }, PREFIX_DATA },
8491 },
8492 {
8493 /* MOD_VEX_0F3A32_L_0 */
8494 { Bad_Opcode },
8495 { "kshiftl%BW", { MaskG, MaskE, Ib }, PREFIX_DATA },
8496 },
8497 {
8498 /* MOD_VEX_0F3A33_L_0 */
8499 { Bad_Opcode },
8500 { "kshiftl%DQ", { MaskG, MaskE, Ib }, PREFIX_DATA },
8501 },
8502 {
8503 /* MOD_VEX_0FXOP_09_12 */
8504 { Bad_Opcode },
8505 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
8506 },
8507
8508 #include "i386-dis-evex-mod.h"
8509 };
8510
8511 static const struct dis386 rm_table[][8] = {
8512 {
8513 /* RM_C6_REG_7 */
8514 { "xabort", { Skip_MODRM, Ib }, 0 },
8515 },
8516 {
8517 /* RM_C7_REG_7 */
8518 { "xbeginT", { Skip_MODRM, Jdqw }, 0 },
8519 },
8520 {
8521 /* RM_0F01_REG_0 */
8522 { "enclv", { Skip_MODRM }, 0 },
8523 { "vmcall", { Skip_MODRM }, 0 },
8524 { "vmlaunch", { Skip_MODRM }, 0 },
8525 { "vmresume", { Skip_MODRM }, 0 },
8526 { "vmxoff", { Skip_MODRM }, 0 },
8527 { "pconfig", { Skip_MODRM }, 0 },
8528 },
8529 {
8530 /* RM_0F01_REG_1 */
8531 { "monitor", { { OP_Monitor, 0 } }, 0 },
8532 { "mwait", { { OP_Mwait, 0 } }, 0 },
8533 { "clac", { Skip_MODRM }, 0 },
8534 { "stac", { Skip_MODRM }, 0 },
8535 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) },
8536 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) },
8537 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) },
8538 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) },
8539 },
8540 {
8541 /* RM_0F01_REG_2 */
8542 { "xgetbv", { Skip_MODRM }, 0 },
8543 { "xsetbv", { Skip_MODRM }, 0 },
8544 { Bad_Opcode },
8545 { Bad_Opcode },
8546 { "vmfunc", { Skip_MODRM }, 0 },
8547 { "xend", { Skip_MODRM }, 0 },
8548 { "xtest", { Skip_MODRM }, 0 },
8549 { "enclu", { Skip_MODRM }, 0 },
8550 },
8551 {
8552 /* RM_0F01_REG_3 */
8553 { "vmrun", { Skip_MODRM }, 0 },
8554 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
8555 { "vmload", { Skip_MODRM }, 0 },
8556 { "vmsave", { Skip_MODRM }, 0 },
8557 { "stgi", { Skip_MODRM }, 0 },
8558 { "clgi", { Skip_MODRM }, 0 },
8559 { "skinit", { Skip_MODRM }, 0 },
8560 { "invlpga", { Skip_MODRM }, 0 },
8561 },
8562 {
8563 /* RM_0F01_REG_5_MOD_3 */
8564 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
8565 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
8566 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
8567 { Bad_Opcode },
8568 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4) },
8569 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5) },
8570 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6) },
8571 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7) },
8572 },
8573 {
8574 /* RM_0F01_REG_7_MOD_3 */
8575 { "swapgs", { Skip_MODRM }, 0 },
8576 { "rdtscp", { Skip_MODRM }, 0 },
8577 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
8578 { "mwaitx", { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
8579 { "clzero", { Skip_MODRM }, 0 },
8580 { "rdpru", { Skip_MODRM }, 0 },
8581 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) },
8582 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) },
8583 },
8584 {
8585 /* RM_0F1E_P_1_MOD_3_REG_7 */
8586 { "nopQ", { Ev }, PREFIX_IGNORED },
8587 { "nopQ", { Ev }, PREFIX_IGNORED },
8588 { "endbr64", { Skip_MODRM }, 0 },
8589 { "endbr32", { Skip_MODRM }, 0 },
8590 { "nopQ", { Ev }, PREFIX_IGNORED },
8591 { "nopQ", { Ev }, PREFIX_IGNORED },
8592 { "nopQ", { Ev }, PREFIX_IGNORED },
8593 { "nopQ", { Ev }, PREFIX_IGNORED },
8594 },
8595 {
8596 /* RM_0F3A0F_P_1_MOD_3_REG_0 */
8597 { "hreset", { Skip_MODRM, Ib }, 0 },
8598 },
8599 {
8600 /* RM_0FAE_REG_6_MOD_3 */
8601 { "mfence", { Skip_MODRM }, 0 },
8602 },
8603 {
8604 /* RM_0FAE_REG_7_MOD_3 */
8605 { "sfence", { Skip_MODRM }, 0 },
8606
8607 },
8608 {
8609 /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
8610 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) },
8611 },
8612 };
8613
8614 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8615
8616 /* We use the high bit to indicate different name for the same
8617 prefix. */
8618 #define REP_PREFIX (0xf3 | 0x100)
8619 #define XACQUIRE_PREFIX (0xf2 | 0x200)
8620 #define XRELEASE_PREFIX (0xf3 | 0x400)
8621 #define BND_PREFIX (0xf2 | 0x400)
8622 #define NOTRACK_PREFIX (0x3e | 0x100)
8623
8624 /* Remember if the current op is a jump instruction. */
8625 static bfd_boolean op_is_jump = FALSE;
8626
8627 static int
8628 ckprefix (void)
8629 {
8630 int newrex, i, length;
8631 rex = 0;
8632 prefixes = 0;
8633 used_prefixes = 0;
8634 rex_used = 0;
8635 last_lock_prefix = -1;
8636 last_repz_prefix = -1;
8637 last_repnz_prefix = -1;
8638 last_data_prefix = -1;
8639 last_addr_prefix = -1;
8640 last_rex_prefix = -1;
8641 last_seg_prefix = -1;
8642 fwait_prefix = -1;
8643 active_seg_prefix = 0;
8644 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
8645 all_prefixes[i] = 0;
8646 i = 0;
8647 length = 0;
8648 /* The maximum instruction length is 15bytes. */
8649 while (length < MAX_CODE_LENGTH - 1)
8650 {
8651 FETCH_DATA (the_info, codep + 1);
8652 newrex = 0;
8653 switch (*codep)
8654 {
8655 /* REX prefixes family. */
8656 case 0x40:
8657 case 0x41:
8658 case 0x42:
8659 case 0x43:
8660 case 0x44:
8661 case 0x45:
8662 case 0x46:
8663 case 0x47:
8664 case 0x48:
8665 case 0x49:
8666 case 0x4a:
8667 case 0x4b:
8668 case 0x4c:
8669 case 0x4d:
8670 case 0x4e:
8671 case 0x4f:
8672 if (address_mode == mode_64bit)
8673 newrex = *codep;
8674 else
8675 return 1;
8676 last_rex_prefix = i;
8677 break;
8678 case 0xf3:
8679 prefixes |= PREFIX_REPZ;
8680 last_repz_prefix = i;
8681 break;
8682 case 0xf2:
8683 prefixes |= PREFIX_REPNZ;
8684 last_repnz_prefix = i;
8685 break;
8686 case 0xf0:
8687 prefixes |= PREFIX_LOCK;
8688 last_lock_prefix = i;
8689 break;
8690 case 0x2e:
8691 prefixes |= PREFIX_CS;
8692 last_seg_prefix = i;
8693
8694 if (address_mode != mode_64bit)
8695 active_seg_prefix = PREFIX_CS;
8696
8697 break;
8698 case 0x36:
8699 prefixes |= PREFIX_SS;
8700 last_seg_prefix = i;
8701
8702 if (address_mode != mode_64bit)
8703 active_seg_prefix = PREFIX_SS;
8704
8705 break;
8706 case 0x3e:
8707 prefixes |= PREFIX_DS;
8708 last_seg_prefix = i;
8709
8710 if (address_mode != mode_64bit)
8711 active_seg_prefix = PREFIX_DS;
8712
8713 break;
8714 case 0x26:
8715 prefixes |= PREFIX_ES;
8716 last_seg_prefix = i;
8717
8718 if (address_mode != mode_64bit)
8719 active_seg_prefix = PREFIX_ES;
8720
8721 break;
8722 case 0x64:
8723 prefixes |= PREFIX_FS;
8724 last_seg_prefix = i;
8725 active_seg_prefix = PREFIX_FS;
8726 break;
8727 case 0x65:
8728 prefixes |= PREFIX_GS;
8729 last_seg_prefix = i;
8730 active_seg_prefix = PREFIX_GS;
8731 break;
8732 case 0x66:
8733 prefixes |= PREFIX_DATA;
8734 last_data_prefix = i;
8735 break;
8736 case 0x67:
8737 prefixes |= PREFIX_ADDR;
8738 last_addr_prefix = i;
8739 break;
8740 case FWAIT_OPCODE:
8741 /* fwait is really an instruction. If there are prefixes
8742 before the fwait, they belong to the fwait, *not* to the
8743 following instruction. */
8744 fwait_prefix = i;
8745 if (prefixes || rex)
8746 {
8747 prefixes |= PREFIX_FWAIT;
8748 codep++;
8749 /* This ensures that the previous REX prefixes are noticed
8750 as unused prefixes, as in the return case below. */
8751 rex_used = rex;
8752 return 1;
8753 }
8754 prefixes = PREFIX_FWAIT;
8755 break;
8756 default:
8757 return 1;
8758 }
8759 /* Rex is ignored when followed by another prefix. */
8760 if (rex)
8761 {
8762 rex_used = rex;
8763 return 1;
8764 }
8765 if (*codep != FWAIT_OPCODE)
8766 all_prefixes[i++] = *codep;
8767 rex = newrex;
8768 codep++;
8769 length++;
8770 }
8771 return 0;
8772 }
8773
8774 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
8775 prefix byte. */
8776
8777 static const char *
8778 prefix_name (int pref, int sizeflag)
8779 {
8780 static const char *rexes [16] =
8781 {
8782 "rex", /* 0x40 */
8783 "rex.B", /* 0x41 */
8784 "rex.X", /* 0x42 */
8785 "rex.XB", /* 0x43 */
8786 "rex.R", /* 0x44 */
8787 "rex.RB", /* 0x45 */
8788 "rex.RX", /* 0x46 */
8789 "rex.RXB", /* 0x47 */
8790 "rex.W", /* 0x48 */
8791 "rex.WB", /* 0x49 */
8792 "rex.WX", /* 0x4a */
8793 "rex.WXB", /* 0x4b */
8794 "rex.WR", /* 0x4c */
8795 "rex.WRB", /* 0x4d */
8796 "rex.WRX", /* 0x4e */
8797 "rex.WRXB", /* 0x4f */
8798 };
8799
8800 switch (pref)
8801 {
8802 /* REX prefixes family. */
8803 case 0x40:
8804 case 0x41:
8805 case 0x42:
8806 case 0x43:
8807 case 0x44:
8808 case 0x45:
8809 case 0x46:
8810 case 0x47:
8811 case 0x48:
8812 case 0x49:
8813 case 0x4a:
8814 case 0x4b:
8815 case 0x4c:
8816 case 0x4d:
8817 case 0x4e:
8818 case 0x4f:
8819 return rexes [pref - 0x40];
8820 case 0xf3:
8821 return "repz";
8822 case 0xf2:
8823 return "repnz";
8824 case 0xf0:
8825 return "lock";
8826 case 0x2e:
8827 return "cs";
8828 case 0x36:
8829 return "ss";
8830 case 0x3e:
8831 return "ds";
8832 case 0x26:
8833 return "es";
8834 case 0x64:
8835 return "fs";
8836 case 0x65:
8837 return "gs";
8838 case 0x66:
8839 return (sizeflag & DFLAG) ? "data16" : "data32";
8840 case 0x67:
8841 if (address_mode == mode_64bit)
8842 return (sizeflag & AFLAG) ? "addr32" : "addr64";
8843 else
8844 return (sizeflag & AFLAG) ? "addr16" : "addr32";
8845 case FWAIT_OPCODE:
8846 return "fwait";
8847 case REP_PREFIX:
8848 return "rep";
8849 case XACQUIRE_PREFIX:
8850 return "xacquire";
8851 case XRELEASE_PREFIX:
8852 return "xrelease";
8853 case BND_PREFIX:
8854 return "bnd";
8855 case NOTRACK_PREFIX:
8856 return "notrack";
8857 default:
8858 return NULL;
8859 }
8860 }
8861
8862 static char op_out[MAX_OPERANDS][100];
8863 static int op_ad, op_index[MAX_OPERANDS];
8864 static int two_source_ops;
8865 static bfd_vma op_address[MAX_OPERANDS];
8866 static bfd_vma op_riprel[MAX_OPERANDS];
8867 static bfd_vma start_pc;
8868
8869 /*
8870 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
8871 * (see topic "Redundant prefixes" in the "Differences from 8086"
8872 * section of the "Virtual 8086 Mode" chapter.)
8873 * 'pc' should be the address of this instruction, it will
8874 * be used to print the target address if this is a relative jump or call
8875 * The function returns the length of this instruction in bytes.
8876 */
8877
8878 static char intel_syntax;
8879 static char intel_mnemonic = !SYSV386_COMPAT;
8880 static char open_char;
8881 static char close_char;
8882 static char separator_char;
8883 static char scale_char;
8884
8885 enum x86_64_isa
8886 {
8887 amd64 = 1,
8888 intel64
8889 };
8890
8891 static enum x86_64_isa isa64;
8892
8893 /* Here for backwards compatibility. When gdb stops using
8894 print_insn_i386_att and print_insn_i386_intel these functions can
8895 disappear, and print_insn_i386 be merged into print_insn. */
8896 int
8897 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
8898 {
8899 intel_syntax = 0;
8900
8901 return print_insn (pc, info);
8902 }
8903
8904 int
8905 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
8906 {
8907 intel_syntax = 1;
8908
8909 return print_insn (pc, info);
8910 }
8911
8912 int
8913 print_insn_i386 (bfd_vma pc, disassemble_info *info)
8914 {
8915 intel_syntax = -1;
8916
8917 return print_insn (pc, info);
8918 }
8919
8920 void
8921 print_i386_disassembler_options (FILE *stream)
8922 {
8923 fprintf (stream, _("\n\
8924 The following i386/x86-64 specific disassembler options are supported for use\n\
8925 with the -M switch (multiple options should be separated by commas):\n"));
8926
8927 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
8928 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
8929 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
8930 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
8931 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
8932 fprintf (stream, _(" att-mnemonic\n"
8933 " Display instruction in AT&T mnemonic\n"));
8934 fprintf (stream, _(" intel-mnemonic\n"
8935 " Display instruction in Intel mnemonic\n"));
8936 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
8937 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
8938 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
8939 fprintf (stream, _(" data32 Assume 32bit data size\n"));
8940 fprintf (stream, _(" data16 Assume 16bit data size\n"));
8941 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
8942 fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n"));
8943 fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n"));
8944 }
8945
8946 /* Bad opcode. */
8947 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
8948
8949 /* Get a pointer to struct dis386 with a valid name. */
8950
8951 static const struct dis386 *
8952 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
8953 {
8954 int vindex, vex_table_index;
8955
8956 if (dp->name != NULL)
8957 return dp;
8958
8959 switch (dp->op[0].bytemode)
8960 {
8961 case USE_REG_TABLE:
8962 dp = &reg_table[dp->op[1].bytemode][modrm.reg];
8963 break;
8964
8965 case USE_MOD_TABLE:
8966 vindex = modrm.mod == 0x3 ? 1 : 0;
8967 dp = &mod_table[dp->op[1].bytemode][vindex];
8968 break;
8969
8970 case USE_RM_TABLE:
8971 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
8972 break;
8973
8974 case USE_PREFIX_TABLE:
8975 if (need_vex)
8976 {
8977 /* The prefix in VEX is implicit. */
8978 switch (vex.prefix)
8979 {
8980 case 0:
8981 vindex = 0;
8982 break;
8983 case REPE_PREFIX_OPCODE:
8984 vindex = 1;
8985 break;
8986 case DATA_PREFIX_OPCODE:
8987 vindex = 2;
8988 break;
8989 case REPNE_PREFIX_OPCODE:
8990 vindex = 3;
8991 break;
8992 default:
8993 abort ();
8994 break;
8995 }
8996 }
8997 else
8998 {
8999 int last_prefix = -1;
9000 int prefix = 0;
9001 vindex = 0;
9002 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
9003 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
9004 last one wins. */
9005 if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9006 {
9007 if (last_repz_prefix > last_repnz_prefix)
9008 {
9009 vindex = 1;
9010 prefix = PREFIX_REPZ;
9011 last_prefix = last_repz_prefix;
9012 }
9013 else
9014 {
9015 vindex = 3;
9016 prefix = PREFIX_REPNZ;
9017 last_prefix = last_repnz_prefix;
9018 }
9019
9020 /* Check if prefix should be ignored. */
9021 if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
9022 & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
9023 & prefix) != 0
9024 && !prefix_table[dp->op[1].bytemode][vindex].name)
9025 vindex = 0;
9026 }
9027
9028 if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
9029 {
9030 vindex = 2;
9031 prefix = PREFIX_DATA;
9032 last_prefix = last_data_prefix;
9033 }
9034
9035 if (vindex != 0)
9036 {
9037 used_prefixes |= prefix;
9038 all_prefixes[last_prefix] = 0;
9039 }
9040 }
9041 dp = &prefix_table[dp->op[1].bytemode][vindex];
9042 break;
9043
9044 case USE_X86_64_TABLE:
9045 vindex = address_mode == mode_64bit ? 1 : 0;
9046 dp = &x86_64_table[dp->op[1].bytemode][vindex];
9047 break;
9048
9049 case USE_3BYTE_TABLE:
9050 FETCH_DATA (info, codep + 2);
9051 vindex = *codep++;
9052 dp = &three_byte_table[dp->op[1].bytemode][vindex];
9053 end_codep = codep;
9054 modrm.mod = (*codep >> 6) & 3;
9055 modrm.reg = (*codep >> 3) & 7;
9056 modrm.rm = *codep & 7;
9057 break;
9058
9059 case USE_VEX_LEN_TABLE:
9060 if (!need_vex)
9061 abort ();
9062
9063 switch (vex.length)
9064 {
9065 case 128:
9066 vindex = 0;
9067 break;
9068 case 256:
9069 vindex = 1;
9070 break;
9071 default:
9072 abort ();
9073 break;
9074 }
9075
9076 dp = &vex_len_table[dp->op[1].bytemode][vindex];
9077 break;
9078
9079 case USE_EVEX_LEN_TABLE:
9080 if (!vex.evex)
9081 abort ();
9082
9083 switch (vex.length)
9084 {
9085 case 128:
9086 vindex = 0;
9087 break;
9088 case 256:
9089 vindex = 1;
9090 break;
9091 case 512:
9092 vindex = 2;
9093 break;
9094 default:
9095 abort ();
9096 break;
9097 }
9098
9099 dp = &evex_len_table[dp->op[1].bytemode][vindex];
9100 break;
9101
9102 case USE_XOP_8F_TABLE:
9103 FETCH_DATA (info, codep + 3);
9104 rex = ~(*codep >> 5) & 0x7;
9105
9106 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
9107 switch ((*codep & 0x1f))
9108 {
9109 default:
9110 dp = &bad_opcode;
9111 return dp;
9112 case 0x8:
9113 vex_table_index = XOP_08;
9114 break;
9115 case 0x9:
9116 vex_table_index = XOP_09;
9117 break;
9118 case 0xa:
9119 vex_table_index = XOP_0A;
9120 break;
9121 }
9122 codep++;
9123 vex.w = *codep & 0x80;
9124 if (vex.w && address_mode == mode_64bit)
9125 rex |= REX_W;
9126
9127 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9128 if (address_mode != mode_64bit)
9129 {
9130 /* In 16/32-bit mode REX_B is silently ignored. */
9131 rex &= ~REX_B;
9132 }
9133
9134 vex.length = (*codep & 0x4) ? 256 : 128;
9135 switch ((*codep & 0x3))
9136 {
9137 case 0:
9138 break;
9139 case 1:
9140 vex.prefix = DATA_PREFIX_OPCODE;
9141 break;
9142 case 2:
9143 vex.prefix = REPE_PREFIX_OPCODE;
9144 break;
9145 case 3:
9146 vex.prefix = REPNE_PREFIX_OPCODE;
9147 break;
9148 }
9149 need_vex = 1;
9150 codep++;
9151 vindex = *codep++;
9152 dp = &xop_table[vex_table_index][vindex];
9153
9154 end_codep = codep;
9155 FETCH_DATA (info, codep + 1);
9156 modrm.mod = (*codep >> 6) & 3;
9157 modrm.reg = (*codep >> 3) & 7;
9158 modrm.rm = *codep & 7;
9159
9160 /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9161 having to decode the bits for every otherwise valid encoding. */
9162 if (vex.prefix)
9163 return &bad_opcode;
9164 break;
9165
9166 case USE_VEX_C4_TABLE:
9167 /* VEX prefix. */
9168 FETCH_DATA (info, codep + 3);
9169 rex = ~(*codep >> 5) & 0x7;
9170 switch ((*codep & 0x1f))
9171 {
9172 default:
9173 dp = &bad_opcode;
9174 return dp;
9175 case 0x1:
9176 vex_table_index = VEX_0F;
9177 break;
9178 case 0x2:
9179 vex_table_index = VEX_0F38;
9180 break;
9181 case 0x3:
9182 vex_table_index = VEX_0F3A;
9183 break;
9184 }
9185 codep++;
9186 vex.w = *codep & 0x80;
9187 if (address_mode == mode_64bit)
9188 {
9189 if (vex.w)
9190 rex |= REX_W;
9191 }
9192 else
9193 {
9194 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9195 is ignored, other REX bits are 0 and the highest bit in
9196 VEX.vvvv is also ignored (but we mustn't clear it here). */
9197 rex = 0;
9198 }
9199 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9200 vex.length = (*codep & 0x4) ? 256 : 128;
9201 switch ((*codep & 0x3))
9202 {
9203 case 0:
9204 break;
9205 case 1:
9206 vex.prefix = DATA_PREFIX_OPCODE;
9207 break;
9208 case 2:
9209 vex.prefix = REPE_PREFIX_OPCODE;
9210 break;
9211 case 3:
9212 vex.prefix = REPNE_PREFIX_OPCODE;
9213 break;
9214 }
9215 need_vex = 1;
9216 codep++;
9217 vindex = *codep++;
9218 dp = &vex_table[vex_table_index][vindex];
9219 end_codep = codep;
9220 /* There is no MODRM byte for VEX0F 77. */
9221 if (vex_table_index != VEX_0F || vindex != 0x77)
9222 {
9223 FETCH_DATA (info, codep + 1);
9224 modrm.mod = (*codep >> 6) & 3;
9225 modrm.reg = (*codep >> 3) & 7;
9226 modrm.rm = *codep & 7;
9227 }
9228 break;
9229
9230 case USE_VEX_C5_TABLE:
9231 /* VEX prefix. */
9232 FETCH_DATA (info, codep + 2);
9233 rex = (*codep & 0x80) ? 0 : REX_R;
9234
9235 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9236 VEX.vvvv is 1. */
9237 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9238 vex.length = (*codep & 0x4) ? 256 : 128;
9239 switch ((*codep & 0x3))
9240 {
9241 case 0:
9242 break;
9243 case 1:
9244 vex.prefix = DATA_PREFIX_OPCODE;
9245 break;
9246 case 2:
9247 vex.prefix = REPE_PREFIX_OPCODE;
9248 break;
9249 case 3:
9250 vex.prefix = REPNE_PREFIX_OPCODE;
9251 break;
9252 }
9253 need_vex = 1;
9254 codep++;
9255 vindex = *codep++;
9256 dp = &vex_table[dp->op[1].bytemode][vindex];
9257 end_codep = codep;
9258 /* There is no MODRM byte for VEX 77. */
9259 if (vindex != 0x77)
9260 {
9261 FETCH_DATA (info, codep + 1);
9262 modrm.mod = (*codep >> 6) & 3;
9263 modrm.reg = (*codep >> 3) & 7;
9264 modrm.rm = *codep & 7;
9265 }
9266 break;
9267
9268 case USE_VEX_W_TABLE:
9269 if (!need_vex)
9270 abort ();
9271
9272 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
9273 break;
9274
9275 case USE_EVEX_TABLE:
9276 two_source_ops = 0;
9277 /* EVEX prefix. */
9278 vex.evex = 1;
9279 FETCH_DATA (info, codep + 4);
9280 /* The first byte after 0x62. */
9281 rex = ~(*codep >> 5) & 0x7;
9282 vex.r = *codep & 0x10;
9283 switch ((*codep & 0xf))
9284 {
9285 default:
9286 return &bad_opcode;
9287 case 0x1:
9288 vex_table_index = EVEX_0F;
9289 break;
9290 case 0x2:
9291 vex_table_index = EVEX_0F38;
9292 break;
9293 case 0x3:
9294 vex_table_index = EVEX_0F3A;
9295 break;
9296 }
9297
9298 /* The second byte after 0x62. */
9299 codep++;
9300 vex.w = *codep & 0x80;
9301 if (vex.w && address_mode == mode_64bit)
9302 rex |= REX_W;
9303
9304 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9305
9306 /* The U bit. */
9307 if (!(*codep & 0x4))
9308 return &bad_opcode;
9309
9310 switch ((*codep & 0x3))
9311 {
9312 case 0:
9313 break;
9314 case 1:
9315 vex.prefix = DATA_PREFIX_OPCODE;
9316 break;
9317 case 2:
9318 vex.prefix = REPE_PREFIX_OPCODE;
9319 break;
9320 case 3:
9321 vex.prefix = REPNE_PREFIX_OPCODE;
9322 break;
9323 }
9324
9325 /* The third byte after 0x62. */
9326 codep++;
9327
9328 /* Remember the static rounding bits. */
9329 vex.ll = (*codep >> 5) & 3;
9330 vex.b = (*codep & 0x10) != 0;
9331
9332 vex.v = *codep & 0x8;
9333 vex.mask_register_specifier = *codep & 0x7;
9334 vex.zeroing = *codep & 0x80;
9335
9336 if (address_mode != mode_64bit)
9337 {
9338 /* In 16/32-bit mode silently ignore following bits. */
9339 rex &= ~REX_B;
9340 vex.r = 1;
9341 vex.v = 1;
9342 }
9343
9344 need_vex = 1;
9345 codep++;
9346 vindex = *codep++;
9347 dp = &evex_table[vex_table_index][vindex];
9348 end_codep = codep;
9349 FETCH_DATA (info, codep + 1);
9350 modrm.mod = (*codep >> 6) & 3;
9351 modrm.reg = (*codep >> 3) & 7;
9352 modrm.rm = *codep & 7;
9353
9354 /* Set vector length. */
9355 if (modrm.mod == 3 && vex.b)
9356 vex.length = 512;
9357 else
9358 {
9359 switch (vex.ll)
9360 {
9361 case 0x0:
9362 vex.length = 128;
9363 break;
9364 case 0x1:
9365 vex.length = 256;
9366 break;
9367 case 0x2:
9368 vex.length = 512;
9369 break;
9370 default:
9371 return &bad_opcode;
9372 }
9373 }
9374 break;
9375
9376 case 0:
9377 dp = &bad_opcode;
9378 break;
9379
9380 default:
9381 abort ();
9382 }
9383
9384 if (dp->name != NULL)
9385 return dp;
9386 else
9387 return get_valid_dis386 (dp, info);
9388 }
9389
9390 static void
9391 get_sib (disassemble_info *info, int sizeflag)
9392 {
9393 /* If modrm.mod == 3, operand must be register. */
9394 if (need_modrm
9395 && ((sizeflag & AFLAG) || address_mode == mode_64bit)
9396 && modrm.mod != 3
9397 && modrm.rm == 4)
9398 {
9399 FETCH_DATA (info, codep + 2);
9400 sib.index = (codep [1] >> 3) & 7;
9401 sib.scale = (codep [1] >> 6) & 3;
9402 sib.base = codep [1] & 7;
9403 }
9404 }
9405
9406 static int
9407 print_insn (bfd_vma pc, disassemble_info *info)
9408 {
9409 const struct dis386 *dp;
9410 int i;
9411 char *op_txt[MAX_OPERANDS];
9412 int needcomma;
9413 int sizeflag, orig_sizeflag;
9414 const char *p;
9415 struct dis_private priv;
9416 int prefix_length;
9417
9418 priv.orig_sizeflag = AFLAG | DFLAG;
9419 if ((info->mach & bfd_mach_i386_i386) != 0)
9420 address_mode = mode_32bit;
9421 else if (info->mach == bfd_mach_i386_i8086)
9422 {
9423 address_mode = mode_16bit;
9424 priv.orig_sizeflag = 0;
9425 }
9426 else
9427 address_mode = mode_64bit;
9428
9429 if (intel_syntax == (char) -1)
9430 intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
9431
9432 for (p = info->disassembler_options; p != NULL; )
9433 {
9434 if (CONST_STRNEQ (p, "amd64"))
9435 isa64 = amd64;
9436 else if (CONST_STRNEQ (p, "intel64"))
9437 isa64 = intel64;
9438 else if (CONST_STRNEQ (p, "x86-64"))
9439 {
9440 address_mode = mode_64bit;
9441 priv.orig_sizeflag |= AFLAG | DFLAG;
9442 }
9443 else if (CONST_STRNEQ (p, "i386"))
9444 {
9445 address_mode = mode_32bit;
9446 priv.orig_sizeflag |= AFLAG | DFLAG;
9447 }
9448 else if (CONST_STRNEQ (p, "i8086"))
9449 {
9450 address_mode = mode_16bit;
9451 priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9452 }
9453 else if (CONST_STRNEQ (p, "intel"))
9454 {
9455 intel_syntax = 1;
9456 if (CONST_STRNEQ (p + 5, "-mnemonic"))
9457 intel_mnemonic = 1;
9458 }
9459 else if (CONST_STRNEQ (p, "att"))
9460 {
9461 intel_syntax = 0;
9462 if (CONST_STRNEQ (p + 3, "-mnemonic"))
9463 intel_mnemonic = 0;
9464 }
9465 else if (CONST_STRNEQ (p, "addr"))
9466 {
9467 if (address_mode == mode_64bit)
9468 {
9469 if (p[4] == '3' && p[5] == '2')
9470 priv.orig_sizeflag &= ~AFLAG;
9471 else if (p[4] == '6' && p[5] == '4')
9472 priv.orig_sizeflag |= AFLAG;
9473 }
9474 else
9475 {
9476 if (p[4] == '1' && p[5] == '6')
9477 priv.orig_sizeflag &= ~AFLAG;
9478 else if (p[4] == '3' && p[5] == '2')
9479 priv.orig_sizeflag |= AFLAG;
9480 }
9481 }
9482 else if (CONST_STRNEQ (p, "data"))
9483 {
9484 if (p[4] == '1' && p[5] == '6')
9485 priv.orig_sizeflag &= ~DFLAG;
9486 else if (p[4] == '3' && p[5] == '2')
9487 priv.orig_sizeflag |= DFLAG;
9488 }
9489 else if (CONST_STRNEQ (p, "suffix"))
9490 priv.orig_sizeflag |= SUFFIX_ALWAYS;
9491
9492 p = strchr (p, ',');
9493 if (p != NULL)
9494 p++;
9495 }
9496
9497 if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9498 {
9499 (*info->fprintf_func) (info->stream,
9500 _("64-bit address is disabled"));
9501 return -1;
9502 }
9503
9504 if (intel_syntax)
9505 {
9506 names64 = intel_names64;
9507 names32 = intel_names32;
9508 names16 = intel_names16;
9509 names8 = intel_names8;
9510 names8rex = intel_names8rex;
9511 names_seg = intel_names_seg;
9512 names_mm = intel_names_mm;
9513 names_bnd = intel_names_bnd;
9514 names_xmm = intel_names_xmm;
9515 names_ymm = intel_names_ymm;
9516 names_zmm = intel_names_zmm;
9517 names_tmm = intel_names_tmm;
9518 index64 = intel_index64;
9519 index32 = intel_index32;
9520 names_mask = intel_names_mask;
9521 index16 = intel_index16;
9522 open_char = '[';
9523 close_char = ']';
9524 separator_char = '+';
9525 scale_char = '*';
9526 }
9527 else
9528 {
9529 names64 = att_names64;
9530 names32 = att_names32;
9531 names16 = att_names16;
9532 names8 = att_names8;
9533 names8rex = att_names8rex;
9534 names_seg = att_names_seg;
9535 names_mm = att_names_mm;
9536 names_bnd = att_names_bnd;
9537 names_xmm = att_names_xmm;
9538 names_ymm = att_names_ymm;
9539 names_zmm = att_names_zmm;
9540 names_tmm = att_names_tmm;
9541 index64 = att_index64;
9542 index32 = att_index32;
9543 names_mask = att_names_mask;
9544 index16 = att_index16;
9545 open_char = '(';
9546 close_char = ')';
9547 separator_char = ',';
9548 scale_char = ',';
9549 }
9550
9551 /* The output looks better if we put 7 bytes on a line, since that
9552 puts most long word instructions on a single line. Use 8 bytes
9553 for Intel L1OM. */
9554 if ((info->mach & bfd_mach_l1om) != 0)
9555 info->bytes_per_line = 8;
9556 else
9557 info->bytes_per_line = 7;
9558
9559 info->private_data = &priv;
9560 priv.max_fetched = priv.the_buffer;
9561 priv.insn_start = pc;
9562
9563 obuf[0] = 0;
9564 for (i = 0; i < MAX_OPERANDS; ++i)
9565 {
9566 op_out[i][0] = 0;
9567 op_index[i] = -1;
9568 }
9569
9570 the_info = info;
9571 start_pc = pc;
9572 start_codep = priv.the_buffer;
9573 codep = priv.the_buffer;
9574
9575 if (OPCODES_SIGSETJMP (priv.bailout) != 0)
9576 {
9577 const char *name;
9578
9579 /* Getting here means we tried for data but didn't get it. That
9580 means we have an incomplete instruction of some sort. Just
9581 print the first byte as a prefix or a .byte pseudo-op. */
9582 if (codep > priv.the_buffer)
9583 {
9584 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
9585 if (name != NULL)
9586 (*info->fprintf_func) (info->stream, "%s", name);
9587 else
9588 {
9589 /* Just print the first byte as a .byte instruction. */
9590 (*info->fprintf_func) (info->stream, ".byte 0x%x",
9591 (unsigned int) priv.the_buffer[0]);
9592 }
9593
9594 return 1;
9595 }
9596
9597 return -1;
9598 }
9599
9600 obufp = obuf;
9601 sizeflag = priv.orig_sizeflag;
9602
9603 if (!ckprefix () || rex_used)
9604 {
9605 /* Too many prefixes or unused REX prefixes. */
9606 for (i = 0;
9607 i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
9608 i++)
9609 (*info->fprintf_func) (info->stream, "%s%s",
9610 i == 0 ? "" : " ",
9611 prefix_name (all_prefixes[i], sizeflag));
9612 return i;
9613 }
9614
9615 insn_codep = codep;
9616
9617 FETCH_DATA (info, codep + 1);
9618 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
9619
9620 if (((prefixes & PREFIX_FWAIT)
9621 && ((*codep < 0xd8) || (*codep > 0xdf))))
9622 {
9623 /* Handle prefixes before fwait. */
9624 for (i = 0; i < fwait_prefix && all_prefixes[i];
9625 i++)
9626 (*info->fprintf_func) (info->stream, "%s ",
9627 prefix_name (all_prefixes[i], sizeflag));
9628 (*info->fprintf_func) (info->stream, "fwait");
9629 return i + 1;
9630 }
9631
9632 if (*codep == 0x0f)
9633 {
9634 unsigned char threebyte;
9635
9636 codep++;
9637 FETCH_DATA (info, codep + 1);
9638 threebyte = *codep;
9639 dp = &dis386_twobyte[threebyte];
9640 need_modrm = twobyte_has_modrm[threebyte];
9641 codep++;
9642 }
9643 else
9644 {
9645 dp = &dis386[*codep];
9646 need_modrm = onebyte_has_modrm[*codep];
9647 codep++;
9648 }
9649
9650 /* Save sizeflag for printing the extra prefixes later before updating
9651 it for mnemonic and operand processing. The prefix names depend
9652 only on the address mode. */
9653 orig_sizeflag = sizeflag;
9654 if (prefixes & PREFIX_ADDR)
9655 sizeflag ^= AFLAG;
9656 if ((prefixes & PREFIX_DATA))
9657 sizeflag ^= DFLAG;
9658
9659 end_codep = codep;
9660 if (need_modrm)
9661 {
9662 FETCH_DATA (info, codep + 1);
9663 modrm.mod = (*codep >> 6) & 3;
9664 modrm.reg = (*codep >> 3) & 7;
9665 modrm.rm = *codep & 7;
9666 }
9667 else
9668 memset (&modrm, 0, sizeof (modrm));
9669
9670 need_vex = 0;
9671 memset (&vex, 0, sizeof (vex));
9672
9673 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9674 {
9675 get_sib (info, sizeflag);
9676 dofloat (sizeflag);
9677 }
9678 else
9679 {
9680 dp = get_valid_dis386 (dp, info);
9681 if (dp != NULL && putop (dp->name, sizeflag) == 0)
9682 {
9683 get_sib (info, sizeflag);
9684 for (i = 0; i < MAX_OPERANDS; ++i)
9685 {
9686 obufp = op_out[i];
9687 op_ad = MAX_OPERANDS - 1 - i;
9688 if (dp->op[i].rtn)
9689 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
9690 /* For EVEX instruction after the last operand masking
9691 should be printed. */
9692 if (i == 0 && vex.evex)
9693 {
9694 /* Don't print {%k0}. */
9695 if (vex.mask_register_specifier)
9696 {
9697 oappend ("{");
9698 oappend (names_mask[vex.mask_register_specifier]);
9699 oappend ("}");
9700 }
9701 if (vex.zeroing)
9702 oappend ("{z}");
9703 }
9704 }
9705 }
9706 }
9707
9708 /* Clear instruction information. */
9709 if (the_info)
9710 {
9711 the_info->insn_info_valid = 0;
9712 the_info->branch_delay_insns = 0;
9713 the_info->data_size = 0;
9714 the_info->insn_type = dis_noninsn;
9715 the_info->target = 0;
9716 the_info->target2 = 0;
9717 }
9718
9719 /* Reset jump operation indicator. */
9720 op_is_jump = FALSE;
9721
9722 {
9723 int jump_detection = 0;
9724
9725 /* Extract flags. */
9726 for (i = 0; i < MAX_OPERANDS; ++i)
9727 {
9728 if ((dp->op[i].rtn == OP_J)
9729 || (dp->op[i].rtn == OP_indirE))
9730 jump_detection |= 1;
9731 else if ((dp->op[i].rtn == BND_Fixup)
9732 || (!dp->op[i].rtn && !dp->op[i].bytemode))
9733 jump_detection |= 2;
9734 else if ((dp->op[i].bytemode == cond_jump_mode)
9735 || (dp->op[i].bytemode == loop_jcxz_mode))
9736 jump_detection |= 4;
9737 }
9738
9739 /* Determine if this is a jump or branch. */
9740 if ((jump_detection & 0x3) == 0x3)
9741 {
9742 op_is_jump = TRUE;
9743 if (jump_detection & 0x4)
9744 the_info->insn_type = dis_condbranch;
9745 else
9746 the_info->insn_type =
9747 (dp->name && !strncmp(dp->name, "call", 4))
9748 ? dis_jsr : dis_branch;
9749 }
9750 }
9751
9752 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
9753 are all 0s in inverted form. */
9754 if (need_vex && vex.register_specifier != 0)
9755 {
9756 (*info->fprintf_func) (info->stream, "(bad)");
9757 return end_codep - priv.the_buffer;
9758 }
9759
9760 switch (dp->prefix_requirement)
9761 {
9762 case PREFIX_DATA:
9763 /* If only the data prefix is marked as mandatory, its absence renders
9764 the encoding invalid. Most other PREFIX_OPCODE rules still apply. */
9765 if (need_vex ? !vex.prefix : !(prefixes & PREFIX_DATA))
9766 {
9767 (*info->fprintf_func) (info->stream, "(bad)");
9768 return end_codep - priv.the_buffer;
9769 }
9770 used_prefixes |= PREFIX_DATA;
9771 /* Fall through. */
9772 case PREFIX_OPCODE:
9773 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
9774 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
9775 used by putop and MMX/SSE operand and may be overridden by the
9776 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
9777 separately. */
9778 if (((need_vex
9779 ? vex.prefix == REPE_PREFIX_OPCODE
9780 || vex.prefix == REPNE_PREFIX_OPCODE
9781 : (prefixes
9782 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9783 && (used_prefixes
9784 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
9785 || (((need_vex
9786 ? vex.prefix == DATA_PREFIX_OPCODE
9787 : ((prefixes
9788 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
9789 == PREFIX_DATA))
9790 && (used_prefixes & PREFIX_DATA) == 0))
9791 || (vex.evex && dp->prefix_requirement != PREFIX_DATA
9792 && !vex.w != !(used_prefixes & PREFIX_DATA)))
9793 {
9794 (*info->fprintf_func) (info->stream, "(bad)");
9795 return end_codep - priv.the_buffer;
9796 }
9797 break;
9798
9799 case PREFIX_IGNORED:
9800 /* Zap data size and rep prefixes from used_prefixes and reinstate their
9801 origins in all_prefixes. */
9802 used_prefixes &= ~PREFIX_OPCODE;
9803 if (last_data_prefix >= 0)
9804 all_prefixes[last_repz_prefix] = 0x66;
9805 if (last_repz_prefix >= 0)
9806 all_prefixes[last_repz_prefix] = 0xf3;
9807 if (last_repnz_prefix >= 0)
9808 all_prefixes[last_repnz_prefix] = 0xf2;
9809 break;
9810 }
9811
9812 /* Check if the REX prefix is used. */
9813 if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
9814 all_prefixes[last_rex_prefix] = 0;
9815
9816 /* Check if the SEG prefix is used. */
9817 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
9818 | PREFIX_FS | PREFIX_GS)) != 0
9819 && (used_prefixes & active_seg_prefix) != 0)
9820 all_prefixes[last_seg_prefix] = 0;
9821
9822 /* Check if the ADDR prefix is used. */
9823 if ((prefixes & PREFIX_ADDR) != 0
9824 && (used_prefixes & PREFIX_ADDR) != 0)
9825 all_prefixes[last_addr_prefix] = 0;
9826
9827 /* Check if the DATA prefix is used. */
9828 if ((prefixes & PREFIX_DATA) != 0
9829 && (used_prefixes & PREFIX_DATA) != 0
9830 && !need_vex)
9831 all_prefixes[last_data_prefix] = 0;
9832
9833 /* Print the extra prefixes. */
9834 prefix_length = 0;
9835 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
9836 if (all_prefixes[i])
9837 {
9838 const char *name;
9839 name = prefix_name (all_prefixes[i], orig_sizeflag);
9840 if (name == NULL)
9841 abort ();
9842 prefix_length += strlen (name) + 1;
9843 (*info->fprintf_func) (info->stream, "%s ", name);
9844 }
9845
9846 /* Check maximum code length. */
9847 if ((codep - start_codep) > MAX_CODE_LENGTH)
9848 {
9849 (*info->fprintf_func) (info->stream, "(bad)");
9850 return MAX_CODE_LENGTH;
9851 }
9852
9853 obufp = mnemonicendp;
9854 for (i = strlen (obuf) + prefix_length; i < 6; i++)
9855 oappend (" ");
9856 oappend (" ");
9857 (*info->fprintf_func) (info->stream, "%s", obuf);
9858
9859 /* The enter and bound instructions are printed with operands in the same
9860 order as the intel book; everything else is printed in reverse order. */
9861 if (intel_syntax || two_source_ops)
9862 {
9863 bfd_vma riprel;
9864
9865 for (i = 0; i < MAX_OPERANDS; ++i)
9866 op_txt[i] = op_out[i];
9867
9868 if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
9869 && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
9870 {
9871 op_txt[2] = op_out[3];
9872 op_txt[3] = op_out[2];
9873 }
9874
9875 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
9876 {
9877 op_ad = op_index[i];
9878 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
9879 op_index[MAX_OPERANDS - 1 - i] = op_ad;
9880 riprel = op_riprel[i];
9881 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
9882 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
9883 }
9884 }
9885 else
9886 {
9887 for (i = 0; i < MAX_OPERANDS; ++i)
9888 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
9889 }
9890
9891 needcomma = 0;
9892 for (i = 0; i < MAX_OPERANDS; ++i)
9893 if (*op_txt[i])
9894 {
9895 if (needcomma)
9896 (*info->fprintf_func) (info->stream, ",");
9897 if (op_index[i] != -1 && !op_riprel[i])
9898 {
9899 bfd_vma target = (bfd_vma) op_address[op_index[i]];
9900
9901 if (the_info && op_is_jump)
9902 {
9903 the_info->insn_info_valid = 1;
9904 the_info->branch_delay_insns = 0;
9905 the_info->data_size = 0;
9906 the_info->target = target;
9907 the_info->target2 = 0;
9908 }
9909 (*info->print_address_func) (target, info);
9910 }
9911 else
9912 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
9913 needcomma = 1;
9914 }
9915
9916 for (i = 0; i < MAX_OPERANDS; i++)
9917 if (op_index[i] != -1 && op_riprel[i])
9918 {
9919 (*info->fprintf_func) (info->stream, " # ");
9920 (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
9921 + op_address[op_index[i]]), info);
9922 break;
9923 }
9924 return codep - priv.the_buffer;
9925 }
9926
9927 static const char *float_mem[] = {
9928 /* d8 */
9929 "fadd{s|}",
9930 "fmul{s|}",
9931 "fcom{s|}",
9932 "fcomp{s|}",
9933 "fsub{s|}",
9934 "fsubr{s|}",
9935 "fdiv{s|}",
9936 "fdivr{s|}",
9937 /* d9 */
9938 "fld{s|}",
9939 "(bad)",
9940 "fst{s|}",
9941 "fstp{s|}",
9942 "fldenv{C|C}",
9943 "fldcw",
9944 "fNstenv{C|C}",
9945 "fNstcw",
9946 /* da */
9947 "fiadd{l|}",
9948 "fimul{l|}",
9949 "ficom{l|}",
9950 "ficomp{l|}",
9951 "fisub{l|}",
9952 "fisubr{l|}",
9953 "fidiv{l|}",
9954 "fidivr{l|}",
9955 /* db */
9956 "fild{l|}",
9957 "fisttp{l|}",
9958 "fist{l|}",
9959 "fistp{l|}",
9960 "(bad)",
9961 "fld{t|}",
9962 "(bad)",
9963 "fstp{t|}",
9964 /* dc */
9965 "fadd{l|}",
9966 "fmul{l|}",
9967 "fcom{l|}",
9968 "fcomp{l|}",
9969 "fsub{l|}",
9970 "fsubr{l|}",
9971 "fdiv{l|}",
9972 "fdivr{l|}",
9973 /* dd */
9974 "fld{l|}",
9975 "fisttp{ll|}",
9976 "fst{l||}",
9977 "fstp{l|}",
9978 "frstor{C|C}",
9979 "(bad)",
9980 "fNsave{C|C}",
9981 "fNstsw",
9982 /* de */
9983 "fiadd{s|}",
9984 "fimul{s|}",
9985 "ficom{s|}",
9986 "ficomp{s|}",
9987 "fisub{s|}",
9988 "fisubr{s|}",
9989 "fidiv{s|}",
9990 "fidivr{s|}",
9991 /* df */
9992 "fild{s|}",
9993 "fisttp{s|}",
9994 "fist{s|}",
9995 "fistp{s|}",
9996 "fbld",
9997 "fild{ll|}",
9998 "fbstp",
9999 "fistp{ll|}",
10000 };
10001
10002 static const unsigned char float_mem_mode[] = {
10003 /* d8 */
10004 d_mode,
10005 d_mode,
10006 d_mode,
10007 d_mode,
10008 d_mode,
10009 d_mode,
10010 d_mode,
10011 d_mode,
10012 /* d9 */
10013 d_mode,
10014 0,
10015 d_mode,
10016 d_mode,
10017 0,
10018 w_mode,
10019 0,
10020 w_mode,
10021 /* da */
10022 d_mode,
10023 d_mode,
10024 d_mode,
10025 d_mode,
10026 d_mode,
10027 d_mode,
10028 d_mode,
10029 d_mode,
10030 /* db */
10031 d_mode,
10032 d_mode,
10033 d_mode,
10034 d_mode,
10035 0,
10036 t_mode,
10037 0,
10038 t_mode,
10039 /* dc */
10040 q_mode,
10041 q_mode,
10042 q_mode,
10043 q_mode,
10044 q_mode,
10045 q_mode,
10046 q_mode,
10047 q_mode,
10048 /* dd */
10049 q_mode,
10050 q_mode,
10051 q_mode,
10052 q_mode,
10053 0,
10054 0,
10055 0,
10056 w_mode,
10057 /* de */
10058 w_mode,
10059 w_mode,
10060 w_mode,
10061 w_mode,
10062 w_mode,
10063 w_mode,
10064 w_mode,
10065 w_mode,
10066 /* df */
10067 w_mode,
10068 w_mode,
10069 w_mode,
10070 w_mode,
10071 t_mode,
10072 q_mode,
10073 t_mode,
10074 q_mode
10075 };
10076
10077 #define ST { OP_ST, 0 }
10078 #define STi { OP_STi, 0 }
10079
10080 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10081 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10082 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10083 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10084 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10085 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10086 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10087 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10088 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10089
10090 static const struct dis386 float_reg[][8] = {
10091 /* d8 */
10092 {
10093 { "fadd", { ST, STi }, 0 },
10094 { "fmul", { ST, STi }, 0 },
10095 { "fcom", { STi }, 0 },
10096 { "fcomp", { STi }, 0 },
10097 { "fsub", { ST, STi }, 0 },
10098 { "fsubr", { ST, STi }, 0 },
10099 { "fdiv", { ST, STi }, 0 },
10100 { "fdivr", { ST, STi }, 0 },
10101 },
10102 /* d9 */
10103 {
10104 { "fld", { STi }, 0 },
10105 { "fxch", { STi }, 0 },
10106 { FGRPd9_2 },
10107 { Bad_Opcode },
10108 { FGRPd9_4 },
10109 { FGRPd9_5 },
10110 { FGRPd9_6 },
10111 { FGRPd9_7 },
10112 },
10113 /* da */
10114 {
10115 { "fcmovb", { ST, STi }, 0 },
10116 { "fcmove", { ST, STi }, 0 },
10117 { "fcmovbe",{ ST, STi }, 0 },
10118 { "fcmovu", { ST, STi }, 0 },
10119 { Bad_Opcode },
10120 { FGRPda_5 },
10121 { Bad_Opcode },
10122 { Bad_Opcode },
10123 },
10124 /* db */
10125 {
10126 { "fcmovnb",{ ST, STi }, 0 },
10127 { "fcmovne",{ ST, STi }, 0 },
10128 { "fcmovnbe",{ ST, STi }, 0 },
10129 { "fcmovnu",{ ST, STi }, 0 },
10130 { FGRPdb_4 },
10131 { "fucomi", { ST, STi }, 0 },
10132 { "fcomi", { ST, STi }, 0 },
10133 { Bad_Opcode },
10134 },
10135 /* dc */
10136 {
10137 { "fadd", { STi, ST }, 0 },
10138 { "fmul", { STi, ST }, 0 },
10139 { Bad_Opcode },
10140 { Bad_Opcode },
10141 { "fsub{!M|r}", { STi, ST }, 0 },
10142 { "fsub{M|}", { STi, ST }, 0 },
10143 { "fdiv{!M|r}", { STi, ST }, 0 },
10144 { "fdiv{M|}", { STi, ST }, 0 },
10145 },
10146 /* dd */
10147 {
10148 { "ffree", { STi }, 0 },
10149 { Bad_Opcode },
10150 { "fst", { STi }, 0 },
10151 { "fstp", { STi }, 0 },
10152 { "fucom", { STi }, 0 },
10153 { "fucomp", { STi }, 0 },
10154 { Bad_Opcode },
10155 { Bad_Opcode },
10156 },
10157 /* de */
10158 {
10159 { "faddp", { STi, ST }, 0 },
10160 { "fmulp", { STi, ST }, 0 },
10161 { Bad_Opcode },
10162 { FGRPde_3 },
10163 { "fsub{!M|r}p", { STi, ST }, 0 },
10164 { "fsub{M|}p", { STi, ST }, 0 },
10165 { "fdiv{!M|r}p", { STi, ST }, 0 },
10166 { "fdiv{M|}p", { STi, ST }, 0 },
10167 },
10168 /* df */
10169 {
10170 { "ffreep", { STi }, 0 },
10171 { Bad_Opcode },
10172 { Bad_Opcode },
10173 { Bad_Opcode },
10174 { FGRPdf_4 },
10175 { "fucomip", { ST, STi }, 0 },
10176 { "fcomip", { ST, STi }, 0 },
10177 { Bad_Opcode },
10178 },
10179 };
10180
10181 static char *fgrps[][8] = {
10182 /* Bad opcode 0 */
10183 {
10184 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10185 },
10186
10187 /* d9_2 1 */
10188 {
10189 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10190 },
10191
10192 /* d9_4 2 */
10193 {
10194 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10195 },
10196
10197 /* d9_5 3 */
10198 {
10199 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10200 },
10201
10202 /* d9_6 4 */
10203 {
10204 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10205 },
10206
10207 /* d9_7 5 */
10208 {
10209 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10210 },
10211
10212 /* da_5 6 */
10213 {
10214 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10215 },
10216
10217 /* db_4 7 */
10218 {
10219 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10220 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10221 },
10222
10223 /* de_3 8 */
10224 {
10225 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10226 },
10227
10228 /* df_4 9 */
10229 {
10230 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10231 },
10232 };
10233
10234 static void
10235 swap_operand (void)
10236 {
10237 mnemonicendp[0] = '.';
10238 mnemonicendp[1] = 's';
10239 mnemonicendp += 2;
10240 }
10241
10242 static void
10243 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
10244 int sizeflag ATTRIBUTE_UNUSED)
10245 {
10246 /* Skip mod/rm byte. */
10247 MODRM_CHECK;
10248 codep++;
10249 }
10250
10251 static void
10252 dofloat (int sizeflag)
10253 {
10254 const struct dis386 *dp;
10255 unsigned char floatop;
10256
10257 floatop = codep[-1];
10258
10259 if (modrm.mod != 3)
10260 {
10261 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
10262
10263 putop (float_mem[fp_indx], sizeflag);
10264 obufp = op_out[0];
10265 op_ad = 2;
10266 OP_E (float_mem_mode[fp_indx], sizeflag);
10267 return;
10268 }
10269 /* Skip mod/rm byte. */
10270 MODRM_CHECK;
10271 codep++;
10272
10273 dp = &float_reg[floatop - 0xd8][modrm.reg];
10274 if (dp->name == NULL)
10275 {
10276 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
10277
10278 /* Instruction fnstsw is only one with strange arg. */
10279 if (floatop == 0xdf && codep[-1] == 0xe0)
10280 strcpy (op_out[0], names16[0]);
10281 }
10282 else
10283 {
10284 putop (dp->name, sizeflag);
10285
10286 obufp = op_out[0];
10287 op_ad = 2;
10288 if (dp->op[0].rtn)
10289 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
10290
10291 obufp = op_out[1];
10292 op_ad = 1;
10293 if (dp->op[1].rtn)
10294 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
10295 }
10296 }
10297
10298 /* Like oappend (below), but S is a string starting with '%'.
10299 In Intel syntax, the '%' is elided. */
10300 static void
10301 oappend_maybe_intel (const char *s)
10302 {
10303 oappend (s + intel_syntax);
10304 }
10305
10306 static void
10307 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10308 {
10309 oappend_maybe_intel ("%st");
10310 }
10311
10312 static void
10313 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10314 {
10315 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
10316 oappend_maybe_intel (scratchbuf);
10317 }
10318
10319 /* Capital letters in template are macros. */
10320 static int
10321 putop (const char *in_template, int sizeflag)
10322 {
10323 const char *p;
10324 int alt = 0;
10325 int cond = 1;
10326 unsigned int l = 0, len = 0;
10327 char last[4];
10328
10329 for (p = in_template; *p; p++)
10330 {
10331 if (len > l)
10332 {
10333 if (l >= sizeof (last) || !ISUPPER (*p))
10334 abort ();
10335 last[l++] = *p;
10336 continue;
10337 }
10338 switch (*p)
10339 {
10340 default:
10341 *obufp++ = *p;
10342 break;
10343 case '%':
10344 len++;
10345 break;
10346 case '!':
10347 cond = 0;
10348 break;
10349 case '{':
10350 if (intel_syntax)
10351 {
10352 while (*++p != '|')
10353 if (*p == '}' || *p == '\0')
10354 abort ();
10355 alt = 1;
10356 }
10357 break;
10358 case '|':
10359 while (*++p != '}')
10360 {
10361 if (*p == '\0')
10362 abort ();
10363 }
10364 break;
10365 case '}':
10366 alt = 0;
10367 break;
10368 case 'A':
10369 if (intel_syntax)
10370 break;
10371 if ((need_modrm && modrm.mod != 3)
10372 || (sizeflag & SUFFIX_ALWAYS))
10373 *obufp++ = 'b';
10374 break;
10375 case 'B':
10376 if (l == 0)
10377 {
10378 case_B:
10379 if (intel_syntax)
10380 break;
10381 if (sizeflag & SUFFIX_ALWAYS)
10382 *obufp++ = 'b';
10383 }
10384 else if (l == 1 && last[0] == 'L')
10385 {
10386 if (address_mode == mode_64bit
10387 && !(prefixes & PREFIX_ADDR))
10388 {
10389 *obufp++ = 'a';
10390 *obufp++ = 'b';
10391 *obufp++ = 's';
10392 }
10393
10394 goto case_B;
10395 }
10396 else
10397 abort ();
10398 break;
10399 case 'C':
10400 if (intel_syntax && !alt)
10401 break;
10402 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10403 {
10404 if (sizeflag & DFLAG)
10405 *obufp++ = intel_syntax ? 'd' : 'l';
10406 else
10407 *obufp++ = intel_syntax ? 'w' : 's';
10408 used_prefixes |= (prefixes & PREFIX_DATA);
10409 }
10410 break;
10411 case 'D':
10412 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10413 break;
10414 USED_REX (REX_W);
10415 if (modrm.mod == 3)
10416 {
10417 if (rex & REX_W)
10418 *obufp++ = 'q';
10419 else
10420 {
10421 if (sizeflag & DFLAG)
10422 *obufp++ = intel_syntax ? 'd' : 'l';
10423 else
10424 *obufp++ = 'w';
10425 used_prefixes |= (prefixes & PREFIX_DATA);
10426 }
10427 }
10428 else
10429 *obufp++ = 'w';
10430 break;
10431 case 'E': /* For jcxz/jecxz */
10432 if (address_mode == mode_64bit)
10433 {
10434 if (sizeflag & AFLAG)
10435 *obufp++ = 'r';
10436 else
10437 *obufp++ = 'e';
10438 }
10439 else
10440 if (sizeflag & AFLAG)
10441 *obufp++ = 'e';
10442 used_prefixes |= (prefixes & PREFIX_ADDR);
10443 break;
10444 case 'F':
10445 if (intel_syntax)
10446 break;
10447 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10448 {
10449 if (sizeflag & AFLAG)
10450 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10451 else
10452 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
10453 used_prefixes |= (prefixes & PREFIX_ADDR);
10454 }
10455 break;
10456 case 'G':
10457 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
10458 break;
10459 if ((rex & REX_W) || (sizeflag & DFLAG))
10460 *obufp++ = 'l';
10461 else
10462 *obufp++ = 'w';
10463 if (!(rex & REX_W))
10464 used_prefixes |= (prefixes & PREFIX_DATA);
10465 break;
10466 case 'H':
10467 if (intel_syntax)
10468 break;
10469 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10470 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10471 {
10472 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
10473 *obufp++ = ',';
10474 *obufp++ = 'p';
10475
10476 /* Set active_seg_prefix even if not set in 64-bit mode
10477 because here it is a valid branch hint. */
10478 if (prefixes & PREFIX_DS)
10479 {
10480 active_seg_prefix = PREFIX_DS;
10481 *obufp++ = 't';
10482 }
10483 else
10484 {
10485 active_seg_prefix = PREFIX_CS;
10486 *obufp++ = 'n';
10487 }
10488 }
10489 break;
10490 case 'K':
10491 USED_REX (REX_W);
10492 if (rex & REX_W)
10493 *obufp++ = 'q';
10494 else
10495 *obufp++ = 'd';
10496 break;
10497 case 'L':
10498 abort ();
10499 case 'M':
10500 if (intel_mnemonic != cond)
10501 *obufp++ = 'r';
10502 break;
10503 case 'N':
10504 if ((prefixes & PREFIX_FWAIT) == 0)
10505 *obufp++ = 'n';
10506 else
10507 used_prefixes |= PREFIX_FWAIT;
10508 break;
10509 case 'O':
10510 USED_REX (REX_W);
10511 if (rex & REX_W)
10512 *obufp++ = 'o';
10513 else if (intel_syntax && (sizeflag & DFLAG))
10514 *obufp++ = 'q';
10515 else
10516 *obufp++ = 'd';
10517 if (!(rex & REX_W))
10518 used_prefixes |= (prefixes & PREFIX_DATA);
10519 break;
10520 case '@':
10521 if (address_mode == mode_64bit
10522 && (isa64 == intel64 || (rex & REX_W)
10523 || !(prefixes & PREFIX_DATA)))
10524 {
10525 if (sizeflag & SUFFIX_ALWAYS)
10526 *obufp++ = 'q';
10527 break;
10528 }
10529 /* Fall through. */
10530 case 'P':
10531 if (l == 0)
10532 {
10533 if ((modrm.mod == 3 || !cond)
10534 && !(sizeflag & SUFFIX_ALWAYS))
10535 break;
10536 /* Fall through. */
10537 case 'T':
10538 if ((!(rex & REX_W) && (prefixes & PREFIX_DATA))
10539 || ((sizeflag & SUFFIX_ALWAYS)
10540 && address_mode != mode_64bit))
10541 {
10542 *obufp++ = (sizeflag & DFLAG) ?
10543 intel_syntax ? 'd' : 'l' : 'w';
10544 used_prefixes |= (prefixes & PREFIX_DATA);
10545 }
10546 else if (sizeflag & SUFFIX_ALWAYS)
10547 *obufp++ = 'q';
10548 }
10549 else if (l == 1 && last[0] == 'L')
10550 {
10551 if ((prefixes & PREFIX_DATA)
10552 || (rex & REX_W)
10553 || (sizeflag & SUFFIX_ALWAYS))
10554 {
10555 USED_REX (REX_W);
10556 if (rex & REX_W)
10557 *obufp++ = 'q';
10558 else
10559 {
10560 if (sizeflag & DFLAG)
10561 *obufp++ = intel_syntax ? 'd' : 'l';
10562 else
10563 *obufp++ = 'w';
10564 used_prefixes |= (prefixes & PREFIX_DATA);
10565 }
10566 }
10567 }
10568 else
10569 abort ();
10570 break;
10571 case 'Q':
10572 if (l == 0)
10573 {
10574 if (intel_syntax && !alt)
10575 break;
10576 USED_REX (REX_W);
10577 if ((need_modrm && modrm.mod != 3)
10578 || (sizeflag & SUFFIX_ALWAYS))
10579 {
10580 if (rex & REX_W)
10581 *obufp++ = 'q';
10582 else
10583 {
10584 if (sizeflag & DFLAG)
10585 *obufp++ = intel_syntax ? 'd' : 'l';
10586 else
10587 *obufp++ = 'w';
10588 used_prefixes |= (prefixes & PREFIX_DATA);
10589 }
10590 }
10591 }
10592 else if (l == 1 && last[0] == 'D')
10593 *obufp++ = vex.w ? 'q' : 'd';
10594 else if (l == 1 && last[0] == 'L')
10595 {
10596 if (cond ? modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
10597 : address_mode != mode_64bit)
10598 break;
10599 if ((rex & REX_W))
10600 {
10601 USED_REX (REX_W);
10602 *obufp++ = 'q';
10603 }
10604 else if((address_mode == mode_64bit && cond)
10605 || (sizeflag & SUFFIX_ALWAYS))
10606 *obufp++ = intel_syntax? 'd' : 'l';
10607 }
10608 else
10609 abort ();
10610 break;
10611 case 'R':
10612 USED_REX (REX_W);
10613 if (rex & REX_W)
10614 *obufp++ = 'q';
10615 else if (sizeflag & DFLAG)
10616 {
10617 if (intel_syntax)
10618 *obufp++ = 'd';
10619 else
10620 *obufp++ = 'l';
10621 }
10622 else
10623 *obufp++ = 'w';
10624 if (intel_syntax && !p[1]
10625 && ((rex & REX_W) || (sizeflag & DFLAG)))
10626 *obufp++ = 'e';
10627 if (!(rex & REX_W))
10628 used_prefixes |= (prefixes & PREFIX_DATA);
10629 break;
10630 case 'S':
10631 if (l == 0)
10632 {
10633 case_S:
10634 if (intel_syntax)
10635 break;
10636 if (sizeflag & SUFFIX_ALWAYS)
10637 {
10638 if (rex & REX_W)
10639 *obufp++ = 'q';
10640 else
10641 {
10642 if (sizeflag & DFLAG)
10643 *obufp++ = 'l';
10644 else
10645 *obufp++ = 'w';
10646 used_prefixes |= (prefixes & PREFIX_DATA);
10647 }
10648 }
10649 }
10650 else if (l == 1 && last[0] == 'L')
10651 {
10652 if (address_mode == mode_64bit
10653 && !(prefixes & PREFIX_ADDR))
10654 {
10655 *obufp++ = 'a';
10656 *obufp++ = 'b';
10657 *obufp++ = 's';
10658 }
10659
10660 goto case_S;
10661 }
10662 else
10663 abort ();
10664 break;
10665 case 'V':
10666 if (l == 0)
10667 abort ();
10668 else if (l == 1
10669 && (last[0] == 'L' || last[0] == 'X'))
10670 {
10671 if (last[0] == 'X')
10672 {
10673 *obufp++ = '{';
10674 *obufp++ = 'v';
10675 *obufp++ = 'e';
10676 *obufp++ = 'x';
10677 *obufp++ = '}';
10678 }
10679 else if (rex & REX_W)
10680 {
10681 *obufp++ = 'a';
10682 *obufp++ = 'b';
10683 *obufp++ = 's';
10684 }
10685 }
10686 else
10687 abort ();
10688 goto case_S;
10689 case 'W':
10690 if (l == 0)
10691 {
10692 /* operand size flag for cwtl, cbtw */
10693 USED_REX (REX_W);
10694 if (rex & REX_W)
10695 {
10696 if (intel_syntax)
10697 *obufp++ = 'd';
10698 else
10699 *obufp++ = 'l';
10700 }
10701 else if (sizeflag & DFLAG)
10702 *obufp++ = 'w';
10703 else
10704 *obufp++ = 'b';
10705 if (!(rex & REX_W))
10706 used_prefixes |= (prefixes & PREFIX_DATA);
10707 }
10708 else if (l == 1)
10709 {
10710 if (!need_vex)
10711 abort ();
10712 if (last[0] == 'X')
10713 *obufp++ = vex.w ? 'd': 's';
10714 else if (last[0] == 'B')
10715 *obufp++ = vex.w ? 'w': 'b';
10716 else
10717 abort ();
10718 }
10719 else
10720 abort ();
10721 break;
10722 case 'X':
10723 if (l != 0)
10724 abort ();
10725 if (need_vex
10726 ? vex.prefix == DATA_PREFIX_OPCODE
10727 : prefixes & PREFIX_DATA)
10728 {
10729 *obufp++ = 'd';
10730 used_prefixes |= PREFIX_DATA;
10731 }
10732 else
10733 *obufp++ = 's';
10734 break;
10735 case 'Y':
10736 if (l == 1 && last[0] == 'X')
10737 {
10738 if (!need_vex)
10739 abort ();
10740 if (intel_syntax
10741 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
10742 break;
10743 switch (vex.length)
10744 {
10745 case 128:
10746 *obufp++ = 'x';
10747 break;
10748 case 256:
10749 *obufp++ = 'y';
10750 break;
10751 case 512:
10752 if (!vex.evex)
10753 default:
10754 abort ();
10755 }
10756 }
10757 else
10758 abort ();
10759 break;
10760 case 'Z':
10761 if (l == 0)
10762 {
10763 /* These insns ignore ModR/M.mod: Force it to 3 for OP_E(). */
10764 modrm.mod = 3;
10765 if (!intel_syntax && (sizeflag & SUFFIX_ALWAYS))
10766 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10767 }
10768 else if (l == 1 && last[0] == 'X')
10769 {
10770 if (!need_vex || !vex.evex)
10771 abort ();
10772 if (intel_syntax
10773 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
10774 break;
10775 switch (vex.length)
10776 {
10777 case 128:
10778 *obufp++ = 'x';
10779 break;
10780 case 256:
10781 *obufp++ = 'y';
10782 break;
10783 case 512:
10784 *obufp++ = 'z';
10785 break;
10786 default:
10787 abort ();
10788 }
10789 }
10790 else
10791 abort ();
10792 break;
10793 case '^':
10794 if (intel_syntax)
10795 break;
10796 if (isa64 == intel64 && (rex & REX_W))
10797 {
10798 USED_REX (REX_W);
10799 *obufp++ = 'q';
10800 break;
10801 }
10802 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10803 {
10804 if (sizeflag & DFLAG)
10805 *obufp++ = 'l';
10806 else
10807 *obufp++ = 'w';
10808 used_prefixes |= (prefixes & PREFIX_DATA);
10809 }
10810 break;
10811 }
10812
10813 if (len == l)
10814 len = l = 0;
10815 }
10816 *obufp = 0;
10817 mnemonicendp = obufp;
10818 return 0;
10819 }
10820
10821 static void
10822 oappend (const char *s)
10823 {
10824 obufp = stpcpy (obufp, s);
10825 }
10826
10827 static void
10828 append_seg (void)
10829 {
10830 /* Only print the active segment register. */
10831 if (!active_seg_prefix)
10832 return;
10833
10834 used_prefixes |= active_seg_prefix;
10835 switch (active_seg_prefix)
10836 {
10837 case PREFIX_CS:
10838 oappend_maybe_intel ("%cs:");
10839 break;
10840 case PREFIX_DS:
10841 oappend_maybe_intel ("%ds:");
10842 break;
10843 case PREFIX_SS:
10844 oappend_maybe_intel ("%ss:");
10845 break;
10846 case PREFIX_ES:
10847 oappend_maybe_intel ("%es:");
10848 break;
10849 case PREFIX_FS:
10850 oappend_maybe_intel ("%fs:");
10851 break;
10852 case PREFIX_GS:
10853 oappend_maybe_intel ("%gs:");
10854 break;
10855 default:
10856 break;
10857 }
10858 }
10859
10860 static void
10861 OP_indirE (int bytemode, int sizeflag)
10862 {
10863 if (!intel_syntax)
10864 oappend ("*");
10865 OP_E (bytemode, sizeflag);
10866 }
10867
10868 static void
10869 print_operand_value (char *buf, int hex, bfd_vma disp)
10870 {
10871 if (address_mode == mode_64bit)
10872 {
10873 if (hex)
10874 {
10875 char tmp[30];
10876 int i;
10877 buf[0] = '0';
10878 buf[1] = 'x';
10879 sprintf_vma (tmp, disp);
10880 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
10881 strcpy (buf + 2, tmp + i);
10882 }
10883 else
10884 {
10885 bfd_signed_vma v = disp;
10886 char tmp[30];
10887 int i;
10888 if (v < 0)
10889 {
10890 *(buf++) = '-';
10891 v = -disp;
10892 /* Check for possible overflow on 0x8000000000000000. */
10893 if (v < 0)
10894 {
10895 strcpy (buf, "9223372036854775808");
10896 return;
10897 }
10898 }
10899 if (!v)
10900 {
10901 strcpy (buf, "0");
10902 return;
10903 }
10904
10905 i = 0;
10906 tmp[29] = 0;
10907 while (v)
10908 {
10909 tmp[28 - i] = (v % 10) + '0';
10910 v /= 10;
10911 i++;
10912 }
10913 strcpy (buf, tmp + 29 - i);
10914 }
10915 }
10916 else
10917 {
10918 if (hex)
10919 sprintf (buf, "0x%x", (unsigned int) disp);
10920 else
10921 sprintf (buf, "%d", (int) disp);
10922 }
10923 }
10924
10925 /* Put DISP in BUF as signed hex number. */
10926
10927 static void
10928 print_displacement (char *buf, bfd_vma disp)
10929 {
10930 bfd_signed_vma val = disp;
10931 char tmp[30];
10932 int i, j = 0;
10933
10934 if (val < 0)
10935 {
10936 buf[j++] = '-';
10937 val = -disp;
10938
10939 /* Check for possible overflow. */
10940 if (val < 0)
10941 {
10942 switch (address_mode)
10943 {
10944 case mode_64bit:
10945 strcpy (buf + j, "0x8000000000000000");
10946 break;
10947 case mode_32bit:
10948 strcpy (buf + j, "0x80000000");
10949 break;
10950 case mode_16bit:
10951 strcpy (buf + j, "0x8000");
10952 break;
10953 }
10954 return;
10955 }
10956 }
10957
10958 buf[j++] = '0';
10959 buf[j++] = 'x';
10960
10961 sprintf_vma (tmp, (bfd_vma) val);
10962 for (i = 0; tmp[i] == '0'; i++)
10963 continue;
10964 if (tmp[i] == '\0')
10965 i--;
10966 strcpy (buf + j, tmp + i);
10967 }
10968
10969 static void
10970 intel_operand_size (int bytemode, int sizeflag)
10971 {
10972 if (vex.evex
10973 && vex.b
10974 && (bytemode == x_mode
10975 || bytemode == evex_half_bcst_xmmq_mode))
10976 {
10977 if (vex.w)
10978 oappend ("QWORD PTR ");
10979 else
10980 oappend ("DWORD PTR ");
10981 return;
10982 }
10983 switch (bytemode)
10984 {
10985 case b_mode:
10986 case b_swap_mode:
10987 case dqb_mode:
10988 case db_mode:
10989 oappend ("BYTE PTR ");
10990 break;
10991 case w_mode:
10992 case dw_mode:
10993 case dqw_mode:
10994 oappend ("WORD PTR ");
10995 break;
10996 case indir_v_mode:
10997 if (address_mode == mode_64bit && isa64 == intel64)
10998 {
10999 oappend ("QWORD PTR ");
11000 break;
11001 }
11002 /* Fall through. */
11003 case stack_v_mode:
11004 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
11005 {
11006 oappend ("QWORD PTR ");
11007 break;
11008 }
11009 /* Fall through. */
11010 case v_mode:
11011 case v_swap_mode:
11012 case dq_mode:
11013 USED_REX (REX_W);
11014 if (rex & REX_W)
11015 oappend ("QWORD PTR ");
11016 else if (bytemode == dq_mode)
11017 oappend ("DWORD PTR ");
11018 else
11019 {
11020 if (sizeflag & DFLAG)
11021 oappend ("DWORD PTR ");
11022 else
11023 oappend ("WORD PTR ");
11024 used_prefixes |= (prefixes & PREFIX_DATA);
11025 }
11026 break;
11027 case z_mode:
11028 if ((rex & REX_W) || (sizeflag & DFLAG))
11029 *obufp++ = 'D';
11030 oappend ("WORD PTR ");
11031 if (!(rex & REX_W))
11032 used_prefixes |= (prefixes & PREFIX_DATA);
11033 break;
11034 case a_mode:
11035 if (sizeflag & DFLAG)
11036 oappend ("QWORD PTR ");
11037 else
11038 oappend ("DWORD PTR ");
11039 used_prefixes |= (prefixes & PREFIX_DATA);
11040 break;
11041 case movsxd_mode:
11042 if (!(sizeflag & DFLAG) && isa64 == intel64)
11043 oappend ("WORD PTR ");
11044 else
11045 oappend ("DWORD PTR ");
11046 used_prefixes |= (prefixes & PREFIX_DATA);
11047 break;
11048 case d_mode:
11049 case d_swap_mode:
11050 case dqd_mode:
11051 oappend ("DWORD PTR ");
11052 break;
11053 case q_mode:
11054 case q_swap_mode:
11055 oappend ("QWORD PTR ");
11056 break;
11057 case m_mode:
11058 if (address_mode == mode_64bit)
11059 oappend ("QWORD PTR ");
11060 else
11061 oappend ("DWORD PTR ");
11062 break;
11063 case f_mode:
11064 if (sizeflag & DFLAG)
11065 oappend ("FWORD PTR ");
11066 else
11067 oappend ("DWORD PTR ");
11068 used_prefixes |= (prefixes & PREFIX_DATA);
11069 break;
11070 case t_mode:
11071 oappend ("TBYTE PTR ");
11072 break;
11073 case x_mode:
11074 case x_swap_mode:
11075 case evex_x_gscat_mode:
11076 case evex_x_nobcst_mode:
11077 case bw_unit_mode:
11078 if (need_vex)
11079 {
11080 switch (vex.length)
11081 {
11082 case 128:
11083 oappend ("XMMWORD PTR ");
11084 break;
11085 case 256:
11086 oappend ("YMMWORD PTR ");
11087 break;
11088 case 512:
11089 oappend ("ZMMWORD PTR ");
11090 break;
11091 default:
11092 abort ();
11093 }
11094 }
11095 else
11096 oappend ("XMMWORD PTR ");
11097 break;
11098 case xmm_mode:
11099 oappend ("XMMWORD PTR ");
11100 break;
11101 case ymm_mode:
11102 oappend ("YMMWORD PTR ");
11103 break;
11104 case xmmq_mode:
11105 case evex_half_bcst_xmmq_mode:
11106 if (!need_vex)
11107 abort ();
11108
11109 switch (vex.length)
11110 {
11111 case 128:
11112 oappend ("QWORD PTR ");
11113 break;
11114 case 256:
11115 oappend ("XMMWORD PTR ");
11116 break;
11117 case 512:
11118 oappend ("YMMWORD PTR ");
11119 break;
11120 default:
11121 abort ();
11122 }
11123 break;
11124 case xmm_mb_mode:
11125 if (!need_vex)
11126 abort ();
11127
11128 switch (vex.length)
11129 {
11130 case 128:
11131 case 256:
11132 case 512:
11133 oappend ("BYTE PTR ");
11134 break;
11135 default:
11136 abort ();
11137 }
11138 break;
11139 case xmm_mw_mode:
11140 if (!need_vex)
11141 abort ();
11142
11143 switch (vex.length)
11144 {
11145 case 128:
11146 case 256:
11147 case 512:
11148 oappend ("WORD PTR ");
11149 break;
11150 default:
11151 abort ();
11152 }
11153 break;
11154 case xmm_md_mode:
11155 if (!need_vex)
11156 abort ();
11157
11158 switch (vex.length)
11159 {
11160 case 128:
11161 case 256:
11162 case 512:
11163 oappend ("DWORD PTR ");
11164 break;
11165 default:
11166 abort ();
11167 }
11168 break;
11169 case xmm_mq_mode:
11170 if (!need_vex)
11171 abort ();
11172
11173 switch (vex.length)
11174 {
11175 case 128:
11176 case 256:
11177 case 512:
11178 oappend ("QWORD PTR ");
11179 break;
11180 default:
11181 abort ();
11182 }
11183 break;
11184 case xmmdw_mode:
11185 if (!need_vex)
11186 abort ();
11187
11188 switch (vex.length)
11189 {
11190 case 128:
11191 oappend ("WORD PTR ");
11192 break;
11193 case 256:
11194 oappend ("DWORD PTR ");
11195 break;
11196 case 512:
11197 oappend ("QWORD PTR ");
11198 break;
11199 default:
11200 abort ();
11201 }
11202 break;
11203 case xmmqd_mode:
11204 if (!need_vex)
11205 abort ();
11206
11207 switch (vex.length)
11208 {
11209 case 128:
11210 oappend ("DWORD PTR ");
11211 break;
11212 case 256:
11213 oappend ("QWORD PTR ");
11214 break;
11215 case 512:
11216 oappend ("XMMWORD PTR ");
11217 break;
11218 default:
11219 abort ();
11220 }
11221 break;
11222 case ymmq_mode:
11223 if (!need_vex)
11224 abort ();
11225
11226 switch (vex.length)
11227 {
11228 case 128:
11229 oappend ("QWORD PTR ");
11230 break;
11231 case 256:
11232 oappend ("YMMWORD PTR ");
11233 break;
11234 case 512:
11235 oappend ("ZMMWORD PTR ");
11236 break;
11237 default:
11238 abort ();
11239 }
11240 break;
11241 case ymmxmm_mode:
11242 if (!need_vex)
11243 abort ();
11244
11245 switch (vex.length)
11246 {
11247 case 128:
11248 case 256:
11249 oappend ("XMMWORD PTR ");
11250 break;
11251 default:
11252 abort ();
11253 }
11254 break;
11255 case o_mode:
11256 oappend ("OWORD PTR ");
11257 break;
11258 case vex_scalar_w_dq_mode:
11259 if (!need_vex)
11260 abort ();
11261
11262 if (vex.w)
11263 oappend ("QWORD PTR ");
11264 else
11265 oappend ("DWORD PTR ");
11266 break;
11267 case vex_vsib_d_w_dq_mode:
11268 case vex_vsib_q_w_dq_mode:
11269 if (!need_vex)
11270 abort ();
11271
11272 if (!vex.evex)
11273 {
11274 if (vex.w)
11275 oappend ("QWORD PTR ");
11276 else
11277 oappend ("DWORD PTR ");
11278 }
11279 else
11280 {
11281 switch (vex.length)
11282 {
11283 case 128:
11284 oappend ("XMMWORD PTR ");
11285 break;
11286 case 256:
11287 oappend ("YMMWORD PTR ");
11288 break;
11289 case 512:
11290 oappend ("ZMMWORD PTR ");
11291 break;
11292 default:
11293 abort ();
11294 }
11295 }
11296 break;
11297 case vex_vsib_q_w_d_mode:
11298 case vex_vsib_d_w_d_mode:
11299 if (!need_vex || !vex.evex)
11300 abort ();
11301
11302 switch (vex.length)
11303 {
11304 case 128:
11305 oappend ("QWORD PTR ");
11306 break;
11307 case 256:
11308 oappend ("XMMWORD PTR ");
11309 break;
11310 case 512:
11311 oappend ("YMMWORD PTR ");
11312 break;
11313 default:
11314 abort ();
11315 }
11316
11317 break;
11318 case mask_bd_mode:
11319 if (!need_vex || vex.length != 128)
11320 abort ();
11321 if (vex.w)
11322 oappend ("DWORD PTR ");
11323 else
11324 oappend ("BYTE PTR ");
11325 break;
11326 case mask_mode:
11327 if (!need_vex)
11328 abort ();
11329 if (vex.w)
11330 oappend ("QWORD PTR ");
11331 else
11332 oappend ("WORD PTR ");
11333 break;
11334 case v_bnd_mode:
11335 case v_bndmk_mode:
11336 default:
11337 break;
11338 }
11339 }
11340
11341 static void
11342 OP_E_register (int bytemode, int sizeflag)
11343 {
11344 int reg = modrm.rm;
11345 const char **names;
11346
11347 USED_REX (REX_B);
11348 if ((rex & REX_B))
11349 reg += 8;
11350
11351 if ((sizeflag & SUFFIX_ALWAYS)
11352 && (bytemode == b_swap_mode
11353 || bytemode == bnd_swap_mode
11354 || bytemode == v_swap_mode))
11355 swap_operand ();
11356
11357 switch (bytemode)
11358 {
11359 case b_mode:
11360 case b_swap_mode:
11361 if (reg & 4)
11362 USED_REX (0);
11363 if (rex)
11364 names = names8rex;
11365 else
11366 names = names8;
11367 break;
11368 case w_mode:
11369 names = names16;
11370 break;
11371 case d_mode:
11372 case dw_mode:
11373 case db_mode:
11374 names = names32;
11375 break;
11376 case q_mode:
11377 names = names64;
11378 break;
11379 case m_mode:
11380 case v_bnd_mode:
11381 names = address_mode == mode_64bit ? names64 : names32;
11382 break;
11383 case bnd_mode:
11384 case bnd_swap_mode:
11385 if (reg > 0x3)
11386 {
11387 oappend ("(bad)");
11388 return;
11389 }
11390 names = names_bnd;
11391 break;
11392 case indir_v_mode:
11393 if (address_mode == mode_64bit && isa64 == intel64)
11394 {
11395 names = names64;
11396 break;
11397 }
11398 /* Fall through. */
11399 case stack_v_mode:
11400 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
11401 {
11402 names = names64;
11403 break;
11404 }
11405 bytemode = v_mode;
11406 /* Fall through. */
11407 case v_mode:
11408 case v_swap_mode:
11409 case dq_mode:
11410 case dqb_mode:
11411 case dqd_mode:
11412 case dqw_mode:
11413 USED_REX (REX_W);
11414 if (rex & REX_W)
11415 names = names64;
11416 else if (bytemode != v_mode && bytemode != v_swap_mode)
11417 names = names32;
11418 else
11419 {
11420 if (sizeflag & DFLAG)
11421 names = names32;
11422 else
11423 names = names16;
11424 used_prefixes |= (prefixes & PREFIX_DATA);
11425 }
11426 break;
11427 case movsxd_mode:
11428 if (!(sizeflag & DFLAG) && isa64 == intel64)
11429 names = names16;
11430 else
11431 names = names32;
11432 used_prefixes |= (prefixes & PREFIX_DATA);
11433 break;
11434 case va_mode:
11435 names = (address_mode == mode_64bit
11436 ? names64 : names32);
11437 if (!(prefixes & PREFIX_ADDR))
11438 names = (address_mode == mode_16bit
11439 ? names16 : names);
11440 else
11441 {
11442 /* Remove "addr16/addr32". */
11443 all_prefixes[last_addr_prefix] = 0;
11444 names = (address_mode != mode_32bit
11445 ? names32 : names16);
11446 used_prefixes |= PREFIX_ADDR;
11447 }
11448 break;
11449 case mask_bd_mode:
11450 case mask_mode:
11451 if (reg > 0x7)
11452 {
11453 oappend ("(bad)");
11454 return;
11455 }
11456 names = names_mask;
11457 break;
11458 case 0:
11459 return;
11460 default:
11461 oappend (INTERNAL_DISASSEMBLER_ERROR);
11462 return;
11463 }
11464 oappend (names[reg]);
11465 }
11466
11467 static void
11468 OP_E_memory (int bytemode, int sizeflag)
11469 {
11470 bfd_vma disp = 0;
11471 int add = (rex & REX_B) ? 8 : 0;
11472 int riprel = 0;
11473 int shift;
11474
11475 if (vex.evex)
11476 {
11477 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
11478 if (vex.b
11479 && bytemode != x_mode
11480 && bytemode != xmmq_mode
11481 && bytemode != evex_half_bcst_xmmq_mode)
11482 {
11483 BadOp ();
11484 return;
11485 }
11486 switch (bytemode)
11487 {
11488 case dqw_mode:
11489 case dw_mode:
11490 case xmm_mw_mode:
11491 shift = 1;
11492 break;
11493 case dqb_mode:
11494 case db_mode:
11495 case xmm_mb_mode:
11496 shift = 0;
11497 break;
11498 case dq_mode:
11499 if (address_mode != mode_64bit)
11500 {
11501 case dqd_mode:
11502 case xmm_md_mode:
11503 case d_mode:
11504 case d_swap_mode:
11505 shift = 2;
11506 break;
11507 }
11508 /* fall through */
11509 case vex_scalar_w_dq_mode:
11510 case vex_vsib_d_w_dq_mode:
11511 case vex_vsib_d_w_d_mode:
11512 case vex_vsib_q_w_dq_mode:
11513 case vex_vsib_q_w_d_mode:
11514 case evex_x_gscat_mode:
11515 shift = vex.w ? 3 : 2;
11516 break;
11517 case x_mode:
11518 case evex_half_bcst_xmmq_mode:
11519 case xmmq_mode:
11520 if (vex.b)
11521 {
11522 shift = vex.w ? 3 : 2;
11523 break;
11524 }
11525 /* Fall through. */
11526 case xmmqd_mode:
11527 case xmmdw_mode:
11528 case ymmq_mode:
11529 case evex_x_nobcst_mode:
11530 case x_swap_mode:
11531 switch (vex.length)
11532 {
11533 case 128:
11534 shift = 4;
11535 break;
11536 case 256:
11537 shift = 5;
11538 break;
11539 case 512:
11540 shift = 6;
11541 break;
11542 default:
11543 abort ();
11544 }
11545 /* Make necessary corrections to shift for modes that need it. */
11546 if (bytemode == xmmq_mode
11547 || bytemode == evex_half_bcst_xmmq_mode
11548 || (bytemode == ymmq_mode && vex.length == 128))
11549 shift -= 1;
11550 else if (bytemode == xmmqd_mode)
11551 shift -= 2;
11552 else if (bytemode == xmmdw_mode)
11553 shift -= 3;
11554 break;
11555 case ymm_mode:
11556 shift = 5;
11557 break;
11558 case xmm_mode:
11559 shift = 4;
11560 break;
11561 case xmm_mq_mode:
11562 case q_mode:
11563 case q_swap_mode:
11564 shift = 3;
11565 break;
11566 case bw_unit_mode:
11567 shift = vex.w ? 1 : 0;
11568 break;
11569 default:
11570 abort ();
11571 }
11572 }
11573 else
11574 shift = 0;
11575
11576 USED_REX (REX_B);
11577 if (intel_syntax)
11578 intel_operand_size (bytemode, sizeflag);
11579 append_seg ();
11580
11581 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11582 {
11583 /* 32/64 bit address mode */
11584 int havedisp;
11585 int havesib;
11586 int havebase;
11587 int haveindex;
11588 int needindex;
11589 int needaddr32;
11590 int base, rbase;
11591 int vindex = 0;
11592 int scale = 0;
11593 int addr32flag = !((sizeflag & AFLAG)
11594 || bytemode == v_bnd_mode
11595 || bytemode == v_bndmk_mode
11596 || bytemode == bnd_mode
11597 || bytemode == bnd_swap_mode);
11598 const char **indexes64 = names64;
11599 const char **indexes32 = names32;
11600
11601 havesib = 0;
11602 havebase = 1;
11603 haveindex = 0;
11604 base = modrm.rm;
11605
11606 if (base == 4)
11607 {
11608 havesib = 1;
11609 vindex = sib.index;
11610 USED_REX (REX_X);
11611 if (rex & REX_X)
11612 vindex += 8;
11613 switch (bytemode)
11614 {
11615 case vex_vsib_d_w_dq_mode:
11616 case vex_vsib_d_w_d_mode:
11617 case vex_vsib_q_w_dq_mode:
11618 case vex_vsib_q_w_d_mode:
11619 if (!need_vex)
11620 abort ();
11621 if (vex.evex)
11622 {
11623 if (!vex.v)
11624 vindex += 16;
11625 }
11626
11627 haveindex = 1;
11628 switch (vex.length)
11629 {
11630 case 128:
11631 indexes64 = indexes32 = names_xmm;
11632 break;
11633 case 256:
11634 if (!vex.w
11635 || bytemode == vex_vsib_q_w_dq_mode
11636 || bytemode == vex_vsib_q_w_d_mode)
11637 indexes64 = indexes32 = names_ymm;
11638 else
11639 indexes64 = indexes32 = names_xmm;
11640 break;
11641 case 512:
11642 if (!vex.w
11643 || bytemode == vex_vsib_q_w_dq_mode
11644 || bytemode == vex_vsib_q_w_d_mode)
11645 indexes64 = indexes32 = names_zmm;
11646 else
11647 indexes64 = indexes32 = names_ymm;
11648 break;
11649 default:
11650 abort ();
11651 }
11652 break;
11653 default:
11654 haveindex = vindex != 4;
11655 break;
11656 }
11657 scale = sib.scale;
11658 base = sib.base;
11659 codep++;
11660 }
11661 else
11662 {
11663 /* mandatory non-vector SIB must have sib */
11664 if (bytemode == vex_sibmem_mode)
11665 {
11666 oappend ("(bad)");
11667 return;
11668 }
11669 }
11670 rbase = base + add;
11671
11672 switch (modrm.mod)
11673 {
11674 case 0:
11675 if (base == 5)
11676 {
11677 havebase = 0;
11678 if (address_mode == mode_64bit && !havesib)
11679 riprel = 1;
11680 disp = get32s ();
11681 if (riprel && bytemode == v_bndmk_mode)
11682 {
11683 oappend ("(bad)");
11684 return;
11685 }
11686 }
11687 break;
11688 case 1:
11689 FETCH_DATA (the_info, codep + 1);
11690 disp = *codep++;
11691 if ((disp & 0x80) != 0)
11692 disp -= 0x100;
11693 if (vex.evex && shift > 0)
11694 disp <<= shift;
11695 break;
11696 case 2:
11697 disp = get32s ();
11698 break;
11699 }
11700
11701 needindex = 0;
11702 needaddr32 = 0;
11703 if (havesib
11704 && !havebase
11705 && !haveindex
11706 && address_mode != mode_16bit)
11707 {
11708 if (address_mode == mode_64bit)
11709 {
11710 if (addr32flag)
11711 {
11712 /* Without base nor index registers, zero-extend the
11713 lower 32-bit displacement to 64 bits. */
11714 disp = (unsigned int) disp;
11715 needindex = 1;
11716 }
11717 needaddr32 = 1;
11718 }
11719 else
11720 {
11721 /* In 32-bit mode, we need index register to tell [offset]
11722 from [eiz*1 + offset]. */
11723 needindex = 1;
11724 }
11725 }
11726
11727 havedisp = (havebase
11728 || needindex
11729 || (havesib && (haveindex || scale != 0)));
11730
11731 if (!intel_syntax)
11732 if (modrm.mod != 0 || base == 5)
11733 {
11734 if (havedisp || riprel)
11735 print_displacement (scratchbuf, disp);
11736 else
11737 print_operand_value (scratchbuf, 1, disp);
11738 oappend (scratchbuf);
11739 if (riprel)
11740 {
11741 set_op (disp, 1);
11742 oappend (!addr32flag ? "(%rip)" : "(%eip)");
11743 }
11744 }
11745
11746 if ((havebase || haveindex || needindex || needaddr32 || riprel)
11747 && (address_mode != mode_64bit
11748 || ((bytemode != v_bnd_mode)
11749 && (bytemode != v_bndmk_mode)
11750 && (bytemode != bnd_mode)
11751 && (bytemode != bnd_swap_mode))))
11752 used_prefixes |= PREFIX_ADDR;
11753
11754 if (havedisp || (intel_syntax && riprel))
11755 {
11756 *obufp++ = open_char;
11757 if (intel_syntax && riprel)
11758 {
11759 set_op (disp, 1);
11760 oappend (!addr32flag ? "rip" : "eip");
11761 }
11762 *obufp = '\0';
11763 if (havebase)
11764 oappend (address_mode == mode_64bit && !addr32flag
11765 ? names64[rbase] : names32[rbase]);
11766 if (havesib)
11767 {
11768 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
11769 print index to tell base + index from base. */
11770 if (scale != 0
11771 || needindex
11772 || haveindex
11773 || (havebase && base != ESP_REG_NUM))
11774 {
11775 if (!intel_syntax || havebase)
11776 {
11777 *obufp++ = separator_char;
11778 *obufp = '\0';
11779 }
11780 if (haveindex)
11781 oappend (address_mode == mode_64bit && !addr32flag
11782 ? indexes64[vindex] : indexes32[vindex]);
11783 else
11784 oappend (address_mode == mode_64bit && !addr32flag
11785 ? index64 : index32);
11786
11787 *obufp++ = scale_char;
11788 *obufp = '\0';
11789 sprintf (scratchbuf, "%d", 1 << scale);
11790 oappend (scratchbuf);
11791 }
11792 }
11793 if (intel_syntax
11794 && (disp || modrm.mod != 0 || base == 5))
11795 {
11796 if (!havedisp || (bfd_signed_vma) disp >= 0)
11797 {
11798 *obufp++ = '+';
11799 *obufp = '\0';
11800 }
11801 else if (modrm.mod != 1 && disp != -disp)
11802 {
11803 *obufp++ = '-';
11804 *obufp = '\0';
11805 disp = -disp;
11806 }
11807
11808 if (havedisp)
11809 print_displacement (scratchbuf, disp);
11810 else
11811 print_operand_value (scratchbuf, 1, disp);
11812 oappend (scratchbuf);
11813 }
11814
11815 *obufp++ = close_char;
11816 *obufp = '\0';
11817 }
11818 else if (intel_syntax)
11819 {
11820 if (modrm.mod != 0 || base == 5)
11821 {
11822 if (!active_seg_prefix)
11823 {
11824 oappend (names_seg[ds_reg - es_reg]);
11825 oappend (":");
11826 }
11827 print_operand_value (scratchbuf, 1, disp);
11828 oappend (scratchbuf);
11829 }
11830 }
11831 }
11832 else if (bytemode == v_bnd_mode
11833 || bytemode == v_bndmk_mode
11834 || bytemode == bnd_mode
11835 || bytemode == bnd_swap_mode)
11836 {
11837 oappend ("(bad)");
11838 return;
11839 }
11840 else
11841 {
11842 /* 16 bit address mode */
11843 used_prefixes |= prefixes & PREFIX_ADDR;
11844 switch (modrm.mod)
11845 {
11846 case 0:
11847 if (modrm.rm == 6)
11848 {
11849 disp = get16 ();
11850 if ((disp & 0x8000) != 0)
11851 disp -= 0x10000;
11852 }
11853 break;
11854 case 1:
11855 FETCH_DATA (the_info, codep + 1);
11856 disp = *codep++;
11857 if ((disp & 0x80) != 0)
11858 disp -= 0x100;
11859 if (vex.evex && shift > 0)
11860 disp <<= shift;
11861 break;
11862 case 2:
11863 disp = get16 ();
11864 if ((disp & 0x8000) != 0)
11865 disp -= 0x10000;
11866 break;
11867 }
11868
11869 if (!intel_syntax)
11870 if (modrm.mod != 0 || modrm.rm == 6)
11871 {
11872 print_displacement (scratchbuf, disp);
11873 oappend (scratchbuf);
11874 }
11875
11876 if (modrm.mod != 0 || modrm.rm != 6)
11877 {
11878 *obufp++ = open_char;
11879 *obufp = '\0';
11880 oappend (index16[modrm.rm]);
11881 if (intel_syntax
11882 && (disp || modrm.mod != 0 || modrm.rm == 6))
11883 {
11884 if ((bfd_signed_vma) disp >= 0)
11885 {
11886 *obufp++ = '+';
11887 *obufp = '\0';
11888 }
11889 else if (modrm.mod != 1)
11890 {
11891 *obufp++ = '-';
11892 *obufp = '\0';
11893 disp = -disp;
11894 }
11895
11896 print_displacement (scratchbuf, disp);
11897 oappend (scratchbuf);
11898 }
11899
11900 *obufp++ = close_char;
11901 *obufp = '\0';
11902 }
11903 else if (intel_syntax)
11904 {
11905 if (!active_seg_prefix)
11906 {
11907 oappend (names_seg[ds_reg - es_reg]);
11908 oappend (":");
11909 }
11910 print_operand_value (scratchbuf, 1, disp & 0xffff);
11911 oappend (scratchbuf);
11912 }
11913 }
11914 if (vex.evex && vex.b
11915 && (bytemode == x_mode
11916 || bytemode == xmmq_mode
11917 || bytemode == evex_half_bcst_xmmq_mode))
11918 {
11919 if (vex.w
11920 || bytemode == xmmq_mode
11921 || bytemode == evex_half_bcst_xmmq_mode)
11922 {
11923 switch (vex.length)
11924 {
11925 case 128:
11926 oappend ("{1to2}");
11927 break;
11928 case 256:
11929 oappend ("{1to4}");
11930 break;
11931 case 512:
11932 oappend ("{1to8}");
11933 break;
11934 default:
11935 abort ();
11936 }
11937 }
11938 else
11939 {
11940 switch (vex.length)
11941 {
11942 case 128:
11943 oappend ("{1to4}");
11944 break;
11945 case 256:
11946 oappend ("{1to8}");
11947 break;
11948 case 512:
11949 oappend ("{1to16}");
11950 break;
11951 default:
11952 abort ();
11953 }
11954 }
11955 }
11956 }
11957
11958 static void
11959 OP_E (int bytemode, int sizeflag)
11960 {
11961 /* Skip mod/rm byte. */
11962 MODRM_CHECK;
11963 codep++;
11964
11965 if (modrm.mod == 3)
11966 OP_E_register (bytemode, sizeflag);
11967 else
11968 OP_E_memory (bytemode, sizeflag);
11969 }
11970
11971 static void
11972 OP_G (int bytemode, int sizeflag)
11973 {
11974 int add = 0;
11975 const char **names;
11976 USED_REX (REX_R);
11977 if (rex & REX_R)
11978 add += 8;
11979 switch (bytemode)
11980 {
11981 case b_mode:
11982 if (modrm.reg & 4)
11983 USED_REX (0);
11984 if (rex)
11985 oappend (names8rex[modrm.reg + add]);
11986 else
11987 oappend (names8[modrm.reg + add]);
11988 break;
11989 case w_mode:
11990 oappend (names16[modrm.reg + add]);
11991 break;
11992 case d_mode:
11993 case db_mode:
11994 case dw_mode:
11995 oappend (names32[modrm.reg + add]);
11996 break;
11997 case q_mode:
11998 oappend (names64[modrm.reg + add]);
11999 break;
12000 case bnd_mode:
12001 if (modrm.reg > 0x3)
12002 {
12003 oappend ("(bad)");
12004 return;
12005 }
12006 oappend (names_bnd[modrm.reg]);
12007 break;
12008 case v_mode:
12009 case dq_mode:
12010 case dqb_mode:
12011 case dqd_mode:
12012 case dqw_mode:
12013 case movsxd_mode:
12014 USED_REX (REX_W);
12015 if (rex & REX_W)
12016 oappend (names64[modrm.reg + add]);
12017 else if (bytemode != v_mode && bytemode != movsxd_mode)
12018 oappend (names32[modrm.reg + add]);
12019 else
12020 {
12021 if (sizeflag & DFLAG)
12022 oappend (names32[modrm.reg + add]);
12023 else
12024 oappend (names16[modrm.reg + add]);
12025 used_prefixes |= (prefixes & PREFIX_DATA);
12026 }
12027 break;
12028 case va_mode:
12029 names = (address_mode == mode_64bit
12030 ? names64 : names32);
12031 if (!(prefixes & PREFIX_ADDR))
12032 {
12033 if (address_mode == mode_16bit)
12034 names = names16;
12035 }
12036 else
12037 {
12038 /* Remove "addr16/addr32". */
12039 all_prefixes[last_addr_prefix] = 0;
12040 names = (address_mode != mode_32bit
12041 ? names32 : names16);
12042 used_prefixes |= PREFIX_ADDR;
12043 }
12044 oappend (names[modrm.reg + add]);
12045 break;
12046 case m_mode:
12047 if (address_mode == mode_64bit)
12048 oappend (names64[modrm.reg + add]);
12049 else
12050 oappend (names32[modrm.reg + add]);
12051 break;
12052 case mask_bd_mode:
12053 case mask_mode:
12054 if ((modrm.reg + add) > 0x7)
12055 {
12056 oappend ("(bad)");
12057 return;
12058 }
12059 oappend (names_mask[modrm.reg + add]);
12060 break;
12061 default:
12062 oappend (INTERNAL_DISASSEMBLER_ERROR);
12063 break;
12064 }
12065 }
12066
12067 static bfd_vma
12068 get64 (void)
12069 {
12070 bfd_vma x;
12071 #ifdef BFD64
12072 unsigned int a;
12073 unsigned int b;
12074
12075 FETCH_DATA (the_info, codep + 8);
12076 a = *codep++ & 0xff;
12077 a |= (*codep++ & 0xff) << 8;
12078 a |= (*codep++ & 0xff) << 16;
12079 a |= (*codep++ & 0xffu) << 24;
12080 b = *codep++ & 0xff;
12081 b |= (*codep++ & 0xff) << 8;
12082 b |= (*codep++ & 0xff) << 16;
12083 b |= (*codep++ & 0xffu) << 24;
12084 x = a + ((bfd_vma) b << 32);
12085 #else
12086 abort ();
12087 x = 0;
12088 #endif
12089 return x;
12090 }
12091
12092 static bfd_signed_vma
12093 get32 (void)
12094 {
12095 bfd_vma x = 0;
12096
12097 FETCH_DATA (the_info, codep + 4);
12098 x = *codep++ & (bfd_vma) 0xff;
12099 x |= (*codep++ & (bfd_vma) 0xff) << 8;
12100 x |= (*codep++ & (bfd_vma) 0xff) << 16;
12101 x |= (*codep++ & (bfd_vma) 0xff) << 24;
12102 return x;
12103 }
12104
12105 static bfd_signed_vma
12106 get32s (void)
12107 {
12108 bfd_vma x = 0;
12109
12110 FETCH_DATA (the_info, codep + 4);
12111 x = *codep++ & (bfd_vma) 0xff;
12112 x |= (*codep++ & (bfd_vma) 0xff) << 8;
12113 x |= (*codep++ & (bfd_vma) 0xff) << 16;
12114 x |= (*codep++ & (bfd_vma) 0xff) << 24;
12115
12116 x = (x ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31);
12117
12118 return x;
12119 }
12120
12121 static int
12122 get16 (void)
12123 {
12124 int x = 0;
12125
12126 FETCH_DATA (the_info, codep + 2);
12127 x = *codep++ & 0xff;
12128 x |= (*codep++ & 0xff) << 8;
12129 return x;
12130 }
12131
12132 static void
12133 set_op (bfd_vma op, int riprel)
12134 {
12135 op_index[op_ad] = op_ad;
12136 if (address_mode == mode_64bit)
12137 {
12138 op_address[op_ad] = op;
12139 op_riprel[op_ad] = riprel;
12140 }
12141 else
12142 {
12143 /* Mask to get a 32-bit address. */
12144 op_address[op_ad] = op & 0xffffffff;
12145 op_riprel[op_ad] = riprel & 0xffffffff;
12146 }
12147 }
12148
12149 static void
12150 OP_REG (int code, int sizeflag)
12151 {
12152 const char *s;
12153 int add;
12154
12155 switch (code)
12156 {
12157 case es_reg: case ss_reg: case cs_reg:
12158 case ds_reg: case fs_reg: case gs_reg:
12159 oappend (names_seg[code - es_reg]);
12160 return;
12161 }
12162
12163 USED_REX (REX_B);
12164 if (rex & REX_B)
12165 add = 8;
12166 else
12167 add = 0;
12168
12169 switch (code)
12170 {
12171 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12172 case sp_reg: case bp_reg: case si_reg: case di_reg:
12173 s = names16[code - ax_reg + add];
12174 break;
12175 case ah_reg: case ch_reg: case dh_reg: case bh_reg:
12176 USED_REX (0);
12177 /* Fall through. */
12178 case al_reg: case cl_reg: case dl_reg: case bl_reg:
12179 if (rex)
12180 s = names8rex[code - al_reg + add];
12181 else
12182 s = names8[code - al_reg];
12183 break;
12184 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12185 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12186 if (address_mode == mode_64bit
12187 && ((sizeflag & DFLAG) || (rex & REX_W)))
12188 {
12189 s = names64[code - rAX_reg + add];
12190 break;
12191 }
12192 code += eAX_reg - rAX_reg;
12193 /* Fall through. */
12194 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12195 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12196 USED_REX (REX_W);
12197 if (rex & REX_W)
12198 s = names64[code - eAX_reg + add];
12199 else
12200 {
12201 if (sizeflag & DFLAG)
12202 s = names32[code - eAX_reg + add];
12203 else
12204 s = names16[code - eAX_reg + add];
12205 used_prefixes |= (prefixes & PREFIX_DATA);
12206 }
12207 break;
12208 default:
12209 s = INTERNAL_DISASSEMBLER_ERROR;
12210 break;
12211 }
12212 oappend (s);
12213 }
12214
12215 static void
12216 OP_IMREG (int code, int sizeflag)
12217 {
12218 const char *s;
12219
12220 switch (code)
12221 {
12222 case indir_dx_reg:
12223 if (intel_syntax)
12224 s = "dx";
12225 else
12226 s = "(%dx)";
12227 break;
12228 case al_reg: case cl_reg:
12229 s = names8[code - al_reg];
12230 break;
12231 case eAX_reg:
12232 USED_REX (REX_W);
12233 if (rex & REX_W)
12234 {
12235 s = *names64;
12236 break;
12237 }
12238 /* Fall through. */
12239 case z_mode_ax_reg:
12240 if ((rex & REX_W) || (sizeflag & DFLAG))
12241 s = *names32;
12242 else
12243 s = *names16;
12244 if (!(rex & REX_W))
12245 used_prefixes |= (prefixes & PREFIX_DATA);
12246 break;
12247 default:
12248 s = INTERNAL_DISASSEMBLER_ERROR;
12249 break;
12250 }
12251 oappend (s);
12252 }
12253
12254 static void
12255 OP_I (int bytemode, int sizeflag)
12256 {
12257 bfd_signed_vma op;
12258 bfd_signed_vma mask = -1;
12259
12260 switch (bytemode)
12261 {
12262 case b_mode:
12263 FETCH_DATA (the_info, codep + 1);
12264 op = *codep++;
12265 mask = 0xff;
12266 break;
12267 case v_mode:
12268 USED_REX (REX_W);
12269 if (rex & REX_W)
12270 op = get32s ();
12271 else
12272 {
12273 if (sizeflag & DFLAG)
12274 {
12275 op = get32 ();
12276 mask = 0xffffffff;
12277 }
12278 else
12279 {
12280 op = get16 ();
12281 mask = 0xfffff;
12282 }
12283 used_prefixes |= (prefixes & PREFIX_DATA);
12284 }
12285 break;
12286 case d_mode:
12287 mask = 0xffffffff;
12288 op = get32 ();
12289 break;
12290 case w_mode:
12291 mask = 0xfffff;
12292 op = get16 ();
12293 break;
12294 case const_1_mode:
12295 if (intel_syntax)
12296 oappend ("1");
12297 return;
12298 default:
12299 oappend (INTERNAL_DISASSEMBLER_ERROR);
12300 return;
12301 }
12302
12303 op &= mask;
12304 scratchbuf[0] = '$';
12305 print_operand_value (scratchbuf + 1, 1, op);
12306 oappend_maybe_intel (scratchbuf);
12307 scratchbuf[0] = '\0';
12308 }
12309
12310 static void
12311 OP_I64 (int bytemode, int sizeflag)
12312 {
12313 if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
12314 {
12315 OP_I (bytemode, sizeflag);
12316 return;
12317 }
12318
12319 USED_REX (REX_W);
12320
12321 scratchbuf[0] = '$';
12322 print_operand_value (scratchbuf + 1, 1, get64 ());
12323 oappend_maybe_intel (scratchbuf);
12324 scratchbuf[0] = '\0';
12325 }
12326
12327 static void
12328 OP_sI (int bytemode, int sizeflag)
12329 {
12330 bfd_signed_vma op;
12331
12332 switch (bytemode)
12333 {
12334 case b_mode:
12335 case b_T_mode:
12336 FETCH_DATA (the_info, codep + 1);
12337 op = *codep++;
12338 if ((op & 0x80) != 0)
12339 op -= 0x100;
12340 if (bytemode == b_T_mode)
12341 {
12342 if (address_mode != mode_64bit
12343 || !((sizeflag & DFLAG) || (rex & REX_W)))
12344 {
12345 /* The operand-size prefix is overridden by a REX prefix. */
12346 if ((sizeflag & DFLAG) || (rex & REX_W))
12347 op &= 0xffffffff;
12348 else
12349 op &= 0xffff;
12350 }
12351 }
12352 else
12353 {
12354 if (!(rex & REX_W))
12355 {
12356 if (sizeflag & DFLAG)
12357 op &= 0xffffffff;
12358 else
12359 op &= 0xffff;
12360 }
12361 }
12362 break;
12363 case v_mode:
12364 /* The operand-size prefix is overridden by a REX prefix. */
12365 if ((sizeflag & DFLAG) || (rex & REX_W))
12366 op = get32s ();
12367 else
12368 op = get16 ();
12369 break;
12370 default:
12371 oappend (INTERNAL_DISASSEMBLER_ERROR);
12372 return;
12373 }
12374
12375 scratchbuf[0] = '$';
12376 print_operand_value (scratchbuf + 1, 1, op);
12377 oappend_maybe_intel (scratchbuf);
12378 }
12379
12380 static void
12381 OP_J (int bytemode, int sizeflag)
12382 {
12383 bfd_vma disp;
12384 bfd_vma mask = -1;
12385 bfd_vma segment = 0;
12386
12387 switch (bytemode)
12388 {
12389 case b_mode:
12390 FETCH_DATA (the_info, codep + 1);
12391 disp = *codep++;
12392 if ((disp & 0x80) != 0)
12393 disp -= 0x100;
12394 break;
12395 case v_mode:
12396 case dqw_mode:
12397 if ((sizeflag & DFLAG)
12398 || (address_mode == mode_64bit
12399 && ((isa64 == intel64 && bytemode != dqw_mode)
12400 || (rex & REX_W))))
12401 disp = get32s ();
12402 else
12403 {
12404 disp = get16 ();
12405 if ((disp & 0x8000) != 0)
12406 disp -= 0x10000;
12407 /* In 16bit mode, address is wrapped around at 64k within
12408 the same segment. Otherwise, a data16 prefix on a jump
12409 instruction means that the pc is masked to 16 bits after
12410 the displacement is added! */
12411 mask = 0xffff;
12412 if ((prefixes & PREFIX_DATA) == 0)
12413 segment = ((start_pc + (codep - start_codep))
12414 & ~((bfd_vma) 0xffff));
12415 }
12416 if (address_mode != mode_64bit
12417 || (isa64 != intel64 && !(rex & REX_W)))
12418 used_prefixes |= (prefixes & PREFIX_DATA);
12419 break;
12420 default:
12421 oappend (INTERNAL_DISASSEMBLER_ERROR);
12422 return;
12423 }
12424 disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
12425 set_op (disp, 0);
12426 print_operand_value (scratchbuf, 1, disp);
12427 oappend (scratchbuf);
12428 }
12429
12430 static void
12431 OP_SEG (int bytemode, int sizeflag)
12432 {
12433 if (bytemode == w_mode)
12434 oappend (names_seg[modrm.reg]);
12435 else
12436 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12437 }
12438
12439 static void
12440 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
12441 {
12442 int seg, offset;
12443
12444 if (sizeflag & DFLAG)
12445 {
12446 offset = get32 ();
12447 seg = get16 ();
12448 }
12449 else
12450 {
12451 offset = get16 ();
12452 seg = get16 ();
12453 }
12454 used_prefixes |= (prefixes & PREFIX_DATA);
12455 if (intel_syntax)
12456 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
12457 else
12458 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
12459 oappend (scratchbuf);
12460 }
12461
12462 static void
12463 OP_OFF (int bytemode, int sizeflag)
12464 {
12465 bfd_vma off;
12466
12467 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12468 intel_operand_size (bytemode, sizeflag);
12469 append_seg ();
12470
12471 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12472 off = get32 ();
12473 else
12474 off = get16 ();
12475
12476 if (intel_syntax)
12477 {
12478 if (!active_seg_prefix)
12479 {
12480 oappend (names_seg[ds_reg - es_reg]);
12481 oappend (":");
12482 }
12483 }
12484 print_operand_value (scratchbuf, 1, off);
12485 oappend (scratchbuf);
12486 }
12487
12488 static void
12489 OP_OFF64 (int bytemode, int sizeflag)
12490 {
12491 bfd_vma off;
12492
12493 if (address_mode != mode_64bit
12494 || (prefixes & PREFIX_ADDR))
12495 {
12496 OP_OFF (bytemode, sizeflag);
12497 return;
12498 }
12499
12500 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12501 intel_operand_size (bytemode, sizeflag);
12502 append_seg ();
12503
12504 off = get64 ();
12505
12506 if (intel_syntax)
12507 {
12508 if (!active_seg_prefix)
12509 {
12510 oappend (names_seg[ds_reg - es_reg]);
12511 oappend (":");
12512 }
12513 }
12514 print_operand_value (scratchbuf, 1, off);
12515 oappend (scratchbuf);
12516 }
12517
12518 static void
12519 ptr_reg (int code, int sizeflag)
12520 {
12521 const char *s;
12522
12523 *obufp++ = open_char;
12524 used_prefixes |= (prefixes & PREFIX_ADDR);
12525 if (address_mode == mode_64bit)
12526 {
12527 if (!(sizeflag & AFLAG))
12528 s = names32[code - eAX_reg];
12529 else
12530 s = names64[code - eAX_reg];
12531 }
12532 else if (sizeflag & AFLAG)
12533 s = names32[code - eAX_reg];
12534 else
12535 s = names16[code - eAX_reg];
12536 oappend (s);
12537 *obufp++ = close_char;
12538 *obufp = 0;
12539 }
12540
12541 static void
12542 OP_ESreg (int code, int sizeflag)
12543 {
12544 if (intel_syntax)
12545 {
12546 switch (codep[-1])
12547 {
12548 case 0x6d: /* insw/insl */
12549 intel_operand_size (z_mode, sizeflag);
12550 break;
12551 case 0xa5: /* movsw/movsl/movsq */
12552 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12553 case 0xab: /* stosw/stosl */
12554 case 0xaf: /* scasw/scasl */
12555 intel_operand_size (v_mode, sizeflag);
12556 break;
12557 default:
12558 intel_operand_size (b_mode, sizeflag);
12559 }
12560 }
12561 oappend_maybe_intel ("%es:");
12562 ptr_reg (code, sizeflag);
12563 }
12564
12565 static void
12566 OP_DSreg (int code, int sizeflag)
12567 {
12568 if (intel_syntax)
12569 {
12570 switch (codep[-1])
12571 {
12572 case 0x6f: /* outsw/outsl */
12573 intel_operand_size (z_mode, sizeflag);
12574 break;
12575 case 0xa5: /* movsw/movsl/movsq */
12576 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12577 case 0xad: /* lodsw/lodsl/lodsq */
12578 intel_operand_size (v_mode, sizeflag);
12579 break;
12580 default:
12581 intel_operand_size (b_mode, sizeflag);
12582 }
12583 }
12584 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
12585 default segment register DS is printed. */
12586 if (!active_seg_prefix)
12587 active_seg_prefix = PREFIX_DS;
12588 append_seg ();
12589 ptr_reg (code, sizeflag);
12590 }
12591
12592 static void
12593 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12594 {
12595 int add;
12596 if (rex & REX_R)
12597 {
12598 USED_REX (REX_R);
12599 add = 8;
12600 }
12601 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
12602 {
12603 all_prefixes[last_lock_prefix] = 0;
12604 used_prefixes |= PREFIX_LOCK;
12605 add = 8;
12606 }
12607 else
12608 add = 0;
12609 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
12610 oappend_maybe_intel (scratchbuf);
12611 }
12612
12613 static void
12614 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12615 {
12616 int add;
12617 USED_REX (REX_R);
12618 if (rex & REX_R)
12619 add = 8;
12620 else
12621 add = 0;
12622 if (intel_syntax)
12623 sprintf (scratchbuf, "dr%d", modrm.reg + add);
12624 else
12625 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
12626 oappend (scratchbuf);
12627 }
12628
12629 static void
12630 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12631 {
12632 sprintf (scratchbuf, "%%tr%d", modrm.reg);
12633 oappend_maybe_intel (scratchbuf);
12634 }
12635
12636 static void
12637 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12638 {
12639 int reg = modrm.reg;
12640 const char **names;
12641
12642 used_prefixes |= (prefixes & PREFIX_DATA);
12643 if (prefixes & PREFIX_DATA)
12644 {
12645 names = names_xmm;
12646 USED_REX (REX_R);
12647 if (rex & REX_R)
12648 reg += 8;
12649 }
12650 else
12651 names = names_mm;
12652 oappend (names[reg]);
12653 }
12654
12655 static void
12656 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12657 {
12658 int reg = modrm.reg;
12659 const char **names;
12660
12661 USED_REX (REX_R);
12662 if (rex & REX_R)
12663 reg += 8;
12664 if (vex.evex)
12665 {
12666 if (!vex.r)
12667 reg += 16;
12668 }
12669
12670 if (need_vex
12671 && bytemode != xmm_mode
12672 && bytemode != xmmq_mode
12673 && bytemode != evex_half_bcst_xmmq_mode
12674 && bytemode != ymm_mode
12675 && bytemode != tmm_mode
12676 && bytemode != scalar_mode)
12677 {
12678 switch (vex.length)
12679 {
12680 case 128:
12681 names = names_xmm;
12682 break;
12683 case 256:
12684 if (vex.w
12685 || (bytemode != vex_vsib_q_w_dq_mode
12686 && bytemode != vex_vsib_q_w_d_mode))
12687 names = names_ymm;
12688 else
12689 names = names_xmm;
12690 break;
12691 case 512:
12692 names = names_zmm;
12693 break;
12694 default:
12695 abort ();
12696 }
12697 }
12698 else if (bytemode == xmmq_mode
12699 || bytemode == evex_half_bcst_xmmq_mode)
12700 {
12701 switch (vex.length)
12702 {
12703 case 128:
12704 case 256:
12705 names = names_xmm;
12706 break;
12707 case 512:
12708 names = names_ymm;
12709 break;
12710 default:
12711 abort ();
12712 }
12713 }
12714 else if (bytemode == tmm_mode)
12715 {
12716 modrm.reg = reg;
12717 if (reg >= 8)
12718 {
12719 oappend ("(bad)");
12720 return;
12721 }
12722 names = names_tmm;
12723 }
12724 else if (bytemode == ymm_mode)
12725 names = names_ymm;
12726 else
12727 names = names_xmm;
12728 oappend (names[reg]);
12729 }
12730
12731 static void
12732 OP_EM (int bytemode, int sizeflag)
12733 {
12734 int reg;
12735 const char **names;
12736
12737 if (modrm.mod != 3)
12738 {
12739 if (intel_syntax
12740 && (bytemode == v_mode || bytemode == v_swap_mode))
12741 {
12742 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12743 used_prefixes |= (prefixes & PREFIX_DATA);
12744 }
12745 OP_E (bytemode, sizeflag);
12746 return;
12747 }
12748
12749 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
12750 swap_operand ();
12751
12752 /* Skip mod/rm byte. */
12753 MODRM_CHECK;
12754 codep++;
12755 used_prefixes |= (prefixes & PREFIX_DATA);
12756 reg = modrm.rm;
12757 if (prefixes & PREFIX_DATA)
12758 {
12759 names = names_xmm;
12760 USED_REX (REX_B);
12761 if (rex & REX_B)
12762 reg += 8;
12763 }
12764 else
12765 names = names_mm;
12766 oappend (names[reg]);
12767 }
12768
12769 /* cvt* are the only instructions in sse2 which have
12770 both SSE and MMX operands and also have 0x66 prefix
12771 in their opcode. 0x66 was originally used to differentiate
12772 between SSE and MMX instruction(operands). So we have to handle the
12773 cvt* separately using OP_EMC and OP_MXC */
12774 static void
12775 OP_EMC (int bytemode, int sizeflag)
12776 {
12777 if (modrm.mod != 3)
12778 {
12779 if (intel_syntax && bytemode == v_mode)
12780 {
12781 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12782 used_prefixes |= (prefixes & PREFIX_DATA);
12783 }
12784 OP_E (bytemode, sizeflag);
12785 return;
12786 }
12787
12788 /* Skip mod/rm byte. */
12789 MODRM_CHECK;
12790 codep++;
12791 used_prefixes |= (prefixes & PREFIX_DATA);
12792 oappend (names_mm[modrm.rm]);
12793 }
12794
12795 static void
12796 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12797 {
12798 used_prefixes |= (prefixes & PREFIX_DATA);
12799 oappend (names_mm[modrm.reg]);
12800 }
12801
12802 static void
12803 OP_EX (int bytemode, int sizeflag)
12804 {
12805 int reg;
12806 const char **names;
12807
12808 /* Skip mod/rm byte. */
12809 MODRM_CHECK;
12810 codep++;
12811
12812 if (modrm.mod != 3)
12813 {
12814 OP_E_memory (bytemode, sizeflag);
12815 return;
12816 }
12817
12818 reg = modrm.rm;
12819 USED_REX (REX_B);
12820 if (rex & REX_B)
12821 reg += 8;
12822 if (vex.evex)
12823 {
12824 USED_REX (REX_X);
12825 if ((rex & REX_X))
12826 reg += 16;
12827 }
12828
12829 if ((sizeflag & SUFFIX_ALWAYS)
12830 && (bytemode == x_swap_mode
12831 || bytemode == d_swap_mode
12832 || bytemode == q_swap_mode))
12833 swap_operand ();
12834
12835 if (need_vex
12836 && bytemode != xmm_mode
12837 && bytemode != xmmdw_mode
12838 && bytemode != xmmqd_mode
12839 && bytemode != xmm_mb_mode
12840 && bytemode != xmm_mw_mode
12841 && bytemode != xmm_md_mode
12842 && bytemode != xmm_mq_mode
12843 && bytemode != xmmq_mode
12844 && bytemode != evex_half_bcst_xmmq_mode
12845 && bytemode != ymm_mode
12846 && bytemode != tmm_mode
12847 && bytemode != vex_scalar_w_dq_mode)
12848 {
12849 switch (vex.length)
12850 {
12851 case 128:
12852 names = names_xmm;
12853 break;
12854 case 256:
12855 names = names_ymm;
12856 break;
12857 case 512:
12858 names = names_zmm;
12859 break;
12860 default:
12861 abort ();
12862 }
12863 }
12864 else if (bytemode == xmmq_mode
12865 || bytemode == evex_half_bcst_xmmq_mode)
12866 {
12867 switch (vex.length)
12868 {
12869 case 128:
12870 case 256:
12871 names = names_xmm;
12872 break;
12873 case 512:
12874 names = names_ymm;
12875 break;
12876 default:
12877 abort ();
12878 }
12879 }
12880 else if (bytemode == tmm_mode)
12881 {
12882 modrm.rm = reg;
12883 if (reg >= 8)
12884 {
12885 oappend ("(bad)");
12886 return;
12887 }
12888 names = names_tmm;
12889 }
12890 else if (bytemode == ymm_mode)
12891 names = names_ymm;
12892 else
12893 names = names_xmm;
12894 oappend (names[reg]);
12895 }
12896
12897 static void
12898 OP_MS (int bytemode, int sizeflag)
12899 {
12900 if (modrm.mod == 3)
12901 OP_EM (bytemode, sizeflag);
12902 else
12903 BadOp ();
12904 }
12905
12906 static void
12907 OP_XS (int bytemode, int sizeflag)
12908 {
12909 if (modrm.mod == 3)
12910 OP_EX (bytemode, sizeflag);
12911 else
12912 BadOp ();
12913 }
12914
12915 static void
12916 OP_M (int bytemode, int sizeflag)
12917 {
12918 if (modrm.mod == 3)
12919 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12920 BadOp ();
12921 else
12922 OP_E (bytemode, sizeflag);
12923 }
12924
12925 static void
12926 OP_0f07 (int bytemode, int sizeflag)
12927 {
12928 if (modrm.mod != 3 || modrm.rm != 0)
12929 BadOp ();
12930 else
12931 OP_E (bytemode, sizeflag);
12932 }
12933
12934 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
12935 32bit mode and "xchg %rax,%rax" in 64bit mode. */
12936
12937 static void
12938 NOP_Fixup1 (int bytemode, int sizeflag)
12939 {
12940 if ((prefixes & PREFIX_DATA) != 0
12941 || (rex != 0
12942 && rex != 0x48
12943 && address_mode == mode_64bit))
12944 OP_REG (bytemode, sizeflag);
12945 else
12946 strcpy (obuf, "nop");
12947 }
12948
12949 static void
12950 NOP_Fixup2 (int bytemode, int sizeflag)
12951 {
12952 if ((prefixes & PREFIX_DATA) != 0
12953 || (rex != 0
12954 && rex != 0x48
12955 && address_mode == mode_64bit))
12956 OP_IMREG (bytemode, sizeflag);
12957 }
12958
12959 static const char *const Suffix3DNow[] = {
12960 /* 00 */ NULL, NULL, NULL, NULL,
12961 /* 04 */ NULL, NULL, NULL, NULL,
12962 /* 08 */ NULL, NULL, NULL, NULL,
12963 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
12964 /* 10 */ NULL, NULL, NULL, NULL,
12965 /* 14 */ NULL, NULL, NULL, NULL,
12966 /* 18 */ NULL, NULL, NULL, NULL,
12967 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
12968 /* 20 */ NULL, NULL, NULL, NULL,
12969 /* 24 */ NULL, NULL, NULL, NULL,
12970 /* 28 */ NULL, NULL, NULL, NULL,
12971 /* 2C */ NULL, NULL, NULL, NULL,
12972 /* 30 */ NULL, NULL, NULL, NULL,
12973 /* 34 */ NULL, NULL, NULL, NULL,
12974 /* 38 */ NULL, NULL, NULL, NULL,
12975 /* 3C */ NULL, NULL, NULL, NULL,
12976 /* 40 */ NULL, NULL, NULL, NULL,
12977 /* 44 */ NULL, NULL, NULL, NULL,
12978 /* 48 */ NULL, NULL, NULL, NULL,
12979 /* 4C */ NULL, NULL, NULL, NULL,
12980 /* 50 */ NULL, NULL, NULL, NULL,
12981 /* 54 */ NULL, NULL, NULL, NULL,
12982 /* 58 */ NULL, NULL, NULL, NULL,
12983 /* 5C */ NULL, NULL, NULL, NULL,
12984 /* 60 */ NULL, NULL, NULL, NULL,
12985 /* 64 */ NULL, NULL, NULL, NULL,
12986 /* 68 */ NULL, NULL, NULL, NULL,
12987 /* 6C */ NULL, NULL, NULL, NULL,
12988 /* 70 */ NULL, NULL, NULL, NULL,
12989 /* 74 */ NULL, NULL, NULL, NULL,
12990 /* 78 */ NULL, NULL, NULL, NULL,
12991 /* 7C */ NULL, NULL, NULL, NULL,
12992 /* 80 */ NULL, NULL, NULL, NULL,
12993 /* 84 */ NULL, NULL, NULL, NULL,
12994 /* 88 */ NULL, NULL, "pfnacc", NULL,
12995 /* 8C */ NULL, NULL, "pfpnacc", NULL,
12996 /* 90 */ "pfcmpge", NULL, NULL, NULL,
12997 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
12998 /* 98 */ NULL, NULL, "pfsub", NULL,
12999 /* 9C */ NULL, NULL, "pfadd", NULL,
13000 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
13001 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
13002 /* A8 */ NULL, NULL, "pfsubr", NULL,
13003 /* AC */ NULL, NULL, "pfacc", NULL,
13004 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
13005 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
13006 /* B8 */ NULL, NULL, NULL, "pswapd",
13007 /* BC */ NULL, NULL, NULL, "pavgusb",
13008 /* C0 */ NULL, NULL, NULL, NULL,
13009 /* C4 */ NULL, NULL, NULL, NULL,
13010 /* C8 */ NULL, NULL, NULL, NULL,
13011 /* CC */ NULL, NULL, NULL, NULL,
13012 /* D0 */ NULL, NULL, NULL, NULL,
13013 /* D4 */ NULL, NULL, NULL, NULL,
13014 /* D8 */ NULL, NULL, NULL, NULL,
13015 /* DC */ NULL, NULL, NULL, NULL,
13016 /* E0 */ NULL, NULL, NULL, NULL,
13017 /* E4 */ NULL, NULL, NULL, NULL,
13018 /* E8 */ NULL, NULL, NULL, NULL,
13019 /* EC */ NULL, NULL, NULL, NULL,
13020 /* F0 */ NULL, NULL, NULL, NULL,
13021 /* F4 */ NULL, NULL, NULL, NULL,
13022 /* F8 */ NULL, NULL, NULL, NULL,
13023 /* FC */ NULL, NULL, NULL, NULL,
13024 };
13025
13026 static void
13027 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13028 {
13029 const char *mnemonic;
13030
13031 FETCH_DATA (the_info, codep + 1);
13032 /* AMD 3DNow! instructions are specified by an opcode suffix in the
13033 place where an 8-bit immediate would normally go. ie. the last
13034 byte of the instruction. */
13035 obufp = mnemonicendp;
13036 mnemonic = Suffix3DNow[*codep++ & 0xff];
13037 if (mnemonic)
13038 oappend (mnemonic);
13039 else
13040 {
13041 /* Since a variable sized modrm/sib chunk is between the start
13042 of the opcode (0x0f0f) and the opcode suffix, we need to do
13043 all the modrm processing first, and don't know until now that
13044 we have a bad opcode. This necessitates some cleaning up. */
13045 op_out[0][0] = '\0';
13046 op_out[1][0] = '\0';
13047 BadOp ();
13048 }
13049 mnemonicendp = obufp;
13050 }
13051
13052 static const struct op simd_cmp_op[] =
13053 {
13054 { STRING_COMMA_LEN ("eq") },
13055 { STRING_COMMA_LEN ("lt") },
13056 { STRING_COMMA_LEN ("le") },
13057 { STRING_COMMA_LEN ("unord") },
13058 { STRING_COMMA_LEN ("neq") },
13059 { STRING_COMMA_LEN ("nlt") },
13060 { STRING_COMMA_LEN ("nle") },
13061 { STRING_COMMA_LEN ("ord") }
13062 };
13063
13064 static const struct op vex_cmp_op[] =
13065 {
13066 { STRING_COMMA_LEN ("eq_uq") },
13067 { STRING_COMMA_LEN ("nge") },
13068 { STRING_COMMA_LEN ("ngt") },
13069 { STRING_COMMA_LEN ("false") },
13070 { STRING_COMMA_LEN ("neq_oq") },
13071 { STRING_COMMA_LEN ("ge") },
13072 { STRING_COMMA_LEN ("gt") },
13073 { STRING_COMMA_LEN ("true") },
13074 { STRING_COMMA_LEN ("eq_os") },
13075 { STRING_COMMA_LEN ("lt_oq") },
13076 { STRING_COMMA_LEN ("le_oq") },
13077 { STRING_COMMA_LEN ("unord_s") },
13078 { STRING_COMMA_LEN ("neq_us") },
13079 { STRING_COMMA_LEN ("nlt_uq") },
13080 { STRING_COMMA_LEN ("nle_uq") },
13081 { STRING_COMMA_LEN ("ord_s") },
13082 { STRING_COMMA_LEN ("eq_us") },
13083 { STRING_COMMA_LEN ("nge_uq") },
13084 { STRING_COMMA_LEN ("ngt_uq") },
13085 { STRING_COMMA_LEN ("false_os") },
13086 { STRING_COMMA_LEN ("neq_os") },
13087 { STRING_COMMA_LEN ("ge_oq") },
13088 { STRING_COMMA_LEN ("gt_oq") },
13089 { STRING_COMMA_LEN ("true_us") },
13090 };
13091
13092 static void
13093 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13094 {
13095 unsigned int cmp_type;
13096
13097 FETCH_DATA (the_info, codep + 1);
13098 cmp_type = *codep++ & 0xff;
13099 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
13100 {
13101 char suffix [3];
13102 char *p = mnemonicendp - 2;
13103 suffix[0] = p[0];
13104 suffix[1] = p[1];
13105 suffix[2] = '\0';
13106 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13107 mnemonicendp += simd_cmp_op[cmp_type].len;
13108 }
13109 else if (need_vex
13110 && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
13111 {
13112 char suffix [3];
13113 char *p = mnemonicendp - 2;
13114 suffix[0] = p[0];
13115 suffix[1] = p[1];
13116 suffix[2] = '\0';
13117 cmp_type -= ARRAY_SIZE (simd_cmp_op);
13118 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13119 mnemonicendp += vex_cmp_op[cmp_type].len;
13120 }
13121 else
13122 {
13123 /* We have a reserved extension byte. Output it directly. */
13124 scratchbuf[0] = '$';
13125 print_operand_value (scratchbuf + 1, 1, cmp_type);
13126 oappend_maybe_intel (scratchbuf);
13127 scratchbuf[0] = '\0';
13128 }
13129 }
13130
13131 static void
13132 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13133 {
13134 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
13135 if (!intel_syntax)
13136 {
13137 strcpy (op_out[0], names32[0]);
13138 strcpy (op_out[1], names32[1]);
13139 if (bytemode == eBX_reg)
13140 strcpy (op_out[2], names32[3]);
13141 two_source_ops = 1;
13142 }
13143 /* Skip mod/rm byte. */
13144 MODRM_CHECK;
13145 codep++;
13146 }
13147
13148 static void
13149 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
13150 int sizeflag ATTRIBUTE_UNUSED)
13151 {
13152 /* monitor %{e,r,}ax,%ecx,%edx" */
13153 if (!intel_syntax)
13154 {
13155 const char **names = (address_mode == mode_64bit
13156 ? names64 : names32);
13157
13158 if (prefixes & PREFIX_ADDR)
13159 {
13160 /* Remove "addr16/addr32". */
13161 all_prefixes[last_addr_prefix] = 0;
13162 names = (address_mode != mode_32bit
13163 ? names32 : names16);
13164 used_prefixes |= PREFIX_ADDR;
13165 }
13166 else if (address_mode == mode_16bit)
13167 names = names16;
13168 strcpy (op_out[0], names[0]);
13169 strcpy (op_out[1], names32[1]);
13170 strcpy (op_out[2], names32[2]);
13171 two_source_ops = 1;
13172 }
13173 /* Skip mod/rm byte. */
13174 MODRM_CHECK;
13175 codep++;
13176 }
13177
13178 static void
13179 BadOp (void)
13180 {
13181 /* Throw away prefixes and 1st. opcode byte. */
13182 codep = insn_codep + 1;
13183 oappend ("(bad)");
13184 }
13185
13186 static void
13187 REP_Fixup (int bytemode, int sizeflag)
13188 {
13189 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13190 lods and stos. */
13191 if (prefixes & PREFIX_REPZ)
13192 all_prefixes[last_repz_prefix] = REP_PREFIX;
13193
13194 switch (bytemode)
13195 {
13196 case al_reg:
13197 case eAX_reg:
13198 case indir_dx_reg:
13199 OP_IMREG (bytemode, sizeflag);
13200 break;
13201 case eDI_reg:
13202 OP_ESreg (bytemode, sizeflag);
13203 break;
13204 case eSI_reg:
13205 OP_DSreg (bytemode, sizeflag);
13206 break;
13207 default:
13208 abort ();
13209 break;
13210 }
13211 }
13212
13213 static void
13214 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13215 {
13216 if ( isa64 != amd64 )
13217 return;
13218
13219 obufp = obuf;
13220 BadOp ();
13221 mnemonicendp = obufp;
13222 ++codep;
13223 }
13224
13225 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13226 "bnd". */
13227
13228 static void
13229 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13230 {
13231 if (prefixes & PREFIX_REPNZ)
13232 all_prefixes[last_repnz_prefix] = BND_PREFIX;
13233 }
13234
13235 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13236 "notrack". */
13237
13238 static void
13239 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
13240 int sizeflag ATTRIBUTE_UNUSED)
13241 {
13242
13243 /* Since active_seg_prefix is not set in 64-bit mode, check whether
13244 we've seen a PREFIX_DS. */
13245 if ((prefixes & PREFIX_DS) != 0
13246 && (address_mode != mode_64bit || last_data_prefix < 0))
13247 {
13248 /* NOTRACK prefix is only valid on indirect branch instructions.
13249 NB: DATA prefix is unsupported for Intel64. */
13250 active_seg_prefix = 0;
13251 all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
13252 }
13253 }
13254
13255 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
13256 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13257 */
13258
13259 static void
13260 HLE_Fixup1 (int bytemode, int sizeflag)
13261 {
13262 if (modrm.mod != 3
13263 && (prefixes & PREFIX_LOCK) != 0)
13264 {
13265 if (prefixes & PREFIX_REPZ)
13266 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13267 if (prefixes & PREFIX_REPNZ)
13268 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13269 }
13270
13271 OP_E (bytemode, sizeflag);
13272 }
13273
13274 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
13275 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
13276 */
13277
13278 static void
13279 HLE_Fixup2 (int bytemode, int sizeflag)
13280 {
13281 if (modrm.mod != 3)
13282 {
13283 if (prefixes & PREFIX_REPZ)
13284 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13285 if (prefixes & PREFIX_REPNZ)
13286 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13287 }
13288
13289 OP_E (bytemode, sizeflag);
13290 }
13291
13292 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
13293 "xrelease" for memory operand. No check for LOCK prefix. */
13294
13295 static void
13296 HLE_Fixup3 (int bytemode, int sizeflag)
13297 {
13298 if (modrm.mod != 3
13299 && last_repz_prefix > last_repnz_prefix
13300 && (prefixes & PREFIX_REPZ) != 0)
13301 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13302
13303 OP_E (bytemode, sizeflag);
13304 }
13305
13306 static void
13307 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
13308 {
13309 USED_REX (REX_W);
13310 if (rex & REX_W)
13311 {
13312 /* Change cmpxchg8b to cmpxchg16b. */
13313 char *p = mnemonicendp - 2;
13314 mnemonicendp = stpcpy (p, "16b");
13315 bytemode = o_mode;
13316 }
13317 else if ((prefixes & PREFIX_LOCK) != 0)
13318 {
13319 if (prefixes & PREFIX_REPZ)
13320 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13321 if (prefixes & PREFIX_REPNZ)
13322 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13323 }
13324
13325 OP_M (bytemode, sizeflag);
13326 }
13327
13328 static void
13329 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
13330 {
13331 const char **names;
13332
13333 if (need_vex)
13334 {
13335 switch (vex.length)
13336 {
13337 case 128:
13338 names = names_xmm;
13339 break;
13340 case 256:
13341 names = names_ymm;
13342 break;
13343 default:
13344 abort ();
13345 }
13346 }
13347 else
13348 names = names_xmm;
13349 oappend (names[reg]);
13350 }
13351
13352 static void
13353 FXSAVE_Fixup (int bytemode, int sizeflag)
13354 {
13355 /* Add proper suffix to "fxsave" and "fxrstor". */
13356 USED_REX (REX_W);
13357 if (rex & REX_W)
13358 {
13359 char *p = mnemonicendp;
13360 *p++ = '6';
13361 *p++ = '4';
13362 *p = '\0';
13363 mnemonicendp = p;
13364 }
13365 OP_M (bytemode, sizeflag);
13366 }
13367
13368 /* Display the destination register operand for instructions with
13369 VEX. */
13370
13371 static void
13372 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13373 {
13374 int reg;
13375 const char **names;
13376
13377 if (!need_vex)
13378 abort ();
13379
13380 reg = vex.register_specifier;
13381 vex.register_specifier = 0;
13382 if (address_mode != mode_64bit)
13383 reg &= 7;
13384 else if (vex.evex && !vex.v)
13385 reg += 16;
13386
13387 if (bytemode == vex_scalar_mode)
13388 {
13389 oappend (names_xmm[reg]);
13390 return;
13391 }
13392
13393 if (bytemode == tmm_mode)
13394 {
13395 /* All 3 TMM registers must be distinct. */
13396 if (reg >= 8)
13397 oappend ("(bad)");
13398 else
13399 {
13400 /* This must be the 3rd operand. */
13401 if (obufp != op_out[2])
13402 abort ();
13403 oappend (names_tmm[reg]);
13404 if (reg == modrm.reg || reg == modrm.rm)
13405 strcpy (obufp, "/(bad)");
13406 }
13407
13408 if (modrm.reg == modrm.rm || modrm.reg == reg || modrm.rm == reg)
13409 {
13410 if (modrm.reg <= 8
13411 && (modrm.reg == modrm.rm || modrm.reg == reg))
13412 strcat (op_out[0], "/(bad)");
13413 if (modrm.rm <= 8
13414 && (modrm.rm == modrm.reg || modrm.rm == reg))
13415 strcat (op_out[1], "/(bad)");
13416 }
13417
13418 return;
13419 }
13420
13421 switch (vex.length)
13422 {
13423 case 128:
13424 switch (bytemode)
13425 {
13426 case vex_mode:
13427 case vex_vsib_q_w_dq_mode:
13428 case vex_vsib_q_w_d_mode:
13429 names = names_xmm;
13430 break;
13431 case dq_mode:
13432 if (rex & REX_W)
13433 names = names64;
13434 else
13435 names = names32;
13436 break;
13437 case mask_bd_mode:
13438 case mask_mode:
13439 if (reg > 0x7)
13440 {
13441 oappend ("(bad)");
13442 return;
13443 }
13444 names = names_mask;
13445 break;
13446 default:
13447 abort ();
13448 return;
13449 }
13450 break;
13451 case 256:
13452 switch (bytemode)
13453 {
13454 case vex_mode:
13455 names = names_ymm;
13456 break;
13457 case vex_vsib_q_w_dq_mode:
13458 case vex_vsib_q_w_d_mode:
13459 names = vex.w ? names_ymm : names_xmm;
13460 break;
13461 case mask_bd_mode:
13462 case mask_mode:
13463 if (reg > 0x7)
13464 {
13465 oappend ("(bad)");
13466 return;
13467 }
13468 names = names_mask;
13469 break;
13470 default:
13471 /* See PR binutils/20893 for a reproducer. */
13472 oappend ("(bad)");
13473 return;
13474 }
13475 break;
13476 case 512:
13477 names = names_zmm;
13478 break;
13479 default:
13480 abort ();
13481 break;
13482 }
13483 oappend (names[reg]);
13484 }
13485
13486 static void
13487 OP_VexR (int bytemode, int sizeflag)
13488 {
13489 if (modrm.mod == 3)
13490 OP_VEX (bytemode, sizeflag);
13491 }
13492
13493 static void
13494 OP_VexW (int bytemode, int sizeflag)
13495 {
13496 OP_VEX (bytemode, sizeflag);
13497
13498 if (vex.w)
13499 {
13500 /* Swap 2nd and 3rd operands. */
13501 strcpy (scratchbuf, op_out[2]);
13502 strcpy (op_out[2], op_out[1]);
13503 strcpy (op_out[1], scratchbuf);
13504 }
13505 }
13506
13507 static void
13508 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13509 {
13510 int reg;
13511 const char **names = names_xmm;
13512
13513 FETCH_DATA (the_info, codep + 1);
13514 reg = *codep++;
13515
13516 if (bytemode != x_mode && bytemode != scalar_mode)
13517 abort ();
13518
13519 reg >>= 4;
13520 if (address_mode != mode_64bit)
13521 reg &= 7;
13522
13523 if (bytemode == x_mode && vex.length == 256)
13524 names = names_ymm;
13525
13526 oappend (names[reg]);
13527
13528 if (vex.w)
13529 {
13530 /* Swap 3rd and 4th operands. */
13531 strcpy (scratchbuf, op_out[3]);
13532 strcpy (op_out[3], op_out[2]);
13533 strcpy (op_out[2], scratchbuf);
13534 }
13535 }
13536
13537 static void
13538 OP_VexI4 (int bytemode ATTRIBUTE_UNUSED,
13539 int sizeflag ATTRIBUTE_UNUSED)
13540 {
13541 scratchbuf[0] = '$';
13542 print_operand_value (scratchbuf + 1, 1, codep[-1] & 0xf);
13543 oappend_maybe_intel (scratchbuf);
13544 }
13545
13546 static void
13547 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
13548 int sizeflag ATTRIBUTE_UNUSED)
13549 {
13550 unsigned int cmp_type;
13551
13552 if (!vex.evex)
13553 abort ();
13554
13555 FETCH_DATA (the_info, codep + 1);
13556 cmp_type = *codep++ & 0xff;
13557 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13558 If it's the case, print suffix, otherwise - print the immediate. */
13559 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
13560 && cmp_type != 3
13561 && cmp_type != 7)
13562 {
13563 char suffix [3];
13564 char *p = mnemonicendp - 2;
13565
13566 /* vpcmp* can have both one- and two-lettered suffix. */
13567 if (p[0] == 'p')
13568 {
13569 p++;
13570 suffix[0] = p[0];
13571 suffix[1] = '\0';
13572 }
13573 else
13574 {
13575 suffix[0] = p[0];
13576 suffix[1] = p[1];
13577 suffix[2] = '\0';
13578 }
13579
13580 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13581 mnemonicendp += simd_cmp_op[cmp_type].len;
13582 }
13583 else
13584 {
13585 /* We have a reserved extension byte. Output it directly. */
13586 scratchbuf[0] = '$';
13587 print_operand_value (scratchbuf + 1, 1, cmp_type);
13588 oappend_maybe_intel (scratchbuf);
13589 scratchbuf[0] = '\0';
13590 }
13591 }
13592
13593 static const struct op xop_cmp_op[] =
13594 {
13595 { STRING_COMMA_LEN ("lt") },
13596 { STRING_COMMA_LEN ("le") },
13597 { STRING_COMMA_LEN ("gt") },
13598 { STRING_COMMA_LEN ("ge") },
13599 { STRING_COMMA_LEN ("eq") },
13600 { STRING_COMMA_LEN ("neq") },
13601 { STRING_COMMA_LEN ("false") },
13602 { STRING_COMMA_LEN ("true") }
13603 };
13604
13605 static void
13606 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
13607 int sizeflag ATTRIBUTE_UNUSED)
13608 {
13609 unsigned int cmp_type;
13610
13611 FETCH_DATA (the_info, codep + 1);
13612 cmp_type = *codep++ & 0xff;
13613 if (cmp_type < ARRAY_SIZE (xop_cmp_op))
13614 {
13615 char suffix[3];
13616 char *p = mnemonicendp - 2;
13617
13618 /* vpcom* can have both one- and two-lettered suffix. */
13619 if (p[0] == 'm')
13620 {
13621 p++;
13622 suffix[0] = p[0];
13623 suffix[1] = '\0';
13624 }
13625 else
13626 {
13627 suffix[0] = p[0];
13628 suffix[1] = p[1];
13629 suffix[2] = '\0';
13630 }
13631
13632 sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
13633 mnemonicendp += xop_cmp_op[cmp_type].len;
13634 }
13635 else
13636 {
13637 /* We have a reserved extension byte. Output it directly. */
13638 scratchbuf[0] = '$';
13639 print_operand_value (scratchbuf + 1, 1, cmp_type);
13640 oappend_maybe_intel (scratchbuf);
13641 scratchbuf[0] = '\0';
13642 }
13643 }
13644
13645 static const struct op pclmul_op[] =
13646 {
13647 { STRING_COMMA_LEN ("lql") },
13648 { STRING_COMMA_LEN ("hql") },
13649 { STRING_COMMA_LEN ("lqh") },
13650 { STRING_COMMA_LEN ("hqh") }
13651 };
13652
13653 static void
13654 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
13655 int sizeflag ATTRIBUTE_UNUSED)
13656 {
13657 unsigned int pclmul_type;
13658
13659 FETCH_DATA (the_info, codep + 1);
13660 pclmul_type = *codep++ & 0xff;
13661 switch (pclmul_type)
13662 {
13663 case 0x10:
13664 pclmul_type = 2;
13665 break;
13666 case 0x11:
13667 pclmul_type = 3;
13668 break;
13669 default:
13670 break;
13671 }
13672 if (pclmul_type < ARRAY_SIZE (pclmul_op))
13673 {
13674 char suffix [4];
13675 char *p = mnemonicendp - 3;
13676 suffix[0] = p[0];
13677 suffix[1] = p[1];
13678 suffix[2] = p[2];
13679 suffix[3] = '\0';
13680 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13681 mnemonicendp += pclmul_op[pclmul_type].len;
13682 }
13683 else
13684 {
13685 /* We have a reserved extension byte. Output it directly. */
13686 scratchbuf[0] = '$';
13687 print_operand_value (scratchbuf + 1, 1, pclmul_type);
13688 oappend_maybe_intel (scratchbuf);
13689 scratchbuf[0] = '\0';
13690 }
13691 }
13692
13693 static void
13694 MOVSXD_Fixup (int bytemode, int sizeflag)
13695 {
13696 /* Add proper suffix to "movsxd". */
13697 char *p = mnemonicendp;
13698
13699 switch (bytemode)
13700 {
13701 case movsxd_mode:
13702 if (intel_syntax)
13703 {
13704 *p++ = 'x';
13705 *p++ = 'd';
13706 goto skip;
13707 }
13708
13709 USED_REX (REX_W);
13710 if (rex & REX_W)
13711 {
13712 *p++ = 'l';
13713 *p++ = 'q';
13714 }
13715 else
13716 {
13717 *p++ = 'x';
13718 *p++ = 'd';
13719 }
13720 break;
13721 default:
13722 oappend (INTERNAL_DISASSEMBLER_ERROR);
13723 break;
13724 }
13725
13726 skip:
13727 mnemonicendp = p;
13728 *p = '\0';
13729 OP_E (bytemode, sizeflag);
13730 }
13731
13732 static void
13733 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13734 {
13735 if (!vex.evex
13736 || (bytemode != mask_mode && bytemode != mask_bd_mode))
13737 abort ();
13738
13739 USED_REX (REX_R);
13740 if ((rex & REX_R) != 0 || !vex.r)
13741 {
13742 BadOp ();
13743 return;
13744 }
13745
13746 oappend (names_mask [modrm.reg]);
13747 }
13748
13749 static void
13750 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13751 {
13752 if (modrm.mod == 3 && vex.b)
13753 switch (bytemode)
13754 {
13755 case evex_rounding_64_mode:
13756 if (address_mode != mode_64bit)
13757 {
13758 oappend ("(bad)");
13759 break;
13760 }
13761 /* Fall through. */
13762 case evex_rounding_mode:
13763 oappend (names_rounding[vex.ll]);
13764 break;
13765 case evex_sae_mode:
13766 oappend ("{sae}");
13767 break;
13768 default:
13769 abort ();
13770 break;
13771 }
13772 }
GDB Binutils - Deliverables
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