1 /* Declarations for Intel 80386 opcode table
2 Copyright (C) 2007-2016 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 #include "opcode/i386.h"
30 /* Position of cpu flags bitfiled. */
34 /* i186 or better required */
36 /* i286 or better required */
38 /* i386 or better required */
40 /* i486 or better required */
42 /* i585 or better required */
44 /* i686 or better required */
46 /* CLFLUSH Instruction support required */
48 /* NOP Instruction support required */
50 /* SYSCALL Instructions support required */
52 /* Floating point support required */
54 /* i287 support required */
56 /* i387 support required */
58 /* i686 and floating point support required */
60 /* SSE3 and floating point support required */
62 /* MMX support required */
64 /* SSE support required */
66 /* SSE2 support required */
68 /* 3dnow! support required */
70 /* 3dnow! Extensions support required */
72 /* SSE3 support required */
74 /* VIA PadLock required */
76 /* AMD Secure Virtual Machine Ext-s required */
78 /* VMX Instructions required */
80 /* SMX Instructions required */
82 /* SSSE3 support required */
84 /* SSE4a support required */
86 /* ABM New Instructions required */
88 /* SSE4.1 support required */
90 /* SSE4.2 support required */
92 /* AVX support required */
94 /* AVX2 support required */
96 /* Intel AVX-512 Foundation Instructions support required */
98 /* Intel AVX-512 Conflict Detection Instructions support required */
100 /* Intel AVX-512 Exponential and Reciprocal Instructions support
103 /* Intel AVX-512 Prefetch Instructions support required */
105 /* Intel AVX-512 VL Instructions support required. */
107 /* Intel AVX-512 DQ Instructions support required. */
109 /* Intel AVX-512 BW Instructions support required. */
111 /* Intel L1OM support required */
113 /* Intel K1OM support required */
115 /* Intel IAMCU support required */
117 /* Xsave/xrstor New Instructions support required */
119 /* Xsaveopt New Instructions support required */
121 /* AES support required */
123 /* PCLMUL support required */
125 /* FMA support required */
127 /* FMA4 support required */
129 /* XOP support required */
131 /* LWP support required */
133 /* BMI support required */
135 /* TBM support required */
137 /* MOVBE Instruction support required */
139 /* CMPXCHG16B instruction support required. */
141 /* EPT Instructions required */
143 /* RDTSCP Instruction support required */
145 /* FSGSBASE Instructions required */
147 /* RDRND Instructions required */
149 /* F16C Instructions required */
151 /* Intel BMI2 support required */
153 /* LZCNT support required */
155 /* HLE support required */
157 /* RTM support required */
159 /* INVPCID Instructions required */
161 /* VMFUNC Instruction required */
163 /* Intel MPX Instructions required */
165 /* 64bit support available, used by -march= in assembler. */
167 /* RDRSEED instruction required. */
169 /* Multi-presisionn add-carry instructions are required. */
171 /* Supports prefetchw and prefetch instructions. */
173 /* SMAP instructions required. */
175 /* SHA instructions required. */
177 /* VREX support required */
179 /* CLFLUSHOPT instruction required */
181 /* XSAVES/XRSTORS instruction required */
183 /* XSAVEC instruction required */
185 /* PREFETCHWT1 instruction required */
187 /* SE1 instruction required */
189 /* CLWB instruction required */
191 /* Intel AVX-512 IFMA Instructions support required. */
193 /* Intel AVX-512 VBMI Instructions support required. */
195 /* Intel AVX-512 4FMAPS Instructions support required. */
197 /* mwaitx instruction required */
199 /* Clzero instruction required */
201 /* OSPKE instruction required */
203 /* RDPID instruction required */
205 /* PTWRITE instruction required */
207 /* MMX register support required */
209 /* XMM register support required */
211 /* YMM register support required */
213 /* ZMM register support required */
215 /* Mask register support required */
217 /* 64bit support required */
219 /* Not supported in the 64bit mode */
221 /* The last bitfield in i386_cpu_flags. */
225 #define CpuNumOfUints \
226 (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
227 #define CpuNumOfBits \
228 (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
230 /* If you get a compiler error for zero width of the unused field,
232 #define CpuUnused (CpuMax + 1)
234 /* We can check if an instruction is available with array instead
236 typedef union i386_cpu_flags
240 unsigned int cpui186
:1;
241 unsigned int cpui286
:1;
242 unsigned int cpui386
:1;
243 unsigned int cpui486
:1;
244 unsigned int cpui586
:1;
245 unsigned int cpui686
:1;
246 unsigned int cpuclflush
:1;
247 unsigned int cpunop
:1;
248 unsigned int cpusyscall
:1;
249 unsigned int cpu8087
:1;
250 unsigned int cpu287
:1;
251 unsigned int cpu387
:1;
252 unsigned int cpu687
:1;
253 unsigned int cpufisttp
:1;
254 unsigned int cpummx
:1;
255 unsigned int cpusse
:1;
256 unsigned int cpusse2
:1;
257 unsigned int cpua3dnow
:1;
258 unsigned int cpua3dnowa
:1;
259 unsigned int cpusse3
:1;
260 unsigned int cpupadlock
:1;
261 unsigned int cpusvme
:1;
262 unsigned int cpuvmx
:1;
263 unsigned int cpusmx
:1;
264 unsigned int cpussse3
:1;
265 unsigned int cpusse4a
:1;
266 unsigned int cpuabm
:1;
267 unsigned int cpusse4_1
:1;
268 unsigned int cpusse4_2
:1;
269 unsigned int cpuavx
:1;
270 unsigned int cpuavx2
:1;
271 unsigned int cpuavx512f
:1;
272 unsigned int cpuavx512cd
:1;
273 unsigned int cpuavx512er
:1;
274 unsigned int cpuavx512pf
:1;
275 unsigned int cpuavx512vl
:1;
276 unsigned int cpuavx512dq
:1;
277 unsigned int cpuavx512bw
:1;
278 unsigned int cpul1om
:1;
279 unsigned int cpuk1om
:1;
280 unsigned int cpuiamcu
:1;
281 unsigned int cpuxsave
:1;
282 unsigned int cpuxsaveopt
:1;
283 unsigned int cpuaes
:1;
284 unsigned int cpupclmul
:1;
285 unsigned int cpufma
:1;
286 unsigned int cpufma4
:1;
287 unsigned int cpuxop
:1;
288 unsigned int cpulwp
:1;
289 unsigned int cpubmi
:1;
290 unsigned int cputbm
:1;
291 unsigned int cpumovbe
:1;
292 unsigned int cpucx16
:1;
293 unsigned int cpuept
:1;
294 unsigned int cpurdtscp
:1;
295 unsigned int cpufsgsbase
:1;
296 unsigned int cpurdrnd
:1;
297 unsigned int cpuf16c
:1;
298 unsigned int cpubmi2
:1;
299 unsigned int cpulzcnt
:1;
300 unsigned int cpuhle
:1;
301 unsigned int cpurtm
:1;
302 unsigned int cpuinvpcid
:1;
303 unsigned int cpuvmfunc
:1;
304 unsigned int cpumpx
:1;
305 unsigned int cpulm
:1;
306 unsigned int cpurdseed
:1;
307 unsigned int cpuadx
:1;
308 unsigned int cpuprfchw
:1;
309 unsigned int cpusmap
:1;
310 unsigned int cpusha
:1;
311 unsigned int cpuvrex
:1;
312 unsigned int cpuclflushopt
:1;
313 unsigned int cpuxsaves
:1;
314 unsigned int cpuxsavec
:1;
315 unsigned int cpuprefetchwt1
:1;
316 unsigned int cpuse1
:1;
317 unsigned int cpuclwb
:1;
318 unsigned int cpuavx512ifma
:1;
319 unsigned int cpuavx512vbmi
:1;
320 unsigned int cpuavx512_4fmaps
:1;
321 unsigned int cpumwaitx
:1;
322 unsigned int cpuclzero
:1;
323 unsigned int cpuospke
:1;
324 unsigned int cpurdpid
:1;
325 unsigned int cpuptwrite
:1;
326 unsigned int cpuregmmx
:1;
327 unsigned int cpuregxmm
:1;
328 unsigned int cpuregymm
:1;
329 unsigned int cpuregzmm
:1;
330 unsigned int cpuregmask
:1;
331 unsigned int cpu64
:1;
332 unsigned int cpuno64
:1;
334 unsigned int unused
:(CpuNumOfBits
- CpuUnused
);
337 unsigned int array
[CpuNumOfUints
];
340 /* Position of opcode_modifier bits. */
344 /* has direction bit. */
346 /* set if operands can be words or dwords encoded the canonical way */
348 /* Skip the current insn and use the next insn in i386-opc.tbl to swap
349 operand in encoding. */
351 /* insn has a modrm byte. */
353 /* register is in low 3 bits of opcode */
355 /* special case for jump insns. */
361 /* special case for intersegment leaps/calls */
363 /* FP insn memory format bit, sized by 0x4 */
365 /* src/dest swap for floats. */
367 /* has float insn direction bit. */
369 /* needs size prefix if in 32-bit mode */
371 /* needs size prefix if in 16-bit mode */
373 /* needs size prefix if in 64-bit mode */
375 /* check register size. */
377 /* instruction ignores operand size prefix and in Intel mode ignores
378 mnemonic size suffix check. */
380 /* default insn size depends on mode */
382 /* b suffix on instruction illegal */
384 /* w suffix on instruction illegal */
386 /* l suffix on instruction illegal */
388 /* s suffix on instruction illegal */
390 /* q suffix on instruction illegal */
392 /* long double suffix on instruction illegal */
394 /* instruction needs FWAIT */
396 /* quick test for string instructions */
398 /* quick test if branch instruction is MPX supported */
400 /* quick test for lockable instructions */
402 /* fake an extra reg operand for clr, imul and special register
403 processing for some instructions. */
405 /* The first operand must be xmm0 */
407 /* An implicit xmm0 as the first operand */
409 /* The HLE prefix is OK:
410 1. With a LOCK prefix.
411 2. With or without a LOCK prefix.
412 3. With a RELEASE (0xf3) prefix.
414 #define HLEPrefixNone 0
415 #define HLEPrefixLock 1
416 #define HLEPrefixAny 2
417 #define HLEPrefixRelease 3
419 /* An instruction on which a "rep" prefix is acceptable. */
421 /* Convert to DWORD */
423 /* Convert to QWORD */
425 /* Address prefix changes operand 0 */
427 /* opcode is a prefix */
429 /* instruction has extension in 8 bit imm */
431 /* instruction don't need Rex64 prefix. */
433 /* instruction require Rex64 prefix. */
435 /* deprecated fp insn, gets a warning */
437 /* insn has VEX prefix:
438 1: 128bit VEX prefix.
439 2: 256bit VEX prefix.
440 3: Scalar VEX prefix.
446 /* How to encode VEX.vvvv:
447 0: VEX.vvvv must be 1111b.
448 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where
449 the content of source registers will be preserved.
450 VEX.DDS. The second register operand is encoded in VEX.vvvv
451 where the content of first source register will be overwritten
453 VEX.NDD2. The second destination register operand is encoded in
454 VEX.vvvv for instructions with 2 destination register operands.
455 For assembler, there are no difference between VEX.NDS, VEX.DDS
457 2. VEX.NDD. Register destination is encoded in VEX.vvvv for
458 instructions with 1 destination register operand.
459 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one
460 of the operands can access a memory location.
466 /* How the VEX.W bit is used:
467 0: Set by the REX.W bit.
468 1: VEX.W0. Should always be 0.
469 2: VEX.W1. Should always be 1.
474 /* VEX opcode prefix:
475 0: VEX 0x0F opcode prefix.
476 1: VEX 0x0F38 opcode prefix.
477 2: VEX 0x0F3A opcode prefix
478 3: XOP 0x08 opcode prefix.
479 4: XOP 0x09 opcode prefix
480 5: XOP 0x0A opcode prefix.
489 /* number of VEX source operands:
490 0: <= 2 source operands.
491 1: 2 XOP source operands.
492 2: 3 source operands.
494 #define XOP2SOURCES 1
495 #define VEX3SOURCES 2
497 /* instruction has VEX 8 bit imm */
499 /* Instruction with vector SIB byte:
500 1: 128bit vector register.
501 2: 256bit vector register.
502 3: 512bit vector register.
508 /* SSE to AVX support required */
510 /* No AVX equivalent */
513 /* insn has EVEX prefix:
514 1: 512bit EVEX prefix.
515 2: 128bit EVEX prefix.
516 3: 256bit EVEX prefix.
517 4: Length-ignored (LIG) EVEX prefix.
525 /* AVX512 masking support:
528 3: Both zeroing and merging masking.
530 #define ZEROING_MASKING 1
531 #define MERGING_MASKING 2
532 #define BOTH_MASKING 3
535 /* Input element size of vector insn:
546 #define NO_BROADCAST 0
547 #define BROADCAST_1TO16 1
548 #define BROADCAST_1TO8 2
549 #define BROADCAST_1TO4 3
550 #define BROADCAST_1TO2 4
553 /* Static rounding control is supported. */
556 /* Supress All Exceptions is supported. */
559 /* Copressed Disp8*N attribute. */
562 /* Default mask isn't allowed. */
565 /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
566 It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
570 /* Compatible with old (<= 2.8.1) versions of gcc */
582 /* The last bitfield in i386_opcode_modifier. */
586 typedef struct i386_opcode_modifier
591 unsigned int modrm
:1;
592 unsigned int shortform
:1;
594 unsigned int jumpdword
:1;
595 unsigned int jumpbyte
:1;
596 unsigned int jumpintersegment
:1;
597 unsigned int floatmf
:1;
598 unsigned int floatr
:1;
599 unsigned int floatd
:1;
600 unsigned int size16
:1;
601 unsigned int size32
:1;
602 unsigned int size64
:1;
603 unsigned int checkregsize
:1;
604 unsigned int ignoresize
:1;
605 unsigned int defaultsize
:1;
606 unsigned int no_bsuf
:1;
607 unsigned int no_wsuf
:1;
608 unsigned int no_lsuf
:1;
609 unsigned int no_ssuf
:1;
610 unsigned int no_qsuf
:1;
611 unsigned int no_ldsuf
:1;
612 unsigned int fwait
:1;
613 unsigned int isstring
:1;
614 unsigned int bndprefixok
:1;
615 unsigned int islockable
:1;
616 unsigned int regkludge
:1;
617 unsigned int firstxmm0
:1;
618 unsigned int implicit1stxmm0
:1;
619 unsigned int hleprefixok
:2;
620 unsigned int repprefixok
:1;
621 unsigned int todword
:1;
622 unsigned int toqword
:1;
623 unsigned int addrprefixop0
:1;
624 unsigned int isprefix
:1;
625 unsigned int immext
:1;
626 unsigned int norex64
:1;
627 unsigned int rex64
:1;
630 unsigned int vexvvvv
:2;
632 unsigned int vexopcode
:3;
633 unsigned int vexsources
:2;
634 unsigned int veximmext
:1;
635 unsigned int vecsib
:2;
636 unsigned int sse2avx
:1;
637 unsigned int noavx
:1;
639 unsigned int masking
:2;
640 unsigned int vecesize
:1;
641 unsigned int broadcast
:3;
642 unsigned int staticrounding
:1;
644 unsigned int disp8memshift
:3;
645 unsigned int nodefmask
:1;
646 unsigned int implicitquadgroup
:1;
647 unsigned int oldgcc
:1;
648 unsigned int attmnemonic
:1;
649 unsigned int attsyntax
:1;
650 unsigned int intelsyntax
:1;
651 unsigned int amd64
:1;
652 unsigned int intel64
:1;
653 } i386_opcode_modifier
;
655 /* Position of operand_type bits. */
667 /* Floating pointer stack register */
675 /* AVX512 registers */
677 /* Vector Mask registers */
679 /* Control register */
685 /* 2 bit segment register */
687 /* 3 bit segment register */
689 /* 1 bit immediate */
691 /* 8 bit immediate */
693 /* 8 bit immediate sign extended */
695 /* 16 bit immediate */
697 /* 32 bit immediate */
699 /* 32 bit immediate sign extended */
701 /* 64 bit immediate */
703 /* 8bit/16bit/32bit displacements are used in different ways,
704 depending on the instruction. For jumps, they specify the
705 size of the PC relative displacement, for instructions with
706 memory operand, they specify the size of the offset relative
707 to the base register, and for instructions with memory offset
708 such as `mov 1234,%al' they specify the size of the offset
709 relative to the segment base. */
710 /* 8 bit displacement */
712 /* 16 bit displacement */
714 /* 32 bit displacement */
716 /* 32 bit signed displacement */
718 /* 64 bit displacement */
720 /* Accumulator %al/%ax/%eax/%rax */
722 /* Floating pointer top stack register %st(0) */
724 /* Register which can be used for base or index in memory operand. */
726 /* Register to hold in/out port addr = dx */
728 /* Register to hold shift count = cl */
730 /* Absolute address for jump. */
732 /* String insn operand with fixed es segment */
734 /* RegMem is for instructions with a modrm byte where the register
735 destination operand should be encoded in the mod and regmem fields.
736 Normally, it will be encoded in the reg field. We add a RegMem
737 flag to the destination register operand to indicate that it should
738 be encoded in the regmem field. */
744 /* WORD memory. 2 byte */
746 /* DWORD memory. 4 byte */
748 /* FWORD memory. 6 byte */
750 /* QWORD memory. 8 byte */
752 /* TBYTE memory. 10 byte */
754 /* XMMWORD memory. */
756 /* YMMWORD memory. */
758 /* ZMMWORD memory. */
760 /* Unspecified memory size. */
762 /* Any memory size. */
765 /* Vector 4 bit immediate. */
768 /* Bound register. */
771 /* Vector 8bit displacement */
774 /* The last bitfield in i386_operand_type. */
778 #define OTNumOfUints \
779 (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
780 #define OTNumOfBits \
781 (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
783 /* If you get a compiler error for zero width of the unused field,
785 #define OTUnused (OTMax + 1)
787 typedef union i386_operand_type
792 unsigned int reg16
:1;
793 unsigned int reg32
:1;
794 unsigned int reg64
:1;
795 unsigned int floatreg
:1;
796 unsigned int regmmx
:1;
797 unsigned int regxmm
:1;
798 unsigned int regymm
:1;
799 unsigned int regzmm
:1;
800 unsigned int regmask
:1;
801 unsigned int control
:1;
802 unsigned int debug
:1;
804 unsigned int sreg2
:1;
805 unsigned int sreg3
:1;
808 unsigned int imm8s
:1;
809 unsigned int imm16
:1;
810 unsigned int imm32
:1;
811 unsigned int imm32s
:1;
812 unsigned int imm64
:1;
813 unsigned int disp8
:1;
814 unsigned int disp16
:1;
815 unsigned int disp32
:1;
816 unsigned int disp32s
:1;
817 unsigned int disp64
:1;
819 unsigned int floatacc
:1;
820 unsigned int baseindex
:1;
821 unsigned int inoutportreg
:1;
822 unsigned int shiftcount
:1;
823 unsigned int jumpabsolute
:1;
824 unsigned int esseg
:1;
825 unsigned int regmem
:1;
829 unsigned int dword
:1;
830 unsigned int fword
:1;
831 unsigned int qword
:1;
832 unsigned int tbyte
:1;
833 unsigned int xmmword
:1;
834 unsigned int ymmword
:1;
835 unsigned int zmmword
:1;
836 unsigned int unspecified
:1;
837 unsigned int anysize
:1;
838 unsigned int vec_imm4
:1;
839 unsigned int regbnd
:1;
840 unsigned int vec_disp8
:1;
842 unsigned int unused
:(OTNumOfBits
- OTUnused
);
845 unsigned int array
[OTNumOfUints
];
848 typedef struct insn_template
850 /* instruction name sans width suffix ("mov" for movl insns) */
853 /* how many operands */
854 unsigned int operands
;
856 /* base_opcode is the fundamental opcode byte without optional
858 unsigned int base_opcode
;
859 #define Opcode_D 0x2 /* Direction bit:
860 set if Reg --> Regmem;
861 unset if Regmem --> Reg. */
862 #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
863 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
865 /* extension_opcode is the 3 bit extension for group <n> insns.
866 This field is also used to store the 8-bit opcode suffix for the
867 AMD 3DNow! instructions.
868 If this template has no extension opcode (the usual case) use None
870 unsigned int extension_opcode
;
871 #define None 0xffff /* If no extension_opcode is possible. */
874 unsigned char opcode_length
;
876 /* cpu feature flags */
877 i386_cpu_flags cpu_flags
;
879 /* the bits in opcode_modifier are used to generate the final opcode from
880 the base_opcode. These bits also are used to detect alternate forms of
881 the same instruction */
882 i386_opcode_modifier opcode_modifier
;
884 /* operand_types[i] describes the type of operand i. This is made
885 by OR'ing together all of the possible type masks. (e.g.
886 'operand_types[i] = Reg|Imm' specifies that operand i can be
887 either a register or an immediate operand. */
888 i386_operand_type operand_types
[MAX_OPERANDS
];
892 extern const insn_template i386_optab
[];
894 /* these are for register name --> number & type hash lookup */
898 i386_operand_type reg_type
;
899 unsigned char reg_flags
;
900 #define RegRex 0x1 /* Extended register. */
901 #define RegRex64 0x2 /* Extended 8 bit register. */
902 #define RegVRex 0x4 /* Extended vector register. */
903 unsigned char reg_num
;
904 #define RegRip ((unsigned char ) ~0)
905 #define RegEip (RegRip - 1)
906 /* EIZ and RIZ are fake index registers. */
907 #define RegEiz (RegEip - 1)
908 #define RegRiz (RegEiz - 1)
909 /* FLAT is a fake segment register (Intel mode). */
910 #define RegFlat ((unsigned char) ~0)
911 signed char dw2_regnum
[2];
912 #define Dw2Inval (-1)
916 /* Entries in i386_regtab. */
919 #define REGNAM_EAX 41
921 extern const reg_entry i386_regtab
[];
922 extern const unsigned int i386_regtab_size
;
927 unsigned int seg_prefix
;
931 extern const seg_entry cs
;
932 extern const seg_entry ds
;
933 extern const seg_entry ss
;
934 extern const seg_entry es
;
935 extern const seg_entry fs
;
936 extern const seg_entry gs
;