1 /* Declarations for Intel 80386 opcode table
2 Copyright (C) 2007-2018 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 #include "opcode/i386.h"
30 /* Position of cpu flags bitfiled. */
34 /* i186 or better required */
36 /* i286 or better required */
38 /* i386 or better required */
40 /* i486 or better required */
42 /* i585 or better required */
44 /* i686 or better required */
46 /* CMOV Instruction support required */
48 /* FXSR Instruction support required */
50 /* CLFLUSH Instruction support required */
52 /* NOP Instruction support required */
54 /* SYSCALL Instructions support required */
56 /* Floating point support required */
58 /* i287 support required */
60 /* i387 support required */
62 /* i686 and floating point support required */
64 /* SSE3 and floating point support required */
66 /* MMX support required */
68 /* SSE support required */
70 /* SSE2 support required */
72 /* 3dnow! support required */
74 /* 3dnow! Extensions support required */
76 /* SSE3 support required */
78 /* VIA PadLock required */
80 /* AMD Secure Virtual Machine Ext-s required */
82 /* VMX Instructions required */
84 /* SMX Instructions required */
86 /* SSSE3 support required */
88 /* SSE4a support required */
90 /* ABM New Instructions required */
92 /* SSE4.1 support required */
94 /* SSE4.2 support required */
96 /* AVX support required */
98 /* AVX2 support required */
100 /* Intel AVX-512 Foundation Instructions support required */
102 /* Intel AVX-512 Conflict Detection Instructions support required */
104 /* Intel AVX-512 Exponential and Reciprocal Instructions support
107 /* Intel AVX-512 Prefetch Instructions support required */
109 /* Intel AVX-512 VL Instructions support required. */
111 /* Intel AVX-512 DQ Instructions support required. */
113 /* Intel AVX-512 BW Instructions support required. */
115 /* Intel L1OM support required */
117 /* Intel K1OM support required */
119 /* Intel IAMCU support required */
121 /* Xsave/xrstor New Instructions support required */
123 /* Xsaveopt New Instructions support required */
125 /* AES support required */
127 /* PCLMUL support required */
129 /* FMA support required */
131 /* FMA4 support required */
133 /* XOP support required */
135 /* LWP support required */
137 /* BMI support required */
139 /* TBM support required */
141 /* MOVBE Instruction support required */
143 /* CMPXCHG16B instruction support required. */
145 /* EPT Instructions required */
147 /* RDTSCP Instruction support required */
149 /* FSGSBASE Instructions required */
151 /* RDRND Instructions required */
153 /* F16C Instructions required */
155 /* Intel BMI2 support required */
157 /* LZCNT support required */
159 /* HLE support required */
161 /* RTM support required */
163 /* INVPCID Instructions required */
165 /* VMFUNC Instruction required */
167 /* Intel MPX Instructions required */
169 /* 64bit support available, used by -march= in assembler. */
171 /* RDRSEED instruction required. */
173 /* Multi-presisionn add-carry instructions are required. */
175 /* Supports prefetchw and prefetch instructions. */
177 /* SMAP instructions required. */
179 /* SHA instructions required. */
181 /* CLFLUSHOPT instruction required */
183 /* XSAVES/XRSTORS instruction required */
185 /* XSAVEC instruction required */
187 /* PREFETCHWT1 instruction required */
189 /* SE1 instruction required */
191 /* CLWB instruction required */
193 /* Intel AVX-512 IFMA Instructions support required. */
195 /* Intel AVX-512 VBMI Instructions support required. */
197 /* Intel AVX-512 4FMAPS Instructions support required. */
199 /* Intel AVX-512 4VNNIW Instructions support required. */
201 /* Intel AVX-512 VPOPCNTDQ Instructions support required. */
203 /* Intel AVX-512 VBMI2 Instructions support required. */
205 /* Intel AVX-512 VNNI Instructions support required. */
207 /* Intel AVX-512 BITALG Instructions support required. */
209 /* mwaitx instruction required */
211 /* Clzero instruction required */
213 /* OSPKE instruction required */
215 /* RDPID instruction required */
217 /* PTWRITE instruction required */
219 /* CET instructions support required */
222 /* GFNI instructions required */
224 /* VAES instructions required */
226 /* VPCLMULQDQ instructions required */
228 /* WBNOINVD instructions required */
230 /* PCONFIG instructions required */
232 /* WAITPKG instructions required */
234 /* CLDEMOTE instruction required */
236 /* MOVDIRI instruction support required */
238 /* MOVDIRR64B instruction required */
240 /* 64bit support required */
242 /* Not supported in the 64bit mode */
244 /* The last bitfield in i386_cpu_flags. */
248 #define CpuNumOfUints \
249 (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
250 #define CpuNumOfBits \
251 (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
253 /* If you get a compiler error for zero width of the unused field,
255 #define CpuUnused (CpuMax + 1)
257 /* We can check if an instruction is available with array instead
259 typedef union i386_cpu_flags
263 unsigned int cpui186
:1;
264 unsigned int cpui286
:1;
265 unsigned int cpui386
:1;
266 unsigned int cpui486
:1;
267 unsigned int cpui586
:1;
268 unsigned int cpui686
:1;
269 unsigned int cpucmov
:1;
270 unsigned int cpufxsr
:1;
271 unsigned int cpuclflush
:1;
272 unsigned int cpunop
:1;
273 unsigned int cpusyscall
:1;
274 unsigned int cpu8087
:1;
275 unsigned int cpu287
:1;
276 unsigned int cpu387
:1;
277 unsigned int cpu687
:1;
278 unsigned int cpufisttp
:1;
279 unsigned int cpummx
:1;
280 unsigned int cpusse
:1;
281 unsigned int cpusse2
:1;
282 unsigned int cpua3dnow
:1;
283 unsigned int cpua3dnowa
:1;
284 unsigned int cpusse3
:1;
285 unsigned int cpupadlock
:1;
286 unsigned int cpusvme
:1;
287 unsigned int cpuvmx
:1;
288 unsigned int cpusmx
:1;
289 unsigned int cpussse3
:1;
290 unsigned int cpusse4a
:1;
291 unsigned int cpuabm
:1;
292 unsigned int cpusse4_1
:1;
293 unsigned int cpusse4_2
:1;
294 unsigned int cpuavx
:1;
295 unsigned int cpuavx2
:1;
296 unsigned int cpuavx512f
:1;
297 unsigned int cpuavx512cd
:1;
298 unsigned int cpuavx512er
:1;
299 unsigned int cpuavx512pf
:1;
300 unsigned int cpuavx512vl
:1;
301 unsigned int cpuavx512dq
:1;
302 unsigned int cpuavx512bw
:1;
303 unsigned int cpul1om
:1;
304 unsigned int cpuk1om
:1;
305 unsigned int cpuiamcu
:1;
306 unsigned int cpuxsave
:1;
307 unsigned int cpuxsaveopt
:1;
308 unsigned int cpuaes
:1;
309 unsigned int cpupclmul
:1;
310 unsigned int cpufma
:1;
311 unsigned int cpufma4
:1;
312 unsigned int cpuxop
:1;
313 unsigned int cpulwp
:1;
314 unsigned int cpubmi
:1;
315 unsigned int cputbm
:1;
316 unsigned int cpumovbe
:1;
317 unsigned int cpucx16
:1;
318 unsigned int cpuept
:1;
319 unsigned int cpurdtscp
:1;
320 unsigned int cpufsgsbase
:1;
321 unsigned int cpurdrnd
:1;
322 unsigned int cpuf16c
:1;
323 unsigned int cpubmi2
:1;
324 unsigned int cpulzcnt
:1;
325 unsigned int cpuhle
:1;
326 unsigned int cpurtm
:1;
327 unsigned int cpuinvpcid
:1;
328 unsigned int cpuvmfunc
:1;
329 unsigned int cpumpx
:1;
330 unsigned int cpulm
:1;
331 unsigned int cpurdseed
:1;
332 unsigned int cpuadx
:1;
333 unsigned int cpuprfchw
:1;
334 unsigned int cpusmap
:1;
335 unsigned int cpusha
:1;
336 unsigned int cpuclflushopt
:1;
337 unsigned int cpuxsaves
:1;
338 unsigned int cpuxsavec
:1;
339 unsigned int cpuprefetchwt1
:1;
340 unsigned int cpuse1
:1;
341 unsigned int cpuclwb
:1;
342 unsigned int cpuavx512ifma
:1;
343 unsigned int cpuavx512vbmi
:1;
344 unsigned int cpuavx512_4fmaps
:1;
345 unsigned int cpuavx512_4vnniw
:1;
346 unsigned int cpuavx512_vpopcntdq
:1;
347 unsigned int cpuavx512_vbmi2
:1;
348 unsigned int cpuavx512_vnni
:1;
349 unsigned int cpuavx512_bitalg
:1;
350 unsigned int cpumwaitx
:1;
351 unsigned int cpuclzero
:1;
352 unsigned int cpuospke
:1;
353 unsigned int cpurdpid
:1;
354 unsigned int cpuptwrite
:1;
355 unsigned int cpuibt
:1;
356 unsigned int cpushstk
:1;
357 unsigned int cpugfni
:1;
358 unsigned int cpuvaes
:1;
359 unsigned int cpuvpclmulqdq
:1;
360 unsigned int cpuwbnoinvd
:1;
361 unsigned int cpupconfig
:1;
362 unsigned int cpuwaitpkg
:1;
363 unsigned int cpucldemote
:1;
364 unsigned int cpumovdiri
:1;
365 unsigned int cpumovdir64b
:1;
366 unsigned int cpu64
:1;
367 unsigned int cpuno64
:1;
369 unsigned int unused
:(CpuNumOfBits
- CpuUnused
);
372 unsigned int array
[CpuNumOfUints
];
375 /* Position of opcode_modifier bits. */
379 /* has direction bit. */
381 /* set if operands can be words or dwords encoded the canonical way */
383 /* load form instruction. Must be placed before store form. */
385 /* insn has a modrm byte. */
387 /* register is in low 3 bits of opcode */
389 /* special case for jump insns. */
395 /* special case for intersegment leaps/calls */
397 /* FP insn memory format bit, sized by 0x4 */
399 /* src/dest swap for floats. */
401 /* needs size prefix if in 32-bit mode */
403 /* needs size prefix if in 16-bit mode */
405 /* needs size prefix if in 64-bit mode */
407 /* check register size. */
409 /* instruction ignores operand size prefix and in Intel mode ignores
410 mnemonic size suffix check. */
412 /* default insn size depends on mode */
414 /* b suffix on instruction illegal */
416 /* w suffix on instruction illegal */
418 /* l suffix on instruction illegal */
420 /* s suffix on instruction illegal */
422 /* q suffix on instruction illegal */
424 /* long double suffix on instruction illegal */
426 /* instruction needs FWAIT */
428 /* quick test for string instructions */
430 /* quick test if branch instruction is MPX supported */
432 /* quick test if NOTRACK prefix is supported */
434 /* quick test for lockable instructions */
436 /* fake an extra reg operand for clr, imul and special register
437 processing for some instructions. */
439 /* An implicit xmm0 as the first operand */
441 /* The HLE prefix is OK:
442 1. With a LOCK prefix.
443 2. With or without a LOCK prefix.
444 3. With a RELEASE (0xf3) prefix.
446 #define HLEPrefixNone 0
447 #define HLEPrefixLock 1
448 #define HLEPrefixAny 2
449 #define HLEPrefixRelease 3
451 /* An instruction on which a "rep" prefix is acceptable. */
453 /* Convert to DWORD */
455 /* Convert to QWORD */
457 /* Address prefix changes register operand */
459 /* opcode is a prefix */
461 /* instruction has extension in 8 bit imm */
463 /* instruction don't need Rex64 prefix. */
465 /* instruction require Rex64 prefix. */
467 /* deprecated fp insn, gets a warning */
469 /* insn has VEX prefix:
470 1: 128bit VEX prefix (or operand dependent).
471 2: 256bit VEX prefix.
472 3: Scalar VEX prefix.
478 /* How to encode VEX.vvvv:
479 0: VEX.vvvv must be 1111b.
480 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where
481 the content of source registers will be preserved.
482 VEX.DDS. The second register operand is encoded in VEX.vvvv
483 where the content of first source register will be overwritten
485 VEX.NDD2. The second destination register operand is encoded in
486 VEX.vvvv for instructions with 2 destination register operands.
487 For assembler, there are no difference between VEX.NDS, VEX.DDS
489 2. VEX.NDD. Register destination is encoded in VEX.vvvv for
490 instructions with 1 destination register operand.
491 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one
492 of the operands can access a memory location.
498 /* How the VEX.W bit is used:
499 0: Set by the REX.W bit.
500 1: VEX.W0. Should always be 0.
501 2: VEX.W1. Should always be 1.
502 3: VEX.WIG. The VEX.W bit is ignored.
508 /* VEX opcode prefix:
509 0: VEX 0x0F opcode prefix.
510 1: VEX 0x0F38 opcode prefix.
511 2: VEX 0x0F3A opcode prefix
512 3: XOP 0x08 opcode prefix.
513 4: XOP 0x09 opcode prefix
514 5: XOP 0x0A opcode prefix.
523 /* number of VEX source operands:
524 0: <= 2 source operands.
525 1: 2 XOP source operands.
526 2: 3 source operands.
528 #define XOP2SOURCES 1
529 #define VEX3SOURCES 2
531 /* Instruction with vector SIB byte:
532 1: 128bit vector register.
533 2: 256bit vector register.
534 3: 512bit vector register.
540 /* SSE to AVX support required */
542 /* No AVX equivalent */
545 /* insn has EVEX prefix:
546 1: 512bit EVEX prefix.
547 2: 128bit EVEX prefix.
548 3: 256bit EVEX prefix.
549 4: Length-ignored (LIG) EVEX prefix.
550 5: Length determined from actual operands.
559 /* AVX512 masking support:
560 1: Zeroing or merging masking depending on operands.
562 3: Both zeroing and merging masking.
564 #define DYNAMIC_MASKING 1
565 #define MERGING_MASKING 2
566 #define BOTH_MASKING 3
569 /* AVX512 broadcast support. The number of bytes to broadcast is
570 1 << (Broadcast - 1):
576 #define BYTE_BROADCAST 1
577 #define WORD_BROADCAST 2
578 #define DWORD_BROADCAST 3
579 #define QWORD_BROADCAST 4
582 /* Static rounding control is supported. */
585 /* Supress All Exceptions is supported. */
588 /* Compressed Disp8*N attribute. */
589 #define DISP8_SHIFT_VL 7
592 /* Default mask isn't allowed. */
595 /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
596 It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
600 /* Support encoding optimization. */
613 /* The last bitfield in i386_opcode_modifier. */
617 typedef struct i386_opcode_modifier
622 unsigned int modrm
:1;
623 unsigned int shortform
:1;
625 unsigned int jumpdword
:1;
626 unsigned int jumpbyte
:1;
627 unsigned int jumpintersegment
:1;
628 unsigned int floatmf
:1;
629 unsigned int floatr
:1;
630 unsigned int size16
:1;
631 unsigned int size32
:1;
632 unsigned int size64
:1;
633 unsigned int checkregsize
:1;
634 unsigned int ignoresize
:1;
635 unsigned int defaultsize
:1;
636 unsigned int no_bsuf
:1;
637 unsigned int no_wsuf
:1;
638 unsigned int no_lsuf
:1;
639 unsigned int no_ssuf
:1;
640 unsigned int no_qsuf
:1;
641 unsigned int no_ldsuf
:1;
642 unsigned int fwait
:1;
643 unsigned int isstring
:1;
644 unsigned int bndprefixok
:1;
645 unsigned int notrackprefixok
:1;
646 unsigned int islockable
:1;
647 unsigned int regkludge
:1;
648 unsigned int implicit1stxmm0
:1;
649 unsigned int hleprefixok
:2;
650 unsigned int repprefixok
:1;
651 unsigned int todword
:1;
652 unsigned int toqword
:1;
653 unsigned int addrprefixopreg
:1;
654 unsigned int isprefix
:1;
655 unsigned int immext
:1;
656 unsigned int norex64
:1;
657 unsigned int rex64
:1;
660 unsigned int vexvvvv
:2;
662 unsigned int vexopcode
:3;
663 unsigned int vexsources
:2;
664 unsigned int vecsib
:2;
665 unsigned int sse2avx
:1;
666 unsigned int noavx
:1;
668 unsigned int masking
:2;
669 unsigned int broadcast
:3;
670 unsigned int staticrounding
:1;
672 unsigned int disp8memshift
:3;
673 unsigned int nodefmask
:1;
674 unsigned int implicitquadgroup
:1;
675 unsigned int optimize
:1;
676 unsigned int attmnemonic
:1;
677 unsigned int attsyntax
:1;
678 unsigned int intelsyntax
:1;
679 unsigned int amd64
:1;
680 unsigned int intel64
:1;
681 } i386_opcode_modifier
;
683 /* Position of operand_type bits. */
687 /* Register (qualified by Byte, Word, etc) */
691 /* Vector registers */
693 /* Vector Mask registers */
695 /* Control register */
701 /* 2 bit segment register */
703 /* 3 bit segment register */
705 /* 1 bit immediate */
707 /* 8 bit immediate */
709 /* 8 bit immediate sign extended */
711 /* 16 bit immediate */
713 /* 32 bit immediate */
715 /* 32 bit immediate sign extended */
717 /* 64 bit immediate */
719 /* 8bit/16bit/32bit displacements are used in different ways,
720 depending on the instruction. For jumps, they specify the
721 size of the PC relative displacement, for instructions with
722 memory operand, they specify the size of the offset relative
723 to the base register, and for instructions with memory offset
724 such as `mov 1234,%al' they specify the size of the offset
725 relative to the segment base. */
726 /* 8 bit displacement */
728 /* 16 bit displacement */
730 /* 32 bit displacement */
732 /* 32 bit signed displacement */
734 /* 64 bit displacement */
736 /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
738 /* Register which can be used for base or index in memory operand. */
740 /* Register to hold in/out port addr = dx */
742 /* Register to hold shift count = cl */
744 /* Absolute address for jump. */
746 /* String insn operand with fixed es segment */
748 /* RegMem is for instructions with a modrm byte where the register
749 destination operand should be encoded in the mod and regmem fields.
750 Normally, it will be encoded in the reg field. We add a RegMem
751 flag to the destination register operand to indicate that it should
752 be encoded in the regmem field. */
758 /* WORD size. 2 byte */
760 /* DWORD size. 4 byte */
762 /* FWORD size. 6 byte */
764 /* QWORD size. 8 byte */
766 /* TBYTE size. 10 byte */
774 /* Unspecified memory size. */
776 /* Any memory size. */
779 /* Vector 4 bit immediate. */
782 /* Bound register. */
785 /* The number of bitfields in i386_operand_type. */
789 #define OTNumOfUints \
790 ((OTNum - 1) / sizeof (unsigned int) / CHAR_BIT + 1)
791 #define OTNumOfBits \
792 (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
794 /* If you get a compiler error for zero width of the unused field,
796 #define OTUnused OTNum
798 typedef union i386_operand_type
803 unsigned int regmmx
:1;
804 unsigned int regsimd
:1;
805 unsigned int regmask
:1;
806 unsigned int control
:1;
807 unsigned int debug
:1;
809 unsigned int sreg2
:1;
810 unsigned int sreg3
:1;
813 unsigned int imm8s
:1;
814 unsigned int imm16
:1;
815 unsigned int imm32
:1;
816 unsigned int imm32s
:1;
817 unsigned int imm64
:1;
818 unsigned int disp8
:1;
819 unsigned int disp16
:1;
820 unsigned int disp32
:1;
821 unsigned int disp32s
:1;
822 unsigned int disp64
:1;
824 unsigned int baseindex
:1;
825 unsigned int inoutportreg
:1;
826 unsigned int shiftcount
:1;
827 unsigned int jumpabsolute
:1;
828 unsigned int esseg
:1;
829 unsigned int regmem
:1;
832 unsigned int dword
:1;
833 unsigned int fword
:1;
834 unsigned int qword
:1;
835 unsigned int tbyte
:1;
836 unsigned int xmmword
:1;
837 unsigned int ymmword
:1;
838 unsigned int zmmword
:1;
839 unsigned int unspecified
:1;
840 unsigned int anysize
:1;
841 unsigned int vec_imm4
:1;
842 unsigned int regbnd
:1;
844 unsigned int unused
:(OTNumOfBits
- OTUnused
);
847 unsigned int array
[OTNumOfUints
];
850 typedef struct insn_template
852 /* instruction name sans width suffix ("mov" for movl insns) */
855 /* how many operands */
856 unsigned int operands
;
858 /* base_opcode is the fundamental opcode byte without optional
860 unsigned int base_opcode
;
861 #define Opcode_D 0x2 /* Direction bit:
862 set if Reg --> Regmem;
863 unset if Regmem --> Reg. */
864 #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
865 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
866 #define Opcode_SIMD_FloatD 0x1 /* Direction bit for SIMD fp insns. */
867 #define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */
869 /* extension_opcode is the 3 bit extension for group <n> insns.
870 This field is also used to store the 8-bit opcode suffix for the
871 AMD 3DNow! instructions.
872 If this template has no extension opcode (the usual case) use None
874 unsigned int extension_opcode
;
875 #define None 0xffff /* If no extension_opcode is possible. */
878 unsigned char opcode_length
;
880 /* cpu feature flags */
881 i386_cpu_flags cpu_flags
;
883 /* the bits in opcode_modifier are used to generate the final opcode from
884 the base_opcode. These bits also are used to detect alternate forms of
885 the same instruction */
886 i386_opcode_modifier opcode_modifier
;
888 /* operand_types[i] describes the type of operand i. This is made
889 by OR'ing together all of the possible type masks. (e.g.
890 'operand_types[i] = Reg|Imm' specifies that operand i can be
891 either a register or an immediate operand. */
892 i386_operand_type operand_types
[MAX_OPERANDS
];
896 extern const insn_template i386_optab
[];
898 /* these are for register name --> number & type hash lookup */
902 i386_operand_type reg_type
;
903 unsigned char reg_flags
;
904 #define RegRex 0x1 /* Extended register. */
905 #define RegRex64 0x2 /* Extended 8 bit register. */
906 #define RegVRex 0x4 /* Extended vector register. */
907 unsigned char reg_num
;
908 #define RegIP ((unsigned char ) ~0)
909 /* EIZ and RIZ are fake index registers. */
910 #define RegIZ (RegIP - 1)
911 /* FLAT is a fake segment register (Intel mode). */
912 #define RegFlat ((unsigned char) ~0)
913 signed char dw2_regnum
[2];
914 #define Dw2Inval (-1)
918 /* Entries in i386_regtab. */
921 #define REGNAM_EAX 41
923 extern const reg_entry i386_regtab
[];
924 extern const unsigned int i386_regtab_size
;
929 unsigned int seg_prefix
;
933 extern const seg_entry cs
;
934 extern const seg_entry ds
;
935 extern const seg_entry ss
;
936 extern const seg_entry es
;
937 extern const seg_entry fs
;
938 extern const seg_entry gs
;