1 /* Declarations for Intel 80386 opcode table
2 Copyright 2007, 2008, 2009
3 Free Software Foundation, Inc.
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
22 #include "opcode/i386.h"
31 /* Position of cpu flags bitfiled. */
33 /* i186 or better required */
35 /* i286 or better required */
36 #define Cpu286 (Cpu186 + 1)
37 /* i386 or better required */
38 #define Cpu386 (Cpu286 + 1)
39 /* i486 or better required */
40 #define Cpu486 (Cpu386 + 1)
41 /* i585 or better required */
42 #define Cpu586 (Cpu486 + 1)
43 /* i686 or better required */
44 #define Cpu686 (Cpu586 + 1)
45 /* CLFLUSH Instuction support required */
46 #define CpuClflush (Cpu686 + 1)
47 /* SYSCALL Instuctions support required */
48 #define CpuSYSCALL (CpuClflush + 1)
49 /* MMX support required */
50 #define CpuMMX (CpuSYSCALL + 1)
51 /* SSE support required */
52 #define CpuSSE (CpuMMX + 1)
53 /* SSE2 support required */
54 #define CpuSSE2 (CpuSSE + 1)
55 /* 3dnow! support required */
56 #define Cpu3dnow (CpuSSE2 + 1)
57 /* 3dnow! Extensions support required */
58 #define Cpu3dnowA (Cpu3dnow + 1)
59 /* SSE3 support required */
60 #define CpuSSE3 (Cpu3dnowA + 1)
61 /* VIA PadLock required */
62 #define CpuPadLock (CpuSSE3 + 1)
63 /* AMD Secure Virtual Machine Ext-s required */
64 #define CpuSVME (CpuPadLock + 1)
65 /* VMX Instructions required */
66 #define CpuVMX (CpuSVME + 1)
67 /* SMX Instructions required */
68 #define CpuSMX (CpuVMX + 1)
69 /* SSSE3 support required */
70 #define CpuSSSE3 (CpuSMX + 1)
71 /* SSE4a support required */
72 #define CpuSSE4a (CpuSSSE3 + 1)
73 /* ABM New Instructions required */
74 #define CpuABM (CpuSSE4a + 1)
75 /* SSE4.1 support required */
76 #define CpuSSE4_1 (CpuABM + 1)
77 /* SSE4.2 support required */
78 #define CpuSSE4_2 (CpuSSE4_1 + 1)
79 /* AVX support required */
80 #define CpuAVX (CpuSSE4_2 + 1)
81 /* Xsave/xrstor New Instuctions support required */
82 #define CpuXsave (CpuAVX + 1)
83 /* AES support required */
84 #define CpuAES (CpuXsave + 1)
85 /* PCLMUL support required */
86 #define CpuPCLMUL (CpuAES + 1)
87 /* FMA support required */
88 #define CpuFMA (CpuPCLMUL + 1)
89 /* FMA4 support required */
90 #define CpuFMA4 (CpuFMA + 1)
91 /* MOVBE Instuction support required */
92 #define CpuMovbe (CpuFMA4 + 1)
93 /* EPT Instructions required */
94 #define CpuEPT (CpuMovbe + 1)
95 /* RDTSCP Instuction support required */
96 #define CpuRdtscp (CpuEPT + 1)
97 /* 64bit support available, used by -march= in assembler. */
98 #define CpuLM (CpuRdtscp + 1)
99 /* 64bit support required */
100 #define Cpu64 (CpuLM + 1)
101 /* Not supported in the 64bit mode */
102 #define CpuNo64 (Cpu64 + 1)
103 /* The last bitfield in i386_cpu_flags. */
104 #define CpuMax CpuNo64
106 #define CpuNumOfUints \
107 (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
108 #define CpuNumOfBits \
109 (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
111 /* If you get a compiler error for zero width of the unused field,
113 #define CpuUnused (CpuMax + 1)
115 /* We can check if an instruction is available with array instead
117 typedef union i386_cpu_flags
121 unsigned int cpui186
:1;
122 unsigned int cpui286
:1;
123 unsigned int cpui386
:1;
124 unsigned int cpui486
:1;
125 unsigned int cpui586
:1;
126 unsigned int cpui686
:1;
127 unsigned int cpuclflush
:1;
128 unsigned int cpusyscall
:1;
129 unsigned int cpummx
:1;
130 unsigned int cpusse
:1;
131 unsigned int cpusse2
:1;
132 unsigned int cpua3dnow
:1;
133 unsigned int cpua3dnowa
:1;
134 unsigned int cpusse3
:1;
135 unsigned int cpupadlock
:1;
136 unsigned int cpusvme
:1;
137 unsigned int cpuvmx
:1;
138 unsigned int cpusmx
:1;
139 unsigned int cpussse3
:1;
140 unsigned int cpusse4a
:1;
141 unsigned int cpuabm
:1;
142 unsigned int cpusse4_1
:1;
143 unsigned int cpusse4_2
:1;
144 unsigned int cpuavx
:1;
145 unsigned int cpuxsave
:1;
146 unsigned int cpuaes
:1;
147 unsigned int cpupclmul
:1;
148 unsigned int cpufma
:1;
149 unsigned int cpufma4
:1;
150 unsigned int cpumovbe
:1;
151 unsigned int cpuept
:1;
152 unsigned int cpurdtscp
:1;
153 unsigned int cpulm
:1;
154 unsigned int cpu64
:1;
155 unsigned int cpuno64
:1;
157 unsigned int unused
:(CpuNumOfBits
- CpuUnused
);
160 unsigned int array
[CpuNumOfUints
];
163 /* Position of opcode_modifier bits. */
165 /* has direction bit. */
167 /* set if operands can be words or dwords encoded the canonical way */
169 /* Skip the current insn and use the next insn in i386-opc.tbl to swap
170 operand in encoding. */
172 /* insn has a modrm byte. */
173 #define Modrm (S + 1)
174 /* register is in low 3 bits of opcode */
175 #define ShortForm (Modrm + 1)
176 /* special case for jump insns. */
177 #define Jump (ShortForm + 1)
179 #define JumpDword (Jump + 1)
181 #define JumpByte (JumpDword + 1)
182 /* special case for intersegment leaps/calls */
183 #define JumpInterSegment (JumpByte + 1)
184 /* FP insn memory format bit, sized by 0x4 */
185 #define FloatMF (JumpInterSegment + 1)
186 /* src/dest swap for floats. */
187 #define FloatR (FloatMF + 1)
188 /* has float insn direction bit. */
189 #define FloatD (FloatR + 1)
190 /* needs size prefix if in 32-bit mode */
191 #define Size16 (FloatD + 1)
192 /* needs size prefix if in 16-bit mode */
193 #define Size32 (Size16 + 1)
194 /* needs size prefix if in 64-bit mode */
195 #define Size64 (Size32 + 1)
196 /* instruction ignores operand size prefix and in Intel mode ignores
197 mnemonic size suffix check. */
198 #define IgnoreSize (Size64 + 1)
199 /* default insn size depends on mode */
200 #define DefaultSize (IgnoreSize + 1)
201 /* b suffix on instruction illegal */
202 #define No_bSuf (DefaultSize + 1)
203 /* w suffix on instruction illegal */
204 #define No_wSuf (No_bSuf + 1)
205 /* l suffix on instruction illegal */
206 #define No_lSuf (No_wSuf + 1)
207 /* s suffix on instruction illegal */
208 #define No_sSuf (No_lSuf + 1)
209 /* q suffix on instruction illegal */
210 #define No_qSuf (No_sSuf + 1)
211 /* long double suffix on instruction illegal */
212 #define No_ldSuf (No_qSuf + 1)
213 /* instruction needs FWAIT */
214 #define FWait (No_ldSuf + 1)
215 /* quick test for string instructions */
216 #define IsString (FWait + 1)
217 /* fake an extra reg operand for clr, imul and special register
218 processing for some instructions. */
219 #define RegKludge (IsString + 1)
220 /* The first operand must be xmm0 */
221 #define FirstXmm0 (RegKludge + 1)
222 /* An implicit xmm0 as the first operand */
223 #define Implicit1stXmm0 (FirstXmm0 + 1)
224 /* BYTE is OK in Intel syntax. */
225 #define ByteOkIntel (Implicit1stXmm0 + 1)
226 /* Convert to DWORD */
227 #define ToDword (ByteOkIntel + 1)
228 /* Convert to QWORD */
229 #define ToQword (ToDword + 1)
230 /* Address prefix changes operand 0 */
231 #define AddrPrefixOp0 (ToQword + 1)
232 /* opcode is a prefix */
233 #define IsPrefix (AddrPrefixOp0 + 1)
234 /* instruction has extension in 8 bit imm */
235 #define ImmExt (IsPrefix + 1)
236 /* instruction don't need Rex64 prefix. */
237 #define NoRex64 (ImmExt + 1)
238 /* instruction require Rex64 prefix. */
239 #define Rex64 (NoRex64 + 1)
240 /* deprecated fp insn, gets a warning */
241 #define Ugh (Rex64 + 1)
242 /* insn has VEX prefix. */
243 #define Vex (Ugh + 1)
244 /* insn has 256bit VEX prefix. */
245 #define Vex256 (Vex + 1)
246 /* insn has VEX NDS. Register-only source is encoded in Vex prefix.
247 We use VexNDS on insns with VEX DDS since the register-only source
248 is the second source register. */
249 #define VexNDS (Vex256 + 1)
250 /* insn has VEX NDD. Register destination is encoded in Vex
252 #define VexNDD (VexNDS + 1)
253 /* insn has VEX W0. */
254 #define VexW0 (VexNDD + 1)
255 /* insn has VEX W1. */
256 #define VexW1 (VexW0 + 1)
257 /* insn has VEX 0x0F opcode prefix. */
258 #define Vex0F (VexW1 + 1)
259 /* insn has VEX 0x0F38 opcode prefix. */
260 #define Vex0F38 (Vex0F + 1)
261 /* insn has VEX 0x0F3A opcode prefix. */
262 #define Vex0F3A (Vex0F38 + 1)
263 /* insn has VEX prefix with 3 soures. */
264 #define Vex3Sources (Vex0F3A + 1)
265 /* instruction has VEX 8 bit imm */
266 #define VexImmExt (Vex3Sources + 1)
267 /* SSE to AVX support required */
268 #define SSE2AVX (VexImmExt + 1)
269 /* No AVX equivalent */
270 #define NoAVX (SSE2AVX + 1)
271 /* Compatible with old (<= 2.8.1) versions of gcc */
272 #define OldGcc (NoAVX + 1)
274 #define ATTMnemonic (OldGcc + 1)
276 #define ATTSyntax (ATTMnemonic + 1)
278 #define IntelSyntax (ATTSyntax + 1)
279 /* The last bitfield in i386_opcode_modifier. */
280 #define Opcode_Modifier_Max IntelSyntax
282 typedef struct i386_opcode_modifier
287 unsigned int modrm
:1;
288 unsigned int shortform
:1;
290 unsigned int jumpdword
:1;
291 unsigned int jumpbyte
:1;
292 unsigned int jumpintersegment
:1;
293 unsigned int floatmf
:1;
294 unsigned int floatr
:1;
295 unsigned int floatd
:1;
296 unsigned int size16
:1;
297 unsigned int size32
:1;
298 unsigned int size64
:1;
299 unsigned int ignoresize
:1;
300 unsigned int defaultsize
:1;
301 unsigned int no_bsuf
:1;
302 unsigned int no_wsuf
:1;
303 unsigned int no_lsuf
:1;
304 unsigned int no_ssuf
:1;
305 unsigned int no_qsuf
:1;
306 unsigned int no_ldsuf
:1;
307 unsigned int fwait
:1;
308 unsigned int isstring
:1;
309 unsigned int regkludge
:1;
310 unsigned int firstxmm0
:1;
311 unsigned int implicit1stxmm0
:1;
312 unsigned int byteokintel
:1;
313 unsigned int todword
:1;
314 unsigned int toqword
:1;
315 unsigned int addrprefixop0
:1;
316 unsigned int isprefix
:1;
317 unsigned int immext
:1;
318 unsigned int norex64
:1;
319 unsigned int rex64
:1;
322 unsigned int vex256
:1;
323 unsigned int vexnds
:1;
324 unsigned int vexndd
:1;
325 unsigned int vexw0
:1;
326 unsigned int vexw1
:1;
327 unsigned int vex0f
:1;
328 unsigned int vex0f38
:1;
329 unsigned int vex0f3a
:1;
330 unsigned int vex3sources
:1;
331 unsigned int veximmext
:1;
332 unsigned int sse2avx
:1;
333 unsigned int noavx
:1;
334 unsigned int oldgcc
:1;
335 unsigned int attmnemonic
:1;
336 unsigned int attsyntax
:1;
337 unsigned int intelsyntax
:1;
338 } i386_opcode_modifier
;
340 /* Position of operand_type bits. */
345 #define Reg16 (Reg8 + 1)
347 #define Reg32 (Reg16 + 1)
349 #define Reg64 (Reg32 + 1)
350 /* Floating pointer stack register */
351 #define FloatReg (Reg64 + 1)
353 #define RegMMX (FloatReg + 1)
355 #define RegXMM (RegMMX + 1)
357 #define RegYMM (RegXMM + 1)
358 /* Control register */
359 #define Control (RegYMM + 1)
361 #define Debug (Control + 1)
363 #define Test (Debug + 1)
364 /* 2 bit segment register */
365 #define SReg2 (Test + 1)
366 /* 3 bit segment register */
367 #define SReg3 (SReg2 + 1)
368 /* 1 bit immediate */
369 #define Imm1 (SReg3 + 1)
370 /* 8 bit immediate */
371 #define Imm8 (Imm1 + 1)
372 /* 8 bit immediate sign extended */
373 #define Imm8S (Imm8 + 1)
374 /* 16 bit immediate */
375 #define Imm16 (Imm8S + 1)
376 /* 32 bit immediate */
377 #define Imm32 (Imm16 + 1)
378 /* 32 bit immediate sign extended */
379 #define Imm32S (Imm32 + 1)
380 /* 64 bit immediate */
381 #define Imm64 (Imm32S + 1)
382 /* 8bit/16bit/32bit displacements are used in different ways,
383 depending on the instruction. For jumps, they specify the
384 size of the PC relative displacement, for instructions with
385 memory operand, they specify the size of the offset relative
386 to the base register, and for instructions with memory offset
387 such as `mov 1234,%al' they specify the size of the offset
388 relative to the segment base. */
389 /* 8 bit displacement */
390 #define Disp8 (Imm64 + 1)
391 /* 16 bit displacement */
392 #define Disp16 (Disp8 + 1)
393 /* 32 bit displacement */
394 #define Disp32 (Disp16 + 1)
395 /* 32 bit signed displacement */
396 #define Disp32S (Disp32 + 1)
397 /* 64 bit displacement */
398 #define Disp64 (Disp32S + 1)
399 /* Accumulator %al/%ax/%eax/%rax */
400 #define Acc (Disp64 + 1)
401 /* Floating pointer top stack register %st(0) */
402 #define FloatAcc (Acc + 1)
403 /* Register which can be used for base or index in memory operand. */
404 #define BaseIndex (FloatAcc + 1)
405 /* Register to hold in/out port addr = dx */
406 #define InOutPortReg (BaseIndex + 1)
407 /* Register to hold shift count = cl */
408 #define ShiftCount (InOutPortReg + 1)
409 /* Absolute address for jump. */
410 #define JumpAbsolute (ShiftCount + 1)
411 /* String insn operand with fixed es segment */
412 #define EsSeg (JumpAbsolute + 1)
413 /* RegMem is for instructions with a modrm byte where the register
414 destination operand should be encoded in the mod and regmem fields.
415 Normally, it will be encoded in the reg field. We add a RegMem
416 flag to the destination register operand to indicate that it should
417 be encoded in the regmem field. */
418 #define RegMem (EsSeg + 1)
420 #define Mem (RegMem + 1)
422 #define Byte (Mem + 1)
423 /* WORD memory. 2 byte */
424 #define Word (Byte + 1)
425 /* DWORD memory. 4 byte */
426 #define Dword (Word + 1)
427 /* FWORD memory. 6 byte */
428 #define Fword (Dword + 1)
429 /* QWORD memory. 8 byte */
430 #define Qword (Fword + 1)
431 /* TBYTE memory. 10 byte */
432 #define Tbyte (Qword + 1)
433 /* XMMWORD memory. */
434 #define Xmmword (Tbyte + 1)
435 /* YMMWORD memory. */
436 #define Ymmword (Xmmword + 1)
437 /* Unspecified memory size. */
438 #define Unspecified (Ymmword + 1)
439 /* Any memory size. */
440 #define Anysize (Unspecified + 1)
442 /* The last bitfield in i386_operand_type. */
443 #define OTMax Anysize
445 #define OTNumOfUints \
446 (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
447 #define OTNumOfBits \
448 (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
450 /* If you get a compiler error for zero width of the unused field,
452 #define OTUnused (OTMax + 1)
454 typedef union i386_operand_type
459 unsigned int reg16
:1;
460 unsigned int reg32
:1;
461 unsigned int reg64
:1;
462 unsigned int floatreg
:1;
463 unsigned int regmmx
:1;
464 unsigned int regxmm
:1;
465 unsigned int regymm
:1;
466 unsigned int control
:1;
467 unsigned int debug
:1;
469 unsigned int sreg2
:1;
470 unsigned int sreg3
:1;
473 unsigned int imm8s
:1;
474 unsigned int imm16
:1;
475 unsigned int imm32
:1;
476 unsigned int imm32s
:1;
477 unsigned int imm64
:1;
478 unsigned int disp8
:1;
479 unsigned int disp16
:1;
480 unsigned int disp32
:1;
481 unsigned int disp32s
:1;
482 unsigned int disp64
:1;
484 unsigned int floatacc
:1;
485 unsigned int baseindex
:1;
486 unsigned int inoutportreg
:1;
487 unsigned int shiftcount
:1;
488 unsigned int jumpabsolute
:1;
489 unsigned int esseg
:1;
490 unsigned int regmem
:1;
494 unsigned int dword
:1;
495 unsigned int fword
:1;
496 unsigned int qword
:1;
497 unsigned int tbyte
:1;
498 unsigned int xmmword
:1;
499 unsigned int ymmword
:1;
500 unsigned int unspecified
:1;
501 unsigned int anysize
:1;
503 unsigned int unused
:(OTNumOfBits
- OTUnused
);
506 unsigned int array
[OTNumOfUints
];
509 typedef struct template
511 /* instruction name sans width suffix ("mov" for movl insns) */
514 /* how many operands */
515 unsigned int operands
;
517 /* base_opcode is the fundamental opcode byte without optional
519 unsigned int base_opcode
;
520 #define Opcode_D 0x2 /* Direction bit:
521 set if Reg --> Regmem;
522 unset if Regmem --> Reg. */
523 #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
524 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
526 /* extension_opcode is the 3 bit extension for group <n> insns.
527 This field is also used to store the 8-bit opcode suffix for the
528 AMD 3DNow! instructions.
529 If this template has no extension opcode (the usual case) use None
531 unsigned int extension_opcode
;
532 #define None 0xffff /* If no extension_opcode is possible. */
535 unsigned char opcode_length
;
537 /* cpu feature flags */
538 i386_cpu_flags cpu_flags
;
540 /* the bits in opcode_modifier are used to generate the final opcode from
541 the base_opcode. These bits also are used to detect alternate forms of
542 the same instruction */
543 i386_opcode_modifier opcode_modifier
;
545 /* operand_types[i] describes the type of operand i. This is made
546 by OR'ing together all of the possible type masks. (e.g.
547 'operand_types[i] = Reg|Imm' specifies that operand i can be
548 either a register or an immediate operand. */
549 i386_operand_type operand_types
[MAX_OPERANDS
];
553 extern const template i386_optab
[];
555 /* these are for register name --> number & type hash lookup */
559 i386_operand_type reg_type
;
560 unsigned char reg_flags
;
561 #define RegRex 0x1 /* Extended register. */
562 #define RegRex64 0x2 /* Extended 8 bit register. */
563 unsigned char reg_num
;
564 #define RegRip ((unsigned char ) ~0)
565 #define RegEip (RegRip - 1)
566 /* EIZ and RIZ are fake index registers. */
567 #define RegEiz (RegEip - 1)
568 #define RegRiz (RegEiz - 1)
569 /* FLAT is a fake segment register (Intel mode). */
570 #define RegFlat ((unsigned char) ~0)
571 signed char dw2_regnum
[2];
572 #define Dw2Inval (-1)
576 /* Entries in i386_regtab. */
579 #define REGNAM_EAX 41
581 extern const reg_entry i386_regtab
[];
582 extern const unsigned int i386_regtab_size
;
587 unsigned int seg_prefix
;
591 extern const seg_entry cs
;
592 extern const seg_entry ds
;
593 extern const seg_entry ss
;
594 extern const seg_entry es
;
595 extern const seg_entry fs
;
596 extern const seg_entry gs
;