1 /* Declarations for Intel 80386 opcode table
2 Copyright 2007, 2008, 2009, 2010, 2012
3 Free Software Foundation, Inc.
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
22 #include "opcode/i386.h"
31 /* Position of cpu flags bitfiled. */
35 /* i186 or better required */
37 /* i286 or better required */
39 /* i386 or better required */
41 /* i486 or better required */
43 /* i585 or better required */
45 /* i686 or better required */
47 /* CLFLUSH Instruction support required */
49 /* NOP Instruction support required */
51 /* SYSCALL Instructions support required */
53 /* Floating point support required */
55 /* i287 support required */
57 /* i387 support required */
59 /* i686 and floating point support required */
61 /* SSE3 and floating point support required */
63 /* MMX support required */
65 /* SSE support required */
67 /* SSE2 support required */
69 /* 3dnow! support required */
71 /* 3dnow! Extensions support required */
73 /* SSE3 support required */
75 /* VIA PadLock required */
77 /* AMD Secure Virtual Machine Ext-s required */
79 /* VMX Instructions required */
81 /* SMX Instructions required */
83 /* SSSE3 support required */
85 /* SSE4a support required */
87 /* ABM New Instructions required */
89 /* SSE4.1 support required */
91 /* SSE4.2 support required */
93 /* AVX support required */
95 /* AVX2 support required */
97 /* Intel AVX-512 Foundation Instructions support required */
99 /* Intel AVX-512 Conflict Detection Instructions support required */
101 /* Intel AVX-512 Exponential and Reciprocal Instructions support
104 /* Intel AVX-512 Prefetch Instructions support required */
106 /* Intel L1OM support required */
108 /* Intel K1OM support required */
110 /* Xsave/xrstor New Instructions support required */
112 /* Xsaveopt New Instructions support required */
114 /* AES support required */
116 /* PCLMUL support required */
118 /* FMA support required */
120 /* FMA4 support required */
122 /* XOP support required */
124 /* LWP support required */
126 /* BMI support required */
128 /* TBM support required */
130 /* MOVBE Instruction support required */
132 /* CMPXCHG16B instruction support required. */
134 /* EPT Instructions required */
136 /* RDTSCP Instruction support required */
138 /* FSGSBASE Instructions required */
140 /* RDRND Instructions required */
142 /* F16C Instructions required */
144 /* Intel BMI2 support required */
146 /* LZCNT support required */
148 /* HLE support required */
150 /* RTM support required */
152 /* INVPCID Instructions required */
154 /* VMFUNC Instruction required */
156 /* Intel MPX Instructions required */
158 /* 64bit support available, used by -march= in assembler. */
160 /* RDRSEED instruction required. */
162 /* Multi-presisionn add-carry instructions are required. */
164 /* Supports prefetchw and prefetch instructions. */
166 /* SMAP instructions required. */
168 /* SHA instructions required. */
170 /* VREX support required */
172 /* CLFLUSHOPT instruction required */
174 /* XSAVES/XRSTORS instruction required */
176 /* XSAVEC instruction required */
178 /* PREFETCHWT1 instruction required */
180 /* 64bit support required */
182 /* Not supported in the 64bit mode */
184 /* The last bitfield in i386_cpu_flags. */
188 #define CpuNumOfUints \
189 (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
190 #define CpuNumOfBits \
191 (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
193 /* If you get a compiler error for zero width of the unused field,
195 #define CpuUnused (CpuMax + 1)
197 /* We can check if an instruction is available with array instead
199 typedef union i386_cpu_flags
203 unsigned int cpui186
:1;
204 unsigned int cpui286
:1;
205 unsigned int cpui386
:1;
206 unsigned int cpui486
:1;
207 unsigned int cpui586
:1;
208 unsigned int cpui686
:1;
209 unsigned int cpuclflush
:1;
210 unsigned int cpunop
:1;
211 unsigned int cpusyscall
:1;
212 unsigned int cpu8087
:1;
213 unsigned int cpu287
:1;
214 unsigned int cpu387
:1;
215 unsigned int cpu687
:1;
216 unsigned int cpufisttp
:1;
217 unsigned int cpummx
:1;
218 unsigned int cpusse
:1;
219 unsigned int cpusse2
:1;
220 unsigned int cpua3dnow
:1;
221 unsigned int cpua3dnowa
:1;
222 unsigned int cpusse3
:1;
223 unsigned int cpupadlock
:1;
224 unsigned int cpusvme
:1;
225 unsigned int cpuvmx
:1;
226 unsigned int cpusmx
:1;
227 unsigned int cpussse3
:1;
228 unsigned int cpusse4a
:1;
229 unsigned int cpuabm
:1;
230 unsigned int cpusse4_1
:1;
231 unsigned int cpusse4_2
:1;
232 unsigned int cpuavx
:1;
233 unsigned int cpuavx2
:1;
234 unsigned int cpuavx512f
:1;
235 unsigned int cpuavx512cd
:1;
236 unsigned int cpuavx512er
:1;
237 unsigned int cpuavx512pf
:1;
238 unsigned int cpul1om
:1;
239 unsigned int cpuk1om
:1;
240 unsigned int cpuxsave
:1;
241 unsigned int cpuxsaveopt
:1;
242 unsigned int cpuaes
:1;
243 unsigned int cpupclmul
:1;
244 unsigned int cpufma
:1;
245 unsigned int cpufma4
:1;
246 unsigned int cpuxop
:1;
247 unsigned int cpulwp
:1;
248 unsigned int cpubmi
:1;
249 unsigned int cputbm
:1;
250 unsigned int cpumovbe
:1;
251 unsigned int cpucx16
:1;
252 unsigned int cpuept
:1;
253 unsigned int cpurdtscp
:1;
254 unsigned int cpufsgsbase
:1;
255 unsigned int cpurdrnd
:1;
256 unsigned int cpuf16c
:1;
257 unsigned int cpubmi2
:1;
258 unsigned int cpulzcnt
:1;
259 unsigned int cpuhle
:1;
260 unsigned int cpurtm
:1;
261 unsigned int cpuinvpcid
:1;
262 unsigned int cpuvmfunc
:1;
263 unsigned int cpumpx
:1;
264 unsigned int cpulm
:1;
265 unsigned int cpurdseed
:1;
266 unsigned int cpuadx
:1;
267 unsigned int cpuprfchw
:1;
268 unsigned int cpusmap
:1;
269 unsigned int cpusha
:1;
270 unsigned int cpuvrex
:1;
271 unsigned int cpuclflushopt
:1;
272 unsigned int cpuxsaves
:1;
273 unsigned int cpuxsavec
:1;
274 unsigned int cpuprefetchwt1
:1;
275 unsigned int cpu64
:1;
276 unsigned int cpuno64
:1;
278 unsigned int unused
:(CpuNumOfBits
- CpuUnused
);
281 unsigned int array
[CpuNumOfUints
];
284 /* Position of opcode_modifier bits. */
288 /* has direction bit. */
290 /* set if operands can be words or dwords encoded the canonical way */
292 /* Skip the current insn and use the next insn in i386-opc.tbl to swap
293 operand in encoding. */
295 /* insn has a modrm byte. */
297 /* register is in low 3 bits of opcode */
299 /* special case for jump insns. */
305 /* special case for intersegment leaps/calls */
307 /* FP insn memory format bit, sized by 0x4 */
309 /* src/dest swap for floats. */
311 /* has float insn direction bit. */
313 /* needs size prefix if in 32-bit mode */
315 /* needs size prefix if in 16-bit mode */
317 /* needs size prefix if in 64-bit mode */
319 /* check register size. */
321 /* instruction ignores operand size prefix and in Intel mode ignores
322 mnemonic size suffix check. */
324 /* default insn size depends on mode */
326 /* b suffix on instruction illegal */
328 /* w suffix on instruction illegal */
330 /* l suffix on instruction illegal */
332 /* s suffix on instruction illegal */
334 /* q suffix on instruction illegal */
336 /* long double suffix on instruction illegal */
338 /* instruction needs FWAIT */
340 /* quick test for string instructions */
342 /* quick test if branch instruction is MPX supported */
344 /* quick test for lockable instructions */
346 /* fake an extra reg operand for clr, imul and special register
347 processing for some instructions. */
349 /* The first operand must be xmm0 */
351 /* An implicit xmm0 as the first operand */
353 /* The HLE prefix is OK:
354 1. With a LOCK prefix.
355 2. With or without a LOCK prefix.
356 3. With a RELEASE (0xf3) prefix.
358 #define HLEPrefixNone 0
359 #define HLEPrefixLock 1
360 #define HLEPrefixAny 2
361 #define HLEPrefixRelease 3
363 /* An instruction on which a "rep" prefix is acceptable. */
365 /* Convert to DWORD */
367 /* Convert to QWORD */
369 /* Address prefix changes operand 0 */
371 /* opcode is a prefix */
373 /* instruction has extension in 8 bit imm */
375 /* instruction don't need Rex64 prefix. */
377 /* instruction require Rex64 prefix. */
379 /* deprecated fp insn, gets a warning */
381 /* insn has VEX prefix:
382 1: 128bit VEX prefix.
383 2: 256bit VEX prefix.
384 3: Scalar VEX prefix.
390 /* How to encode VEX.vvvv:
391 0: VEX.vvvv must be 1111b.
392 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where
393 the content of source registers will be preserved.
394 VEX.DDS. The second register operand is encoded in VEX.vvvv
395 where the content of first source register will be overwritten
397 VEX.NDD2. The second destination register operand is encoded in
398 VEX.vvvv for instructions with 2 destination register operands.
399 For assembler, there are no difference between VEX.NDS, VEX.DDS
401 2. VEX.NDD. Register destination is encoded in VEX.vvvv for
402 instructions with 1 destination register operand.
403 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one
404 of the operands can access a memory location.
410 /* How the VEX.W bit is used:
411 0: Set by the REX.W bit.
412 1: VEX.W0. Should always be 0.
413 2: VEX.W1. Should always be 1.
418 /* VEX opcode prefix:
419 0: VEX 0x0F opcode prefix.
420 1: VEX 0x0F38 opcode prefix.
421 2: VEX 0x0F3A opcode prefix
422 3: XOP 0x08 opcode prefix.
423 4: XOP 0x09 opcode prefix
424 5: XOP 0x0A opcode prefix.
433 /* number of VEX source operands:
434 0: <= 2 source operands.
435 1: 2 XOP source operands.
436 2: 3 source operands.
438 #define XOP2SOURCES 1
439 #define VEX3SOURCES 2
441 /* instruction has VEX 8 bit imm */
443 /* Instruction with vector SIB byte:
444 1: 128bit vector register.
445 2: 256bit vector register.
446 3: 512bit vector register.
452 /* SSE to AVX support required */
454 /* No AVX equivalent */
457 /* insn has EVEX prefix:
458 1: 512bit EVEX prefix.
459 2: 128bit EVEX prefix.
460 3: 256bit EVEX prefix.
461 4: Length-ignored (LIG) EVEX prefix.
469 /* AVX512 masking support:
472 3: Both zeroing and merging masking.
474 #define ZEROING_MASKING 1
475 #define MERGING_MASKING 2
476 #define BOTH_MASKING 3
479 /* Input element size of vector insn:
490 #define NO_BROADCAST 0
491 #define BROADCAST_1TO16 1
492 #define BROADCAST_1TO8 2
495 /* Static rounding control is supported. */
498 /* Supress All Exceptions is supported. */
501 /* Copressed Disp8*N attribute. */
504 /* Default mask isn't allowed. */
507 /* Compatible with old (<= 2.8.1) versions of gcc */
515 /* The last bitfield in i386_opcode_modifier. */
519 typedef struct i386_opcode_modifier
524 unsigned int modrm
:1;
525 unsigned int shortform
:1;
527 unsigned int jumpdword
:1;
528 unsigned int jumpbyte
:1;
529 unsigned int jumpintersegment
:1;
530 unsigned int floatmf
:1;
531 unsigned int floatr
:1;
532 unsigned int floatd
:1;
533 unsigned int size16
:1;
534 unsigned int size32
:1;
535 unsigned int size64
:1;
536 unsigned int checkregsize
:1;
537 unsigned int ignoresize
:1;
538 unsigned int defaultsize
:1;
539 unsigned int no_bsuf
:1;
540 unsigned int no_wsuf
:1;
541 unsigned int no_lsuf
:1;
542 unsigned int no_ssuf
:1;
543 unsigned int no_qsuf
:1;
544 unsigned int no_ldsuf
:1;
545 unsigned int fwait
:1;
546 unsigned int isstring
:1;
547 unsigned int bndprefixok
:1;
548 unsigned int islockable
:1;
549 unsigned int regkludge
:1;
550 unsigned int firstxmm0
:1;
551 unsigned int implicit1stxmm0
:1;
552 unsigned int hleprefixok
:2;
553 unsigned int repprefixok
:1;
554 unsigned int todword
:1;
555 unsigned int toqword
:1;
556 unsigned int addrprefixop0
:1;
557 unsigned int isprefix
:1;
558 unsigned int immext
:1;
559 unsigned int norex64
:1;
560 unsigned int rex64
:1;
563 unsigned int vexvvvv
:2;
565 unsigned int vexopcode
:3;
566 unsigned int vexsources
:2;
567 unsigned int veximmext
:1;
568 unsigned int vecsib
:2;
569 unsigned int sse2avx
:1;
570 unsigned int noavx
:1;
572 unsigned int masking
:2;
573 unsigned int vecesize
:1;
574 unsigned int broadcast
:3;
575 unsigned int staticrounding
:1;
577 unsigned int disp8memshift
:3;
578 unsigned int nodefmask
:1;
579 unsigned int oldgcc
:1;
580 unsigned int attmnemonic
:1;
581 unsigned int attsyntax
:1;
582 unsigned int intelsyntax
:1;
583 } i386_opcode_modifier
;
585 /* Position of operand_type bits. */
597 /* Floating pointer stack register */
605 /* AVX512 registers */
607 /* Vector Mask registers */
609 /* Control register */
615 /* 2 bit segment register */
617 /* 3 bit segment register */
619 /* 1 bit immediate */
621 /* 8 bit immediate */
623 /* 8 bit immediate sign extended */
625 /* 16 bit immediate */
627 /* 32 bit immediate */
629 /* 32 bit immediate sign extended */
631 /* 64 bit immediate */
633 /* 8bit/16bit/32bit displacements are used in different ways,
634 depending on the instruction. For jumps, they specify the
635 size of the PC relative displacement, for instructions with
636 memory operand, they specify the size of the offset relative
637 to the base register, and for instructions with memory offset
638 such as `mov 1234,%al' they specify the size of the offset
639 relative to the segment base. */
640 /* 8 bit displacement */
642 /* 16 bit displacement */
644 /* 32 bit displacement */
646 /* 32 bit signed displacement */
648 /* 64 bit displacement */
650 /* Accumulator %al/%ax/%eax/%rax */
652 /* Floating pointer top stack register %st(0) */
654 /* Register which can be used for base or index in memory operand. */
656 /* Register to hold in/out port addr = dx */
658 /* Register to hold shift count = cl */
660 /* Absolute address for jump. */
662 /* String insn operand with fixed es segment */
664 /* RegMem is for instructions with a modrm byte where the register
665 destination operand should be encoded in the mod and regmem fields.
666 Normally, it will be encoded in the reg field. We add a RegMem
667 flag to the destination register operand to indicate that it should
668 be encoded in the regmem field. */
674 /* WORD memory. 2 byte */
676 /* DWORD memory. 4 byte */
678 /* FWORD memory. 6 byte */
680 /* QWORD memory. 8 byte */
682 /* TBYTE memory. 10 byte */
684 /* XMMWORD memory. */
686 /* YMMWORD memory. */
688 /* ZMMWORD memory. */
690 /* Unspecified memory size. */
692 /* Any memory size. */
695 /* Vector 4 bit immediate. */
698 /* Bound register. */
701 /* Vector 8bit displacement */
704 /* The last bitfield in i386_operand_type. */
708 #define OTNumOfUints \
709 (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
710 #define OTNumOfBits \
711 (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
713 /* If you get a compiler error for zero width of the unused field,
715 #define OTUnused (OTMax + 1)
717 typedef union i386_operand_type
722 unsigned int reg16
:1;
723 unsigned int reg32
:1;
724 unsigned int reg64
:1;
725 unsigned int floatreg
:1;
726 unsigned int regmmx
:1;
727 unsigned int regxmm
:1;
728 unsigned int regymm
:1;
729 unsigned int regzmm
:1;
730 unsigned int regmask
:1;
731 unsigned int control
:1;
732 unsigned int debug
:1;
734 unsigned int sreg2
:1;
735 unsigned int sreg3
:1;
738 unsigned int imm8s
:1;
739 unsigned int imm16
:1;
740 unsigned int imm32
:1;
741 unsigned int imm32s
:1;
742 unsigned int imm64
:1;
743 unsigned int disp8
:1;
744 unsigned int disp16
:1;
745 unsigned int disp32
:1;
746 unsigned int disp32s
:1;
747 unsigned int disp64
:1;
749 unsigned int floatacc
:1;
750 unsigned int baseindex
:1;
751 unsigned int inoutportreg
:1;
752 unsigned int shiftcount
:1;
753 unsigned int jumpabsolute
:1;
754 unsigned int esseg
:1;
755 unsigned int regmem
:1;
759 unsigned int dword
:1;
760 unsigned int fword
:1;
761 unsigned int qword
:1;
762 unsigned int tbyte
:1;
763 unsigned int xmmword
:1;
764 unsigned int ymmword
:1;
765 unsigned int zmmword
:1;
766 unsigned int unspecified
:1;
767 unsigned int anysize
:1;
768 unsigned int vec_imm4
:1;
769 unsigned int regbnd
:1;
770 unsigned int vec_disp8
:1;
772 unsigned int unused
:(OTNumOfBits
- OTUnused
);
775 unsigned int array
[OTNumOfUints
];
778 typedef struct insn_template
780 /* instruction name sans width suffix ("mov" for movl insns) */
783 /* how many operands */
784 unsigned int operands
;
786 /* base_opcode is the fundamental opcode byte without optional
788 unsigned int base_opcode
;
789 #define Opcode_D 0x2 /* Direction bit:
790 set if Reg --> Regmem;
791 unset if Regmem --> Reg. */
792 #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
793 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
795 /* extension_opcode is the 3 bit extension for group <n> insns.
796 This field is also used to store the 8-bit opcode suffix for the
797 AMD 3DNow! instructions.
798 If this template has no extension opcode (the usual case) use None
800 unsigned int extension_opcode
;
801 #define None 0xffff /* If no extension_opcode is possible. */
804 unsigned char opcode_length
;
806 /* cpu feature flags */
807 i386_cpu_flags cpu_flags
;
809 /* the bits in opcode_modifier are used to generate the final opcode from
810 the base_opcode. These bits also are used to detect alternate forms of
811 the same instruction */
812 i386_opcode_modifier opcode_modifier
;
814 /* operand_types[i] describes the type of operand i. This is made
815 by OR'ing together all of the possible type masks. (e.g.
816 'operand_types[i] = Reg|Imm' specifies that operand i can be
817 either a register or an immediate operand. */
818 i386_operand_type operand_types
[MAX_OPERANDS
];
822 extern const insn_template i386_optab
[];
824 /* these are for register name --> number & type hash lookup */
828 i386_operand_type reg_type
;
829 unsigned char reg_flags
;
830 #define RegRex 0x1 /* Extended register. */
831 #define RegRex64 0x2 /* Extended 8 bit register. */
832 #define RegVRex 0x4 /* Extended vector register. */
833 unsigned char reg_num
;
834 #define RegRip ((unsigned char ) ~0)
835 #define RegEip (RegRip - 1)
836 /* EIZ and RIZ are fake index registers. */
837 #define RegEiz (RegEip - 1)
838 #define RegRiz (RegEiz - 1)
839 /* FLAT is a fake segment register (Intel mode). */
840 #define RegFlat ((unsigned char) ~0)
841 signed char dw2_regnum
[2];
842 #define Dw2Inval (-1)
846 /* Entries in i386_regtab. */
849 #define REGNAM_EAX 41
851 extern const reg_entry i386_regtab
[];
852 extern const unsigned int i386_regtab_size
;
857 unsigned int seg_prefix
;
861 extern const seg_entry cs
;
862 extern const seg_entry ds
;
863 extern const seg_entry ss
;
864 extern const seg_entry es
;
865 extern const seg_entry fs
;
866 extern const seg_entry gs
;