1 /* Declarations for Intel 80386 opcode table
2 Copyright (C) 2007-2019 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 #include "opcode/i386.h"
30 /* Position of cpu flags bitfiled. */
34 /* i186 or better required */
36 /* i286 or better required */
38 /* i386 or better required */
40 /* i486 or better required */
42 /* i585 or better required */
44 /* i686 or better required */
46 /* CMOV Instruction support required */
48 /* FXSR Instruction support required */
50 /* CLFLUSH Instruction support required */
52 /* NOP Instruction support required */
54 /* SYSCALL Instructions support required */
56 /* Floating point support required */
58 /* i287 support required */
60 /* i387 support required */
62 /* i686 and floating point support required */
64 /* SSE3 and floating point support required */
66 /* MMX support required */
68 /* SSE support required */
70 /* SSE2 support required */
72 /* 3dnow! support required */
74 /* 3dnow! Extensions support required */
76 /* SSE3 support required */
78 /* VIA PadLock required */
80 /* AMD Secure Virtual Machine Ext-s required */
82 /* VMX Instructions required */
84 /* SMX Instructions required */
86 /* SSSE3 support required */
88 /* SSE4a support required */
90 /* ABM New Instructions required */
92 /* SSE4.1 support required */
94 /* SSE4.2 support required */
96 /* AVX support required */
98 /* AVX2 support required */
100 /* Intel AVX-512 Foundation Instructions support required */
102 /* Intel AVX-512 Conflict Detection Instructions support required */
104 /* Intel AVX-512 Exponential and Reciprocal Instructions support
107 /* Intel AVX-512 Prefetch Instructions support required */
109 /* Intel AVX-512 VL Instructions support required. */
111 /* Intel AVX-512 DQ Instructions support required. */
113 /* Intel AVX-512 BW Instructions support required. */
115 /* Intel L1OM support required */
117 /* Intel K1OM support required */
119 /* Intel IAMCU support required */
121 /* Xsave/xrstor New Instructions support required */
123 /* Xsaveopt New Instructions support required */
125 /* AES support required */
127 /* PCLMUL support required */
129 /* FMA support required */
131 /* FMA4 support required */
133 /* XOP support required */
135 /* LWP support required */
137 /* BMI support required */
139 /* TBM support required */
141 /* MOVBE Instruction support required */
143 /* CMPXCHG16B instruction support required. */
145 /* EPT Instructions required */
147 /* RDTSCP Instruction support required */
149 /* FSGSBASE Instructions required */
151 /* RDRND Instructions required */
153 /* F16C Instructions required */
155 /* Intel BMI2 support required */
157 /* LZCNT support required */
159 /* HLE support required */
161 /* RTM support required */
163 /* INVPCID Instructions required */
165 /* VMFUNC Instruction required */
167 /* Intel MPX Instructions required */
169 /* 64bit support available, used by -march= in assembler. */
171 /* RDRSEED instruction required. */
173 /* Multi-presisionn add-carry instructions are required. */
175 /* Supports prefetchw and prefetch instructions. */
177 /* SMAP instructions required. */
179 /* SHA instructions required. */
181 /* CLFLUSHOPT instruction required */
183 /* XSAVES/XRSTORS instruction required */
185 /* XSAVEC instruction required */
187 /* PREFETCHWT1 instruction required */
189 /* SE1 instruction required */
191 /* CLWB instruction required */
193 /* Intel AVX-512 IFMA Instructions support required. */
195 /* Intel AVX-512 VBMI Instructions support required. */
197 /* Intel AVX-512 4FMAPS Instructions support required. */
199 /* Intel AVX-512 4VNNIW Instructions support required. */
201 /* Intel AVX-512 VPOPCNTDQ Instructions support required. */
203 /* Intel AVX-512 VBMI2 Instructions support required. */
205 /* Intel AVX-512 VNNI Instructions support required. */
207 /* Intel AVX-512 BITALG Instructions support required. */
209 /* Intel AVX-512 BF16 Instructions support required. */
211 /* Intel AVX-512 VP2INTERSECT Instructions support required. */
212 CpuAVX512_VP2INTERSECT
,
213 /* mwaitx instruction required */
215 /* Clzero instruction required */
217 /* OSPKE instruction required */
219 /* RDPID instruction required */
221 /* PTWRITE instruction required */
223 /* CET instructions support required */
226 /* GFNI instructions required */
228 /* VAES instructions required */
230 /* VPCLMULQDQ instructions required */
232 /* WBNOINVD instructions required */
234 /* PCONFIG instructions required */
236 /* WAITPKG instructions required */
238 /* CLDEMOTE instruction required */
240 /* MOVDIRI instruction support required */
242 /* MOVDIRR64B instruction required */
244 /* ENQCMD instruction required */
246 /* 64bit support required */
248 /* Not supported in the 64bit mode */
250 /* The last bitfield in i386_cpu_flags. */
254 #define CpuNumOfUints \
255 (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
256 #define CpuNumOfBits \
257 (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
259 /* If you get a compiler error for zero width of the unused field,
261 #define CpuUnused (CpuMax + 1)
263 /* We can check if an instruction is available with array instead
265 typedef union i386_cpu_flags
269 unsigned int cpui186
:1;
270 unsigned int cpui286
:1;
271 unsigned int cpui386
:1;
272 unsigned int cpui486
:1;
273 unsigned int cpui586
:1;
274 unsigned int cpui686
:1;
275 unsigned int cpucmov
:1;
276 unsigned int cpufxsr
:1;
277 unsigned int cpuclflush
:1;
278 unsigned int cpunop
:1;
279 unsigned int cpusyscall
:1;
280 unsigned int cpu8087
:1;
281 unsigned int cpu287
:1;
282 unsigned int cpu387
:1;
283 unsigned int cpu687
:1;
284 unsigned int cpufisttp
:1;
285 unsigned int cpummx
:1;
286 unsigned int cpusse
:1;
287 unsigned int cpusse2
:1;
288 unsigned int cpua3dnow
:1;
289 unsigned int cpua3dnowa
:1;
290 unsigned int cpusse3
:1;
291 unsigned int cpupadlock
:1;
292 unsigned int cpusvme
:1;
293 unsigned int cpuvmx
:1;
294 unsigned int cpusmx
:1;
295 unsigned int cpussse3
:1;
296 unsigned int cpusse4a
:1;
297 unsigned int cpuabm
:1;
298 unsigned int cpusse4_1
:1;
299 unsigned int cpusse4_2
:1;
300 unsigned int cpuavx
:1;
301 unsigned int cpuavx2
:1;
302 unsigned int cpuavx512f
:1;
303 unsigned int cpuavx512cd
:1;
304 unsigned int cpuavx512er
:1;
305 unsigned int cpuavx512pf
:1;
306 unsigned int cpuavx512vl
:1;
307 unsigned int cpuavx512dq
:1;
308 unsigned int cpuavx512bw
:1;
309 unsigned int cpul1om
:1;
310 unsigned int cpuk1om
:1;
311 unsigned int cpuiamcu
:1;
312 unsigned int cpuxsave
:1;
313 unsigned int cpuxsaveopt
:1;
314 unsigned int cpuaes
:1;
315 unsigned int cpupclmul
:1;
316 unsigned int cpufma
:1;
317 unsigned int cpufma4
:1;
318 unsigned int cpuxop
:1;
319 unsigned int cpulwp
:1;
320 unsigned int cpubmi
:1;
321 unsigned int cputbm
:1;
322 unsigned int cpumovbe
:1;
323 unsigned int cpucx16
:1;
324 unsigned int cpuept
:1;
325 unsigned int cpurdtscp
:1;
326 unsigned int cpufsgsbase
:1;
327 unsigned int cpurdrnd
:1;
328 unsigned int cpuf16c
:1;
329 unsigned int cpubmi2
:1;
330 unsigned int cpulzcnt
:1;
331 unsigned int cpuhle
:1;
332 unsigned int cpurtm
:1;
333 unsigned int cpuinvpcid
:1;
334 unsigned int cpuvmfunc
:1;
335 unsigned int cpumpx
:1;
336 unsigned int cpulm
:1;
337 unsigned int cpurdseed
:1;
338 unsigned int cpuadx
:1;
339 unsigned int cpuprfchw
:1;
340 unsigned int cpusmap
:1;
341 unsigned int cpusha
:1;
342 unsigned int cpuclflushopt
:1;
343 unsigned int cpuxsaves
:1;
344 unsigned int cpuxsavec
:1;
345 unsigned int cpuprefetchwt1
:1;
346 unsigned int cpuse1
:1;
347 unsigned int cpuclwb
:1;
348 unsigned int cpuavx512ifma
:1;
349 unsigned int cpuavx512vbmi
:1;
350 unsigned int cpuavx512_4fmaps
:1;
351 unsigned int cpuavx512_4vnniw
:1;
352 unsigned int cpuavx512_vpopcntdq
:1;
353 unsigned int cpuavx512_vbmi2
:1;
354 unsigned int cpuavx512_vnni
:1;
355 unsigned int cpuavx512_bitalg
:1;
356 unsigned int cpuavx512_bf16
:1;
357 unsigned int cpuavx512_vp2intersect
:1;
358 unsigned int cpumwaitx
:1;
359 unsigned int cpuclzero
:1;
360 unsigned int cpuospke
:1;
361 unsigned int cpurdpid
:1;
362 unsigned int cpuptwrite
:1;
363 unsigned int cpuibt
:1;
364 unsigned int cpushstk
:1;
365 unsigned int cpugfni
:1;
366 unsigned int cpuvaes
:1;
367 unsigned int cpuvpclmulqdq
:1;
368 unsigned int cpuwbnoinvd
:1;
369 unsigned int cpupconfig
:1;
370 unsigned int cpuwaitpkg
:1;
371 unsigned int cpucldemote
:1;
372 unsigned int cpumovdiri
:1;
373 unsigned int cpumovdir64b
:1;
374 unsigned int cpuenqcmd
:1;
375 unsigned int cpu64
:1;
376 unsigned int cpuno64
:1;
378 unsigned int unused
:(CpuNumOfBits
- CpuUnused
);
381 unsigned int array
[CpuNumOfUints
];
384 /* Position of opcode_modifier bits. */
388 /* has direction bit. */
390 /* set if operands can be words or dwords encoded the canonical way */
392 /* load form instruction. Must be placed before store form. */
394 /* insn has a modrm byte. */
396 /* register is in low 3 bits of opcode */
398 /* special case for jump insns. */
404 /* special case for intersegment leaps/calls */
406 /* FP insn memory format bit, sized by 0x4 */
408 /* src/dest swap for floats. */
410 /* needs size prefix if in 32-bit mode */
412 /* needs size prefix if in 16-bit mode */
414 /* needs size prefix if in 64-bit mode */
417 /* check register size. */
419 /* instruction ignores operand size prefix and in Intel mode ignores
420 mnemonic size suffix check. */
422 /* default insn size depends on mode */
424 /* b suffix on instruction illegal */
426 /* w suffix on instruction illegal */
428 /* l suffix on instruction illegal */
430 /* s suffix on instruction illegal */
432 /* q suffix on instruction illegal */
434 /* long double suffix on instruction illegal */
436 /* instruction needs FWAIT */
438 /* quick test for string instructions */
440 /* RegMem is for instructions with a modrm byte where the register
441 destination operand should be encoded in the mod and regmem fields.
442 Normally, it will be encoded in the reg field. We add a RegMem
443 flag to indicate that it should be encoded in the regmem field. */
445 /* quick test if branch instruction is MPX supported */
447 /* quick test if NOTRACK prefix is supported */
449 /* quick test for lockable instructions */
451 /* fake an extra reg operand for clr, imul and special register
452 processing for some instructions. */
454 /* An implicit xmm0 as the first operand */
456 /* The HLE prefix is OK:
457 1. With a LOCK prefix.
458 2. With or without a LOCK prefix.
459 3. With a RELEASE (0xf3) prefix.
461 #define HLEPrefixNone 0
462 #define HLEPrefixLock 1
463 #define HLEPrefixAny 2
464 #define HLEPrefixRelease 3
466 /* An instruction on which a "rep" prefix is acceptable. */
468 /* Convert to DWORD */
470 /* Convert to QWORD */
472 /* Address prefix changes register operand */
474 /* opcode is a prefix */
476 /* instruction has extension in 8 bit imm */
478 /* instruction don't need Rex64 prefix. */
480 /* instruction require Rex64 prefix. */
482 /* deprecated fp insn, gets a warning */
484 /* insn has VEX prefix:
485 1: 128bit VEX prefix (or operand dependent).
486 2: 256bit VEX prefix.
487 3: Scalar VEX prefix.
493 /* How to encode VEX.vvvv:
494 0: VEX.vvvv must be 1111b.
495 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where
496 the content of source registers will be preserved.
497 VEX.DDS. The second register operand is encoded in VEX.vvvv
498 where the content of first source register will be overwritten
500 VEX.NDD2. The second destination register operand is encoded in
501 VEX.vvvv for instructions with 2 destination register operands.
502 For assembler, there are no difference between VEX.NDS, VEX.DDS
504 2. VEX.NDD. Register destination is encoded in VEX.vvvv for
505 instructions with 1 destination register operand.
506 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one
507 of the operands can access a memory location.
513 /* How the VEX.W bit is used:
514 0: Set by the REX.W bit.
515 1: VEX.W0. Should always be 0.
516 2: VEX.W1. Should always be 1.
517 3: VEX.WIG. The VEX.W bit is ignored.
523 /* VEX opcode prefix:
524 0: VEX 0x0F opcode prefix.
525 1: VEX 0x0F38 opcode prefix.
526 2: VEX 0x0F3A opcode prefix
527 3: XOP 0x08 opcode prefix.
528 4: XOP 0x09 opcode prefix
529 5: XOP 0x0A opcode prefix.
538 /* number of VEX source operands:
539 0: <= 2 source operands.
540 1: 2 XOP source operands.
541 2: 3 source operands.
543 #define XOP2SOURCES 1
544 #define VEX3SOURCES 2
546 /* Instruction with vector SIB byte:
547 1: 128bit vector register.
548 2: 256bit vector register.
549 3: 512bit vector register.
555 /* SSE to AVX support required */
557 /* No AVX equivalent */
560 /* insn has EVEX prefix:
561 1: 512bit EVEX prefix.
562 2: 128bit EVEX prefix.
563 3: 256bit EVEX prefix.
564 4: Length-ignored (LIG) EVEX prefix.
565 5: Length determined from actual operands.
574 /* AVX512 masking support:
575 1: Zeroing or merging masking depending on operands.
577 3: Both zeroing and merging masking.
579 #define DYNAMIC_MASKING 1
580 #define MERGING_MASKING 2
581 #define BOTH_MASKING 3
584 /* AVX512 broadcast support. The number of bytes to broadcast is
585 1 << (Broadcast - 1):
591 #define BYTE_BROADCAST 1
592 #define WORD_BROADCAST 2
593 #define DWORD_BROADCAST 3
594 #define QWORD_BROADCAST 4
597 /* Static rounding control is supported. */
600 /* Supress All Exceptions is supported. */
603 /* Compressed Disp8*N attribute. */
604 #define DISP8_SHIFT_VL 7
607 /* Default mask isn't allowed. */
610 /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
611 It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
615 /* Support encoding optimization. */
628 /* The last bitfield in i386_opcode_modifier. */
632 typedef struct i386_opcode_modifier
637 unsigned int modrm
:1;
638 unsigned int shortform
:1;
640 unsigned int jumpdword
:1;
641 unsigned int jumpbyte
:1;
642 unsigned int jumpintersegment
:1;
643 unsigned int floatmf
:1;
644 unsigned int floatr
:1;
646 unsigned int checkregsize
:1;
647 unsigned int ignoresize
:1;
648 unsigned int defaultsize
:1;
649 unsigned int no_bsuf
:1;
650 unsigned int no_wsuf
:1;
651 unsigned int no_lsuf
:1;
652 unsigned int no_ssuf
:1;
653 unsigned int no_qsuf
:1;
654 unsigned int no_ldsuf
:1;
655 unsigned int fwait
:1;
656 unsigned int isstring
:1;
657 unsigned int regmem
:1;
658 unsigned int bndprefixok
:1;
659 unsigned int notrackprefixok
:1;
660 unsigned int islockable
:1;
661 unsigned int regkludge
:1;
662 unsigned int implicit1stxmm0
:1;
663 unsigned int hleprefixok
:2;
664 unsigned int repprefixok
:1;
665 unsigned int todword
:1;
666 unsigned int toqword
:1;
667 unsigned int addrprefixopreg
:1;
668 unsigned int isprefix
:1;
669 unsigned int immext
:1;
670 unsigned int norex64
:1;
671 unsigned int rex64
:1;
674 unsigned int vexvvvv
:2;
676 unsigned int vexopcode
:3;
677 unsigned int vexsources
:2;
678 unsigned int vecsib
:2;
679 unsigned int sse2avx
:1;
680 unsigned int noavx
:1;
682 unsigned int masking
:2;
683 unsigned int broadcast
:3;
684 unsigned int staticrounding
:1;
686 unsigned int disp8memshift
:3;
687 unsigned int nodefmask
:1;
688 unsigned int implicitquadgroup
:1;
689 unsigned int optimize
:1;
690 unsigned int attmnemonic
:1;
691 unsigned int attsyntax
:1;
692 unsigned int intelsyntax
:1;
693 unsigned int amd64
:1;
694 unsigned int intel64
:1;
695 } i386_opcode_modifier
;
697 /* Position of operand_type bits. */
701 /* Register (qualified by Byte, Word, etc) */
705 /* Vector registers */
707 /* Vector Mask registers */
709 /* Control register */
715 /* Segment register */
717 /* 1 bit immediate */
719 /* 8 bit immediate */
721 /* 8 bit immediate sign extended */
723 /* 16 bit immediate */
725 /* 32 bit immediate */
727 /* 32 bit immediate sign extended */
729 /* 64 bit immediate */
731 /* 8bit/16bit/32bit displacements are used in different ways,
732 depending on the instruction. For jumps, they specify the
733 size of the PC relative displacement, for instructions with
734 memory operand, they specify the size of the offset relative
735 to the base register, and for instructions with memory offset
736 such as `mov 1234,%al' they specify the size of the offset
737 relative to the segment base. */
738 /* 8 bit displacement */
740 /* 16 bit displacement */
742 /* 32 bit displacement */
744 /* 32 bit signed displacement */
746 /* 64 bit displacement */
748 /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
750 /* Register which can be used for base or index in memory operand. */
752 /* Register to hold in/out port addr = dx */
754 /* Register to hold shift count = cl */
756 /* Absolute address for jump. */
758 /* String insn operand with fixed es segment */
762 /* WORD size. 2 byte */
764 /* DWORD size. 4 byte */
766 /* FWORD size. 6 byte */
768 /* QWORD size. 8 byte */
770 /* TBYTE size. 10 byte */
778 /* Unspecified memory size. */
780 /* Any memory size. */
783 /* Bound register. */
786 /* The number of bitfields in i386_operand_type. */
790 #define OTNumOfUints \
791 ((OTNum - 1) / sizeof (unsigned int) / CHAR_BIT + 1)
792 #define OTNumOfBits \
793 (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
795 /* If you get a compiler error for zero width of the unused field,
797 #define OTUnused OTNum
799 typedef union i386_operand_type
804 unsigned int regmmx
:1;
805 unsigned int regsimd
:1;
806 unsigned int regmask
:1;
807 unsigned int control
:1;
808 unsigned int debug
:1;
813 unsigned int imm8s
:1;
814 unsigned int imm16
:1;
815 unsigned int imm32
:1;
816 unsigned int imm32s
:1;
817 unsigned int imm64
:1;
818 unsigned int disp8
:1;
819 unsigned int disp16
:1;
820 unsigned int disp32
:1;
821 unsigned int disp32s
:1;
822 unsigned int disp64
:1;
824 unsigned int baseindex
:1;
825 unsigned int inoutportreg
:1;
826 unsigned int shiftcount
:1;
827 unsigned int jumpabsolute
:1;
828 unsigned int esseg
:1;
831 unsigned int dword
:1;
832 unsigned int fword
:1;
833 unsigned int qword
:1;
834 unsigned int tbyte
:1;
835 unsigned int xmmword
:1;
836 unsigned int ymmword
:1;
837 unsigned int zmmword
:1;
838 unsigned int unspecified
:1;
839 unsigned int anysize
:1;
840 unsigned int regbnd
:1;
842 unsigned int unused
:(OTNumOfBits
- OTUnused
);
845 unsigned int array
[OTNumOfUints
];
848 typedef struct insn_template
850 /* instruction name sans width suffix ("mov" for movl insns) */
853 /* how many operands */
854 unsigned int operands
;
856 /* base_opcode is the fundamental opcode byte without optional
858 unsigned int base_opcode
;
859 #define Opcode_D 0x2 /* Direction bit:
860 set if Reg --> Regmem;
861 unset if Regmem --> Reg. */
862 #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
863 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
864 #define Opcode_SIMD_FloatD 0x1 /* Direction bit for SIMD fp insns. */
865 #define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */
867 /* extension_opcode is the 3 bit extension for group <n> insns.
868 This field is also used to store the 8-bit opcode suffix for the
869 AMD 3DNow! instructions.
870 If this template has no extension opcode (the usual case) use None
872 unsigned int extension_opcode
;
873 #define None 0xffff /* If no extension_opcode is possible. */
876 unsigned char opcode_length
;
878 /* cpu feature flags */
879 i386_cpu_flags cpu_flags
;
881 /* the bits in opcode_modifier are used to generate the final opcode from
882 the base_opcode. These bits also are used to detect alternate forms of
883 the same instruction */
884 i386_opcode_modifier opcode_modifier
;
886 /* operand_types[i] describes the type of operand i. This is made
887 by OR'ing together all of the possible type masks. (e.g.
888 'operand_types[i] = Reg|Imm' specifies that operand i can be
889 either a register or an immediate operand. */
890 i386_operand_type operand_types
[MAX_OPERANDS
];
894 extern const insn_template i386_optab
[];
896 /* these are for register name --> number & type hash lookup */
900 i386_operand_type reg_type
;
901 unsigned char reg_flags
;
902 #define RegRex 0x1 /* Extended register. */
903 #define RegRex64 0x2 /* Extended 8 bit register. */
904 #define RegVRex 0x4 /* Extended vector register. */
905 unsigned char reg_num
;
906 #define RegIP ((unsigned char ) ~0)
907 /* EIZ and RIZ are fake index registers. */
908 #define RegIZ (RegIP - 1)
909 /* FLAT is a fake segment register (Intel mode). */
910 #define RegFlat ((unsigned char) ~0)
911 signed char dw2_regnum
[2];
912 #define Dw2Inval (-1)
916 /* Entries in i386_regtab. */
919 #define REGNAM_EAX 41
921 extern const reg_entry i386_regtab
[];
922 extern const unsigned int i386_regtab_size
;
927 unsigned int seg_prefix
;
931 extern const seg_entry cs
;
932 extern const seg_entry ds
;
933 extern const seg_entry ss
;
934 extern const seg_entry es
;
935 extern const seg_entry fs
;
936 extern const seg_entry gs
;