opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright 2007, 2008, 2009, 2010
   3    Free Software Foundation, Inc.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  20    02110-1301, USA.  */
  21
  22 #include "opcode/i386.h"
  23 #ifdef HAVE_LIMITS_H
  24 #include <limits.h>
  25 #endif
  26
  27 #ifndef CHAR_BIT
  28 #define CHAR_BIT 8
  29 #endif
  30
  31 /* Position of cpu flags bitfiled.  */
  32
  33 enum
  34 {
  35   /* i186 or better required */
  36   Cpu186 = 0,
  37   /* i286 or better required */
  38   Cpu286,
  39   /* i386 or better required */
  40   Cpu386,
  41   /* i486 or better required */
  42   Cpu486,
  43   /* i585 or better required */
  44   Cpu586,
  45   /* i686 or better required */
  46   Cpu686,
  47   /* CLFLUSH Instruction support required */
  48   CpuClflush,
  49   /* NOP Instruction support required */
  50   CpuNop,
  51   /* SYSCALL Instructions support required */
  52   CpuSYSCALL,
  53   /* Floating point support required */
  54   Cpu8087,
  55   /* i287 support required */
  56   Cpu287,
  57   /* i387 support required */
  58   Cpu387,
  59   /* i686 and floating point support required */
  60   Cpu687,
  61   /* SSE3 and floating point support required */
  62   CpuFISTTP,
  63   /* MMX support required */
  64   CpuMMX,
  65   /* SSE support required */
  66   CpuSSE,
  67   /* SSE2 support required */
  68   CpuSSE2,
  69   /* 3dnow! support required */
  70   Cpu3dnow,
  71   /* 3dnow! Extensions support required */
  72   Cpu3dnowA,
  73   /* SSE3 support required */
  74   CpuSSE3,
  75   /* VIA PadLock required */
  76   CpuPadLock,
  77   /* AMD Secure Virtual Machine Ext-s required */
  78   CpuSVME,
  79   /* VMX Instructions required */
  80   CpuVMX,
  81   /* SMX Instructions required */
  82   CpuSMX,
  83   /* SSSE3 support required */
  84   CpuSSSE3,
  85   /* SSE4a support required */
  86   CpuSSE4a,
  87   /* ABM New Instructions required */
  88   CpuABM,
  89   /* SSE4.1 support required */
  90   CpuSSE4_1,
  91   /* SSE4.2 support required */
  92   CpuSSE4_2,
  93   /* AVX support required */
  94   CpuAVX,
  95   /* Intel L1OM support required */
  96   CpuL1OM,
  97   /* Xsave/xrstor New Instructions support required */
  98   CpuXsave,
  99   /* Xsaveopt New Instructions support required */
 100   CpuXsaveopt,
 101   /* AES support required */
 102   CpuAES,
 103   /* PCLMUL support required */
 104   CpuPCLMUL,
 105   /* FMA support required */
 106   CpuFMA,
 107   /* FMA4 support required */
 108   CpuFMA4,
 109   /* XOP support required */
 110   CpuXOP,
 111   /* LWP support required */
 112   CpuLWP,
 113   /* BMI support required */
 114   CpuBMI,
 115   /* MOVBE Instruction support required */
 116   CpuMovbe,
 117   /* EPT Instructions required */
 118   CpuEPT,
 119   /* RDTSCP Instruction support required */
 120   CpuRdtscp,
 121   /* FSGSBASE Instructions required */
 122   CpuFSGSBase,
 123   /* RDRND Instructions required */
 124   CpuRdRnd,
 125   /* F16C Instructions required */
 126   CpuF16C,
 127   /* 64bit support available, used by -march= in assembler.  */
 128   CpuLM,
 129   /* 64bit support required  */
 130   Cpu64,
 131   /* Not supported in the 64bit mode  */
 132   CpuNo64,
 133   /* The last bitfield in i386_cpu_flags.  */
 134   CpuMax = CpuNo64
 135 };
 136
 137 #define CpuNumOfUints \
 138   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 139 #define CpuNumOfBits \
 140   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 141
 142 /* If you get a compiler error for zero width of the unused field,
 143    comment it out.  */
 144 #define CpuUnused       (CpuMax + 1)
 145
 146 /* We can check if an instruction is available with array instead
 147    of bitfield. */
 148 typedef union i386_cpu_flags
 149 {
 150   struct
 151     {
 152       unsigned int cpui186:1;
 153       unsigned int cpui286:1;
 154       unsigned int cpui386:1;
 155       unsigned int cpui486:1;
 156       unsigned int cpui586:1;
 157       unsigned int cpui686:1;
 158       unsigned int cpuclflush:1;
 159       unsigned int cpunop:1;
 160       unsigned int cpusyscall:1;
 161       unsigned int cpu8087:1;
 162       unsigned int cpu287:1;
 163       unsigned int cpu387:1;
 164       unsigned int cpu687:1;
 165       unsigned int cpufisttp:1;
 166       unsigned int cpummx:1;
 167       unsigned int cpusse:1;
 168       unsigned int cpusse2:1;
 169       unsigned int cpua3dnow:1;
 170       unsigned int cpua3dnowa:1;
 171       unsigned int cpusse3:1;
 172       unsigned int cpupadlock:1;
 173       unsigned int cpusvme:1;
 174       unsigned int cpuvmx:1;
 175       unsigned int cpusmx:1;
 176       unsigned int cpussse3:1;
 177       unsigned int cpusse4a:1;
 178       unsigned int cpuabm:1;
 179       unsigned int cpusse4_1:1;
 180       unsigned int cpusse4_2:1;
 181       unsigned int cpuavx:1;
 182       unsigned int cpul1om:1;
 183       unsigned int cpuxsave:1;
 184       unsigned int cpuxsaveopt:1;
 185       unsigned int cpuaes:1;
 186       unsigned int cpupclmul:1;
 187       unsigned int cpufma:1;
 188       unsigned int cpufma4:1;
 189       unsigned int cpuxop:1;
 190       unsigned int cpulwp:1;
 191       unsigned int cpubmi:1;
 192       unsigned int cpumovbe:1;
 193       unsigned int cpuept:1;
 194       unsigned int cpurdtscp:1;
 195       unsigned int cpufsgsbase:1;
 196       unsigned int cpurdrnd:1;
 197       unsigned int cpuf16c:1;
 198       unsigned int cpulm:1;
 199       unsigned int cpu64:1;
 200       unsigned int cpuno64:1;
 201 #ifdef CpuUnused
 202       unsigned int unused:(CpuNumOfBits - CpuUnused);
 203 #endif
 204     } bitfield;
 205   unsigned int array[CpuNumOfUints];
 206 } i386_cpu_flags;
 207
 208 /* Position of opcode_modifier bits.  */
 209
 210 enum
 211 {
 212   /* has direction bit. */
 213   D = 0,
 214   /* set if operands can be words or dwords encoded the canonical way */
 215   W,
 216   /* Skip the current insn and use the next insn in i386-opc.tbl to swap
 217      operand in encoding.  */
 218   S,
 219   /* insn has a modrm byte. */
 220   Modrm,
 221   /* register is in low 3 bits of opcode */
 222   ShortForm,
 223   /* special case for jump insns.  */
 224   Jump,
 225   /* call and jump */
 226   JumpDword,
 227   /* loop and jecxz */
 228   JumpByte,
 229   /* special case for intersegment leaps/calls */
 230   JumpInterSegment,
 231   /* FP insn memory format bit, sized by 0x4 */
 232   FloatMF,
 233   /* src/dest swap for floats. */
 234   FloatR,
 235   /* has float insn direction bit. */
 236   FloatD,
 237   /* needs size prefix if in 32-bit mode */
 238   Size16,
 239   /* needs size prefix if in 16-bit mode */
 240   Size32,
 241   /* needs size prefix if in 64-bit mode */
 242   Size64,
 243   /* check register size.  */
 244   CheckRegSize,
 245   /* instruction ignores operand size prefix and in Intel mode ignores
 246      mnemonic size suffix check.  */
 247   IgnoreSize,
 248   /* default insn size depends on mode */
 249   DefaultSize,
 250   /* b suffix on instruction illegal */
 251   No_bSuf,
 252   /* w suffix on instruction illegal */
 253   No_wSuf,
 254   /* l suffix on instruction illegal */
 255   No_lSuf,
 256   /* s suffix on instruction illegal */
 257   No_sSuf,
 258   /* q suffix on instruction illegal */
 259   No_qSuf,
 260   /* long double suffix on instruction illegal */
 261   No_ldSuf,
 262   /* instruction needs FWAIT */
 263   FWait,
 264   /* quick test for string instructions */
 265   IsString,
 266   /* quick test for lockable instructions */
 267   IsLockable,
 268   /* fake an extra reg operand for clr, imul and special register
 269      processing for some instructions.  */
 270   RegKludge,
 271   /* The first operand must be xmm0 */
 272   FirstXmm0,
 273   /* An implicit xmm0 as the first operand */
 274   Implicit1stXmm0,
 275   /* Convert to DWORD */
 276   ToDword,
 277   /* Convert to QWORD */
 278   ToQword,
 279   /* Address prefix changes operand 0 */
 280   AddrPrefixOp0,
 281   /* opcode is a prefix */
 282   IsPrefix,
 283   /* instruction has extension in 8 bit imm */
 284   ImmExt,
 285   /* instruction don't need Rex64 prefix.  */
 286   NoRex64,
 287   /* instruction require Rex64 prefix.  */
 288   Rex64,
 289   /* deprecated fp insn, gets a warning */
 290   Ugh,
 291   /* insn has VEX prefix:
 292         1: 128bit VEX prefix.
 293         2: 256bit VEX prefix.
 294         3: Scalar VEX prefix.
 295    */
 296 #define VEX128          1
 297 #define VEX256          2
 298 #define VEXScalar       3
 299   Vex,
 300   /* How to encode VEX.vvvv:
 301      0: VEX.vvvv must be 1111b.
 302      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 303         the content of source registers will be preserved.
 304         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 305         where the content of first source register will be overwritten
 306         by the result.
 307         For assembler, there are no difference between VEX.NDS and
 308         VEX.DDS.
 309      2. VEX.NDD.  Register destination is encoded in VEX.vvvv.
 310      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 311         of the operands can access a memory location.
 312    */
 313 #define VEXXDS  1
 314 #define VEXNDD  2
 315 #define VEXLWP  3
 316   VexVVVV,
 317   /* How the VEX.W bit is used:
 318      0: Set by the REX.W bit.
 319      1: VEX.W0.  Should always be 0.
 320      2: VEX.W1.  Should always be 1.
 321    */
 322 #define VEXW0   1
 323 #define VEXW1   2
 324   VexW,
 325   /* VEX opcode prefix:
 326      0: VEX 0x0F opcode prefix.
 327      1: VEX 0x0F38 opcode prefix.
 328      2: VEX 0x0F3A opcode prefix
 329      3: XOP 0x08 opcode prefix.
 330      4: XOP 0x09 opcode prefix
 331      5: XOP 0x0A opcode prefix.
 332    */
 333 #define VEX0F           0
 334 #define VEX0F38         1
 335 #define VEX0F3A         2
 336 #define XOP08           3
 337 #define XOP09           4
 338 #define XOP0A           5
 339   VexOpcode,
 340   /* number of VEX source operands:
 341      0: <= 2 source operands.
 342      1: 2 XOP source operands.
 343      2: 3 source operands.
 344    */
 345 #define XOP2SOURCES     1
 346 #define VEX3SOURCES     2
 347   VexSources,
 348   /* instruction has VEX 8 bit imm */
 349   VexImmExt,
 350   /* SSE to AVX support required */
 351   SSE2AVX,
 352   /* No AVX equivalent */
 353   NoAVX,
 354   /* Compatible with old (<= 2.8.1) versions of gcc  */
 355   OldGcc,
 356   /* AT&T mnemonic.  */
 357   ATTMnemonic,
 358   /* AT&T syntax.  */
 359   ATTSyntax,
 360   /* Intel syntax.  */
 361   IntelSyntax,
 362   /* The last bitfield in i386_opcode_modifier.  */
 363   Opcode_Modifier_Max
 364 };
 365
 366 typedef struct i386_opcode_modifier
 367 {
 368   unsigned int d:1;
 369   unsigned int w:1;
 370   unsigned int s:1;
 371   unsigned int modrm:1;
 372   unsigned int shortform:1;
 373   unsigned int jump:1;
 374   unsigned int jumpdword:1;
 375   unsigned int jumpbyte:1;
 376   unsigned int jumpintersegment:1;
 377   unsigned int floatmf:1;
 378   unsigned int floatr:1;
 379   unsigned int floatd:1;
 380   unsigned int size16:1;
 381   unsigned int size32:1;
 382   unsigned int size64:1;
 383   unsigned int checkregsize:1;
 384   unsigned int ignoresize:1;
 385   unsigned int defaultsize:1;
 386   unsigned int no_bsuf:1;
 387   unsigned int no_wsuf:1;
 388   unsigned int no_lsuf:1;
 389   unsigned int no_ssuf:1;
 390   unsigned int no_qsuf:1;
 391   unsigned int no_ldsuf:1;
 392   unsigned int fwait:1;
 393   unsigned int isstring:1;
 394   unsigned int islockable:1;
 395   unsigned int regkludge:1;
 396   unsigned int firstxmm0:1;
 397   unsigned int implicit1stxmm0:1;
 398   unsigned int todword:1;
 399   unsigned int toqword:1;
 400   unsigned int addrprefixop0:1;
 401   unsigned int isprefix:1;
 402   unsigned int immext:1;
 403   unsigned int norex64:1;
 404   unsigned int rex64:1;
 405   unsigned int ugh:1;
 406   unsigned int vex:2;
 407   unsigned int vexvvvv:2;
 408   unsigned int vexw:2;
 409   unsigned int vexopcode:3;
 410   unsigned int vexsources:2;
 411   unsigned int veximmext:1;
 412   unsigned int sse2avx:1;
 413   unsigned int noavx:1;
 414   unsigned int oldgcc:1;
 415   unsigned int attmnemonic:1;
 416   unsigned int attsyntax:1;
 417   unsigned int intelsyntax:1;
 418 } i386_opcode_modifier;
 419
 420 /* Position of operand_type bits.  */
 421
 422 enum
 423 {
 424   /* 8bit register */
 425   Reg8 = 0,
 426   /* 16bit register */
 427   Reg16,
 428   /* 32bit register */
 429   Reg32,
 430   /* 64bit register */
 431   Reg64,
 432   /* Floating pointer stack register */
 433   FloatReg,
 434   /* MMX register */
 435   RegMMX,
 436   /* SSE register */
 437   RegXMM,
 438   /* AVX registers */
 439   RegYMM,
 440   /* Control register */
 441   Control,
 442   /* Debug register */
 443   Debug,
 444   /* Test register */
 445   Test,
 446   /* 2 bit segment register */
 447   SReg2,
 448   /* 3 bit segment register */
 449   SReg3,
 450   /* 1 bit immediate */
 451   Imm1,
 452   /* 8 bit immediate */
 453   Imm8,
 454   /* 8 bit immediate sign extended */
 455   Imm8S,
 456   /* 16 bit immediate */
 457   Imm16,
 458   /* 32 bit immediate */
 459   Imm32,
 460   /* 32 bit immediate sign extended */
 461   Imm32S,
 462   /* 64 bit immediate */
 463   Imm64,
 464   /* 8bit/16bit/32bit displacements are used in different ways,
 465      depending on the instruction.  For jumps, they specify the
 466      size of the PC relative displacement, for instructions with
 467      memory operand, they specify the size of the offset relative
 468      to the base register, and for instructions with memory offset
 469      such as `mov 1234,%al' they specify the size of the offset
 470      relative to the segment base.  */
 471   /* 8 bit displacement */
 472   Disp8,
 473   /* 16 bit displacement */
 474   Disp16,
 475   /* 32 bit displacement */
 476   Disp32,
 477   /* 32 bit signed displacement */
 478   Disp32S,
 479   /* 64 bit displacement */
 480   Disp64,
 481   /* Accumulator %al/%ax/%eax/%rax */
 482   Acc,
 483   /* Floating pointer top stack register %st(0) */
 484   FloatAcc,
 485   /* Register which can be used for base or index in memory operand.  */
 486   BaseIndex,
 487   /* Register to hold in/out port addr = dx */
 488   InOutPortReg,
 489   /* Register to hold shift count = cl */
 490   ShiftCount,
 491   /* Absolute address for jump.  */
 492   JumpAbsolute,
 493   /* String insn operand with fixed es segment */
 494   EsSeg,
 495   /* RegMem is for instructions with a modrm byte where the register
 496      destination operand should be encoded in the mod and regmem fields.
 497      Normally, it will be encoded in the reg field. We add a RegMem
 498      flag to the destination register operand to indicate that it should
 499      be encoded in the regmem field.  */
 500   RegMem,
 501   /* Memory.  */
 502   Mem,
 503   /* BYTE memory. */
 504   Byte,
 505   /* WORD memory. 2 byte */
 506   Word,
 507   /* DWORD memory. 4 byte */
 508   Dword,
 509   /* FWORD memory. 6 byte */
 510   Fword,
 511   /* QWORD memory. 8 byte */
 512   Qword,
 513   /* TBYTE memory. 10 byte */
 514   Tbyte,
 515   /* XMMWORD memory. */
 516   Xmmword,
 517   /* YMMWORD memory. */
 518   Ymmword,
 519   /* Unspecified memory size.  */
 520   Unspecified,
 521   /* Any memory size.  */
 522   Anysize,
 523
 524   /* Vector 4 bit immediate.  */
 525   Vec_Imm4,
 526
 527   /* The last bitfield in i386_operand_type.  */
 528   OTMax
 529 };
 530
 531 #define OTNumOfUints \
 532   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 533 #define OTNumOfBits \
 534   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 535
 536 /* If you get a compiler error for zero width of the unused field,
 537    comment it out.  */
 538 #define OTUnused                (OTMax + 1)
 539
 540 typedef union i386_operand_type
 541 {
 542   struct
 543     {
 544       unsigned int reg8:1;
 545       unsigned int reg16:1;
 546       unsigned int reg32:1;
 547       unsigned int reg64:1;
 548       unsigned int floatreg:1;
 549       unsigned int regmmx:1;
 550       unsigned int regxmm:1;
 551       unsigned int regymm:1;
 552       unsigned int control:1;
 553       unsigned int debug:1;
 554       unsigned int test:1;
 555       unsigned int sreg2:1;
 556       unsigned int sreg3:1;
 557       unsigned int imm1:1;
 558       unsigned int imm8:1;
 559       unsigned int imm8s:1;
 560       unsigned int imm16:1;
 561       unsigned int imm32:1;
 562       unsigned int imm32s:1;
 563       unsigned int imm64:1;
 564       unsigned int disp8:1;
 565       unsigned int disp16:1;
 566       unsigned int disp32:1;
 567       unsigned int disp32s:1;
 568       unsigned int disp64:1;
 569       unsigned int acc:1;
 570       unsigned int floatacc:1;
 571       unsigned int baseindex:1;
 572       unsigned int inoutportreg:1;
 573       unsigned int shiftcount:1;
 574       unsigned int jumpabsolute:1;
 575       unsigned int esseg:1;
 576       unsigned int regmem:1;
 577       unsigned int mem:1;
 578       unsigned int byte:1;
 579       unsigned int word:1;
 580       unsigned int dword:1;
 581       unsigned int fword:1;
 582       unsigned int qword:1;
 583       unsigned int tbyte:1;
 584       unsigned int xmmword:1;
 585       unsigned int ymmword:1;
 586       unsigned int unspecified:1;
 587       unsigned int anysize:1;
 588       unsigned int vec_imm4:1;
 589 #ifdef OTUnused
 590       unsigned int unused:(OTNumOfBits - OTUnused);
 591 #endif
 592     } bitfield;
 593   unsigned int array[OTNumOfUints];
 594 } i386_operand_type;
 595
 596 typedef struct insn_template
 597 {
 598   /* instruction name sans width suffix ("mov" for movl insns) */
 599   char *name;
 600
 601   /* how many operands */
 602   unsigned int operands;
 603
 604   /* base_opcode is the fundamental opcode byte without optional
 605      prefix(es).  */
 606   unsigned int base_opcode;
 607 #define Opcode_D        0x2 /* Direction bit:
 608                                set if Reg --> Regmem;
 609                                unset if Regmem --> Reg. */
 610 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 611 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 612
 613   /* extension_opcode is the 3 bit extension for group <n> insns.
 614      This field is also used to store the 8-bit opcode suffix for the
 615      AMD 3DNow! instructions.
 616      If this template has no extension opcode (the usual case) use None
 617      Instructions */
 618   unsigned int extension_opcode;
 619 #define None 0xffff             /* If no extension_opcode is possible.  */
 620
 621   /* Opcode length.  */
 622   unsigned char opcode_length;
 623
 624   /* cpu feature flags */
 625   i386_cpu_flags cpu_flags;
 626
 627   /* the bits in opcode_modifier are used to generate the final opcode from
 628      the base_opcode.  These bits also are used to detect alternate forms of
 629      the same instruction */
 630   i386_opcode_modifier opcode_modifier;
 631
 632   /* operand_types[i] describes the type of operand i.  This is made
 633      by OR'ing together all of the possible type masks.  (e.g.
 634      'operand_types[i] = Reg|Imm' specifies that operand i can be
 635      either a register or an immediate operand.  */
 636   i386_operand_type operand_types[MAX_OPERANDS];
 637 }
 638 insn_template;
 639
 640 extern const insn_template i386_optab[];
 641
 642 /* these are for register name --> number & type hash lookup */
 643 typedef struct
 644 {
 645   char *reg_name;
 646   i386_operand_type reg_type;
 647   unsigned char reg_flags;
 648 #define RegRex      0x1  /* Extended register.  */
 649 #define RegRex64    0x2  /* Extended 8 bit register.  */
 650   unsigned char reg_num;
 651 #define RegRip  ((unsigned char ) ~0)
 652 #define RegEip  (RegRip - 1)
 653 /* EIZ and RIZ are fake index registers.  */
 654 #define RegEiz  (RegEip - 1)
 655 #define RegRiz  (RegEiz - 1)
 656 /* FLAT is a fake segment register (Intel mode).  */
 657 #define RegFlat     ((unsigned char) ~0)
 658   signed char dw2_regnum[2];
 659 #define Dw2Inval (-1)
 660 }
 661 reg_entry;
 662
 663 /* Entries in i386_regtab.  */
 664 #define REGNAM_AL 1
 665 #define REGNAM_AX 25
 666 #define REGNAM_EAX 41
 667
 668 extern const reg_entry i386_regtab[];
 669 extern const unsigned int i386_regtab_size;
 670
 671 typedef struct
 672 {
 673   char *seg_name;
 674   unsigned int seg_prefix;
 675 }
 676 seg_entry;
 677
 678 extern const seg_entry cs;
 679 extern const seg_entry ds;
 680 extern const seg_entry ss;
 681 extern const seg_entry es;
 682 extern const seg_entry fs;
 683 extern const seg_entry gs;