1 /* Declarations for Intel 80386 opcode table
3 Free Software Foundation, Inc.
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
22 #include "opcode/i386.h"
31 /* Position of cpu flags bitfiled. */
33 /* i186 or better required */
35 /* i286 or better required */
36 #define Cpu286 (Cpu186 + 1)
37 /* i386 or better required */
38 #define Cpu386 (Cpu286 + 1)
39 /* i486 or better required */
40 #define Cpu486 (Cpu386 + 1)
41 /* i585 or better required */
42 #define Cpu586 (Cpu486 + 1)
43 /* i686 or better required */
44 #define Cpu686 (Cpu586 + 1)
45 /* Pentium4 or better required */
46 #define CpuP4 (Cpu686 + 1)
47 /* AMD K6 or better required*/
48 #define CpuK6 (CpuP4 + 1)
49 /* AMD K8 or better required */
50 #define CpuK8 (CpuK6 + 1)
51 /* MMX support required */
52 #define CpuMMX (CpuK8 + 1)
53 /* SSE support required */
54 #define CpuSSE (CpuMMX + 1)
55 /* SSE2 support required */
56 #define CpuSSE2 (CpuSSE + 1)
57 /* 3dnow! support required */
58 #define Cpu3dnow (CpuSSE2 + 1)
59 /* 3dnow! Extensions support required */
60 #define Cpu3dnowA (Cpu3dnow + 1)
61 /* SSE3 support required */
62 #define CpuSSE3 (Cpu3dnowA + 1)
63 /* VIA PadLock required */
64 #define CpuPadLock (CpuSSE3 + 1)
65 /* AMD Secure Virtual Machine Ext-s required */
66 #define CpuSVME (CpuPadLock + 1)
67 /* VMX Instructions required */
68 #define CpuVMX (CpuSVME + 1)
69 /* SMX Instructions required */
70 #define CpuSMX (CpuVMX + 1)
71 /* SSSE3 support required */
72 #define CpuSSSE3 (CpuSMX + 1)
73 /* SSE4a support required */
74 #define CpuSSE4a (CpuSSSE3 + 1)
75 /* ABM New Instructions required */
76 #define CpuABM (CpuSSE4a + 1)
77 /* SSE4.1 support required */
78 #define CpuSSE4_1 (CpuABM + 1)
79 /* SSE4.2 support required */
80 #define CpuSSE4_2 (CpuSSE4_1 + 1)
81 /* SSE5 support required */
82 #define CpuSSE5 (CpuSSE4_2 + 1)
83 /* AVX support required */
84 #define CpuAVX (CpuSSE5 + 1)
85 /* Xsave/xrstor New Instuctions support required */
86 #define CpuXsave (CpuAVX + 1)
87 /* AES support required */
88 #define CpuAES (CpuXsave + 1)
89 /* PCLMUL support required */
90 #define CpuPCLMUL (CpuAES + 1)
91 /* FMA support required */
92 #define CpuFMA (CpuPCLMUL + 1)
93 /* MOVBE Instuction support required */
94 #define CpuMovbe (CpuFMA + 1)
95 /* EPT Instructions required */
96 #define CpuEPT (CpuMovbe + 1)
97 /* 64bit support available, used by -march= in assembler. */
98 #define CpuLM (CpuEPT + 1)
99 /* 64bit support required */
100 #define Cpu64 (CpuLM + 1)
101 /* Not supported in the 64bit mode */
102 #define CpuNo64 (Cpu64 + 1)
103 /* The last bitfield in i386_cpu_flags. */
104 #define CpuMax CpuNo64
106 #define CpuNumOfUints \
107 (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
108 #define CpuNumOfBits \
109 (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
111 /* If you get a compiler error for zero width of the unused field,
113 #define CpuUnused (CpuMax + 1)
115 /* We can check if an instruction is available with array instead
117 typedef union i386_cpu_flags
121 unsigned int cpui186
:1;
122 unsigned int cpui286
:1;
123 unsigned int cpui386
:1;
124 unsigned int cpui486
:1;
125 unsigned int cpui586
:1;
126 unsigned int cpui686
:1;
127 unsigned int cpup4
:1;
128 unsigned int cpuk6
:1;
129 unsigned int cpuk8
:1;
130 unsigned int cpummx
:1;
131 unsigned int cpusse
:1;
132 unsigned int cpusse2
:1;
133 unsigned int cpua3dnow
:1;
134 unsigned int cpua3dnowa
:1;
135 unsigned int cpusse3
:1;
136 unsigned int cpupadlock
:1;
137 unsigned int cpusvme
:1;
138 unsigned int cpuvmx
:1;
139 unsigned int cpusmx
:1;
140 unsigned int cpussse3
:1;
141 unsigned int cpusse4a
:1;
142 unsigned int cpuabm
:1;
143 unsigned int cpusse4_1
:1;
144 unsigned int cpusse4_2
:1;
145 unsigned int cpusse5
:1;
146 unsigned int cpuavx
:1;
147 unsigned int cpuxsave
:1;
148 unsigned int cpuaes
:1;
149 unsigned int cpupclmul
:1;
150 unsigned int cpufma
:1;
151 unsigned int cpumovbe
:1;
152 unsigned int cpuept
:1;
153 unsigned int cpulm
:1;
154 unsigned int cpu64
:1;
155 unsigned int cpuno64
:1;
157 unsigned int unused
:(CpuNumOfBits
- CpuUnused
);
160 unsigned int array
[CpuNumOfUints
];
163 /* Position of opcode_modifier bits. */
165 /* has direction bit. */
167 /* set if operands can be words or dwords encoded the canonical way */
169 /* Skip the current insn and use the next insn in i386-opc.tbl to swap
170 operand in encoding. */
172 /* insn has a modrm byte. */
173 #define Modrm (S + 1)
174 /* register is in low 3 bits of opcode */
175 #define ShortForm (Modrm + 1)
176 /* special case for jump insns. */
177 #define Jump (ShortForm + 1)
179 #define JumpDword (Jump + 1)
181 #define JumpByte (JumpDword + 1)
182 /* special case for intersegment leaps/calls */
183 #define JumpInterSegment (JumpByte + 1)
184 /* FP insn memory format bit, sized by 0x4 */
185 #define FloatMF (JumpInterSegment + 1)
186 /* src/dest swap for floats. */
187 #define FloatR (FloatMF + 1)
188 /* has float insn direction bit. */
189 #define FloatD (FloatR + 1)
190 /* needs size prefix if in 32-bit mode */
191 #define Size16 (FloatD + 1)
192 /* needs size prefix if in 16-bit mode */
193 #define Size32 (Size16 + 1)
194 /* needs size prefix if in 64-bit mode */
195 #define Size64 (Size32 + 1)
196 /* instruction ignores operand size prefix and in Intel mode ignores
197 mnemonic size suffix check. */
198 #define IgnoreSize (Size64 + 1)
199 /* default insn size depends on mode */
200 #define DefaultSize (IgnoreSize + 1)
201 /* b suffix on instruction illegal */
202 #define No_bSuf (DefaultSize + 1)
203 /* w suffix on instruction illegal */
204 #define No_wSuf (No_bSuf + 1)
205 /* l suffix on instruction illegal */
206 #define No_lSuf (No_wSuf + 1)
207 /* s suffix on instruction illegal */
208 #define No_sSuf (No_lSuf + 1)
209 /* q suffix on instruction illegal */
210 #define No_qSuf (No_sSuf + 1)
211 /* long double suffix on instruction illegal */
212 #define No_ldSuf (No_qSuf + 1)
213 /* instruction needs FWAIT */
214 #define FWait (No_ldSuf + 1)
215 /* quick test for string instructions */
216 #define IsString (FWait + 1)
217 /* fake an extra reg operand for clr, imul and special register
218 processing for some instructions. */
219 #define RegKludge (IsString + 1)
220 /* The first operand must be xmm0 */
221 #define FirstXmm0 (RegKludge + 1)
222 /* An implicit xmm0 as the first operand */
223 #define Implicit1stXmm0 (FirstXmm0 + 1)
224 /* BYTE is OK in Intel syntax. */
225 #define ByteOkIntel (Implicit1stXmm0 + 1)
226 /* Convert to DWORD */
227 #define ToDword (ByteOkIntel + 1)
228 /* Convert to QWORD */
229 #define ToQword (ToDword + 1)
230 /* Address prefix changes operand 0 */
231 #define AddrPrefixOp0 (ToQword + 1)
232 /* opcode is a prefix */
233 #define IsPrefix (AddrPrefixOp0 + 1)
234 /* instruction has extension in 8 bit imm */
235 #define ImmExt (IsPrefix + 1)
236 /* instruction don't need Rex64 prefix. */
237 #define NoRex64 (ImmExt + 1)
238 /* instruction require Rex64 prefix. */
239 #define Rex64 (NoRex64 + 1)
240 /* deprecated fp insn, gets a warning */
241 #define Ugh (Rex64 + 1)
242 #define Drex (Ugh + 1)
243 /* instruction needs DREX with multiple encodings for memory ops */
244 #define Drexv (Drex + 1)
245 /* special DREX for comparisons */
246 #define Drexc (Drexv + 1)
247 /* insn has VEX prefix. */
248 #define Vex (Drexc + 1)
249 /* insn has 256bit VEX prefix. */
250 #define Vex256 (Vex + 1)
251 /* insn has VEX NDS. Register-only source is encoded in Vex
253 #define VexNDS (Vex256 + 1)
254 /* insn has VEX NDD. Register destination is encoded in Vex
256 #define VexNDD (VexNDS + 1)
257 /* insn has VEX W0. */
258 #define VexW0 (VexNDD + 1)
259 /* insn has VEX W1. */
260 #define VexW1 (VexW0 + 1)
261 /* insn has VEX 0x0F opcode prefix. */
262 #define Vex0F (VexW1 + 1)
263 /* insn has VEX 0x0F38 opcode prefix. */
264 #define Vex0F38 (Vex0F + 1)
265 /* insn has VEX 0x0F3A opcode prefix. */
266 #define Vex0F3A (Vex0F38 + 1)
267 /* insn has VEX prefix with 3 soures. */
268 #define Vex3Sources (Vex0F3A + 1)
269 /* instruction has VEX 8 bit imm */
270 #define VexImmExt (Vex3Sources + 1)
271 /* SSE to AVX support required */
272 #define SSE2AVX (VexImmExt + 1)
273 /* No AVX equivalent */
274 #define NoAVX (SSE2AVX + 1)
275 /* Compatible with old (<= 2.8.1) versions of gcc */
276 #define OldGcc (NoAVX + 1)
278 #define ATTMnemonic (OldGcc + 1)
280 #define ATTSyntax (ATTMnemonic + 1)
282 #define IntelSyntax (ATTSyntax + 1)
283 /* The last bitfield in i386_opcode_modifier. */
284 #define Opcode_Modifier_Max IntelSyntax
286 typedef struct i386_opcode_modifier
291 unsigned int modrm
:1;
292 unsigned int shortform
:1;
294 unsigned int jumpdword
:1;
295 unsigned int jumpbyte
:1;
296 unsigned int jumpintersegment
:1;
297 unsigned int floatmf
:1;
298 unsigned int floatr
:1;
299 unsigned int floatd
:1;
300 unsigned int size16
:1;
301 unsigned int size32
:1;
302 unsigned int size64
:1;
303 unsigned int ignoresize
:1;
304 unsigned int defaultsize
:1;
305 unsigned int no_bsuf
:1;
306 unsigned int no_wsuf
:1;
307 unsigned int no_lsuf
:1;
308 unsigned int no_ssuf
:1;
309 unsigned int no_qsuf
:1;
310 unsigned int no_ldsuf
:1;
311 unsigned int fwait
:1;
312 unsigned int isstring
:1;
313 unsigned int regkludge
:1;
314 unsigned int firstxmm0
:1;
315 unsigned int implicit1stxmm0
:1;
316 unsigned int byteokintel
:1;
317 unsigned int todword
:1;
318 unsigned int toqword
:1;
319 unsigned int addrprefixop0
:1;
320 unsigned int isprefix
:1;
321 unsigned int immext
:1;
322 unsigned int norex64
:1;
323 unsigned int rex64
:1;
326 unsigned int drexv
:1;
327 unsigned int drexc
:1;
329 unsigned int vex256
:1;
330 unsigned int vexnds
:1;
331 unsigned int vexndd
:1;
332 unsigned int vexw0
:1;
333 unsigned int vexw1
:1;
334 unsigned int vex0f
:1;
335 unsigned int vex0f38
:1;
336 unsigned int vex0f3a
:1;
337 unsigned int vex3sources
:1;
338 unsigned int veximmext
:1;
339 unsigned int sse2avx
:1;
340 unsigned int noavx
:1;
341 unsigned int oldgcc
:1;
342 unsigned int attmnemonic
:1;
343 unsigned int attsyntax
:1;
344 unsigned int intelsyntax
:1;
345 } i386_opcode_modifier
;
347 /* Position of operand_type bits. */
352 #define Reg16 (Reg8 + 1)
354 #define Reg32 (Reg16 + 1)
356 #define Reg64 (Reg32 + 1)
357 /* Floating pointer stack register */
358 #define FloatReg (Reg64 + 1)
360 #define RegMMX (FloatReg + 1)
362 #define RegXMM (RegMMX + 1)
364 #define RegYMM (RegXMM + 1)
365 /* Control register */
366 #define Control (RegYMM + 1)
368 #define Debug (Control + 1)
370 #define Test (Debug + 1)
371 /* 2 bit segment register */
372 #define SReg2 (Test + 1)
373 /* 3 bit segment register */
374 #define SReg3 (SReg2 + 1)
375 /* 1 bit immediate */
376 #define Imm1 (SReg3 + 1)
377 /* 8 bit immediate */
378 #define Imm8 (Imm1 + 1)
379 /* 8 bit immediate sign extended */
380 #define Imm8S (Imm8 + 1)
381 /* 16 bit immediate */
382 #define Imm16 (Imm8S + 1)
383 /* 32 bit immediate */
384 #define Imm32 (Imm16 + 1)
385 /* 32 bit immediate sign extended */
386 #define Imm32S (Imm32 + 1)
387 /* 64 bit immediate */
388 #define Imm64 (Imm32S + 1)
389 /* 8bit/16bit/32bit displacements are used in different ways,
390 depending on the instruction. For jumps, they specify the
391 size of the PC relative displacement, for instructions with
392 memory operand, they specify the size of the offset relative
393 to the base register, and for instructions with memory offset
394 such as `mov 1234,%al' they specify the size of the offset
395 relative to the segment base. */
396 /* 8 bit displacement */
397 #define Disp8 (Imm64 + 1)
398 /* 16 bit displacement */
399 #define Disp16 (Disp8 + 1)
400 /* 32 bit displacement */
401 #define Disp32 (Disp16 + 1)
402 /* 32 bit signed displacement */
403 #define Disp32S (Disp32 + 1)
404 /* 64 bit displacement */
405 #define Disp64 (Disp32S + 1)
406 /* Accumulator %al/%ax/%eax/%rax */
407 #define Acc (Disp64 + 1)
408 /* Floating pointer top stack register %st(0) */
409 #define FloatAcc (Acc + 1)
410 /* Register which can be used for base or index in memory operand. */
411 #define BaseIndex (FloatAcc + 1)
412 /* Register to hold in/out port addr = dx */
413 #define InOutPortReg (BaseIndex + 1)
414 /* Register to hold shift count = cl */
415 #define ShiftCount (InOutPortReg + 1)
416 /* Absolute address for jump. */
417 #define JumpAbsolute (ShiftCount + 1)
418 /* String insn operand with fixed es segment */
419 #define EsSeg (JumpAbsolute + 1)
420 /* RegMem is for instructions with a modrm byte where the register
421 destination operand should be encoded in the mod and regmem fields.
422 Normally, it will be encoded in the reg field. We add a RegMem
423 flag to the destination register operand to indicate that it should
424 be encoded in the regmem field. */
425 #define RegMem (EsSeg + 1)
427 #define Mem (RegMem + 1)
429 #define Byte (Mem + 1)
430 /* WORD memory. 2 byte */
431 #define Word (Byte + 1)
432 /* DWORD memory. 4 byte */
433 #define Dword (Word + 1)
434 /* FWORD memory. 6 byte */
435 #define Fword (Dword + 1)
436 /* QWORD memory. 8 byte */
437 #define Qword (Fword + 1)
438 /* TBYTE memory. 10 byte */
439 #define Tbyte (Qword + 1)
440 /* XMMWORD memory. */
441 #define Xmmword (Tbyte + 1)
442 /* YMMWORD memory. */
443 #define Ymmword (Xmmword + 1)
444 /* Unspecified memory size. */
445 #define Unspecified (Ymmword + 1)
446 /* Any memory size. */
447 #define Anysize (Unspecified + 1)
449 /* VEX 4 bit immediate */
450 #define Vex_Imm4 (Anysize + 1)
452 /* The last bitfield in i386_operand_type. */
453 #define OTMax Vex_Imm4
455 #define OTNumOfUints \
456 (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
457 #define OTNumOfBits \
458 (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
460 /* If you get a compiler error for zero width of the unused field,
462 #define OTUnused (OTMax + 1)
464 typedef union i386_operand_type
469 unsigned int reg16
:1;
470 unsigned int reg32
:1;
471 unsigned int reg64
:1;
472 unsigned int floatreg
:1;
473 unsigned int regmmx
:1;
474 unsigned int regxmm
:1;
475 unsigned int regymm
:1;
476 unsigned int control
:1;
477 unsigned int debug
:1;
479 unsigned int sreg2
:1;
480 unsigned int sreg3
:1;
483 unsigned int imm8s
:1;
484 unsigned int imm16
:1;
485 unsigned int imm32
:1;
486 unsigned int imm32s
:1;
487 unsigned int imm64
:1;
488 unsigned int disp8
:1;
489 unsigned int disp16
:1;
490 unsigned int disp32
:1;
491 unsigned int disp32s
:1;
492 unsigned int disp64
:1;
494 unsigned int floatacc
:1;
495 unsigned int baseindex
:1;
496 unsigned int inoutportreg
:1;
497 unsigned int shiftcount
:1;
498 unsigned int jumpabsolute
:1;
499 unsigned int esseg
:1;
500 unsigned int regmem
:1;
504 unsigned int dword
:1;
505 unsigned int fword
:1;
506 unsigned int qword
:1;
507 unsigned int tbyte
:1;
508 unsigned int xmmword
:1;
509 unsigned int ymmword
:1;
510 unsigned int unspecified
:1;
511 unsigned int anysize
:1;
512 unsigned int vex_imm4
:1;
514 unsigned int unused
:(OTNumOfBits
- OTUnused
);
517 unsigned int array
[OTNumOfUints
];
520 typedef struct template
522 /* instruction name sans width suffix ("mov" for movl insns) */
525 /* how many operands */
526 unsigned int operands
;
528 /* base_opcode is the fundamental opcode byte without optional
530 unsigned int base_opcode
;
531 #define Opcode_D 0x2 /* Direction bit:
532 set if Reg --> Regmem;
533 unset if Regmem --> Reg. */
534 #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
535 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
537 /* extension_opcode is the 3 bit extension for group <n> insns.
538 This field is also used to store the 8-bit opcode suffix for the
539 AMD 3DNow! instructions.
540 If this template has no extension opcode (the usual case) use None
541 Instructions with Drex use this to specify 2 bits for OC */
542 unsigned int extension_opcode
;
543 #define None 0xffff /* If no extension_opcode is possible. */
546 unsigned char opcode_length
;
548 /* cpu feature flags */
549 i386_cpu_flags cpu_flags
;
551 /* the bits in opcode_modifier are used to generate the final opcode from
552 the base_opcode. These bits also are used to detect alternate forms of
553 the same instruction */
554 i386_opcode_modifier opcode_modifier
;
556 /* operand_types[i] describes the type of operand i. This is made
557 by OR'ing together all of the possible type masks. (e.g.
558 'operand_types[i] = Reg|Imm' specifies that operand i can be
559 either a register or an immediate operand. */
560 i386_operand_type operand_types
[MAX_OPERANDS
];
564 extern const template i386_optab
[];
566 /* these are for register name --> number & type hash lookup */
570 i386_operand_type reg_type
;
571 unsigned char reg_flags
;
572 #define RegRex 0x1 /* Extended register. */
573 #define RegRex64 0x2 /* Extended 8 bit register. */
574 unsigned char reg_num
;
575 #define RegRip ((unsigned char ) ~0)
576 #define RegEip (RegRip - 1)
577 /* EIZ and RIZ are fake index registers. */
578 #define RegEiz (RegEip - 1)
579 #define RegRiz (RegEiz - 1)
580 /* FLAT is a fake segment register (Intel mode). */
581 #define RegFlat ((unsigned char) ~0)
582 signed char dw2_regnum
[2];
583 #define Dw2Inval (-1)
587 /* Entries in i386_regtab. */
590 #define REGNAM_EAX 41
592 extern const reg_entry i386_regtab
[];
593 extern const unsigned int i386_regtab_size
;
598 unsigned int seg_prefix
;
602 extern const seg_entry cs
;
603 extern const seg_entry ds
;
604 extern const seg_entry ss
;
605 extern const seg_entry es
;
606 extern const seg_entry fs
;
607 extern const seg_entry gs
;