opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2018 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #ifdef HAVE_LIMITS_H
  23 #include <limits.h>
  24 #endif
  25
  26 #ifndef CHAR_BIT
  27 #define CHAR_BIT 8
  28 #endif
  29
  30 /* Position of cpu flags bitfiled.  */
  31
  32 enum
  33 {
  34   /* i186 or better required */
  35   Cpu186 = 0,
  36   /* i286 or better required */
  37   Cpu286,
  38   /* i386 or better required */
  39   Cpu386,
  40   /* i486 or better required */
  41   Cpu486,
  42   /* i585 or better required */
  43   Cpu586,
  44   /* i686 or better required */
  45   Cpu686,
  46   /* CLFLUSH Instruction support required */
  47   CpuClflush,
  48   /* NOP Instruction support required */
  49   CpuNop,
  50   /* SYSCALL Instructions support required */
  51   CpuSYSCALL,
  52   /* Floating point support required */
  53   Cpu8087,
  54   /* i287 support required */
  55   Cpu287,
  56   /* i387 support required */
  57   Cpu387,
  58   /* i686 and floating point support required */
  59   Cpu687,
  60   /* SSE3 and floating point support required */
  61   CpuFISTTP,
  62   /* MMX support required */
  63   CpuMMX,
  64   /* SSE support required */
  65   CpuSSE,
  66   /* SSE2 support required */
  67   CpuSSE2,
  68   /* 3dnow! support required */
  69   Cpu3dnow,
  70   /* 3dnow! Extensions support required */
  71   Cpu3dnowA,
  72   /* SSE3 support required */
  73   CpuSSE3,
  74   /* VIA PadLock required */
  75   CpuPadLock,
  76   /* AMD Secure Virtual Machine Ext-s required */
  77   CpuSVME,
  78   /* VMX Instructions required */
  79   CpuVMX,
  80   /* SMX Instructions required */
  81   CpuSMX,
  82   /* SSSE3 support required */
  83   CpuSSSE3,
  84   /* SSE4a support required */
  85   CpuSSE4a,
  86   /* ABM New Instructions required */
  87   CpuABM,
  88   /* SSE4.1 support required */
  89   CpuSSE4_1,
  90   /* SSE4.2 support required */
  91   CpuSSE4_2,
  92   /* AVX support required */
  93   CpuAVX,
  94   /* AVX2 support required */
  95   CpuAVX2,
  96   /* Intel AVX-512 Foundation Instructions support required */
  97   CpuAVX512F,
  98   /* Intel AVX-512 Conflict Detection Instructions support required */
  99   CpuAVX512CD,
 100   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 101      required */
 102   CpuAVX512ER,
 103   /* Intel AVX-512 Prefetch Instructions support required */
 104   CpuAVX512PF,
 105   /* Intel AVX-512 VL Instructions support required.  */
 106   CpuAVX512VL,
 107   /* Intel AVX-512 DQ Instructions support required.  */
 108   CpuAVX512DQ,
 109   /* Intel AVX-512 BW Instructions support required.  */
 110   CpuAVX512BW,
 111   /* Intel L1OM support required */
 112   CpuL1OM,
 113   /* Intel K1OM support required */
 114   CpuK1OM,
 115   /* Intel IAMCU support required */
 116   CpuIAMCU,
 117   /* Xsave/xrstor New Instructions support required */
 118   CpuXsave,
 119   /* Xsaveopt New Instructions support required */
 120   CpuXsaveopt,
 121   /* AES support required */
 122   CpuAES,
 123   /* PCLMUL support required */
 124   CpuPCLMUL,
 125   /* FMA support required */
 126   CpuFMA,
 127   /* FMA4 support required */
 128   CpuFMA4,
 129   /* XOP support required */
 130   CpuXOP,
 131   /* LWP support required */
 132   CpuLWP,
 133   /* BMI support required */
 134   CpuBMI,
 135   /* TBM support required */
 136   CpuTBM,
 137   /* MOVBE Instruction support required */
 138   CpuMovbe,
 139   /* CMPXCHG16B instruction support required.  */
 140   CpuCX16,
 141   /* EPT Instructions required */
 142   CpuEPT,
 143   /* RDTSCP Instruction support required */
 144   CpuRdtscp,
 145   /* FSGSBASE Instructions required */
 146   CpuFSGSBase,
 147   /* RDRND Instructions required */
 148   CpuRdRnd,
 149   /* F16C Instructions required */
 150   CpuF16C,
 151   /* Intel BMI2 support required */
 152   CpuBMI2,
 153   /* LZCNT support required */
 154   CpuLZCNT,
 155   /* HLE support required */
 156   CpuHLE,
 157   /* RTM support required */
 158   CpuRTM,
 159   /* INVPCID Instructions required */
 160   CpuINVPCID,
 161   /* VMFUNC Instruction required */
 162   CpuVMFUNC,
 163   /* Intel MPX Instructions required  */
 164   CpuMPX,
 165   /* 64bit support available, used by -march= in assembler.  */
 166   CpuLM,
 167   /* RDRSEED instruction required.  */
 168   CpuRDSEED,
 169   /* Multi-presisionn add-carry instructions are required.  */
 170   CpuADX,
 171   /* Supports prefetchw and prefetch instructions.  */
 172   CpuPRFCHW,
 173   /* SMAP instructions required.  */
 174   CpuSMAP,
 175   /* SHA instructions required.  */
 176   CpuSHA,
 177   /* VREX support required  */
 178   CpuVREX,
 179   /* CLFLUSHOPT instruction required */
 180   CpuClflushOpt,
 181   /* XSAVES/XRSTORS instruction required */
 182   CpuXSAVES,
 183   /* XSAVEC instruction required */
 184   CpuXSAVEC,
 185   /* PREFETCHWT1 instruction required */
 186   CpuPREFETCHWT1,
 187   /* SE1 instruction required */
 188   CpuSE1,
 189   /* CLWB instruction required */
 190   CpuCLWB,
 191   /* Intel AVX-512 IFMA Instructions support required.  */
 192   CpuAVX512IFMA,
 193   /* Intel AVX-512 VBMI Instructions support required.  */
 194   CpuAVX512VBMI,
 195   /* Intel AVX-512 4FMAPS Instructions support required.  */
 196   CpuAVX512_4FMAPS,
 197   /* Intel AVX-512 4VNNIW Instructions support required.  */
 198   CpuAVX512_4VNNIW,
 199   /* Intel AVX-512 VPOPCNTDQ Instructions support required.  */
 200   CpuAVX512_VPOPCNTDQ,
 201   /* Intel AVX-512 VBMI2 Instructions support required.  */
 202   CpuAVX512_VBMI2,
 203   /* Intel AVX-512 VNNI Instructions support required.  */
 204   CpuAVX512_VNNI,
 205   /* Intel AVX-512 BITALG Instructions support required.  */
 206   CpuAVX512_BITALG,
 207   /* mwaitx instruction required */
 208   CpuMWAITX,
 209   /* Clzero instruction required */
 210   CpuCLZERO,
 211   /* OSPKE instruction required */
 212   CpuOSPKE,
 213   /* RDPID instruction required */
 214   CpuRDPID,
 215   /* PTWRITE instruction required */
 216   CpuPTWRITE,
 217   /* CET instructions support required */
 218   CpuIBT,
 219   CpuSHSTK,
 220   /* GFNI instructions required */
 221   CpuGFNI,
 222   /* VAES instructions required */
 223   CpuVAES,
 224   /* VPCLMULQDQ instructions required */
 225   CpuVPCLMULQDQ,
 226   /* WBNOINVD instructions required */
 227   CpuWBNOINVD,
 228   /* PCONFIG instructions required */
 229   CpuPCONFIG,
 230   /* WAITPKG instructions required */
 231   CpuWAITPKG,
 232   /* CLDEMOTE instruction required */
 233   CpuCLDEMOTE,
 234   /* MOVDIRI instruction support required */
 235   CpuMOVDIRI,
 236   /* MOVDIRR64B instruction required */
 237   CpuMOVDIR64B,
 238   /* 64bit support required  */
 239   Cpu64,
 240   /* Not supported in the 64bit mode  */
 241   CpuNo64,
 242   /* The last bitfield in i386_cpu_flags.  */
 243   CpuMax = CpuNo64
 244 };
 245
 246 #define CpuNumOfUints \
 247   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 248 #define CpuNumOfBits \
 249   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 250
 251 /* If you get a compiler error for zero width of the unused field,
 252    comment it out.  */
 253 #define CpuUnused       (CpuMax + 1)
 254
 255 /* We can check if an instruction is available with array instead
 256    of bitfield. */
 257 typedef union i386_cpu_flags
 258 {
 259   struct
 260     {
 261       unsigned int cpui186:1;
 262       unsigned int cpui286:1;
 263       unsigned int cpui386:1;
 264       unsigned int cpui486:1;
 265       unsigned int cpui586:1;
 266       unsigned int cpui686:1;
 267       unsigned int cpuclflush:1;
 268       unsigned int cpunop:1;
 269       unsigned int cpusyscall:1;
 270       unsigned int cpu8087:1;
 271       unsigned int cpu287:1;
 272       unsigned int cpu387:1;
 273       unsigned int cpu687:1;
 274       unsigned int cpufisttp:1;
 275       unsigned int cpummx:1;
 276       unsigned int cpusse:1;
 277       unsigned int cpusse2:1;
 278       unsigned int cpua3dnow:1;
 279       unsigned int cpua3dnowa:1;
 280       unsigned int cpusse3:1;
 281       unsigned int cpupadlock:1;
 282       unsigned int cpusvme:1;
 283       unsigned int cpuvmx:1;
 284       unsigned int cpusmx:1;
 285       unsigned int cpussse3:1;
 286       unsigned int cpusse4a:1;
 287       unsigned int cpuabm:1;
 288       unsigned int cpusse4_1:1;
 289       unsigned int cpusse4_2:1;
 290       unsigned int cpuavx:1;
 291       unsigned int cpuavx2:1;
 292       unsigned int cpuavx512f:1;
 293       unsigned int cpuavx512cd:1;
 294       unsigned int cpuavx512er:1;
 295       unsigned int cpuavx512pf:1;
 296       unsigned int cpuavx512vl:1;
 297       unsigned int cpuavx512dq:1;
 298       unsigned int cpuavx512bw:1;
 299       unsigned int cpul1om:1;
 300       unsigned int cpuk1om:1;
 301       unsigned int cpuiamcu:1;
 302       unsigned int cpuxsave:1;
 303       unsigned int cpuxsaveopt:1;
 304       unsigned int cpuaes:1;
 305       unsigned int cpupclmul:1;
 306       unsigned int cpufma:1;
 307       unsigned int cpufma4:1;
 308       unsigned int cpuxop:1;
 309       unsigned int cpulwp:1;
 310       unsigned int cpubmi:1;
 311       unsigned int cputbm:1;
 312       unsigned int cpumovbe:1;
 313       unsigned int cpucx16:1;
 314       unsigned int cpuept:1;
 315       unsigned int cpurdtscp:1;
 316       unsigned int cpufsgsbase:1;
 317       unsigned int cpurdrnd:1;
 318       unsigned int cpuf16c:1;
 319       unsigned int cpubmi2:1;
 320       unsigned int cpulzcnt:1;
 321       unsigned int cpuhle:1;
 322       unsigned int cpurtm:1;
 323       unsigned int cpuinvpcid:1;
 324       unsigned int cpuvmfunc:1;
 325       unsigned int cpumpx:1;
 326       unsigned int cpulm:1;
 327       unsigned int cpurdseed:1;
 328       unsigned int cpuadx:1;
 329       unsigned int cpuprfchw:1;
 330       unsigned int cpusmap:1;
 331       unsigned int cpusha:1;
 332       unsigned int cpuvrex:1;
 333       unsigned int cpuclflushopt:1;
 334       unsigned int cpuxsaves:1;
 335       unsigned int cpuxsavec:1;
 336       unsigned int cpuprefetchwt1:1;
 337       unsigned int cpuse1:1;
 338       unsigned int cpuclwb:1;
 339       unsigned int cpuavx512ifma:1;
 340       unsigned int cpuavx512vbmi:1;
 341       unsigned int cpuavx512_4fmaps:1;
 342       unsigned int cpuavx512_4vnniw:1;
 343       unsigned int cpuavx512_vpopcntdq:1;
 344       unsigned int cpuavx512_vbmi2:1;
 345       unsigned int cpuavx512_vnni:1;
 346       unsigned int cpuavx512_bitalg:1;
 347       unsigned int cpumwaitx:1;
 348       unsigned int cpuclzero:1;
 349       unsigned int cpuospke:1;
 350       unsigned int cpurdpid:1;
 351       unsigned int cpuptwrite:1;
 352       unsigned int cpuibt:1;
 353       unsigned int cpushstk:1;
 354       unsigned int cpugfni:1;
 355       unsigned int cpuvaes:1;
 356       unsigned int cpuvpclmulqdq:1;
 357       unsigned int cpuwbnoinvd:1;
 358       unsigned int cpupconfig:1;
 359       unsigned int cpuwaitpkg:1;
 360       unsigned int cpucldemote:1;
 361       unsigned int cpumovdiri:1;
 362       unsigned int cpumovdir64b:1;
 363       unsigned int cpu64:1;
 364       unsigned int cpuno64:1;
 365 #ifdef CpuUnused
 366       unsigned int unused:(CpuNumOfBits - CpuUnused);
 367 #endif
 368     } bitfield;
 369   unsigned int array[CpuNumOfUints];
 370 } i386_cpu_flags;
 371
 372 /* Position of opcode_modifier bits.  */
 373
 374 enum
 375 {
 376   /* has direction bit. */
 377   D = 0,
 378   /* set if operands can be words or dwords encoded the canonical way */
 379   W,
 380   /* load form instruction. Must be placed before store form.  */
 381   Load,
 382   /* insn has a modrm byte. */
 383   Modrm,
 384   /* register is in low 3 bits of opcode */
 385   ShortForm,
 386   /* special case for jump insns.  */
 387   Jump,
 388   /* call and jump */
 389   JumpDword,
 390   /* loop and jecxz */
 391   JumpByte,
 392   /* special case for intersegment leaps/calls */
 393   JumpInterSegment,
 394   /* FP insn memory format bit, sized by 0x4 */
 395   FloatMF,
 396   /* src/dest swap for floats. */
 397   FloatR,
 398   /* needs size prefix if in 32-bit mode */
 399   Size16,
 400   /* needs size prefix if in 16-bit mode */
 401   Size32,
 402   /* needs size prefix if in 64-bit mode */
 403   Size64,
 404   /* check register size.  */
 405   CheckRegSize,
 406   /* instruction ignores operand size prefix and in Intel mode ignores
 407      mnemonic size suffix check.  */
 408   IgnoreSize,
 409   /* default insn size depends on mode */
 410   DefaultSize,
 411   /* b suffix on instruction illegal */
 412   No_bSuf,
 413   /* w suffix on instruction illegal */
 414   No_wSuf,
 415   /* l suffix on instruction illegal */
 416   No_lSuf,
 417   /* s suffix on instruction illegal */
 418   No_sSuf,
 419   /* q suffix on instruction illegal */
 420   No_qSuf,
 421   /* long double suffix on instruction illegal */
 422   No_ldSuf,
 423   /* instruction needs FWAIT */
 424   FWait,
 425   /* quick test for string instructions */
 426   IsString,
 427   /* quick test if branch instruction is MPX supported */
 428   BNDPrefixOk,
 429   /* quick test if NOTRACK prefix is supported */
 430   NoTrackPrefixOk,
 431   /* quick test for lockable instructions */
 432   IsLockable,
 433   /* fake an extra reg operand for clr, imul and special register
 434      processing for some instructions.  */
 435   RegKludge,
 436   /* An implicit xmm0 as the first operand */
 437   Implicit1stXmm0,
 438   /* The HLE prefix is OK:
 439      1. With a LOCK prefix.
 440      2. With or without a LOCK prefix.
 441      3. With a RELEASE (0xf3) prefix.
 442    */
 443 #define HLEPrefixNone           0
 444 #define HLEPrefixLock           1
 445 #define HLEPrefixAny            2
 446 #define HLEPrefixRelease        3
 447   HLEPrefixOk,
 448   /* An instruction on which a "rep" prefix is acceptable.  */
 449   RepPrefixOk,
 450   /* Convert to DWORD */
 451   ToDword,
 452   /* Convert to QWORD */
 453   ToQword,
 454   /* Address prefix changes register operand */
 455   AddrPrefixOpReg,
 456   /* opcode is a prefix */
 457   IsPrefix,
 458   /* instruction has extension in 8 bit imm */
 459   ImmExt,
 460   /* instruction don't need Rex64 prefix.  */
 461   NoRex64,
 462   /* instruction require Rex64 prefix.  */
 463   Rex64,
 464   /* deprecated fp insn, gets a warning */
 465   Ugh,
 466   /* insn has VEX prefix:
 467         1: 128bit VEX prefix (or operand dependent).
 468         2: 256bit VEX prefix.
 469         3: Scalar VEX prefix.
 470    */
 471 #define VEX128          1
 472 #define VEX256          2
 473 #define VEXScalar       3
 474   Vex,
 475   /* How to encode VEX.vvvv:
 476      0: VEX.vvvv must be 1111b.
 477      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 478         the content of source registers will be preserved.
 479         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 480         where the content of first source register will be overwritten
 481         by the result.
 482         VEX.NDD2.  The second destination register operand is encoded in
 483         VEX.vvvv for instructions with 2 destination register operands.
 484         For assembler, there are no difference between VEX.NDS, VEX.DDS
 485         and VEX.NDD2.
 486      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 487      instructions with 1 destination register operand.
 488      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 489         of the operands can access a memory location.
 490    */
 491 #define VEXXDS  1
 492 #define VEXNDD  2
 493 #define VEXLWP  3
 494   VexVVVV,
 495   /* How the VEX.W bit is used:
 496      0: Set by the REX.W bit.
 497      1: VEX.W0.  Should always be 0.
 498      2: VEX.W1.  Should always be 1.
 499    */
 500 #define VEXW0   1
 501 #define VEXW1   2
 502   VexW,
 503   /* VEX opcode prefix:
 504      0: VEX 0x0F opcode prefix.
 505      1: VEX 0x0F38 opcode prefix.
 506      2: VEX 0x0F3A opcode prefix
 507      3: XOP 0x08 opcode prefix.
 508      4: XOP 0x09 opcode prefix
 509      5: XOP 0x0A opcode prefix.
 510    */
 511 #define VEX0F           0
 512 #define VEX0F38         1
 513 #define VEX0F3A         2
 514 #define XOP08           3
 515 #define XOP09           4
 516 #define XOP0A           5
 517   VexOpcode,
 518   /* number of VEX source operands:
 519      0: <= 2 source operands.
 520      1: 2 XOP source operands.
 521      2: 3 source operands.
 522    */
 523 #define XOP2SOURCES     1
 524 #define VEX3SOURCES     2
 525   VexSources,
 526   /* Instruction with vector SIB byte:
 527         1: 128bit vector register.
 528         2: 256bit vector register.
 529         3: 512bit vector register.
 530    */
 531 #define VecSIB128       1
 532 #define VecSIB256       2
 533 #define VecSIB512       3
 534   VecSIB,
 535   /* SSE to AVX support required */
 536   SSE2AVX,
 537   /* No AVX equivalent */
 538   NoAVX,
 539
 540   /* insn has EVEX prefix:
 541         1: 512bit EVEX prefix.
 542         2: 128bit EVEX prefix.
 543         3: 256bit EVEX prefix.
 544         4: Length-ignored (LIG) EVEX prefix.
 545         5: Length determined from actual operands.
 546    */
 547 #define EVEX512                1
 548 #define EVEX128                2
 549 #define EVEX256                3
 550 #define EVEXLIG                4
 551 #define EVEXDYN                5
 552   EVex,
 553
 554   /* AVX512 masking support:
 555         1: Zeroing-masking.
 556         2: Merging-masking.
 557         3: Both zeroing and merging masking.
 558    */
 559 #define ZEROING_MASKING 1
 560 #define MERGING_MASKING 2
 561 #define BOTH_MASKING    3
 562   Masking,
 563
 564   Broadcast,
 565
 566   /* Static rounding control is supported.  */
 567   StaticRounding,
 568
 569   /* Supress All Exceptions is supported.  */
 570   SAE,
 571
 572   /* Copressed Disp8*N attribute.  */
 573   Disp8MemShift,
 574
 575   /* Default mask isn't allowed.  */
 576   NoDefMask,
 577
 578   /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
 579      It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
 580    */
 581   ImplicitQuadGroup,
 582
 583   /* Support encoding optimization.  */
 584   Optimize,
 585
 586   /* AT&T mnemonic.  */
 587   ATTMnemonic,
 588   /* AT&T syntax.  */
 589   ATTSyntax,
 590   /* Intel syntax.  */
 591   IntelSyntax,
 592   /* AMD64.  */
 593   AMD64,
 594   /* Intel64.  */
 595   Intel64,
 596   /* The last bitfield in i386_opcode_modifier.  */
 597   Opcode_Modifier_Max
 598 };
 599
 600 typedef struct i386_opcode_modifier
 601 {
 602   unsigned int d:1;
 603   unsigned int w:1;
 604   unsigned int load:1;
 605   unsigned int modrm:1;
 606   unsigned int shortform:1;
 607   unsigned int jump:1;
 608   unsigned int jumpdword:1;
 609   unsigned int jumpbyte:1;
 610   unsigned int jumpintersegment:1;
 611   unsigned int floatmf:1;
 612   unsigned int floatr:1;
 613   unsigned int size16:1;
 614   unsigned int size32:1;
 615   unsigned int size64:1;
 616   unsigned int checkregsize:1;
 617   unsigned int ignoresize:1;
 618   unsigned int defaultsize:1;
 619   unsigned int no_bsuf:1;
 620   unsigned int no_wsuf:1;
 621   unsigned int no_lsuf:1;
 622   unsigned int no_ssuf:1;
 623   unsigned int no_qsuf:1;
 624   unsigned int no_ldsuf:1;
 625   unsigned int fwait:1;
 626   unsigned int isstring:1;
 627   unsigned int bndprefixok:1;
 628   unsigned int notrackprefixok:1;
 629   unsigned int islockable:1;
 630   unsigned int regkludge:1;
 631   unsigned int implicit1stxmm0:1;
 632   unsigned int hleprefixok:2;
 633   unsigned int repprefixok:1;
 634   unsigned int todword:1;
 635   unsigned int toqword:1;
 636   unsigned int addrprefixopreg:1;
 637   unsigned int isprefix:1;
 638   unsigned int immext:1;
 639   unsigned int norex64:1;
 640   unsigned int rex64:1;
 641   unsigned int ugh:1;
 642   unsigned int vex:2;
 643   unsigned int vexvvvv:2;
 644   unsigned int vexw:2;
 645   unsigned int vexopcode:3;
 646   unsigned int vexsources:2;
 647   unsigned int vecsib:2;
 648   unsigned int sse2avx:1;
 649   unsigned int noavx:1;
 650   unsigned int evex:3;
 651   unsigned int masking:2;
 652   unsigned int broadcast:1;
 653   unsigned int staticrounding:1;
 654   unsigned int sae:1;
 655   unsigned int disp8memshift:3;
 656   unsigned int nodefmask:1;
 657   unsigned int implicitquadgroup:1;
 658   unsigned int optimize:1;
 659   unsigned int attmnemonic:1;
 660   unsigned int attsyntax:1;
 661   unsigned int intelsyntax:1;
 662   unsigned int amd64:1;
 663   unsigned int intel64:1;
 664 } i386_opcode_modifier;
 665
 666 /* Position of operand_type bits.  */
 667
 668 enum
 669 {
 670   /* Register (qualified by Byte, Word, etc) */
 671   Reg = 0,
 672   /* MMX register */
 673   RegMMX,
 674   /* Vector registers */
 675   RegSIMD,
 676   /* Vector Mask registers */
 677   RegMask,
 678   /* Control register */
 679   Control,
 680   /* Debug register */
 681   Debug,
 682   /* Test register */
 683   Test,
 684   /* 2 bit segment register */
 685   SReg2,
 686   /* 3 bit segment register */
 687   SReg3,
 688   /* 1 bit immediate */
 689   Imm1,
 690   /* 8 bit immediate */
 691   Imm8,
 692   /* 8 bit immediate sign extended */
 693   Imm8S,
 694   /* 16 bit immediate */
 695   Imm16,
 696   /* 32 bit immediate */
 697   Imm32,
 698   /* 32 bit immediate sign extended */
 699   Imm32S,
 700   /* 64 bit immediate */
 701   Imm64,
 702   /* 8bit/16bit/32bit displacements are used in different ways,
 703      depending on the instruction.  For jumps, they specify the
 704      size of the PC relative displacement, for instructions with
 705      memory operand, they specify the size of the offset relative
 706      to the base register, and for instructions with memory offset
 707      such as `mov 1234,%al' they specify the size of the offset
 708      relative to the segment base.  */
 709   /* 8 bit displacement */
 710   Disp8,
 711   /* 16 bit displacement */
 712   Disp16,
 713   /* 32 bit displacement */
 714   Disp32,
 715   /* 32 bit signed displacement */
 716   Disp32S,
 717   /* 64 bit displacement */
 718   Disp64,
 719   /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
 720   Acc,
 721   /* Register which can be used for base or index in memory operand.  */
 722   BaseIndex,
 723   /* Register to hold in/out port addr = dx */
 724   InOutPortReg,
 725   /* Register to hold shift count = cl */
 726   ShiftCount,
 727   /* Absolute address for jump.  */
 728   JumpAbsolute,
 729   /* String insn operand with fixed es segment */
 730   EsSeg,
 731   /* RegMem is for instructions with a modrm byte where the register
 732      destination operand should be encoded in the mod and regmem fields.
 733      Normally, it will be encoded in the reg field. We add a RegMem
 734      flag to the destination register operand to indicate that it should
 735      be encoded in the regmem field.  */
 736   RegMem,
 737   /* Memory.  */
 738   Mem,
 739   /* BYTE memory. */
 740   Byte,
 741   /* WORD memory. 2 byte */
 742   Word,
 743   /* DWORD memory. 4 byte */
 744   Dword,
 745   /* FWORD memory. 6 byte */
 746   Fword,
 747   /* QWORD memory. 8 byte */
 748   Qword,
 749   /* TBYTE memory. 10 byte */
 750   Tbyte,
 751   /* XMMWORD memory. */
 752   Xmmword,
 753   /* YMMWORD memory. */
 754   Ymmword,
 755   /* ZMMWORD memory.  */
 756   Zmmword,
 757   /* Unspecified memory size.  */
 758   Unspecified,
 759   /* Any memory size.  */
 760   Anysize,
 761
 762   /* Vector 4 bit immediate.  */
 763   Vec_Imm4,
 764
 765   /* Bound register.  */
 766   RegBND,
 767
 768   /* The last bitfield in i386_operand_type.  */
 769   OTMax
 770 };
 771
 772 #define OTNumOfUints \
 773   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 774 #define OTNumOfBits \
 775   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 776
 777 /* If you get a compiler error for zero width of the unused field,
 778    comment it out.  */
 779 #define OTUnused                (OTMax + 1)
 780
 781 typedef union i386_operand_type
 782 {
 783   struct
 784     {
 785       unsigned int reg:1;
 786       unsigned int regmmx:1;
 787       unsigned int regsimd:1;
 788       unsigned int regmask:1;
 789       unsigned int control:1;
 790       unsigned int debug:1;
 791       unsigned int test:1;
 792       unsigned int sreg2:1;
 793       unsigned int sreg3:1;
 794       unsigned int imm1:1;
 795       unsigned int imm8:1;
 796       unsigned int imm8s:1;
 797       unsigned int imm16:1;
 798       unsigned int imm32:1;
 799       unsigned int imm32s:1;
 800       unsigned int imm64:1;
 801       unsigned int disp8:1;
 802       unsigned int disp16:1;
 803       unsigned int disp32:1;
 804       unsigned int disp32s:1;
 805       unsigned int disp64:1;
 806       unsigned int acc:1;
 807       unsigned int baseindex:1;
 808       unsigned int inoutportreg:1;
 809       unsigned int shiftcount:1;
 810       unsigned int jumpabsolute:1;
 811       unsigned int esseg:1;
 812       unsigned int regmem:1;
 813       unsigned int mem:1;
 814       unsigned int byte:1;
 815       unsigned int word:1;
 816       unsigned int dword:1;
 817       unsigned int fword:1;
 818       unsigned int qword:1;
 819       unsigned int tbyte:1;
 820       unsigned int xmmword:1;
 821       unsigned int ymmword:1;
 822       unsigned int zmmword:1;
 823       unsigned int unspecified:1;
 824       unsigned int anysize:1;
 825       unsigned int vec_imm4:1;
 826       unsigned int regbnd:1;
 827 #ifdef OTUnused
 828       unsigned int unused:(OTNumOfBits - OTUnused);
 829 #endif
 830     } bitfield;
 831   unsigned int array[OTNumOfUints];
 832 } i386_operand_type;
 833
 834 typedef struct insn_template
 835 {
 836   /* instruction name sans width suffix ("mov" for movl insns) */
 837   char *name;
 838
 839   /* how many operands */
 840   unsigned int operands;
 841
 842   /* base_opcode is the fundamental opcode byte without optional
 843      prefix(es).  */
 844   unsigned int base_opcode;
 845 #define Opcode_D        0x2 /* Direction bit:
 846                                set if Reg --> Regmem;
 847                                unset if Regmem --> Reg. */
 848 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 849 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 850
 851   /* extension_opcode is the 3 bit extension for group <n> insns.
 852      This field is also used to store the 8-bit opcode suffix for the
 853      AMD 3DNow! instructions.
 854      If this template has no extension opcode (the usual case) use None
 855      Instructions */
 856   unsigned int extension_opcode;
 857 #define None 0xffff             /* If no extension_opcode is possible.  */
 858
 859   /* Opcode length.  */
 860   unsigned char opcode_length;
 861
 862   /* cpu feature flags */
 863   i386_cpu_flags cpu_flags;
 864
 865   /* the bits in opcode_modifier are used to generate the final opcode from
 866      the base_opcode.  These bits also are used to detect alternate forms of
 867      the same instruction */
 868   i386_opcode_modifier opcode_modifier;
 869
 870   /* operand_types[i] describes the type of operand i.  This is made
 871      by OR'ing together all of the possible type masks.  (e.g.
 872      'operand_types[i] = Reg|Imm' specifies that operand i can be
 873      either a register or an immediate operand.  */
 874   i386_operand_type operand_types[MAX_OPERANDS];
 875 }
 876 insn_template;
 877
 878 extern const insn_template i386_optab[];
 879
 880 /* these are for register name --> number & type hash lookup */
 881 typedef struct
 882 {
 883   char *reg_name;
 884   i386_operand_type reg_type;
 885   unsigned char reg_flags;
 886 #define RegRex      0x1  /* Extended register.  */
 887 #define RegRex64    0x2  /* Extended 8 bit register.  */
 888 #define RegVRex     0x4  /* Extended vector register.  */
 889   unsigned char reg_num;
 890 #define RegRip  ((unsigned char ) ~0)
 891 #define RegEip  (RegRip - 1)
 892 /* EIZ and RIZ are fake index registers.  */
 893 #define RegEiz  (RegEip - 1)
 894 #define RegRiz  (RegEiz - 1)
 895 /* FLAT is a fake segment register (Intel mode).  */
 896 #define RegFlat     ((unsigned char) ~0)
 897   signed char dw2_regnum[2];
 898 #define Dw2Inval (-1)
 899 }
 900 reg_entry;
 901
 902 /* Entries in i386_regtab.  */
 903 #define REGNAM_AL 1
 904 #define REGNAM_AX 25
 905 #define REGNAM_EAX 41
 906
 907 extern const reg_entry i386_regtab[];
 908 extern const unsigned int i386_regtab_size;
 909
 910 typedef struct
 911 {
 912   char *seg_name;
 913   unsigned int seg_prefix;
 914 }
 915 seg_entry;
 916
 917 extern const seg_entry cs;
 918 extern const seg_entry ds;
 919 extern const seg_entry ss;
 920 extern const seg_entry es;
 921 extern const seg_entry fs;
 922 extern const seg_entry gs;