1 /* Declarations for Intel 80386 opcode table
2 Copyright 2007, 2008, 2009, 2010
3 Free Software Foundation, Inc.
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
22 #include "opcode/i386.h"
31 /* Position of cpu flags bitfiled. */
35 /* i186 or better required */
37 /* i286 or better required */
39 /* i386 or better required */
41 /* i486 or better required */
43 /* i585 or better required */
45 /* i686 or better required */
47 /* CLFLUSH Instruction support required */
49 /* NOP Instruction support required */
51 /* SYSCALL Instructions support required */
53 /* Floating point support required */
55 /* i287 support required */
57 /* i387 support required */
59 /* i686 and floating point support required */
61 /* SSE3 and floating point support required */
63 /* MMX support required */
65 /* SSE support required */
67 /* SSE2 support required */
69 /* 3dnow! support required */
71 /* 3dnow! Extensions support required */
73 /* SSE3 support required */
75 /* VIA PadLock required */
77 /* AMD Secure Virtual Machine Ext-s required */
79 /* VMX Instructions required */
81 /* SMX Instructions required */
83 /* SSSE3 support required */
85 /* SSE4a support required */
87 /* ABM New Instructions required */
89 /* SSE4.1 support required */
91 /* SSE4.2 support required */
93 /* AVX support required */
95 /* AVX2 support required */
97 /* Intel L1OM support required */
99 /* Intel K1OM support required */
101 /* Xsave/xrstor New Instructions support required */
103 /* Xsaveopt New Instructions support required */
105 /* AES support required */
107 /* PCLMUL support required */
109 /* FMA support required */
111 /* FMA4 support required */
113 /* XOP support required */
115 /* LWP support required */
117 /* BMI support required */
119 /* TBM support required */
121 /* MOVBE Instruction support required */
123 /* EPT Instructions required */
125 /* RDTSCP Instruction support required */
127 /* FSGSBASE Instructions required */
129 /* RDRND Instructions required */
131 /* F16C Instructions required */
133 /* Intel BMI2 support required */
135 /* LZCNT support required */
137 /* INVPCID Instructions required */
139 /* VMFUNC Instruction required */
141 /* 64bit support available, used by -march= in assembler. */
143 /* 64bit support required */
145 /* Not supported in the 64bit mode */
147 /* The last bitfield in i386_cpu_flags. */
151 #define CpuNumOfUints \
152 (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
153 #define CpuNumOfBits \
154 (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
156 /* If you get a compiler error for zero width of the unused field,
158 #define CpuUnused (CpuMax + 1)
160 /* We can check if an instruction is available with array instead
162 typedef union i386_cpu_flags
166 unsigned int cpui186
:1;
167 unsigned int cpui286
:1;
168 unsigned int cpui386
:1;
169 unsigned int cpui486
:1;
170 unsigned int cpui586
:1;
171 unsigned int cpui686
:1;
172 unsigned int cpuclflush
:1;
173 unsigned int cpunop
:1;
174 unsigned int cpusyscall
:1;
175 unsigned int cpu8087
:1;
176 unsigned int cpu287
:1;
177 unsigned int cpu387
:1;
178 unsigned int cpu687
:1;
179 unsigned int cpufisttp
:1;
180 unsigned int cpummx
:1;
181 unsigned int cpusse
:1;
182 unsigned int cpusse2
:1;
183 unsigned int cpua3dnow
:1;
184 unsigned int cpua3dnowa
:1;
185 unsigned int cpusse3
:1;
186 unsigned int cpupadlock
:1;
187 unsigned int cpusvme
:1;
188 unsigned int cpuvmx
:1;
189 unsigned int cpusmx
:1;
190 unsigned int cpussse3
:1;
191 unsigned int cpusse4a
:1;
192 unsigned int cpuabm
:1;
193 unsigned int cpusse4_1
:1;
194 unsigned int cpusse4_2
:1;
195 unsigned int cpuavx
:1;
196 unsigned int cpuavx2
:1;
197 unsigned int cpul1om
:1;
198 unsigned int cpuk1om
:1;
199 unsigned int cpuxsave
:1;
200 unsigned int cpuxsaveopt
:1;
201 unsigned int cpuaes
:1;
202 unsigned int cpupclmul
:1;
203 unsigned int cpufma
:1;
204 unsigned int cpufma4
:1;
205 unsigned int cpuxop
:1;
206 unsigned int cpulwp
:1;
207 unsigned int cpubmi
:1;
208 unsigned int cputbm
:1;
209 unsigned int cpumovbe
:1;
210 unsigned int cpuept
:1;
211 unsigned int cpurdtscp
:1;
212 unsigned int cpufsgsbase
:1;
213 unsigned int cpurdrnd
:1;
214 unsigned int cpuf16c
:1;
215 unsigned int cpubmi2
:1;
216 unsigned int cpulzcnt
:1;
217 unsigned int cpuinvpcid
:1;
218 unsigned int cpuvmfunc
:1;
219 unsigned int cpulm
:1;
220 unsigned int cpu64
:1;
221 unsigned int cpuno64
:1;
223 unsigned int unused
:(CpuNumOfBits
- CpuUnused
);
226 unsigned int array
[CpuNumOfUints
];
229 /* Position of opcode_modifier bits. */
233 /* has direction bit. */
235 /* set if operands can be words or dwords encoded the canonical way */
237 /* Skip the current insn and use the next insn in i386-opc.tbl to swap
238 operand in encoding. */
240 /* insn has a modrm byte. */
242 /* register is in low 3 bits of opcode */
244 /* special case for jump insns. */
250 /* special case for intersegment leaps/calls */
252 /* FP insn memory format bit, sized by 0x4 */
254 /* src/dest swap for floats. */
256 /* has float insn direction bit. */
258 /* needs size prefix if in 32-bit mode */
260 /* needs size prefix if in 16-bit mode */
262 /* needs size prefix if in 64-bit mode */
264 /* check register size. */
266 /* instruction ignores operand size prefix and in Intel mode ignores
267 mnemonic size suffix check. */
269 /* default insn size depends on mode */
271 /* b suffix on instruction illegal */
273 /* w suffix on instruction illegal */
275 /* l suffix on instruction illegal */
277 /* s suffix on instruction illegal */
279 /* q suffix on instruction illegal */
281 /* long double suffix on instruction illegal */
283 /* instruction needs FWAIT */
285 /* quick test for string instructions */
287 /* quick test for lockable instructions */
289 /* fake an extra reg operand for clr, imul and special register
290 processing for some instructions. */
292 /* The first operand must be xmm0 */
294 /* An implicit xmm0 as the first operand */
296 /* Convert to DWORD */
298 /* Convert to QWORD */
300 /* Address prefix changes operand 0 */
302 /* opcode is a prefix */
304 /* instruction has extension in 8 bit imm */
306 /* instruction don't need Rex64 prefix. */
308 /* instruction require Rex64 prefix. */
310 /* deprecated fp insn, gets a warning */
312 /* insn has VEX prefix:
313 1: 128bit VEX prefix.
314 2: 256bit VEX prefix.
315 3: Scalar VEX prefix.
321 /* How to encode VEX.vvvv:
322 0: VEX.vvvv must be 1111b.
323 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where
324 the content of source registers will be preserved.
325 VEX.DDS. The second register operand is encoded in VEX.vvvv
326 where the content of first source register will be overwritten
328 VEX.NDD2. The second destination register operand is encoded in
329 VEX.vvvv for instructions with 2 destination register operands.
330 For assembler, there are no difference between VEX.NDS, VEX.DDS
332 2. VEX.NDD. Register destination is encoded in VEX.vvvv for
333 instructions with 1 destination register operand.
334 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one
335 of the operands can access a memory location.
341 /* How the VEX.W bit is used:
342 0: Set by the REX.W bit.
343 1: VEX.W0. Should always be 0.
344 2: VEX.W1. Should always be 1.
349 /* VEX opcode prefix:
350 0: VEX 0x0F opcode prefix.
351 1: VEX 0x0F38 opcode prefix.
352 2: VEX 0x0F3A opcode prefix
353 3: XOP 0x08 opcode prefix.
354 4: XOP 0x09 opcode prefix
355 5: XOP 0x0A opcode prefix.
364 /* number of VEX source operands:
365 0: <= 2 source operands.
366 1: 2 XOP source operands.
367 2: 3 source operands.
369 #define XOP2SOURCES 1
370 #define VEX3SOURCES 2
372 /* instruction has VEX 8 bit imm */
374 /* Instruction with vector SIB byte:
375 1: 128bit vector register.
376 2: 256bit vector register.
381 /* SSE to AVX support required */
383 /* No AVX equivalent */
385 /* Compatible with old (<= 2.8.1) versions of gcc */
393 /* The last bitfield in i386_opcode_modifier. */
397 typedef struct i386_opcode_modifier
402 unsigned int modrm
:1;
403 unsigned int shortform
:1;
405 unsigned int jumpdword
:1;
406 unsigned int jumpbyte
:1;
407 unsigned int jumpintersegment
:1;
408 unsigned int floatmf
:1;
409 unsigned int floatr
:1;
410 unsigned int floatd
:1;
411 unsigned int size16
:1;
412 unsigned int size32
:1;
413 unsigned int size64
:1;
414 unsigned int checkregsize
:1;
415 unsigned int ignoresize
:1;
416 unsigned int defaultsize
:1;
417 unsigned int no_bsuf
:1;
418 unsigned int no_wsuf
:1;
419 unsigned int no_lsuf
:1;
420 unsigned int no_ssuf
:1;
421 unsigned int no_qsuf
:1;
422 unsigned int no_ldsuf
:1;
423 unsigned int fwait
:1;
424 unsigned int isstring
:1;
425 unsigned int islockable
:1;
426 unsigned int regkludge
:1;
427 unsigned int firstxmm0
:1;
428 unsigned int implicit1stxmm0
:1;
429 unsigned int todword
:1;
430 unsigned int toqword
:1;
431 unsigned int addrprefixop0
:1;
432 unsigned int isprefix
:1;
433 unsigned int immext
:1;
434 unsigned int norex64
:1;
435 unsigned int rex64
:1;
438 unsigned int vexvvvv
:2;
440 unsigned int vexopcode
:3;
441 unsigned int vexsources
:2;
442 unsigned int veximmext
:1;
443 unsigned int vecsib
:2;
444 unsigned int sse2avx
:1;
445 unsigned int noavx
:1;
446 unsigned int oldgcc
:1;
447 unsigned int attmnemonic
:1;
448 unsigned int attsyntax
:1;
449 unsigned int intelsyntax
:1;
450 } i386_opcode_modifier
;
452 /* Position of operand_type bits. */
464 /* Floating pointer stack register */
472 /* Control register */
478 /* 2 bit segment register */
480 /* 3 bit segment register */
482 /* 1 bit immediate */
484 /* 8 bit immediate */
486 /* 8 bit immediate sign extended */
488 /* 16 bit immediate */
490 /* 32 bit immediate */
492 /* 32 bit immediate sign extended */
494 /* 64 bit immediate */
496 /* 8bit/16bit/32bit displacements are used in different ways,
497 depending on the instruction. For jumps, they specify the
498 size of the PC relative displacement, for instructions with
499 memory operand, they specify the size of the offset relative
500 to the base register, and for instructions with memory offset
501 such as `mov 1234,%al' they specify the size of the offset
502 relative to the segment base. */
503 /* 8 bit displacement */
505 /* 16 bit displacement */
507 /* 32 bit displacement */
509 /* 32 bit signed displacement */
511 /* 64 bit displacement */
513 /* Accumulator %al/%ax/%eax/%rax */
515 /* Floating pointer top stack register %st(0) */
517 /* Register which can be used for base or index in memory operand. */
519 /* Register to hold in/out port addr = dx */
521 /* Register to hold shift count = cl */
523 /* Absolute address for jump. */
525 /* String insn operand with fixed es segment */
527 /* RegMem is for instructions with a modrm byte where the register
528 destination operand should be encoded in the mod and regmem fields.
529 Normally, it will be encoded in the reg field. We add a RegMem
530 flag to the destination register operand to indicate that it should
531 be encoded in the regmem field. */
537 /* WORD memory. 2 byte */
539 /* DWORD memory. 4 byte */
541 /* FWORD memory. 6 byte */
543 /* QWORD memory. 8 byte */
545 /* TBYTE memory. 10 byte */
547 /* XMMWORD memory. */
549 /* YMMWORD memory. */
551 /* Unspecified memory size. */
553 /* Any memory size. */
556 /* Vector 4 bit immediate. */
559 /* The last bitfield in i386_operand_type. */
563 #define OTNumOfUints \
564 (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
565 #define OTNumOfBits \
566 (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
568 /* If you get a compiler error for zero width of the unused field,
570 #define OTUnused (OTMax + 1)
572 typedef union i386_operand_type
577 unsigned int reg16
:1;
578 unsigned int reg32
:1;
579 unsigned int reg64
:1;
580 unsigned int floatreg
:1;
581 unsigned int regmmx
:1;
582 unsigned int regxmm
:1;
583 unsigned int regymm
:1;
584 unsigned int control
:1;
585 unsigned int debug
:1;
587 unsigned int sreg2
:1;
588 unsigned int sreg3
:1;
591 unsigned int imm8s
:1;
592 unsigned int imm16
:1;
593 unsigned int imm32
:1;
594 unsigned int imm32s
:1;
595 unsigned int imm64
:1;
596 unsigned int disp8
:1;
597 unsigned int disp16
:1;
598 unsigned int disp32
:1;
599 unsigned int disp32s
:1;
600 unsigned int disp64
:1;
602 unsigned int floatacc
:1;
603 unsigned int baseindex
:1;
604 unsigned int inoutportreg
:1;
605 unsigned int shiftcount
:1;
606 unsigned int jumpabsolute
:1;
607 unsigned int esseg
:1;
608 unsigned int regmem
:1;
612 unsigned int dword
:1;
613 unsigned int fword
:1;
614 unsigned int qword
:1;
615 unsigned int tbyte
:1;
616 unsigned int xmmword
:1;
617 unsigned int ymmword
:1;
618 unsigned int unspecified
:1;
619 unsigned int anysize
:1;
620 unsigned int vec_imm4
:1;
622 unsigned int unused
:(OTNumOfBits
- OTUnused
);
625 unsigned int array
[OTNumOfUints
];
628 typedef struct insn_template
630 /* instruction name sans width suffix ("mov" for movl insns) */
633 /* how many operands */
634 unsigned int operands
;
636 /* base_opcode is the fundamental opcode byte without optional
638 unsigned int base_opcode
;
639 #define Opcode_D 0x2 /* Direction bit:
640 set if Reg --> Regmem;
641 unset if Regmem --> Reg. */
642 #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
643 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
645 /* extension_opcode is the 3 bit extension for group <n> insns.
646 This field is also used to store the 8-bit opcode suffix for the
647 AMD 3DNow! instructions.
648 If this template has no extension opcode (the usual case) use None
650 unsigned int extension_opcode
;
651 #define None 0xffff /* If no extension_opcode is possible. */
654 unsigned char opcode_length
;
656 /* cpu feature flags */
657 i386_cpu_flags cpu_flags
;
659 /* the bits in opcode_modifier are used to generate the final opcode from
660 the base_opcode. These bits also are used to detect alternate forms of
661 the same instruction */
662 i386_opcode_modifier opcode_modifier
;
664 /* operand_types[i] describes the type of operand i. This is made
665 by OR'ing together all of the possible type masks. (e.g.
666 'operand_types[i] = Reg|Imm' specifies that operand i can be
667 either a register or an immediate operand. */
668 i386_operand_type operand_types
[MAX_OPERANDS
];
672 extern const insn_template i386_optab
[];
674 /* these are for register name --> number & type hash lookup */
678 i386_operand_type reg_type
;
679 unsigned char reg_flags
;
680 #define RegRex 0x1 /* Extended register. */
681 #define RegRex64 0x2 /* Extended 8 bit register. */
682 unsigned char reg_num
;
683 #define RegRip ((unsigned char ) ~0)
684 #define RegEip (RegRip - 1)
685 /* EIZ and RIZ are fake index registers. */
686 #define RegEiz (RegEip - 1)
687 #define RegRiz (RegEiz - 1)
688 /* FLAT is a fake segment register (Intel mode). */
689 #define RegFlat ((unsigned char) ~0)
690 signed char dw2_regnum
[2];
691 #define Dw2Inval (-1)
695 /* Entries in i386_regtab. */
698 #define REGNAM_EAX 41
700 extern const reg_entry i386_regtab
[];
701 extern const unsigned int i386_regtab_size
;
706 unsigned int seg_prefix
;
710 extern const seg_entry cs
;
711 extern const seg_entry ds
;
712 extern const seg_entry ss
;
713 extern const seg_entry es
;
714 extern const seg_entry fs
;
715 extern const seg_entry gs
;