1 /* Declarations for Intel 80386 opcode table
2 Copyright (C) 2007-2016 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 #include "opcode/i386.h"
30 /* Position of cpu flags bitfiled. */
34 /* i186 or better required */
36 /* i286 or better required */
38 /* i386 or better required */
40 /* i486 or better required */
42 /* i585 or better required */
44 /* i686 or better required */
46 /* CLFLUSH Instruction support required */
48 /* NOP Instruction support required */
50 /* SYSCALL Instructions support required */
52 /* Floating point support required */
54 /* i287 support required */
56 /* i387 support required */
58 /* i686 and floating point support required */
60 /* SSE3 and floating point support required */
62 /* MMX support required */
64 /* SSE support required */
66 /* SSE2 support required */
68 /* 3dnow! support required */
70 /* 3dnow! Extensions support required */
72 /* SSE3 support required */
74 /* VIA PadLock required */
76 /* AMD Secure Virtual Machine Ext-s required */
78 /* VMX Instructions required */
80 /* SMX Instructions required */
82 /* SSSE3 support required */
84 /* SSE4a support required */
86 /* ABM New Instructions required */
88 /* SSE4.1 support required */
90 /* SSE4.2 support required */
92 /* AVX support required */
94 /* AVX2 support required */
96 /* Intel AVX-512 Foundation Instructions support required */
98 /* Intel AVX-512 Conflict Detection Instructions support required */
100 /* Intel AVX-512 Exponential and Reciprocal Instructions support
103 /* Intel AVX-512 Prefetch Instructions support required */
105 /* Intel AVX-512 VL Instructions support required. */
107 /* Intel AVX-512 DQ Instructions support required. */
109 /* Intel AVX-512 BW Instructions support required. */
111 /* Intel L1OM support required */
113 /* Intel K1OM support required */
115 /* Intel IAMCU support required */
117 /* Xsave/xrstor New Instructions support required */
119 /* Xsaveopt New Instructions support required */
121 /* AES support required */
123 /* PCLMUL support required */
125 /* FMA support required */
127 /* FMA4 support required */
129 /* XOP support required */
131 /* LWP support required */
133 /* BMI support required */
135 /* TBM support required */
137 /* MOVBE Instruction support required */
139 /* CMPXCHG16B instruction support required. */
141 /* EPT Instructions required */
143 /* RDTSCP Instruction support required */
145 /* FSGSBASE Instructions required */
147 /* RDRND Instructions required */
149 /* F16C Instructions required */
151 /* Intel BMI2 support required */
153 /* LZCNT support required */
155 /* HLE support required */
157 /* RTM support required */
159 /* INVPCID Instructions required */
161 /* VMFUNC Instruction required */
163 /* Intel MPX Instructions required */
165 /* 64bit support available, used by -march= in assembler. */
167 /* RDRSEED instruction required. */
169 /* Multi-presisionn add-carry instructions are required. */
171 /* Supports prefetchw and prefetch instructions. */
173 /* SMAP instructions required. */
175 /* SHA instructions required. */
177 /* VREX support required */
179 /* CLFLUSHOPT instruction required */
181 /* XSAVES/XRSTORS instruction required */
183 /* XSAVEC instruction required */
185 /* PREFETCHWT1 instruction required */
187 /* SE1 instruction required */
189 /* CLWB instruction required */
191 /* Intel AVX-512 IFMA Instructions support required. */
193 /* Intel AVX-512 VBMI Instructions support required. */
195 /* Intel AVX-512 4FMAPS Instructions support required. */
197 /* Intel AVX-512 4VNNIW Instructions support required. */
199 /* mwaitx instruction required */
201 /* Clzero instruction required */
203 /* OSPKE instruction required */
205 /* RDPID instruction required */
207 /* PTWRITE instruction required */
209 /* MMX register support required */
211 /* XMM register support required */
213 /* YMM register support required */
215 /* ZMM register support required */
217 /* Mask register support required */
219 /* 64bit support required */
221 /* Not supported in the 64bit mode */
223 /* The last bitfield in i386_cpu_flags. */
227 #define CpuNumOfUints \
228 (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
229 #define CpuNumOfBits \
230 (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
232 /* If you get a compiler error for zero width of the unused field,
234 #define CpuUnused (CpuMax + 1)
236 /* We can check if an instruction is available with array instead
238 typedef union i386_cpu_flags
242 unsigned int cpui186
:1;
243 unsigned int cpui286
:1;
244 unsigned int cpui386
:1;
245 unsigned int cpui486
:1;
246 unsigned int cpui586
:1;
247 unsigned int cpui686
:1;
248 unsigned int cpuclflush
:1;
249 unsigned int cpunop
:1;
250 unsigned int cpusyscall
:1;
251 unsigned int cpu8087
:1;
252 unsigned int cpu287
:1;
253 unsigned int cpu387
:1;
254 unsigned int cpu687
:1;
255 unsigned int cpufisttp
:1;
256 unsigned int cpummx
:1;
257 unsigned int cpusse
:1;
258 unsigned int cpusse2
:1;
259 unsigned int cpua3dnow
:1;
260 unsigned int cpua3dnowa
:1;
261 unsigned int cpusse3
:1;
262 unsigned int cpupadlock
:1;
263 unsigned int cpusvme
:1;
264 unsigned int cpuvmx
:1;
265 unsigned int cpusmx
:1;
266 unsigned int cpussse3
:1;
267 unsigned int cpusse4a
:1;
268 unsigned int cpuabm
:1;
269 unsigned int cpusse4_1
:1;
270 unsigned int cpusse4_2
:1;
271 unsigned int cpuavx
:1;
272 unsigned int cpuavx2
:1;
273 unsigned int cpuavx512f
:1;
274 unsigned int cpuavx512cd
:1;
275 unsigned int cpuavx512er
:1;
276 unsigned int cpuavx512pf
:1;
277 unsigned int cpuavx512vl
:1;
278 unsigned int cpuavx512dq
:1;
279 unsigned int cpuavx512bw
:1;
280 unsigned int cpul1om
:1;
281 unsigned int cpuk1om
:1;
282 unsigned int cpuiamcu
:1;
283 unsigned int cpuxsave
:1;
284 unsigned int cpuxsaveopt
:1;
285 unsigned int cpuaes
:1;
286 unsigned int cpupclmul
:1;
287 unsigned int cpufma
:1;
288 unsigned int cpufma4
:1;
289 unsigned int cpuxop
:1;
290 unsigned int cpulwp
:1;
291 unsigned int cpubmi
:1;
292 unsigned int cputbm
:1;
293 unsigned int cpumovbe
:1;
294 unsigned int cpucx16
:1;
295 unsigned int cpuept
:1;
296 unsigned int cpurdtscp
:1;
297 unsigned int cpufsgsbase
:1;
298 unsigned int cpurdrnd
:1;
299 unsigned int cpuf16c
:1;
300 unsigned int cpubmi2
:1;
301 unsigned int cpulzcnt
:1;
302 unsigned int cpuhle
:1;
303 unsigned int cpurtm
:1;
304 unsigned int cpuinvpcid
:1;
305 unsigned int cpuvmfunc
:1;
306 unsigned int cpumpx
:1;
307 unsigned int cpulm
:1;
308 unsigned int cpurdseed
:1;
309 unsigned int cpuadx
:1;
310 unsigned int cpuprfchw
:1;
311 unsigned int cpusmap
:1;
312 unsigned int cpusha
:1;
313 unsigned int cpuvrex
:1;
314 unsigned int cpuclflushopt
:1;
315 unsigned int cpuxsaves
:1;
316 unsigned int cpuxsavec
:1;
317 unsigned int cpuprefetchwt1
:1;
318 unsigned int cpuse1
:1;
319 unsigned int cpuclwb
:1;
320 unsigned int cpuavx512ifma
:1;
321 unsigned int cpuavx512vbmi
:1;
322 unsigned int cpuavx512_4fmaps
:1;
323 unsigned int cpuavx512_4vnniw
:1;
324 unsigned int cpumwaitx
:1;
325 unsigned int cpuclzero
:1;
326 unsigned int cpuospke
:1;
327 unsigned int cpurdpid
:1;
328 unsigned int cpuptwrite
:1;
329 unsigned int cpuregmmx
:1;
330 unsigned int cpuregxmm
:1;
331 unsigned int cpuregymm
:1;
332 unsigned int cpuregzmm
:1;
333 unsigned int cpuregmask
:1;
334 unsigned int cpu64
:1;
335 unsigned int cpuno64
:1;
337 unsigned int unused
:(CpuNumOfBits
- CpuUnused
);
340 unsigned int array
[CpuNumOfUints
];
343 /* Position of opcode_modifier bits. */
347 /* has direction bit. */
349 /* set if operands can be words or dwords encoded the canonical way */
351 /* Skip the current insn and use the next insn in i386-opc.tbl to swap
352 operand in encoding. */
354 /* insn has a modrm byte. */
356 /* register is in low 3 bits of opcode */
358 /* special case for jump insns. */
364 /* special case for intersegment leaps/calls */
366 /* FP insn memory format bit, sized by 0x4 */
368 /* src/dest swap for floats. */
370 /* has float insn direction bit. */
372 /* needs size prefix if in 32-bit mode */
374 /* needs size prefix if in 16-bit mode */
376 /* needs size prefix if in 64-bit mode */
378 /* check register size. */
380 /* instruction ignores operand size prefix and in Intel mode ignores
381 mnemonic size suffix check. */
383 /* default insn size depends on mode */
385 /* b suffix on instruction illegal */
387 /* w suffix on instruction illegal */
389 /* l suffix on instruction illegal */
391 /* s suffix on instruction illegal */
393 /* q suffix on instruction illegal */
395 /* long double suffix on instruction illegal */
397 /* instruction needs FWAIT */
399 /* quick test for string instructions */
401 /* quick test if branch instruction is MPX supported */
403 /* quick test for lockable instructions */
405 /* fake an extra reg operand for clr, imul and special register
406 processing for some instructions. */
408 /* The first operand must be xmm0 */
410 /* An implicit xmm0 as the first operand */
412 /* The HLE prefix is OK:
413 1. With a LOCK prefix.
414 2. With or without a LOCK prefix.
415 3. With a RELEASE (0xf3) prefix.
417 #define HLEPrefixNone 0
418 #define HLEPrefixLock 1
419 #define HLEPrefixAny 2
420 #define HLEPrefixRelease 3
422 /* An instruction on which a "rep" prefix is acceptable. */
424 /* Convert to DWORD */
426 /* Convert to QWORD */
428 /* Address prefix changes operand 0 */
430 /* opcode is a prefix */
432 /* instruction has extension in 8 bit imm */
434 /* instruction don't need Rex64 prefix. */
436 /* instruction require Rex64 prefix. */
438 /* deprecated fp insn, gets a warning */
440 /* insn has VEX prefix:
441 1: 128bit VEX prefix.
442 2: 256bit VEX prefix.
443 3: Scalar VEX prefix.
449 /* How to encode VEX.vvvv:
450 0: VEX.vvvv must be 1111b.
451 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where
452 the content of source registers will be preserved.
453 VEX.DDS. The second register operand is encoded in VEX.vvvv
454 where the content of first source register will be overwritten
456 VEX.NDD2. The second destination register operand is encoded in
457 VEX.vvvv for instructions with 2 destination register operands.
458 For assembler, there are no difference between VEX.NDS, VEX.DDS
460 2. VEX.NDD. Register destination is encoded in VEX.vvvv for
461 instructions with 1 destination register operand.
462 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one
463 of the operands can access a memory location.
469 /* How the VEX.W bit is used:
470 0: Set by the REX.W bit.
471 1: VEX.W0. Should always be 0.
472 2: VEX.W1. Should always be 1.
477 /* VEX opcode prefix:
478 0: VEX 0x0F opcode prefix.
479 1: VEX 0x0F38 opcode prefix.
480 2: VEX 0x0F3A opcode prefix
481 3: XOP 0x08 opcode prefix.
482 4: XOP 0x09 opcode prefix
483 5: XOP 0x0A opcode prefix.
492 /* number of VEX source operands:
493 0: <= 2 source operands.
494 1: 2 XOP source operands.
495 2: 3 source operands.
497 #define XOP2SOURCES 1
498 #define VEX3SOURCES 2
500 /* instruction has VEX 8 bit imm */
502 /* Instruction with vector SIB byte:
503 1: 128bit vector register.
504 2: 256bit vector register.
505 3: 512bit vector register.
511 /* SSE to AVX support required */
513 /* No AVX equivalent */
516 /* insn has EVEX prefix:
517 1: 512bit EVEX prefix.
518 2: 128bit EVEX prefix.
519 3: 256bit EVEX prefix.
520 4: Length-ignored (LIG) EVEX prefix.
528 /* AVX512 masking support:
531 3: Both zeroing and merging masking.
533 #define ZEROING_MASKING 1
534 #define MERGING_MASKING 2
535 #define BOTH_MASKING 3
538 /* Input element size of vector insn:
549 #define NO_BROADCAST 0
550 #define BROADCAST_1TO16 1
551 #define BROADCAST_1TO8 2
552 #define BROADCAST_1TO4 3
553 #define BROADCAST_1TO2 4
556 /* Static rounding control is supported. */
559 /* Supress All Exceptions is supported. */
562 /* Copressed Disp8*N attribute. */
565 /* Default mask isn't allowed. */
568 /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
569 It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
573 /* Compatible with old (<= 2.8.1) versions of gcc */
585 /* The last bitfield in i386_opcode_modifier. */
589 typedef struct i386_opcode_modifier
594 unsigned int modrm
:1;
595 unsigned int shortform
:1;
597 unsigned int jumpdword
:1;
598 unsigned int jumpbyte
:1;
599 unsigned int jumpintersegment
:1;
600 unsigned int floatmf
:1;
601 unsigned int floatr
:1;
602 unsigned int floatd
:1;
603 unsigned int size16
:1;
604 unsigned int size32
:1;
605 unsigned int size64
:1;
606 unsigned int checkregsize
:1;
607 unsigned int ignoresize
:1;
608 unsigned int defaultsize
:1;
609 unsigned int no_bsuf
:1;
610 unsigned int no_wsuf
:1;
611 unsigned int no_lsuf
:1;
612 unsigned int no_ssuf
:1;
613 unsigned int no_qsuf
:1;
614 unsigned int no_ldsuf
:1;
615 unsigned int fwait
:1;
616 unsigned int isstring
:1;
617 unsigned int bndprefixok
:1;
618 unsigned int islockable
:1;
619 unsigned int regkludge
:1;
620 unsigned int firstxmm0
:1;
621 unsigned int implicit1stxmm0
:1;
622 unsigned int hleprefixok
:2;
623 unsigned int repprefixok
:1;
624 unsigned int todword
:1;
625 unsigned int toqword
:1;
626 unsigned int addrprefixop0
:1;
627 unsigned int isprefix
:1;
628 unsigned int immext
:1;
629 unsigned int norex64
:1;
630 unsigned int rex64
:1;
633 unsigned int vexvvvv
:2;
635 unsigned int vexopcode
:3;
636 unsigned int vexsources
:2;
637 unsigned int veximmext
:1;
638 unsigned int vecsib
:2;
639 unsigned int sse2avx
:1;
640 unsigned int noavx
:1;
642 unsigned int masking
:2;
643 unsigned int vecesize
:1;
644 unsigned int broadcast
:3;
645 unsigned int staticrounding
:1;
647 unsigned int disp8memshift
:3;
648 unsigned int nodefmask
:1;
649 unsigned int implicitquadgroup
:1;
650 unsigned int oldgcc
:1;
651 unsigned int attmnemonic
:1;
652 unsigned int attsyntax
:1;
653 unsigned int intelsyntax
:1;
654 unsigned int amd64
:1;
655 unsigned int intel64
:1;
656 } i386_opcode_modifier
;
658 /* Position of operand_type bits. */
670 /* Floating pointer stack register */
678 /* AVX512 registers */
680 /* Vector Mask registers */
682 /* Control register */
688 /* 2 bit segment register */
690 /* 3 bit segment register */
692 /* 1 bit immediate */
694 /* 8 bit immediate */
696 /* 8 bit immediate sign extended */
698 /* 16 bit immediate */
700 /* 32 bit immediate */
702 /* 32 bit immediate sign extended */
704 /* 64 bit immediate */
706 /* 8bit/16bit/32bit displacements are used in different ways,
707 depending on the instruction. For jumps, they specify the
708 size of the PC relative displacement, for instructions with
709 memory operand, they specify the size of the offset relative
710 to the base register, and for instructions with memory offset
711 such as `mov 1234,%al' they specify the size of the offset
712 relative to the segment base. */
713 /* 8 bit displacement */
715 /* 16 bit displacement */
717 /* 32 bit displacement */
719 /* 32 bit signed displacement */
721 /* 64 bit displacement */
723 /* Accumulator %al/%ax/%eax/%rax */
725 /* Floating pointer top stack register %st(0) */
727 /* Register which can be used for base or index in memory operand. */
729 /* Register to hold in/out port addr = dx */
731 /* Register to hold shift count = cl */
733 /* Absolute address for jump. */
735 /* String insn operand with fixed es segment */
737 /* RegMem is for instructions with a modrm byte where the register
738 destination operand should be encoded in the mod and regmem fields.
739 Normally, it will be encoded in the reg field. We add a RegMem
740 flag to the destination register operand to indicate that it should
741 be encoded in the regmem field. */
747 /* WORD memory. 2 byte */
749 /* DWORD memory. 4 byte */
751 /* FWORD memory. 6 byte */
753 /* QWORD memory. 8 byte */
755 /* TBYTE memory. 10 byte */
757 /* XMMWORD memory. */
759 /* YMMWORD memory. */
761 /* ZMMWORD memory. */
763 /* Unspecified memory size. */
765 /* Any memory size. */
768 /* Vector 4 bit immediate. */
771 /* Bound register. */
774 /* Vector 8bit displacement */
777 /* The last bitfield in i386_operand_type. */
781 #define OTNumOfUints \
782 (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
783 #define OTNumOfBits \
784 (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
786 /* If you get a compiler error for zero width of the unused field,
788 #define OTUnused (OTMax + 1)
790 typedef union i386_operand_type
795 unsigned int reg16
:1;
796 unsigned int reg32
:1;
797 unsigned int reg64
:1;
798 unsigned int floatreg
:1;
799 unsigned int regmmx
:1;
800 unsigned int regxmm
:1;
801 unsigned int regymm
:1;
802 unsigned int regzmm
:1;
803 unsigned int regmask
:1;
804 unsigned int control
:1;
805 unsigned int debug
:1;
807 unsigned int sreg2
:1;
808 unsigned int sreg3
:1;
811 unsigned int imm8s
:1;
812 unsigned int imm16
:1;
813 unsigned int imm32
:1;
814 unsigned int imm32s
:1;
815 unsigned int imm64
:1;
816 unsigned int disp8
:1;
817 unsigned int disp16
:1;
818 unsigned int disp32
:1;
819 unsigned int disp32s
:1;
820 unsigned int disp64
:1;
822 unsigned int floatacc
:1;
823 unsigned int baseindex
:1;
824 unsigned int inoutportreg
:1;
825 unsigned int shiftcount
:1;
826 unsigned int jumpabsolute
:1;
827 unsigned int esseg
:1;
828 unsigned int regmem
:1;
832 unsigned int dword
:1;
833 unsigned int fword
:1;
834 unsigned int qword
:1;
835 unsigned int tbyte
:1;
836 unsigned int xmmword
:1;
837 unsigned int ymmword
:1;
838 unsigned int zmmword
:1;
839 unsigned int unspecified
:1;
840 unsigned int anysize
:1;
841 unsigned int vec_imm4
:1;
842 unsigned int regbnd
:1;
843 unsigned int vec_disp8
:1;
845 unsigned int unused
:(OTNumOfBits
- OTUnused
);
848 unsigned int array
[OTNumOfUints
];
851 typedef struct insn_template
853 /* instruction name sans width suffix ("mov" for movl insns) */
856 /* how many operands */
857 unsigned int operands
;
859 /* base_opcode is the fundamental opcode byte without optional
861 unsigned int base_opcode
;
862 #define Opcode_D 0x2 /* Direction bit:
863 set if Reg --> Regmem;
864 unset if Regmem --> Reg. */
865 #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
866 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
868 /* extension_opcode is the 3 bit extension for group <n> insns.
869 This field is also used to store the 8-bit opcode suffix for the
870 AMD 3DNow! instructions.
871 If this template has no extension opcode (the usual case) use None
873 unsigned int extension_opcode
;
874 #define None 0xffff /* If no extension_opcode is possible. */
877 unsigned char opcode_length
;
879 /* cpu feature flags */
880 i386_cpu_flags cpu_flags
;
882 /* the bits in opcode_modifier are used to generate the final opcode from
883 the base_opcode. These bits also are used to detect alternate forms of
884 the same instruction */
885 i386_opcode_modifier opcode_modifier
;
887 /* operand_types[i] describes the type of operand i. This is made
888 by OR'ing together all of the possible type masks. (e.g.
889 'operand_types[i] = Reg|Imm' specifies that operand i can be
890 either a register or an immediate operand. */
891 i386_operand_type operand_types
[MAX_OPERANDS
];
895 extern const insn_template i386_optab
[];
897 /* these are for register name --> number & type hash lookup */
901 i386_operand_type reg_type
;
902 unsigned char reg_flags
;
903 #define RegRex 0x1 /* Extended register. */
904 #define RegRex64 0x2 /* Extended 8 bit register. */
905 #define RegVRex 0x4 /* Extended vector register. */
906 unsigned char reg_num
;
907 #define RegRip ((unsigned char ) ~0)
908 #define RegEip (RegRip - 1)
909 /* EIZ and RIZ are fake index registers. */
910 #define RegEiz (RegEip - 1)
911 #define RegRiz (RegEiz - 1)
912 /* FLAT is a fake segment register (Intel mode). */
913 #define RegFlat ((unsigned char) ~0)
914 signed char dw2_regnum
[2];
915 #define Dw2Inval (-1)
919 /* Entries in i386_regtab. */
922 #define REGNAM_EAX 41
924 extern const reg_entry i386_regtab
[];
925 extern const unsigned int i386_regtab_size
;
930 unsigned int seg_prefix
;
934 extern const seg_entry cs
;
935 extern const seg_entry ds
;
936 extern const seg_entry ss
;
937 extern const seg_entry es
;
938 extern const seg_entry fs
;
939 extern const seg_entry gs
;