opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright 2007, 2008, 2009, 2010, 2012
   3    Free Software Foundation, Inc.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  20    02110-1301, USA.  */
  21
  22 #include "opcode/i386.h"
  23 #ifdef HAVE_LIMITS_H
  24 #include <limits.h>
  25 #endif
  26
  27 #ifndef CHAR_BIT
  28 #define CHAR_BIT 8
  29 #endif
  30
  31 /* Position of cpu flags bitfiled.  */
  32
  33 enum
  34 {
  35   /* i186 or better required */
  36   Cpu186 = 0,
  37   /* i286 or better required */
  38   Cpu286,
  39   /* i386 or better required */
  40   Cpu386,
  41   /* i486 or better required */
  42   Cpu486,
  43   /* i585 or better required */
  44   Cpu586,
  45   /* i686 or better required */
  46   Cpu686,
  47   /* CLFLUSH Instruction support required */
  48   CpuClflush,
  49   /* NOP Instruction support required */
  50   CpuNop,
  51   /* SYSCALL Instructions support required */
  52   CpuSYSCALL,
  53   /* Floating point support required */
  54   Cpu8087,
  55   /* i287 support required */
  56   Cpu287,
  57   /* i387 support required */
  58   Cpu387,
  59   /* i686 and floating point support required */
  60   Cpu687,
  61   /* SSE3 and floating point support required */
  62   CpuFISTTP,
  63   /* MMX support required */
  64   CpuMMX,
  65   /* SSE support required */
  66   CpuSSE,
  67   /* SSE2 support required */
  68   CpuSSE2,
  69   /* 3dnow! support required */
  70   Cpu3dnow,
  71   /* 3dnow! Extensions support required */
  72   Cpu3dnowA,
  73   /* SSE3 support required */
  74   CpuSSE3,
  75   /* VIA PadLock required */
  76   CpuPadLock,
  77   /* AMD Secure Virtual Machine Ext-s required */
  78   CpuSVME,
  79   /* VMX Instructions required */
  80   CpuVMX,
  81   /* SMX Instructions required */
  82   CpuSMX,
  83   /* SSSE3 support required */
  84   CpuSSSE3,
  85   /* SSE4a support required */
  86   CpuSSE4a,
  87   /* ABM New Instructions required */
  88   CpuABM,
  89   /* SSE4.1 support required */
  90   CpuSSE4_1,
  91   /* SSE4.2 support required */
  92   CpuSSE4_2,
  93   /* AVX support required */
  94   CpuAVX,
  95   /* AVX2 support required */
  96   CpuAVX2,
  97   /* Intel L1OM support required */
  98   CpuL1OM,
  99   /* Intel K1OM support required */
 100   CpuK1OM,
 101   /* Xsave/xrstor New Instructions support required */
 102   CpuXsave,
 103   /* Xsaveopt New Instructions support required */
 104   CpuXsaveopt,
 105   /* AES support required */
 106   CpuAES,
 107   /* PCLMUL support required */
 108   CpuPCLMUL,
 109   /* FMA support required */
 110   CpuFMA,
 111   /* FMA4 support required */
 112   CpuFMA4,
 113   /* XOP support required */
 114   CpuXOP,
 115   /* LWP support required */
 116   CpuLWP,
 117   /* BMI support required */
 118   CpuBMI,
 119   /* TBM support required */
 120   CpuTBM,
 121   /* MOVBE Instruction support required */
 122   CpuMovbe,
 123   /* CMPXCHG16B instruction support required.  */
 124   CpuCX16,
 125   /* EPT Instructions required */
 126   CpuEPT,
 127   /* RDTSCP Instruction support required */
 128   CpuRdtscp,
 129   /* FSGSBASE Instructions required */
 130   CpuFSGSBase,
 131   /* RDRND Instructions required */
 132   CpuRdRnd,
 133   /* F16C Instructions required */
 134   CpuF16C,
 135   /* Intel BMI2 support required */
 136   CpuBMI2,
 137   /* LZCNT support required */
 138   CpuLZCNT,
 139   /* HLE support required */
 140   CpuHLE,
 141   /* RTM support required */
 142   CpuRTM,
 143   /* INVPCID Instructions required */
 144   CpuINVPCID,
 145   /* VMFUNC Instruction required */
 146   CpuVMFUNC,
 147   /* 64bit support available, used by -march= in assembler.  */
 148   CpuLM,
 149   /* RDRSEED instruction required.  */
 150   CpuRDSEED,
 151   /* Multi-presisionn add-carry instructions are required.  */
 152   CpuADX,
 153   /* Supports prefetchw and prefetch instructions.  */
 154   CpuPRFCHW,
 155   /* 64bit support required  */
 156   Cpu64,
 157   /* Not supported in the 64bit mode  */
 158   CpuNo64,
 159   /* The last bitfield in i386_cpu_flags.  */
 160   CpuMax = CpuNo64
 161 };
 162
 163 #define CpuNumOfUints \
 164   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 165 #define CpuNumOfBits \
 166   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 167
 168 /* If you get a compiler error for zero width of the unused field,
 169    comment it out.  */
 170 #define CpuUnused       (CpuMax + 1)
 171
 172 /* We can check if an instruction is available with array instead
 173    of bitfield. */
 174 typedef union i386_cpu_flags
 175 {
 176   struct
 177     {
 178       unsigned int cpui186:1;
 179       unsigned int cpui286:1;
 180       unsigned int cpui386:1;
 181       unsigned int cpui486:1;
 182       unsigned int cpui586:1;
 183       unsigned int cpui686:1;
 184       unsigned int cpuclflush:1;
 185       unsigned int cpunop:1;
 186       unsigned int cpusyscall:1;
 187       unsigned int cpu8087:1;
 188       unsigned int cpu287:1;
 189       unsigned int cpu387:1;
 190       unsigned int cpu687:1;
 191       unsigned int cpufisttp:1;
 192       unsigned int cpummx:1;
 193       unsigned int cpusse:1;
 194       unsigned int cpusse2:1;
 195       unsigned int cpua3dnow:1;
 196       unsigned int cpua3dnowa:1;
 197       unsigned int cpusse3:1;
 198       unsigned int cpupadlock:1;
 199       unsigned int cpusvme:1;
 200       unsigned int cpuvmx:1;
 201       unsigned int cpusmx:1;
 202       unsigned int cpussse3:1;
 203       unsigned int cpusse4a:1;
 204       unsigned int cpuabm:1;
 205       unsigned int cpusse4_1:1;
 206       unsigned int cpusse4_2:1;
 207       unsigned int cpuavx:1;
 208       unsigned int cpuavx2:1;
 209       unsigned int cpul1om:1;
 210       unsigned int cpuk1om:1;
 211       unsigned int cpuxsave:1;
 212       unsigned int cpuxsaveopt:1;
 213       unsigned int cpuaes:1;
 214       unsigned int cpupclmul:1;
 215       unsigned int cpufma:1;
 216       unsigned int cpufma4:1;
 217       unsigned int cpuxop:1;
 218       unsigned int cpulwp:1;
 219       unsigned int cpubmi:1;
 220       unsigned int cputbm:1;
 221       unsigned int cpumovbe:1;
 222       unsigned int cpucx16:1;
 223       unsigned int cpuept:1;
 224       unsigned int cpurdtscp:1;
 225       unsigned int cpufsgsbase:1;
 226       unsigned int cpurdrnd:1;
 227       unsigned int cpuf16c:1;
 228       unsigned int cpubmi2:1;
 229       unsigned int cpulzcnt:1;
 230       unsigned int cpuhle:1;
 231       unsigned int cpurtm:1;
 232       unsigned int cpuinvpcid:1;
 233       unsigned int cpuvmfunc:1;
 234       unsigned int cpulm:1;
 235       unsigned int cpurdseed:1;
 236       unsigned int cpuadx:1;
 237       unsigned int cpuprfchw:1;
 238       unsigned int cpu64:1;
 239       unsigned int cpuno64:1;
 240 #ifdef CpuUnused
 241       unsigned int unused:(CpuNumOfBits - CpuUnused);
 242 #endif
 243     } bitfield;
 244   unsigned int array[CpuNumOfUints];
 245 } i386_cpu_flags;
 246
 247 /* Position of opcode_modifier bits.  */
 248
 249 enum
 250 {
 251   /* has direction bit. */
 252   D = 0,
 253   /* set if operands can be words or dwords encoded the canonical way */
 254   W,
 255   /* Skip the current insn and use the next insn in i386-opc.tbl to swap
 256      operand in encoding.  */
 257   S,
 258   /* insn has a modrm byte. */
 259   Modrm,
 260   /* register is in low 3 bits of opcode */
 261   ShortForm,
 262   /* special case for jump insns.  */
 263   Jump,
 264   /* call and jump */
 265   JumpDword,
 266   /* loop and jecxz */
 267   JumpByte,
 268   /* special case for intersegment leaps/calls */
 269   JumpInterSegment,
 270   /* FP insn memory format bit, sized by 0x4 */
 271   FloatMF,
 272   /* src/dest swap for floats. */
 273   FloatR,
 274   /* has float insn direction bit. */
 275   FloatD,
 276   /* needs size prefix if in 32-bit mode */
 277   Size16,
 278   /* needs size prefix if in 16-bit mode */
 279   Size32,
 280   /* needs size prefix if in 64-bit mode */
 281   Size64,
 282   /* check register size.  */
 283   CheckRegSize,
 284   /* instruction ignores operand size prefix and in Intel mode ignores
 285      mnemonic size suffix check.  */
 286   IgnoreSize,
 287   /* default insn size depends on mode */
 288   DefaultSize,
 289   /* b suffix on instruction illegal */
 290   No_bSuf,
 291   /* w suffix on instruction illegal */
 292   No_wSuf,
 293   /* l suffix on instruction illegal */
 294   No_lSuf,
 295   /* s suffix on instruction illegal */
 296   No_sSuf,
 297   /* q suffix on instruction illegal */
 298   No_qSuf,
 299   /* long double suffix on instruction illegal */
 300   No_ldSuf,
 301   /* instruction needs FWAIT */
 302   FWait,
 303   /* quick test for string instructions */
 304   IsString,
 305   /* quick test for lockable instructions */
 306   IsLockable,
 307   /* fake an extra reg operand for clr, imul and special register
 308      processing for some instructions.  */
 309   RegKludge,
 310   /* The first operand must be xmm0 */
 311   FirstXmm0,
 312   /* An implicit xmm0 as the first operand */
 313   Implicit1stXmm0,
 314   /* The HLE prefix is OK:
 315      1. With a LOCK prefix.
 316      2. With or without a LOCK prefix.
 317      3. With a RELEASE (0xf3) prefix.
 318    */
 319 #define HLEPrefixNone           0
 320 #define HLEPrefixLock           1
 321 #define HLEPrefixAny            2
 322 #define HLEPrefixRelease        3
 323   HLEPrefixOk,
 324   /* An instruction on which a "rep" prefix is acceptable.  */
 325   RepPrefixOk,
 326   /* Convert to DWORD */
 327   ToDword,
 328   /* Convert to QWORD */
 329   ToQword,
 330   /* Address prefix changes operand 0 */
 331   AddrPrefixOp0,
 332   /* opcode is a prefix */
 333   IsPrefix,
 334   /* instruction has extension in 8 bit imm */
 335   ImmExt,
 336   /* instruction don't need Rex64 prefix.  */
 337   NoRex64,
 338   /* instruction require Rex64 prefix.  */
 339   Rex64,
 340   /* deprecated fp insn, gets a warning */
 341   Ugh,
 342   /* insn has VEX prefix:
 343         1: 128bit VEX prefix.
 344         2: 256bit VEX prefix.
 345         3: Scalar VEX prefix.
 346    */
 347 #define VEX128          1
 348 #define VEX256          2
 349 #define VEXScalar       3
 350   Vex,
 351   /* How to encode VEX.vvvv:
 352      0: VEX.vvvv must be 1111b.
 353      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 354         the content of source registers will be preserved.
 355         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 356         where the content of first source register will be overwritten
 357         by the result.
 358         VEX.NDD2.  The second destination register operand is encoded in
 359         VEX.vvvv for instructions with 2 destination register operands.
 360         For assembler, there are no difference between VEX.NDS, VEX.DDS
 361         and VEX.NDD2.
 362      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 363      instructions with 1 destination register operand.
 364      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 365         of the operands can access a memory location.
 366    */
 367 #define VEXXDS  1
 368 #define VEXNDD  2
 369 #define VEXLWP  3
 370   VexVVVV,
 371   /* How the VEX.W bit is used:
 372      0: Set by the REX.W bit.
 373      1: VEX.W0.  Should always be 0.
 374      2: VEX.W1.  Should always be 1.
 375    */
 376 #define VEXW0   1
 377 #define VEXW1   2
 378   VexW,
 379   /* VEX opcode prefix:
 380      0: VEX 0x0F opcode prefix.
 381      1: VEX 0x0F38 opcode prefix.
 382      2: VEX 0x0F3A opcode prefix
 383      3: XOP 0x08 opcode prefix.
 384      4: XOP 0x09 opcode prefix
 385      5: XOP 0x0A opcode prefix.
 386    */
 387 #define VEX0F           0
 388 #define VEX0F38         1
 389 #define VEX0F3A         2
 390 #define XOP08           3
 391 #define XOP09           4
 392 #define XOP0A           5
 393   VexOpcode,
 394   /* number of VEX source operands:
 395      0: <= 2 source operands.
 396      1: 2 XOP source operands.
 397      2: 3 source operands.
 398    */
 399 #define XOP2SOURCES     1
 400 #define VEX3SOURCES     2
 401   VexSources,
 402   /* instruction has VEX 8 bit imm */
 403   VexImmExt,
 404   /* Instruction with vector SIB byte:
 405         1: 128bit vector register.
 406         2: 256bit vector register.
 407    */
 408 #define VecSIB128       1
 409 #define VecSIB256       2
 410   VecSIB,
 411   /* SSE to AVX support required */
 412   SSE2AVX,
 413   /* No AVX equivalent */
 414   NoAVX,
 415   /* Compatible with old (<= 2.8.1) versions of gcc  */
 416   OldGcc,
 417   /* AT&T mnemonic.  */
 418   ATTMnemonic,
 419   /* AT&T syntax.  */
 420   ATTSyntax,
 421   /* Intel syntax.  */
 422   IntelSyntax,
 423   /* The last bitfield in i386_opcode_modifier.  */
 424   Opcode_Modifier_Max
 425 };
 426
 427 typedef struct i386_opcode_modifier
 428 {
 429   unsigned int d:1;
 430   unsigned int w:1;
 431   unsigned int s:1;
 432   unsigned int modrm:1;
 433   unsigned int shortform:1;
 434   unsigned int jump:1;
 435   unsigned int jumpdword:1;
 436   unsigned int jumpbyte:1;
 437   unsigned int jumpintersegment:1;
 438   unsigned int floatmf:1;
 439   unsigned int floatr:1;
 440   unsigned int floatd:1;
 441   unsigned int size16:1;
 442   unsigned int size32:1;
 443   unsigned int size64:1;
 444   unsigned int checkregsize:1;
 445   unsigned int ignoresize:1;
 446   unsigned int defaultsize:1;
 447   unsigned int no_bsuf:1;
 448   unsigned int no_wsuf:1;
 449   unsigned int no_lsuf:1;
 450   unsigned int no_ssuf:1;
 451   unsigned int no_qsuf:1;
 452   unsigned int no_ldsuf:1;
 453   unsigned int fwait:1;
 454   unsigned int isstring:1;
 455   unsigned int islockable:1;
 456   unsigned int regkludge:1;
 457   unsigned int firstxmm0:1;
 458   unsigned int implicit1stxmm0:1;
 459   unsigned int hleprefixok:2;
 460   unsigned int repprefixok:1;
 461   unsigned int todword:1;
 462   unsigned int toqword:1;
 463   unsigned int addrprefixop0:1;
 464   unsigned int isprefix:1;
 465   unsigned int immext:1;
 466   unsigned int norex64:1;
 467   unsigned int rex64:1;
 468   unsigned int ugh:1;
 469   unsigned int vex:2;
 470   unsigned int vexvvvv:2;
 471   unsigned int vexw:2;
 472   unsigned int vexopcode:3;
 473   unsigned int vexsources:2;
 474   unsigned int veximmext:1;
 475   unsigned int vecsib:2;
 476   unsigned int sse2avx:1;
 477   unsigned int noavx:1;
 478   unsigned int oldgcc:1;
 479   unsigned int attmnemonic:1;
 480   unsigned int attsyntax:1;
 481   unsigned int intelsyntax:1;
 482 } i386_opcode_modifier;
 483
 484 /* Position of operand_type bits.  */
 485
 486 enum
 487 {
 488   /* 8bit register */
 489   Reg8 = 0,
 490   /* 16bit register */
 491   Reg16,
 492   /* 32bit register */
 493   Reg32,
 494   /* 64bit register */
 495   Reg64,
 496   /* Floating pointer stack register */
 497   FloatReg,
 498   /* MMX register */
 499   RegMMX,
 500   /* SSE register */
 501   RegXMM,
 502   /* AVX registers */
 503   RegYMM,
 504   /* Control register */
 505   Control,
 506   /* Debug register */
 507   Debug,
 508   /* Test register */
 509   Test,
 510   /* 2 bit segment register */
 511   SReg2,
 512   /* 3 bit segment register */
 513   SReg3,
 514   /* 1 bit immediate */
 515   Imm1,
 516   /* 8 bit immediate */
 517   Imm8,
 518   /* 8 bit immediate sign extended */
 519   Imm8S,
 520   /* 16 bit immediate */
 521   Imm16,
 522   /* 32 bit immediate */
 523   Imm32,
 524   /* 32 bit immediate sign extended */
 525   Imm32S,
 526   /* 64 bit immediate */
 527   Imm64,
 528   /* 8bit/16bit/32bit displacements are used in different ways,
 529      depending on the instruction.  For jumps, they specify the
 530      size of the PC relative displacement, for instructions with
 531      memory operand, they specify the size of the offset relative
 532      to the base register, and for instructions with memory offset
 533      such as `mov 1234,%al' they specify the size of the offset
 534      relative to the segment base.  */
 535   /* 8 bit displacement */
 536   Disp8,
 537   /* 16 bit displacement */
 538   Disp16,
 539   /* 32 bit displacement */
 540   Disp32,
 541   /* 32 bit signed displacement */
 542   Disp32S,
 543   /* 64 bit displacement */
 544   Disp64,
 545   /* Accumulator %al/%ax/%eax/%rax */
 546   Acc,
 547   /* Floating pointer top stack register %st(0) */
 548   FloatAcc,
 549   /* Register which can be used for base or index in memory operand.  */
 550   BaseIndex,
 551   /* Register to hold in/out port addr = dx */
 552   InOutPortReg,
 553   /* Register to hold shift count = cl */
 554   ShiftCount,
 555   /* Absolute address for jump.  */
 556   JumpAbsolute,
 557   /* String insn operand with fixed es segment */
 558   EsSeg,
 559   /* RegMem is for instructions with a modrm byte where the register
 560      destination operand should be encoded in the mod and regmem fields.
 561      Normally, it will be encoded in the reg field. We add a RegMem
 562      flag to the destination register operand to indicate that it should
 563      be encoded in the regmem field.  */
 564   RegMem,
 565   /* Memory.  */
 566   Mem,
 567   /* BYTE memory. */
 568   Byte,
 569   /* WORD memory. 2 byte */
 570   Word,
 571   /* DWORD memory. 4 byte */
 572   Dword,
 573   /* FWORD memory. 6 byte */
 574   Fword,
 575   /* QWORD memory. 8 byte */
 576   Qword,
 577   /* TBYTE memory. 10 byte */
 578   Tbyte,
 579   /* XMMWORD memory. */
 580   Xmmword,
 581   /* YMMWORD memory. */
 582   Ymmword,
 583   /* Unspecified memory size.  */
 584   Unspecified,
 585   /* Any memory size.  */
 586   Anysize,
 587
 588   /* Vector 4 bit immediate.  */
 589   Vec_Imm4,
 590
 591   /* The last bitfield in i386_operand_type.  */
 592   OTMax
 593 };
 594
 595 #define OTNumOfUints \
 596   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 597 #define OTNumOfBits \
 598   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 599
 600 /* If you get a compiler error for zero width of the unused field,
 601    comment it out.  */
 602 #define OTUnused                (OTMax + 1)
 603
 604 typedef union i386_operand_type
 605 {
 606   struct
 607     {
 608       unsigned int reg8:1;
 609       unsigned int reg16:1;
 610       unsigned int reg32:1;
 611       unsigned int reg64:1;
 612       unsigned int floatreg:1;
 613       unsigned int regmmx:1;
 614       unsigned int regxmm:1;
 615       unsigned int regymm:1;
 616       unsigned int control:1;
 617       unsigned int debug:1;
 618       unsigned int test:1;
 619       unsigned int sreg2:1;
 620       unsigned int sreg3:1;
 621       unsigned int imm1:1;
 622       unsigned int imm8:1;
 623       unsigned int imm8s:1;
 624       unsigned int imm16:1;
 625       unsigned int imm32:1;
 626       unsigned int imm32s:1;
 627       unsigned int imm64:1;
 628       unsigned int disp8:1;
 629       unsigned int disp16:1;
 630       unsigned int disp32:1;
 631       unsigned int disp32s:1;
 632       unsigned int disp64:1;
 633       unsigned int acc:1;
 634       unsigned int floatacc:1;
 635       unsigned int baseindex:1;
 636       unsigned int inoutportreg:1;
 637       unsigned int shiftcount:1;
 638       unsigned int jumpabsolute:1;
 639       unsigned int esseg:1;
 640       unsigned int regmem:1;
 641       unsigned int mem:1;
 642       unsigned int byte:1;
 643       unsigned int word:1;
 644       unsigned int dword:1;
 645       unsigned int fword:1;
 646       unsigned int qword:1;
 647       unsigned int tbyte:1;
 648       unsigned int xmmword:1;
 649       unsigned int ymmword:1;
 650       unsigned int unspecified:1;
 651       unsigned int anysize:1;
 652       unsigned int vec_imm4:1;
 653 #ifdef OTUnused
 654       unsigned int unused:(OTNumOfBits - OTUnused);
 655 #endif
 656     } bitfield;
 657   unsigned int array[OTNumOfUints];
 658 } i386_operand_type;
 659
 660 typedef struct insn_template
 661 {
 662   /* instruction name sans width suffix ("mov" for movl insns) */
 663   char *name;
 664
 665   /* how many operands */
 666   unsigned int operands;
 667
 668   /* base_opcode is the fundamental opcode byte without optional
 669      prefix(es).  */
 670   unsigned int base_opcode;
 671 #define Opcode_D        0x2 /* Direction bit:
 672                                set if Reg --> Regmem;
 673                                unset if Regmem --> Reg. */
 674 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 675 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 676
 677   /* extension_opcode is the 3 bit extension for group <n> insns.
 678      This field is also used to store the 8-bit opcode suffix for the
 679      AMD 3DNow! instructions.
 680      If this template has no extension opcode (the usual case) use None
 681      Instructions */
 682   unsigned int extension_opcode;
 683 #define None 0xffff             /* If no extension_opcode is possible.  */
 684
 685   /* Opcode length.  */
 686   unsigned char opcode_length;
 687
 688   /* cpu feature flags */
 689   i386_cpu_flags cpu_flags;
 690
 691   /* the bits in opcode_modifier are used to generate the final opcode from
 692      the base_opcode.  These bits also are used to detect alternate forms of
 693      the same instruction */
 694   i386_opcode_modifier opcode_modifier;
 695
 696   /* operand_types[i] describes the type of operand i.  This is made
 697      by OR'ing together all of the possible type masks.  (e.g.
 698      'operand_types[i] = Reg|Imm' specifies that operand i can be
 699      either a register or an immediate operand.  */
 700   i386_operand_type operand_types[MAX_OPERANDS];
 701 }
 702 insn_template;
 703
 704 extern const insn_template i386_optab[];
 705
 706 /* these are for register name --> number & type hash lookup */
 707 typedef struct
 708 {
 709   char *reg_name;
 710   i386_operand_type reg_type;
 711   unsigned char reg_flags;
 712 #define RegRex      0x1  /* Extended register.  */
 713 #define RegRex64    0x2  /* Extended 8 bit register.  */
 714   unsigned char reg_num;
 715 #define RegRip  ((unsigned char ) ~0)
 716 #define RegEip  (RegRip - 1)
 717 /* EIZ and RIZ are fake index registers.  */
 718 #define RegEiz  (RegEip - 1)
 719 #define RegRiz  (RegEiz - 1)
 720 /* FLAT is a fake segment register (Intel mode).  */
 721 #define RegFlat     ((unsigned char) ~0)
 722   signed char dw2_regnum[2];
 723 #define Dw2Inval (-1)
 724 }
 725 reg_entry;
 726
 727 /* Entries in i386_regtab.  */
 728 #define REGNAM_AL 1
 729 #define REGNAM_AX 25
 730 #define REGNAM_EAX 41
 731
 732 extern const reg_entry i386_regtab[];
 733 extern const unsigned int i386_regtab_size;
 734
 735 typedef struct
 736 {
 737   char *seg_name;
 738   unsigned int seg_prefix;
 739 }
 740 seg_entry;
 741
 742 extern const seg_entry cs;
 743 extern const seg_entry ds;
 744 extern const seg_entry ss;
 745 extern const seg_entry es;
 746 extern const seg_entry fs;
 747 extern const seg_entry gs;