opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright 2007, 2008
   3    Free Software Foundation, Inc.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  20    02110-1301, USA.  */
  21
  22 #include "opcode/i386.h"
  23 #ifdef HAVE_LIMITS_H
  24 #include <limits.h>
  25 #endif
  26
  27 #ifndef CHAR_BIT
  28 #define CHAR_BIT 8
  29 #endif
  30
  31 /* Position of cpu flags bitfiled.  */
  32
  33 /* i186 or better required */
  34 #define Cpu186          0
  35 /* i286 or better required */
  36 #define Cpu286          (Cpu186 + 1)
  37 /* i386 or better required */
  38 #define Cpu386          (Cpu286 + 1)
  39 /* i486 or better required */
  40 #define Cpu486          (Cpu386 + 1)
  41 /* i585 or better required */
  42 #define Cpu586          (Cpu486 + 1)
  43 /* i686 or better required */
  44 #define Cpu686          (Cpu586 + 1)
  45 /* Pentium4 or better required */
  46 #define CpuP4           (Cpu686 + 1)
  47 /* AMD K6 or better required*/
  48 #define CpuK6           (CpuP4 + 1)
  49 /* AMD K8 or better required */
  50 #define CpuK8           (CpuK6 + 1)
  51 /* MMX support required */
  52 #define CpuMMX          (CpuK8 + 1)
  53 /* SSE support required */
  54 #define CpuSSE          (CpuMMX + 1)
  55 /* SSE2 support required */
  56 #define CpuSSE2         (CpuSSE + 1)
  57 /* 3dnow! support required */
  58 #define Cpu3dnow        (CpuSSE2 + 1)
  59 /* 3dnow! Extensions support required */
  60 #define Cpu3dnowA       (Cpu3dnow + 1)
  61 /* SSE3 support required */
  62 #define CpuSSE3         (Cpu3dnowA + 1)
  63 /* VIA PadLock required */
  64 #define CpuPadLock      (CpuSSE3 + 1)
  65 /* AMD Secure Virtual Machine Ext-s required */
  66 #define CpuSVME         (CpuPadLock + 1)
  67 /* VMX Instructions required */
  68 #define CpuVMX          (CpuSVME + 1)
  69 /* SMX Instructions required */
  70 #define CpuSMX          (CpuVMX + 1)
  71 /* SSSE3 support required */
  72 #define CpuSSSE3        (CpuSMX + 1)
  73 /* SSE4a support required */
  74 #define CpuSSE4a        (CpuSSSE3 + 1)
  75 /* ABM New Instructions required */
  76 #define CpuABM          (CpuSSE4a + 1)
  77 /* SSE4.1 support required */
  78 #define CpuSSE4_1       (CpuABM + 1)
  79 /* SSE4.2 support required */
  80 #define CpuSSE4_2       (CpuSSE4_1 + 1)
  81 /* SSE5 support required */
  82 #define CpuSSE5         (CpuSSE4_2 + 1)
  83 /* AVX support required */
  84 #define CpuAVX          (CpuSSE5 + 1)
  85 /* Xsave/xrstor New Instuctions support required */
  86 #define CpuXsave        (CpuAVX + 1)
  87 /* AES support required */
  88 #define CpuAES          (CpuXsave + 1)
  89 /* PCLMUL support required */
  90 #define CpuPCLMUL       (CpuAES + 1)
  91 /* FMA support required */
  92 #define CpuFMA          (CpuPCLMUL + 1)
  93 /* 64bit support available, used by -march= in assembler.  */
  94 #define CpuLM           (CpuFMA + 1)
  95 /* 64bit support required  */
  96 #define Cpu64           (CpuLM + 1)
  97 /* Not supported in the 64bit mode  */
  98 #define CpuNo64         (Cpu64 + 1)
  99 /* The last bitfield in i386_cpu_flags.  */
 100 #define CpuMax          CpuNo64
 101
 102 #define CpuNumOfUints \
 103   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 104 #define CpuNumOfBits \
 105   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 106
 107 /* If you get a compiler error for zero width of the unused field,
 108    comment it out.  */
 109 #define CpuUnused       (CpuMax + 1)
 110
 111 /* We can check if an instruction is available with array instead
 112    of bitfield. */
 113 typedef union i386_cpu_flags
 114 {
 115   struct
 116     {
 117       unsigned int cpui186:1;
 118       unsigned int cpui286:1;
 119       unsigned int cpui386:1;
 120       unsigned int cpui486:1;
 121       unsigned int cpui586:1;
 122       unsigned int cpui686:1;
 123       unsigned int cpup4:1;
 124       unsigned int cpuk6:1;
 125       unsigned int cpuk8:1;
 126       unsigned int cpummx:1;
 127       unsigned int cpusse:1;
 128       unsigned int cpusse2:1;
 129       unsigned int cpua3dnow:1;
 130       unsigned int cpua3dnowa:1;
 131       unsigned int cpusse3:1;
 132       unsigned int cpupadlock:1;
 133       unsigned int cpusvme:1;
 134       unsigned int cpuvmx:1;
 135       unsigned int cpusmx:1;
 136       unsigned int cpussse3:1;
 137       unsigned int cpusse4a:1;
 138       unsigned int cpuabm:1;
 139       unsigned int cpusse4_1:1;
 140       unsigned int cpusse4_2:1;
 141       unsigned int cpusse5:1;
 142       unsigned int cpuavx:1;
 143       unsigned int cpuxsave:1;
 144       unsigned int cpuaes:1;
 145       unsigned int cpupclmul:1;
 146       unsigned int cpufma:1;
 147       unsigned int cpulm:1;
 148       unsigned int cpu64:1;
 149       unsigned int cpuno64:1;
 150 #ifdef CpuUnused
 151       unsigned int unused:(CpuNumOfBits - CpuUnused);
 152 #endif
 153     } bitfield;
 154   unsigned int array[CpuNumOfUints];
 155 } i386_cpu_flags;
 156
 157 /* Position of opcode_modifier bits.  */
 158
 159 /* has direction bit. */
 160 #define D                       0
 161 /* set if operands can be words or dwords encoded the canonical way */
 162 #define W                       (D + 1)
 163 /* insn has a modrm byte. */
 164 #define Modrm                   (W + 1)
 165 /* register is in low 3 bits of opcode */
 166 #define ShortForm               (Modrm + 1)
 167 /* special case for jump insns.  */
 168 #define Jump                    (ShortForm + 1)
 169 /* call and jump */
 170 #define JumpDword               (Jump + 1)
 171 /* loop and jecxz */
 172 #define JumpByte                (JumpDword + 1)
 173 /* special case for intersegment leaps/calls */
 174 #define JumpInterSegment        (JumpByte + 1)
 175 /* FP insn memory format bit, sized by 0x4 */
 176 #define FloatMF                 (JumpInterSegment + 1)
 177 /* src/dest swap for floats. */
 178 #define FloatR                  (FloatMF + 1)
 179 /* has float insn direction bit. */
 180 #define FloatD                  (FloatR + 1)
 181 /* needs size prefix if in 32-bit mode */
 182 #define Size16                  (FloatD + 1)
 183 /* needs size prefix if in 16-bit mode */
 184 #define Size32                  (Size16 + 1)
 185 /* needs size prefix if in 64-bit mode */
 186 #define Size64                  (Size32 + 1)
 187 /* instruction ignores operand size prefix and in Intel mode ignores
 188    mnemonic size suffix check.  */
 189 #define IgnoreSize              (Size64 + 1)
 190 /* default insn size depends on mode */
 191 #define DefaultSize             (IgnoreSize + 1)
 192 /* b suffix on instruction illegal */
 193 #define No_bSuf                 (DefaultSize + 1)
 194 /* w suffix on instruction illegal */
 195 #define No_wSuf                 (No_bSuf + 1)
 196 /* l suffix on instruction illegal */
 197 #define No_lSuf                 (No_wSuf + 1)
 198 /* s suffix on instruction illegal */
 199 #define No_sSuf                 (No_lSuf + 1)
 200 /* q suffix on instruction illegal */
 201 #define No_qSuf                 (No_sSuf + 1)
 202 /* long double suffix on instruction illegal */
 203 #define No_ldSuf                (No_qSuf + 1)
 204 /* instruction needs FWAIT */
 205 #define FWait                   (No_ldSuf + 1)
 206 /* quick test for string instructions */
 207 #define IsString                (FWait + 1)
 208 /* fake an extra reg operand for clr, imul and special register
 209    processing for some instructions.  */
 210 #define RegKludge               (IsString + 1)
 211 /* The first operand must be xmm0 */
 212 #define FirstXmm0               (RegKludge + 1)
 213 /* An implicit xmm0 as the first operand */
 214 #define Implicit1stXmm0         (FirstXmm0 + 1)
 215 /* BYTE is OK in Intel syntax. */
 216 #define ByteOkIntel             (Implicit1stXmm0 + 1)
 217 /* Convert to DWORD */
 218 #define ToDword                 (ByteOkIntel + 1)
 219 /* Convert to QWORD */
 220 #define ToQword                 (ToDword + 1)
 221 /* Address prefix changes operand 0 */
 222 #define AddrPrefixOp0           (ToQword + 1)
 223 /* opcode is a prefix */
 224 #define IsPrefix                (AddrPrefixOp0 + 1)
 225 /* instruction has extension in 8 bit imm */
 226 #define ImmExt                  (IsPrefix + 1)
 227 /* instruction don't need Rex64 prefix.  */
 228 #define NoRex64                 (ImmExt + 1)
 229 /* instruction require Rex64 prefix.  */
 230 #define Rex64                   (NoRex64 + 1)
 231 /* deprecated fp insn, gets a warning */
 232 #define Ugh                     (Rex64 + 1)
 233 #define Drex                    (Ugh + 1)
 234 /* instruction needs DREX with multiple encodings for memory ops */
 235 #define Drexv                   (Drex + 1)
 236 /* special DREX for comparisons */
 237 #define Drexc                   (Drexv + 1)
 238 /* insn has VEX prefix. */
 239 #define Vex                     (Drexc + 1)
 240 /* insn has 256bit VEX prefix. */
 241 #define Vex256                  (Vex + 1)
 242 /* insn has VEX NDS. Register-only source is encoded in Vex
 243    prefix. */
 244 #define VexNDS                  (Vex256 + 1)
 245 /* insn has VEX NDD. Register destination is encoded in Vex
 246    prefix. */
 247 #define VexNDD                  (VexNDS + 1)
 248 /* insn has VEX W0. */
 249 #define VexW0                   (VexNDD + 1)
 250 /* insn has VEX W1. */
 251 #define VexW1                   (VexW0 + 1)
 252 /* insn has VEX 0x0F opcode prefix. */
 253 #define Vex0F                   (VexW1 + 1)
 254 /* insn has VEX 0x0F38 opcode prefix. */
 255 #define Vex0F38                 (Vex0F + 1)
 256 /* insn has VEX 0x0F3A opcode prefix. */
 257 #define Vex0F3A                 (Vex0F38 + 1)
 258 /* insn has VEX prefix with 3 soures. */
 259 #define Vex3Sources             (Vex0F3A + 1)
 260 /* instruction has VEX 8 bit imm */
 261 #define VexImmExt               (Vex3Sources + 1)
 262 /* SSE to AVX support required */
 263 #define SSE2AVX                 (VexImmExt + 1)
 264 /* No AVX equivalent */
 265 #define NoAVX                   (SSE2AVX + 1)
 266 /* Compatible with old (<= 2.8.1) versions of gcc  */
 267 #define OldGcc                  (NoAVX + 1)
 268 /* AT&T mnemonic.  */
 269 #define ATTMnemonic             (OldGcc + 1)
 270 /* AT&T syntax.  */
 271 #define ATTSyntax               (ATTMnemonic + 1)
 272 /* Intel syntax.  */
 273 #define IntelSyntax             (ATTSyntax + 1)
 274 /* The last bitfield in i386_opcode_modifier.  */
 275 #define Opcode_Modifier_Max     IntelSyntax
 276
 277 typedef struct i386_opcode_modifier
 278 {
 279   unsigned int d:1;
 280   unsigned int w:1;
 281   unsigned int modrm:1;
 282   unsigned int shortform:1;
 283   unsigned int jump:1;
 284   unsigned int jumpdword:1;
 285   unsigned int jumpbyte:1;
 286   unsigned int jumpintersegment:1;
 287   unsigned int floatmf:1;
 288   unsigned int floatr:1;
 289   unsigned int floatd:1;
 290   unsigned int size16:1;
 291   unsigned int size32:1;
 292   unsigned int size64:1;
 293   unsigned int ignoresize:1;
 294   unsigned int defaultsize:1;
 295   unsigned int no_bsuf:1;
 296   unsigned int no_wsuf:1;
 297   unsigned int no_lsuf:1;
 298   unsigned int no_ssuf:1;
 299   unsigned int no_qsuf:1;
 300   unsigned int no_ldsuf:1;
 301   unsigned int fwait:1;
 302   unsigned int isstring:1;
 303   unsigned int regkludge:1;
 304   unsigned int firstxmm0:1;
 305   unsigned int implicit1stxmm0:1;
 306   unsigned int byteokintel:1;
 307   unsigned int todword:1;
 308   unsigned int toqword:1;
 309   unsigned int addrprefixop0:1;
 310   unsigned int isprefix:1;
 311   unsigned int immext:1;
 312   unsigned int norex64:1;
 313   unsigned int rex64:1;
 314   unsigned int ugh:1;
 315   unsigned int drex:1;
 316   unsigned int drexv:1;
 317   unsigned int drexc:1;
 318   unsigned int vex:1;
 319   unsigned int vex256:1;
 320   unsigned int vexnds:1;
 321   unsigned int vexndd:1;
 322   unsigned int vexw0:1;
 323   unsigned int vexw1:1;
 324   unsigned int vex0f:1;
 325   unsigned int vex0f38:1;
 326   unsigned int vex0f3a:1;
 327   unsigned int vex3sources:1;
 328   unsigned int veximmext:1;
 329   unsigned int sse2avx:1;
 330   unsigned int noavx:1;
 331   unsigned int oldgcc:1;
 332   unsigned int attmnemonic:1;
 333   unsigned int attsyntax:1;
 334   unsigned int intelsyntax:1;
 335 } i386_opcode_modifier;
 336
 337 /* Position of operand_type bits.  */
 338
 339 /* 8bit register */
 340 #define Reg8                    0
 341 /* 16bit register */
 342 #define Reg16                   (Reg8 + 1)
 343 /* 32bit register */
 344 #define Reg32                   (Reg16 + 1)
 345 /* 64bit register */
 346 #define Reg64                   (Reg32 + 1)
 347 /* Floating pointer stack register */
 348 #define FloatReg                (Reg64 + 1)
 349 /* MMX register */
 350 #define RegMMX                  (FloatReg + 1)
 351 /* SSE register */
 352 #define RegXMM                  (RegMMX + 1)
 353 /* AVX registers */
 354 #define RegYMM                  (RegXMM + 1)
 355 /* Control register */
 356 #define Control                 (RegYMM + 1)
 357 /* Debug register */
 358 #define Debug                   (Control + 1)
 359 /* Test register */
 360 #define Test                    (Debug + 1)
 361 /* 2 bit segment register */
 362 #define SReg2                   (Test + 1)
 363 /* 3 bit segment register */
 364 #define SReg3                   (SReg2 + 1)
 365 /* 1 bit immediate */
 366 #define Imm1                    (SReg3 + 1)
 367 /* 8 bit immediate */
 368 #define Imm8                    (Imm1 + 1)
 369 /* 8 bit immediate sign extended */
 370 #define Imm8S                   (Imm8 + 1)
 371 /* 16 bit immediate */
 372 #define Imm16                   (Imm8S + 1)
 373 /* 32 bit immediate */
 374 #define Imm32                   (Imm16 + 1)
 375 /* 32 bit immediate sign extended */
 376 #define Imm32S                  (Imm32 + 1)
 377 /* 64 bit immediate */
 378 #define Imm64                   (Imm32S + 1)
 379 /* 8bit/16bit/32bit displacements are used in different ways,
 380    depending on the instruction.  For jumps, they specify the
 381    size of the PC relative displacement, for instructions with
 382    memory operand, they specify the size of the offset relative
 383    to the base register, and for instructions with memory offset
 384    such as `mov 1234,%al' they specify the size of the offset
 385    relative to the segment base.  */
 386 /* 8 bit displacement */
 387 #define Disp8                   (Imm64 + 1)
 388 /* 16 bit displacement */
 389 #define Disp16                  (Disp8 + 1)
 390 /* 32 bit displacement */
 391 #define Disp32                  (Disp16 + 1)
 392 /* 32 bit signed displacement */
 393 #define Disp32S                 (Disp32 + 1)
 394 /* 64 bit displacement */
 395 #define Disp64                  (Disp32S + 1)
 396 /* Accumulator %al/%ax/%eax/%rax */
 397 #define Acc                     (Disp64 + 1)
 398 /* Floating pointer top stack register %st(0) */
 399 #define FloatAcc                (Acc + 1)
 400 /* Register which can be used for base or index in memory operand.  */
 401 #define BaseIndex               (FloatAcc + 1)
 402 /* Register to hold in/out port addr = dx */
 403 #define InOutPortReg            (BaseIndex + 1)
 404 /* Register to hold shift count = cl */
 405 #define ShiftCount              (InOutPortReg + 1)
 406 /* Absolute address for jump.  */
 407 #define JumpAbsolute            (ShiftCount + 1)
 408 /* String insn operand with fixed es segment */
 409 #define EsSeg                   (JumpAbsolute + 1)
 410 /* RegMem is for instructions with a modrm byte where the register
 411    destination operand should be encoded in the mod and regmem fields.
 412    Normally, it will be encoded in the reg field. We add a RegMem
 413    flag to the destination register operand to indicate that it should
 414    be encoded in the regmem field.  */
 415 #define RegMem                  (EsSeg + 1)
 416 /* Memory.  */
 417 #define Mem                     (RegMem + 1)
 418 /* BYTE memory. */
 419 #define Byte                    (Mem + 1)
 420 /* WORD memory. 2 byte */
 421 #define Word                    (Byte + 1)
 422 /* DWORD memory. 4 byte */
 423 #define Dword                   (Word + 1)
 424 /* FWORD memory. 6 byte */
 425 #define Fword                   (Dword + 1)
 426 /* QWORD memory. 8 byte */
 427 #define Qword                   (Fword + 1)
 428 /* TBYTE memory. 10 byte */
 429 #define Tbyte                   (Qword + 1)
 430 /* XMMWORD memory. */
 431 #define Xmmword                 (Tbyte + 1)
 432 /* YMMWORD memory. */
 433 #define Ymmword                 (Xmmword + 1)
 434 /* Unspecified memory size.  */
 435 #define Unspecified             (Ymmword + 1)
 436 /* Any memory size.  */
 437 #define Anysize                 (Unspecified  + 1)
 438
 439 /* VEX 4 bit immediate */
 440 #define Vex_Imm4                (Anysize + 1)
 441
 442 /* The last bitfield in i386_operand_type.  */
 443 #define OTMax                   Vex_Imm4
 444
 445 #define OTNumOfUints \
 446   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 447 #define OTNumOfBits \
 448   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 449
 450 /* If you get a compiler error for zero width of the unused field,
 451    comment it out.  */
 452 #define OTUnused                (OTMax + 1)
 453
 454 typedef union i386_operand_type
 455 {
 456   struct
 457     {
 458       unsigned int reg8:1;
 459       unsigned int reg16:1;
 460       unsigned int reg32:1;
 461       unsigned int reg64:1;
 462       unsigned int floatreg:1;
 463       unsigned int regmmx:1;
 464       unsigned int regxmm:1;
 465       unsigned int regymm:1;
 466       unsigned int control:1;
 467       unsigned int debug:1;
 468       unsigned int test:1;
 469       unsigned int sreg2:1;
 470       unsigned int sreg3:1;
 471       unsigned int imm1:1;
 472       unsigned int imm8:1;
 473       unsigned int imm8s:1;
 474       unsigned int imm16:1;
 475       unsigned int imm32:1;
 476       unsigned int imm32s:1;
 477       unsigned int imm64:1;
 478       unsigned int disp8:1;
 479       unsigned int disp16:1;
 480       unsigned int disp32:1;
 481       unsigned int disp32s:1;
 482       unsigned int disp64:1;
 483       unsigned int acc:1;
 484       unsigned int floatacc:1;
 485       unsigned int baseindex:1;
 486       unsigned int inoutportreg:1;
 487       unsigned int shiftcount:1;
 488       unsigned int jumpabsolute:1;
 489       unsigned int esseg:1;
 490       unsigned int regmem:1;
 491       unsigned int mem:1;
 492       unsigned int byte:1;
 493       unsigned int word:1;
 494       unsigned int dword:1;
 495       unsigned int fword:1;
 496       unsigned int qword:1;
 497       unsigned int tbyte:1;
 498       unsigned int xmmword:1;
 499       unsigned int ymmword:1;
 500       unsigned int unspecified:1;
 501       unsigned int anysize:1;
 502       unsigned int vex_imm4:1;
 503 #ifdef OTUnused
 504       unsigned int unused:(OTNumOfBits - OTUnused);
 505 #endif
 506     } bitfield;
 507   unsigned int array[OTNumOfUints];
 508 } i386_operand_type;
 509
 510 typedef struct template
 511 {
 512   /* instruction name sans width suffix ("mov" for movl insns) */
 513   char *name;
 514
 515   /* how many operands */
 516   unsigned int operands;
 517
 518   /* base_opcode is the fundamental opcode byte without optional
 519      prefix(es).  */
 520   unsigned int base_opcode;
 521 #define Opcode_D        0x2 /* Direction bit:
 522                                set if Reg --> Regmem;
 523                                unset if Regmem --> Reg. */
 524 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 525 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 526
 527   /* extension_opcode is the 3 bit extension for group <n> insns.
 528      This field is also used to store the 8-bit opcode suffix for the
 529      AMD 3DNow! instructions.
 530      If this template has no extension opcode (the usual case) use None
 531      Instructions with Drex use this to specify 2 bits for OC */
 532   unsigned int extension_opcode;
 533 #define None 0xffff             /* If no extension_opcode is possible.  */
 534
 535   /* Opcode length.  */
 536   unsigned char opcode_length;
 537
 538   /* cpu feature flags */
 539   i386_cpu_flags cpu_flags;
 540
 541   /* the bits in opcode_modifier are used to generate the final opcode from
 542      the base_opcode.  These bits also are used to detect alternate forms of
 543      the same instruction */
 544   i386_opcode_modifier opcode_modifier;
 545
 546   /* operand_types[i] describes the type of operand i.  This is made
 547      by OR'ing together all of the possible type masks.  (e.g.
 548      'operand_types[i] = Reg|Imm' specifies that operand i can be
 549      either a register or an immediate operand.  */
 550   i386_operand_type operand_types[MAX_OPERANDS];
 551 }
 552 template;
 553
 554 extern const template i386_optab[];
 555
 556 /* these are for register name --> number & type hash lookup */
 557 typedef struct
 558 {
 559   char *reg_name;
 560   i386_operand_type reg_type;
 561   unsigned char reg_flags;
 562 #define RegRex      0x1  /* Extended register.  */
 563 #define RegRex64    0x2  /* Extended 8 bit register.  */
 564   unsigned char reg_num;
 565 #define RegRip  ((unsigned char ) ~0)
 566 #define RegEip  (RegRip - 1)
 567 /* EIZ and RIZ are fake index registers.  */
 568 #define RegEiz  (RegEip - 1)
 569 #define RegRiz  (RegEiz - 1)
 570 /* FLAT is a fake segment register (Intel mode).  */
 571 #define RegFlat     ((unsigned char) ~0)
 572   signed char dw2_regnum[2];
 573 #define Dw2Inval (-1)
 574 }
 575 reg_entry;
 576
 577 /* Entries in i386_regtab.  */
 578 #define REGNAM_AL 1
 579 #define REGNAM_AX 25
 580 #define REGNAM_EAX 41
 581
 582 extern const reg_entry i386_regtab[];
 583 extern const unsigned int i386_regtab_size;
 584
 585 typedef struct
 586 {
 587   char *seg_name;
 588   unsigned int seg_prefix;
 589 }
 590 seg_entry;
 591
 592 extern const seg_entry cs;
 593 extern const seg_entry ds;
 594 extern const seg_entry ss;
 595 extern const seg_entry es;
 596 extern const seg_entry fs;
 597 extern const seg_entry gs;