1 /* Declarations for Intel 80386 opcode table
3 Free Software Foundation, Inc.
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
22 #include "opcode/i386.h"
31 /* Position of cpu flags bitfiled. */
33 /* i186 or better required */
35 /* i286 or better required */
36 #define Cpu286 (Cpu186 + 1)
37 /* i386 or better required */
38 #define Cpu386 (Cpu286 + 1)
39 /* i486 or better required */
40 #define Cpu486 (Cpu386 + 1)
41 /* i585 or better required */
42 #define Cpu586 (Cpu486 + 1)
43 /* i686 or better required */
44 #define Cpu686 (Cpu586 + 1)
45 /* Pentium4 or better required */
46 #define CpuP4 (Cpu686 + 1)
47 /* AMD K6 or better required*/
48 #define CpuK6 (CpuP4 + 1)
49 /* AMD K8 or better required */
50 #define CpuK8 (CpuK6 + 1)
51 /* MMX support required */
52 #define CpuMMX (CpuK8 + 1)
53 /* extended MMX support (with SSE or 3DNow!Ext) required */
54 #define CpuMMX2 (CpuMMX + 1)
55 /* SSE support required */
56 #define CpuSSE (CpuMMX2 + 1)
57 /* SSE2 support required */
58 #define CpuSSE2 (CpuSSE + 1)
59 /* 3dnow! support required */
60 #define Cpu3dnow (CpuSSE2 + 1)
61 /* 3dnow! Extensions support required */
62 #define Cpu3dnowA (Cpu3dnow + 1)
63 /* SSE3 support required */
64 #define CpuSSE3 (Cpu3dnowA + 1)
65 /* VIA PadLock required */
66 #define CpuPadLock (CpuSSE3 + 1)
67 /* AMD Secure Virtual Machine Ext-s required */
68 #define CpuSVME (CpuPadLock + 1)
69 /* VMX Instructions required */
70 #define CpuVMX (CpuSVME + 1)
71 /* SMX Instructions required */
72 #define CpuSMX (CpuVMX + 1)
73 /* SSSE3 support required */
74 #define CpuSSSE3 (CpuSMX + 1)
75 /* SSE4a support required */
76 #define CpuSSE4a (CpuSSSE3 + 1)
77 /* ABM New Instructions required */
78 #define CpuABM (CpuSSE4a + 1)
79 /* SSE4.1 support required */
80 #define CpuSSE4_1 (CpuABM + 1)
81 /* SSE4.2 support required */
82 #define CpuSSE4_2 (CpuSSE4_1 + 1)
83 /* SSE5 support required */
84 #define CpuSSE5 (CpuSSE4_2 + 1)
85 /* SSE4.1 or SSE5 support required */
86 #define CpuSSE4_1_Or_5 (CpuSSE5 + 1)
87 /* 64bit support available, used by -march= in assembler. */
88 #define CpuLM (CpuSSE4_1_Or_5 + 1)
89 /* 64bit support required */
90 #define Cpu64 (CpuLM + 1)
91 /* Not supported in the 64bit mode */
92 #define CpuNo64 (Cpu64 + 1)
93 /* The last bitfield in i386_cpu_flags. */
94 #define CpuMax CpuNo64
96 #define CpuNumOfUints \
97 (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
98 #define CpuNumOfBits \
99 (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
101 /* If you get a compiler error for zero width of the unused field,
103 #define CpuUnused (CpuMax + 1)
105 /* We can check if an instruction is available with array instead
107 typedef union i386_cpu_flags
111 unsigned int cpui186
:1;
112 unsigned int cpui286
:1;
113 unsigned int cpui386
:1;
114 unsigned int cpui486
:1;
115 unsigned int cpui586
:1;
116 unsigned int cpui686
:1;
117 unsigned int cpup4
:1;
118 unsigned int cpuk6
:1;
119 unsigned int cpuk8
:1;
120 unsigned int cpummx
:1;
121 unsigned int cpummx2
:1;
122 unsigned int cpusse
:1;
123 unsigned int cpusse2
:1;
124 unsigned int cpua3dnow
:1;
125 unsigned int cpua3dnowa
:1;
126 unsigned int cpusse3
:1;
127 unsigned int cpupadlock
:1;
128 unsigned int cpusvme
:1;
129 unsigned int cpuvmx
:1;
130 unsigned int cpusmx
:1;
131 unsigned int cpussse3
:1;
132 unsigned int cpusse4a
:1;
133 unsigned int cpuabm
:1;
134 unsigned int cpusse4_1
:1;
135 unsigned int cpusse4_2
:1;
136 unsigned int cpusse5
:1;
137 unsigned int cpusse4_1_or_5
:1;
138 unsigned int cpulm
:1;
139 unsigned int cpu64
:1;
140 unsigned int cpuno64
:1;
142 unsigned int unused
:(CpuNumOfBits
- CpuUnused
);
145 unsigned int array
[CpuNumOfUints
];
148 /* Position of opcode_modifier bits. */
150 /* has direction bit. */
152 /* set if operands can be words or dwords encoded the canonical way */
154 /* insn has a modrm byte. */
155 #define Modrm (W + 1)
156 /* register is in low 3 bits of opcode */
157 #define ShortForm (Modrm + 1)
158 /* special case for jump insns. */
159 #define Jump (ShortForm + 1)
161 #define JumpDword (Jump + 1)
163 #define JumpByte (JumpDword + 1)
164 /* special case for intersegment leaps/calls */
165 #define JumpInterSegment (JumpByte + 1)
166 /* FP insn memory format bit, sized by 0x4 */
167 #define FloatMF (JumpInterSegment + 1)
168 /* src/dest swap for floats. */
169 #define FloatR (FloatMF + 1)
170 /* has float insn direction bit. */
171 #define FloatD (FloatR + 1)
172 /* needs size prefix if in 32-bit mode */
173 #define Size16 (FloatD + 1)
174 /* needs size prefix if in 16-bit mode */
175 #define Size32 (Size16 + 1)
176 /* needs size prefix if in 64-bit mode */
177 #define Size64 (Size32 + 1)
178 /* instruction ignores operand size prefix and in Intel mode ignores
179 mnemonic size suffix check. */
180 #define IgnoreSize (Size64 + 1)
181 /* default insn size depends on mode */
182 #define DefaultSize (IgnoreSize + 1)
183 /* b suffix on instruction illegal */
184 #define No_bSuf (DefaultSize + 1)
185 /* w suffix on instruction illegal */
186 #define No_wSuf (No_bSuf + 1)
187 /* l suffix on instruction illegal */
188 #define No_lSuf (No_wSuf + 1)
189 /* s suffix on instruction illegal */
190 #define No_sSuf (No_lSuf + 1)
191 /* q suffix on instruction illegal */
192 #define No_qSuf (No_sSuf + 1)
193 /* long double suffix on instruction illegal */
194 #define No_ldSuf (No_qSuf + 1)
195 /* x suffix on instruction illegal */
196 #define No_xSuf (No_ldSuf + 1)
197 /* check memory size on instruction in Intel mode if it is specified. */
198 #define CheckSize (No_xSuf + 1)
199 /* BYTE memory on instruction */
200 #define Byte (CheckSize + 1)
201 /* WORD memory on instruction */
202 #define Word (Byte + 1)
203 /* DWORD memory on instruction */
204 #define Dword (Word + 1)
205 /* QWORD memory on instruction */
206 #define Qword (Dword + 1)
207 /* XMMWORD memory on instruction */
208 #define Xmmword (Qword + 1)
209 /* instruction needs FWAIT */
210 #define FWait (Xmmword + 1)
211 /* quick test for string instructions */
212 #define IsString (FWait + 1)
213 /* fake an extra reg operand for clr, imul and special register
214 processing for some instructions. */
215 #define RegKludge (IsString + 1)
216 /* The first operand must be xmm0 */
217 #define FirstXmm0 (RegKludge + 1)
218 /* BYTE is OK in Intel syntax. */
219 #define ByteOkIntel (FirstXmm0 + 1)
220 /* Convert to DWORD */
221 #define ToDword (ByteOkIntel + 1)
222 /* Convert to QWORD */
223 #define ToQword (ToDword + 1)
224 /* Address prefix changes operand 0 */
225 #define AddrPrefixOp0 (ToQword + 1)
226 /* opcode is a prefix */
227 #define IsPrefix (AddrPrefixOp0 + 1)
228 /* instruction has extension in 8 bit imm */
229 #define ImmExt (IsPrefix + 1)
230 /* instruction don't need Rex64 prefix. */
231 #define NoRex64 (ImmExt + 1)
232 /* instruction require Rex64 prefix. */
233 #define Rex64 (NoRex64 + 1)
234 /* deprecated fp insn, gets a warning */
235 #define Ugh (Rex64 + 1)
236 #define Drex (Ugh + 1)
237 /* instruction needs DREX with multiple encodings for memory ops */
238 #define Drexv (Drex + 1)
239 /* special DREX for comparisons */
240 #define Drexc (Drexv + 1)
241 /* Compatible with old (<= 2.8.1) versions of gcc */
242 #define OldGcc (Drexc + 1)
244 #define ATTMnemonic (OldGcc + 1)
245 /* Intel mnemonic. */
246 #define IntelMnemonic (ATTMnemonic + 1)
247 /* The last bitfield in i386_opcode_modifier. */
248 #define Opcode_Modifier_Max IntelMnemonic
250 typedef struct i386_opcode_modifier
254 unsigned int modrm
:1;
255 unsigned int shortform
:1;
257 unsigned int jumpdword
:1;
258 unsigned int jumpbyte
:1;
259 unsigned int jumpintersegment
:1;
260 unsigned int floatmf
:1;
261 unsigned int floatr
:1;
262 unsigned int floatd
:1;
263 unsigned int size16
:1;
264 unsigned int size32
:1;
265 unsigned int size64
:1;
266 unsigned int ignoresize
:1;
267 unsigned int defaultsize
:1;
268 unsigned int no_bsuf
:1;
269 unsigned int no_wsuf
:1;
270 unsigned int no_lsuf
:1;
271 unsigned int no_ssuf
:1;
272 unsigned int no_qsuf
:1;
273 unsigned int no_ldsuf
:1;
274 unsigned int no_xsuf
:1;
275 unsigned int checksize
:1;
278 unsigned int dword
:1;
279 unsigned int qword
:1;
280 unsigned int xmmword
:1;
281 unsigned int fwait
:1;
282 unsigned int isstring
:1;
283 unsigned int regkludge
:1;
284 unsigned int firstxmm0
:1;
285 unsigned int byteokintel
:1;
286 unsigned int todword
:1;
287 unsigned int toqword
:1;
288 unsigned int addrprefixop0
:1;
289 unsigned int isprefix
:1;
290 unsigned int immext
:1;
291 unsigned int norex64
:1;
292 unsigned int rex64
:1;
295 unsigned int drexv
:1;
296 unsigned int drexc
:1;
297 unsigned int oldgcc
:1;
298 unsigned int attmnemonic
:1;
299 unsigned int intelmnemonic
:1;
300 } i386_opcode_modifier
;
302 /* Position of operand_type bits. */
309 #define Reg16 (Reg8 + 1)
311 #define Reg32 (Reg16 + 1)
313 #define Reg64 (Reg32 + 1)
317 /* 8 bit immediate */
318 #define Imm8 (Reg64 + 1)
319 /* 8 bit immediate sign extended */
320 #define Imm8S (Imm8 + 1)
321 /* 16 bit immediate */
322 #define Imm16 (Imm8S + 1)
323 /* 32 bit immediate */
324 #define Imm32 (Imm16 + 1)
325 /* 32 bit immediate sign extended */
326 #define Imm32S (Imm32 + 1)
327 /* 64 bit immediate */
328 #define Imm64 (Imm32S + 1)
329 /* 1 bit immediate */
330 #define Imm1 (Imm64 + 1)
334 #define BaseIndex (Imm1 + 1)
335 /* Disp8,16,32 are used in different ways, depending on the
336 instruction. For jumps, they specify the size of the PC relative
337 displacement, for baseindex type instructions, they specify the
338 size of the offset relative to the base register, and for memory
339 offset instructions such as `mov 1234,%al' they specify the size of
340 the offset relative to the segment base. */
341 /* 8 bit displacement */
342 #define Disp8 (BaseIndex + 1)
343 /* 16 bit displacement */
344 #define Disp16 (Disp8 + 1)
345 /* 32 bit displacement */
346 #define Disp32 (Disp16 + 1)
347 /* 32 bit signed displacement */
348 #define Disp32S (Disp32 + 1)
349 /* 64 bit displacement */
350 #define Disp64 (Disp32S + 1)
354 /* register to hold in/out port addr = dx */
355 #define InOutPortReg (Disp64 + 1)
356 /* register to hold shift count = cl */
357 #define ShiftCount (InOutPortReg + 1)
358 /* Control register */
359 #define Control (ShiftCount + 1)
361 #define Debug (Control + 1)
363 #define Test (Debug + 1)
365 #define FloatReg (Test + 1)
366 /* Float stack top %st(0) */
367 #define FloatAcc (FloatReg + 1)
368 /* 2 bit segment register */
369 #define SReg2 (FloatAcc + 1)
370 /* 3 bit segment register */
371 #define SReg3 (SReg2 + 1)
372 /* Accumulator %al or %ax or %eax */
373 #define Acc (SReg3 + 1)
374 #define JumpAbsolute (Acc + 1)
376 #define RegMMX (JumpAbsolute + 1)
377 /* XMM registers in PIII */
378 #define RegXMM (RegMMX + 1)
379 /* String insn operand with fixed es segment */
380 #define EsSeg (RegXMM + 1)
382 /* RegMem is for instructions with a modrm byte where the register
383 destination operand should be encoded in the mod and regmem fields.
384 Normally, it will be encoded in the reg field. We add a RegMem
385 flag to the destination register operand to indicate that it should
386 be encoded in the regmem field. */
387 #define RegMem (EsSeg + 1)
389 /* The last bitfield in i386_operand_type. */
392 #define OTNumOfUints \
393 (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
394 #define OTNumOfBits \
395 (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
397 /* If you get a compiler error for zero width of the unused field,
400 #define OTUnused (OTMax + 1)
403 typedef union i386_operand_type
408 unsigned int reg16
:1;
409 unsigned int reg32
:1;
410 unsigned int reg64
:1;
412 unsigned int imm8s
:1;
413 unsigned int imm16
:1;
414 unsigned int imm32
:1;
415 unsigned int imm32s
:1;
416 unsigned int imm64
:1;
418 unsigned int baseindex
:1;
419 unsigned int disp8
:1;
420 unsigned int disp16
:1;
421 unsigned int disp32
:1;
422 unsigned int disp32s
:1;
423 unsigned int disp64
:1;
424 unsigned int inoutportreg
:1;
425 unsigned int shiftcount
:1;
426 unsigned int control
:1;
427 unsigned int debug
:1;
429 unsigned int floatreg
:1;
430 unsigned int floatacc
:1;
431 unsigned int sreg2
:1;
432 unsigned int sreg3
:1;
434 unsigned int jumpabsolute
:1;
435 unsigned int regmmx
:1;
436 unsigned int regxmm
:1;
437 unsigned int esseg
:1;
438 unsigned int regmem
:1;
440 unsigned int unused
:(OTNumOfBits
- OTUnused
);
443 unsigned int array
[OTNumOfUints
];
446 typedef struct template
448 /* instruction name sans width suffix ("mov" for movl insns) */
451 /* how many operands */
452 unsigned int operands
;
454 /* base_opcode is the fundamental opcode byte without optional
456 unsigned int base_opcode
;
457 #define Opcode_D 0x2 /* Direction bit:
458 set if Reg --> Regmem;
459 unset if Regmem --> Reg. */
460 #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
461 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
463 /* extension_opcode is the 3 bit extension for group <n> insns.
464 This field is also used to store the 8-bit opcode suffix for the
465 AMD 3DNow! instructions.
466 If this template has no extension opcode (the usual case) use None
467 Instructions with Drex use this to specify 2 bits for OC */
468 unsigned int extension_opcode
;
469 #define None 0xffff /* If no extension_opcode is possible. */
472 unsigned char opcode_length
;
474 /* cpu feature flags */
475 i386_cpu_flags cpu_flags
;
477 /* the bits in opcode_modifier are used to generate the final opcode from
478 the base_opcode. These bits also are used to detect alternate forms of
479 the same instruction */
480 i386_opcode_modifier opcode_modifier
;
482 /* operand_types[i] describes the type of operand i. This is made
483 by OR'ing together all of the possible type masks. (e.g.
484 'operand_types[i] = Reg|Imm' specifies that operand i can be
485 either a register or an immediate operand. */
486 i386_operand_type operand_types
[MAX_OPERANDS
];
490 extern const template i386_optab
[];
492 /* these are for register name --> number & type hash lookup */
496 i386_operand_type reg_type
;
497 unsigned int reg_flags
;
498 #define RegRex 0x1 /* Extended register. */
499 #define RegRex64 0x2 /* Extended 8 bit register. */
500 unsigned int reg_num
;
501 #define RegRip ((unsigned int ) ~0)
502 #define RegEip (RegRip - 1)
503 /* EIZ and RIZ are fake index registers. */
504 #define RegEiz (RegEip - 1)
505 #define RegRiz (RegEiz - 1)
509 /* Entries in i386_regtab. */
512 #define REGNAM_EAX 41
514 extern const reg_entry i386_regtab
[];
515 extern const unsigned int i386_regtab_size
;
520 unsigned int seg_prefix
;
524 extern const seg_entry cs
;
525 extern const seg_entry ds
;
526 extern const seg_entry ss
;
527 extern const seg_entry es
;
528 extern const seg_entry fs
;
529 extern const seg_entry gs
;