1 /* Declarations for Intel 80386 opcode table
2 Copyright (C) 2007-2017 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 #include "opcode/i386.h"
30 /* Position of cpu flags bitfiled. */
34 /* i186 or better required */
36 /* i286 or better required */
38 /* i386 or better required */
40 /* i486 or better required */
42 /* i585 or better required */
44 /* i686 or better required */
46 /* CLFLUSH Instruction support required */
48 /* NOP Instruction support required */
50 /* SYSCALL Instructions support required */
52 /* Floating point support required */
54 /* i287 support required */
56 /* i387 support required */
58 /* i686 and floating point support required */
60 /* SSE3 and floating point support required */
62 /* MMX support required */
64 /* SSE support required */
66 /* SSE2 support required */
68 /* 3dnow! support required */
70 /* 3dnow! Extensions support required */
72 /* SSE3 support required */
74 /* VIA PadLock required */
76 /* AMD Secure Virtual Machine Ext-s required */
78 /* VMX Instructions required */
80 /* SMX Instructions required */
82 /* SSSE3 support required */
84 /* SSE4a support required */
86 /* ABM New Instructions required */
88 /* SSE4.1 support required */
90 /* SSE4.2 support required */
92 /* AVX support required */
94 /* AVX2 support required */
96 /* Intel AVX-512 Foundation Instructions support required */
98 /* Intel AVX-512 Conflict Detection Instructions support required */
100 /* Intel AVX-512 Exponential and Reciprocal Instructions support
103 /* Intel AVX-512 Prefetch Instructions support required */
105 /* Intel AVX-512 VL Instructions support required. */
107 /* Intel AVX-512 DQ Instructions support required. */
109 /* Intel AVX-512 BW Instructions support required. */
111 /* Intel L1OM support required */
113 /* Intel K1OM support required */
115 /* Intel IAMCU support required */
117 /* Xsave/xrstor New Instructions support required */
119 /* Xsaveopt New Instructions support required */
121 /* AES support required */
123 /* PCLMUL support required */
125 /* FMA support required */
127 /* FMA4 support required */
129 /* XOP support required */
131 /* LWP support required */
133 /* BMI support required */
135 /* TBM support required */
137 /* MOVBE Instruction support required */
139 /* CMPXCHG16B instruction support required. */
141 /* EPT Instructions required */
143 /* RDTSCP Instruction support required */
145 /* FSGSBASE Instructions required */
147 /* RDRND Instructions required */
149 /* F16C Instructions required */
151 /* Intel BMI2 support required */
153 /* LZCNT support required */
155 /* HLE support required */
157 /* RTM support required */
159 /* INVPCID Instructions required */
161 /* VMFUNC Instruction required */
163 /* Intel MPX Instructions required */
165 /* 64bit support available, used by -march= in assembler. */
167 /* RDRSEED instruction required. */
169 /* Multi-presisionn add-carry instructions are required. */
171 /* Supports prefetchw and prefetch instructions. */
173 /* SMAP instructions required. */
175 /* SHA instructions required. */
177 /* VREX support required */
179 /* CLFLUSHOPT instruction required */
181 /* XSAVES/XRSTORS instruction required */
183 /* XSAVEC instruction required */
185 /* PREFETCHWT1 instruction required */
187 /* SE1 instruction required */
189 /* CLWB instruction required */
191 /* Intel AVX-512 IFMA Instructions support required. */
193 /* Intel AVX-512 VBMI Instructions support required. */
195 /* Intel AVX-512 4FMAPS Instructions support required. */
197 /* Intel AVX-512 4VNNIW Instructions support required. */
199 /* Intel AVX-512 VPOPCNTDQ Instructions support required. */
201 /* mwaitx instruction required */
203 /* Clzero instruction required */
205 /* OSPKE instruction required */
207 /* RDPID instruction required */
209 /* PTWRITE instruction required */
211 /* CET instruction support required */
213 /* MMX register support required */
215 /* XMM register support required */
217 /* YMM register support required */
219 /* ZMM register support required */
221 /* Mask register support required */
223 /* 64bit support required */
225 /* Not supported in the 64bit mode */
227 /* The last bitfield in i386_cpu_flags. */
231 #define CpuNumOfUints \
232 (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
233 #define CpuNumOfBits \
234 (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
236 /* If you get a compiler error for zero width of the unused field,
239 #define CpuUnused (CpuMax + 1)
242 /* We can check if an instruction is available with array instead
244 typedef union i386_cpu_flags
248 unsigned int cpui186
:1;
249 unsigned int cpui286
:1;
250 unsigned int cpui386
:1;
251 unsigned int cpui486
:1;
252 unsigned int cpui586
:1;
253 unsigned int cpui686
:1;
254 unsigned int cpuclflush
:1;
255 unsigned int cpunop
:1;
256 unsigned int cpusyscall
:1;
257 unsigned int cpu8087
:1;
258 unsigned int cpu287
:1;
259 unsigned int cpu387
:1;
260 unsigned int cpu687
:1;
261 unsigned int cpufisttp
:1;
262 unsigned int cpummx
:1;
263 unsigned int cpusse
:1;
264 unsigned int cpusse2
:1;
265 unsigned int cpua3dnow
:1;
266 unsigned int cpua3dnowa
:1;
267 unsigned int cpusse3
:1;
268 unsigned int cpupadlock
:1;
269 unsigned int cpusvme
:1;
270 unsigned int cpuvmx
:1;
271 unsigned int cpusmx
:1;
272 unsigned int cpussse3
:1;
273 unsigned int cpusse4a
:1;
274 unsigned int cpuabm
:1;
275 unsigned int cpusse4_1
:1;
276 unsigned int cpusse4_2
:1;
277 unsigned int cpuavx
:1;
278 unsigned int cpuavx2
:1;
279 unsigned int cpuavx512f
:1;
280 unsigned int cpuavx512cd
:1;
281 unsigned int cpuavx512er
:1;
282 unsigned int cpuavx512pf
:1;
283 unsigned int cpuavx512vl
:1;
284 unsigned int cpuavx512dq
:1;
285 unsigned int cpuavx512bw
:1;
286 unsigned int cpul1om
:1;
287 unsigned int cpuk1om
:1;
288 unsigned int cpuiamcu
:1;
289 unsigned int cpuxsave
:1;
290 unsigned int cpuxsaveopt
:1;
291 unsigned int cpuaes
:1;
292 unsigned int cpupclmul
:1;
293 unsigned int cpufma
:1;
294 unsigned int cpufma4
:1;
295 unsigned int cpuxop
:1;
296 unsigned int cpulwp
:1;
297 unsigned int cpubmi
:1;
298 unsigned int cputbm
:1;
299 unsigned int cpumovbe
:1;
300 unsigned int cpucx16
:1;
301 unsigned int cpuept
:1;
302 unsigned int cpurdtscp
:1;
303 unsigned int cpufsgsbase
:1;
304 unsigned int cpurdrnd
:1;
305 unsigned int cpuf16c
:1;
306 unsigned int cpubmi2
:1;
307 unsigned int cpulzcnt
:1;
308 unsigned int cpuhle
:1;
309 unsigned int cpurtm
:1;
310 unsigned int cpuinvpcid
:1;
311 unsigned int cpuvmfunc
:1;
312 unsigned int cpumpx
:1;
313 unsigned int cpulm
:1;
314 unsigned int cpurdseed
:1;
315 unsigned int cpuadx
:1;
316 unsigned int cpuprfchw
:1;
317 unsigned int cpusmap
:1;
318 unsigned int cpusha
:1;
319 unsigned int cpuvrex
:1;
320 unsigned int cpuclflushopt
:1;
321 unsigned int cpuxsaves
:1;
322 unsigned int cpuxsavec
:1;
323 unsigned int cpuprefetchwt1
:1;
324 unsigned int cpuse1
:1;
325 unsigned int cpuclwb
:1;
326 unsigned int cpuavx512ifma
:1;
327 unsigned int cpuavx512vbmi
:1;
328 unsigned int cpuavx512_4fmaps
:1;
329 unsigned int cpuavx512_4vnniw
:1;
330 unsigned int cpuavx512_vpopcntdq
:1;
331 unsigned int cpumwaitx
:1;
332 unsigned int cpuclzero
:1;
333 unsigned int cpuospke
:1;
334 unsigned int cpurdpid
:1;
335 unsigned int cpuptwrite
:1;
336 unsigned int cpucet
:1;
337 unsigned int cpuregmmx
:1;
338 unsigned int cpuregxmm
:1;
339 unsigned int cpuregymm
:1;
340 unsigned int cpuregzmm
:1;
341 unsigned int cpuregmask
:1;
342 unsigned int cpu64
:1;
343 unsigned int cpuno64
:1;
345 unsigned int unused
:(CpuNumOfBits
- CpuUnused
);
348 unsigned int array
[CpuNumOfUints
];
351 /* Position of opcode_modifier bits. */
355 /* has direction bit. */
357 /* set if operands can be words or dwords encoded the canonical way */
359 /* load form instruction. Must be placed before store form. */
361 /* insn has a modrm byte. */
363 /* register is in low 3 bits of opcode */
365 /* special case for jump insns. */
371 /* special case for intersegment leaps/calls */
373 /* FP insn memory format bit, sized by 0x4 */
375 /* src/dest swap for floats. */
377 /* has float insn direction bit. */
379 /* needs size prefix if in 32-bit mode */
381 /* needs size prefix if in 16-bit mode */
383 /* needs size prefix if in 64-bit mode */
385 /* check register size. */
387 /* instruction ignores operand size prefix and in Intel mode ignores
388 mnemonic size suffix check. */
390 /* default insn size depends on mode */
392 /* b suffix on instruction illegal */
394 /* w suffix on instruction illegal */
396 /* l suffix on instruction illegal */
398 /* s suffix on instruction illegal */
400 /* q suffix on instruction illegal */
402 /* long double suffix on instruction illegal */
404 /* instruction needs FWAIT */
406 /* quick test for string instructions */
408 /* quick test if branch instruction is MPX supported */
410 /* quick test if NOTRACK prefix is supported */
412 /* quick test for lockable instructions */
414 /* fake an extra reg operand for clr, imul and special register
415 processing for some instructions. */
417 /* The first operand must be xmm0 */
419 /* An implicit xmm0 as the first operand */
421 /* The HLE prefix is OK:
422 1. With a LOCK prefix.
423 2. With or without a LOCK prefix.
424 3. With a RELEASE (0xf3) prefix.
426 #define HLEPrefixNone 0
427 #define HLEPrefixLock 1
428 #define HLEPrefixAny 2
429 #define HLEPrefixRelease 3
431 /* An instruction on which a "rep" prefix is acceptable. */
433 /* Convert to DWORD */
435 /* Convert to QWORD */
437 /* Address prefix changes operand 0 */
439 /* opcode is a prefix */
441 /* instruction has extension in 8 bit imm */
443 /* instruction don't need Rex64 prefix. */
445 /* instruction require Rex64 prefix. */
447 /* deprecated fp insn, gets a warning */
449 /* insn has VEX prefix:
450 1: 128bit VEX prefix.
451 2: 256bit VEX prefix.
452 3: Scalar VEX prefix.
458 /* How to encode VEX.vvvv:
459 0: VEX.vvvv must be 1111b.
460 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where
461 the content of source registers will be preserved.
462 VEX.DDS. The second register operand is encoded in VEX.vvvv
463 where the content of first source register will be overwritten
465 VEX.NDD2. The second destination register operand is encoded in
466 VEX.vvvv for instructions with 2 destination register operands.
467 For assembler, there are no difference between VEX.NDS, VEX.DDS
469 2. VEX.NDD. Register destination is encoded in VEX.vvvv for
470 instructions with 1 destination register operand.
471 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one
472 of the operands can access a memory location.
478 /* How the VEX.W bit is used:
479 0: Set by the REX.W bit.
480 1: VEX.W0. Should always be 0.
481 2: VEX.W1. Should always be 1.
486 /* VEX opcode prefix:
487 0: VEX 0x0F opcode prefix.
488 1: VEX 0x0F38 opcode prefix.
489 2: VEX 0x0F3A opcode prefix
490 3: XOP 0x08 opcode prefix.
491 4: XOP 0x09 opcode prefix
492 5: XOP 0x0A opcode prefix.
501 /* number of VEX source operands:
502 0: <= 2 source operands.
503 1: 2 XOP source operands.
504 2: 3 source operands.
506 #define XOP2SOURCES 1
507 #define VEX3SOURCES 2
509 /* instruction has VEX 8 bit imm */
511 /* Instruction with vector SIB byte:
512 1: 128bit vector register.
513 2: 256bit vector register.
514 3: 512bit vector register.
520 /* SSE to AVX support required */
522 /* No AVX equivalent */
525 /* insn has EVEX prefix:
526 1: 512bit EVEX prefix.
527 2: 128bit EVEX prefix.
528 3: 256bit EVEX prefix.
529 4: Length-ignored (LIG) EVEX prefix.
537 /* AVX512 masking support:
540 3: Both zeroing and merging masking.
542 #define ZEROING_MASKING 1
543 #define MERGING_MASKING 2
544 #define BOTH_MASKING 3
547 /* Input element size of vector insn:
558 #define NO_BROADCAST 0
559 #define BROADCAST_1TO16 1
560 #define BROADCAST_1TO8 2
561 #define BROADCAST_1TO4 3
562 #define BROADCAST_1TO2 4
565 /* Static rounding control is supported. */
568 /* Supress All Exceptions is supported. */
571 /* Copressed Disp8*N attribute. */
574 /* Default mask isn't allowed. */
577 /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
578 It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
582 /* Compatible with old (<= 2.8.1) versions of gcc */
594 /* The last bitfield in i386_opcode_modifier. */
598 typedef struct i386_opcode_modifier
603 unsigned int modrm
:1;
604 unsigned int shortform
:1;
606 unsigned int jumpdword
:1;
607 unsigned int jumpbyte
:1;
608 unsigned int jumpintersegment
:1;
609 unsigned int floatmf
:1;
610 unsigned int floatr
:1;
611 unsigned int floatd
:1;
612 unsigned int size16
:1;
613 unsigned int size32
:1;
614 unsigned int size64
:1;
615 unsigned int checkregsize
:1;
616 unsigned int ignoresize
:1;
617 unsigned int defaultsize
:1;
618 unsigned int no_bsuf
:1;
619 unsigned int no_wsuf
:1;
620 unsigned int no_lsuf
:1;
621 unsigned int no_ssuf
:1;
622 unsigned int no_qsuf
:1;
623 unsigned int no_ldsuf
:1;
624 unsigned int fwait
:1;
625 unsigned int isstring
:1;
626 unsigned int bndprefixok
:1;
627 unsigned int notrackprefixok
:1;
628 unsigned int islockable
:1;
629 unsigned int regkludge
:1;
630 unsigned int firstxmm0
:1;
631 unsigned int implicit1stxmm0
:1;
632 unsigned int hleprefixok
:2;
633 unsigned int repprefixok
:1;
634 unsigned int todword
:1;
635 unsigned int toqword
:1;
636 unsigned int addrprefixop0
:1;
637 unsigned int isprefix
:1;
638 unsigned int immext
:1;
639 unsigned int norex64
:1;
640 unsigned int rex64
:1;
643 unsigned int vexvvvv
:2;
645 unsigned int vexopcode
:3;
646 unsigned int vexsources
:2;
647 unsigned int veximmext
:1;
648 unsigned int vecsib
:2;
649 unsigned int sse2avx
:1;
650 unsigned int noavx
:1;
652 unsigned int masking
:2;
653 unsigned int vecesize
:1;
654 unsigned int broadcast
:3;
655 unsigned int staticrounding
:1;
657 unsigned int disp8memshift
:3;
658 unsigned int nodefmask
:1;
659 unsigned int implicitquadgroup
:1;
660 unsigned int oldgcc
:1;
661 unsigned int attmnemonic
:1;
662 unsigned int attsyntax
:1;
663 unsigned int intelsyntax
:1;
664 unsigned int amd64
:1;
665 unsigned int intel64
:1;
666 } i386_opcode_modifier
;
668 /* Position of operand_type bits. */
680 /* Floating pointer stack register */
688 /* AVX512 registers */
690 /* Vector Mask registers */
692 /* Control register */
698 /* 2 bit segment register */
700 /* 3 bit segment register */
702 /* 1 bit immediate */
704 /* 8 bit immediate */
706 /* 8 bit immediate sign extended */
708 /* 16 bit immediate */
710 /* 32 bit immediate */
712 /* 32 bit immediate sign extended */
714 /* 64 bit immediate */
716 /* 8bit/16bit/32bit displacements are used in different ways,
717 depending on the instruction. For jumps, they specify the
718 size of the PC relative displacement, for instructions with
719 memory operand, they specify the size of the offset relative
720 to the base register, and for instructions with memory offset
721 such as `mov 1234,%al' they specify the size of the offset
722 relative to the segment base. */
723 /* 8 bit displacement */
725 /* 16 bit displacement */
727 /* 32 bit displacement */
729 /* 32 bit signed displacement */
731 /* 64 bit displacement */
733 /* Accumulator %al/%ax/%eax/%rax */
735 /* Floating pointer top stack register %st(0) */
737 /* Register which can be used for base or index in memory operand. */
739 /* Register to hold in/out port addr = dx */
741 /* Register to hold shift count = cl */
743 /* Absolute address for jump. */
745 /* String insn operand with fixed es segment */
747 /* RegMem is for instructions with a modrm byte where the register
748 destination operand should be encoded in the mod and regmem fields.
749 Normally, it will be encoded in the reg field. We add a RegMem
750 flag to the destination register operand to indicate that it should
751 be encoded in the regmem field. */
757 /* WORD memory. 2 byte */
759 /* DWORD memory. 4 byte */
761 /* FWORD memory. 6 byte */
763 /* QWORD memory. 8 byte */
765 /* TBYTE memory. 10 byte */
767 /* XMMWORD memory. */
769 /* YMMWORD memory. */
771 /* ZMMWORD memory. */
773 /* Unspecified memory size. */
775 /* Any memory size. */
778 /* Vector 4 bit immediate. */
781 /* Bound register. */
784 /* Vector 8bit displacement */
787 /* The last bitfield in i386_operand_type. */
791 #define OTNumOfUints \
792 (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
793 #define OTNumOfBits \
794 (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
796 /* If you get a compiler error for zero width of the unused field,
798 #define OTUnused (OTMax + 1)
800 typedef union i386_operand_type
805 unsigned int reg16
:1;
806 unsigned int reg32
:1;
807 unsigned int reg64
:1;
808 unsigned int floatreg
:1;
809 unsigned int regmmx
:1;
810 unsigned int regxmm
:1;
811 unsigned int regymm
:1;
812 unsigned int regzmm
:1;
813 unsigned int regmask
:1;
814 unsigned int control
:1;
815 unsigned int debug
:1;
817 unsigned int sreg2
:1;
818 unsigned int sreg3
:1;
821 unsigned int imm8s
:1;
822 unsigned int imm16
:1;
823 unsigned int imm32
:1;
824 unsigned int imm32s
:1;
825 unsigned int imm64
:1;
826 unsigned int disp8
:1;
827 unsigned int disp16
:1;
828 unsigned int disp32
:1;
829 unsigned int disp32s
:1;
830 unsigned int disp64
:1;
832 unsigned int floatacc
:1;
833 unsigned int baseindex
:1;
834 unsigned int inoutportreg
:1;
835 unsigned int shiftcount
:1;
836 unsigned int jumpabsolute
:1;
837 unsigned int esseg
:1;
838 unsigned int regmem
:1;
842 unsigned int dword
:1;
843 unsigned int fword
:1;
844 unsigned int qword
:1;
845 unsigned int tbyte
:1;
846 unsigned int xmmword
:1;
847 unsigned int ymmword
:1;
848 unsigned int zmmword
:1;
849 unsigned int unspecified
:1;
850 unsigned int anysize
:1;
851 unsigned int vec_imm4
:1;
852 unsigned int regbnd
:1;
853 unsigned int vec_disp8
:1;
855 unsigned int unused
:(OTNumOfBits
- OTUnused
);
858 unsigned int array
[OTNumOfUints
];
861 typedef struct insn_template
863 /* instruction name sans width suffix ("mov" for movl insns) */
866 /* how many operands */
867 unsigned int operands
;
869 /* base_opcode is the fundamental opcode byte without optional
871 unsigned int base_opcode
;
872 #define Opcode_D 0x2 /* Direction bit:
873 set if Reg --> Regmem;
874 unset if Regmem --> Reg. */
875 #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
876 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
878 /* extension_opcode is the 3 bit extension for group <n> insns.
879 This field is also used to store the 8-bit opcode suffix for the
880 AMD 3DNow! instructions.
881 If this template has no extension opcode (the usual case) use None
883 unsigned int extension_opcode
;
884 #define None 0xffff /* If no extension_opcode is possible. */
887 unsigned char opcode_length
;
889 /* cpu feature flags */
890 i386_cpu_flags cpu_flags
;
892 /* the bits in opcode_modifier are used to generate the final opcode from
893 the base_opcode. These bits also are used to detect alternate forms of
894 the same instruction */
895 i386_opcode_modifier opcode_modifier
;
897 /* operand_types[i] describes the type of operand i. This is made
898 by OR'ing together all of the possible type masks. (e.g.
899 'operand_types[i] = Reg|Imm' specifies that operand i can be
900 either a register or an immediate operand. */
901 i386_operand_type operand_types
[MAX_OPERANDS
];
905 extern const insn_template i386_optab
[];
907 /* these are for register name --> number & type hash lookup */
911 i386_operand_type reg_type
;
912 unsigned char reg_flags
;
913 #define RegRex 0x1 /* Extended register. */
914 #define RegRex64 0x2 /* Extended 8 bit register. */
915 #define RegVRex 0x4 /* Extended vector register. */
916 unsigned char reg_num
;
917 #define RegRip ((unsigned char ) ~0)
918 #define RegEip (RegRip - 1)
919 /* EIZ and RIZ are fake index registers. */
920 #define RegEiz (RegEip - 1)
921 #define RegRiz (RegEiz - 1)
922 /* FLAT is a fake segment register (Intel mode). */
923 #define RegFlat ((unsigned char) ~0)
924 signed char dw2_regnum
[2];
925 #define Dw2Inval (-1)
929 /* Entries in i386_regtab. */
932 #define REGNAM_EAX 41
934 extern const reg_entry i386_regtab
[];
935 extern const unsigned int i386_regtab_size
;
940 unsigned int seg_prefix
;
944 extern const seg_entry cs
;
945 extern const seg_entry ds
;
946 extern const seg_entry ss
;
947 extern const seg_entry es
;
948 extern const seg_entry fs
;
949 extern const seg_entry gs
;