1 /* Declarations for Intel 80386 opcode table
2 Copyright (C) 2007-2014 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 #include "opcode/i386.h"
30 /* Position of cpu flags bitfiled. */
34 /* i186 or better required */
36 /* i286 or better required */
38 /* i386 or better required */
40 /* i486 or better required */
42 /* i585 or better required */
44 /* i686 or better required */
46 /* CLFLUSH Instruction support required */
48 /* NOP Instruction support required */
50 /* SYSCALL Instructions support required */
52 /* Floating point support required */
54 /* i287 support required */
56 /* i387 support required */
58 /* i686 and floating point support required */
60 /* SSE3 and floating point support required */
62 /* MMX support required */
64 /* SSE support required */
66 /* SSE2 support required */
68 /* 3dnow! support required */
70 /* 3dnow! Extensions support required */
72 /* SSE3 support required */
74 /* VIA PadLock required */
76 /* AMD Secure Virtual Machine Ext-s required */
78 /* VMX Instructions required */
80 /* SMX Instructions required */
82 /* SSSE3 support required */
84 /* SSE4a support required */
86 /* ABM New Instructions required */
88 /* SSE4.1 support required */
90 /* SSE4.2 support required */
92 /* AVX support required */
94 /* AVX2 support required */
96 /* Intel AVX-512 Foundation Instructions support required */
98 /* Intel AVX-512 Conflict Detection Instructions support required */
100 /* Intel AVX-512 Exponential and Reciprocal Instructions support
103 /* Intel AVX-512 Prefetch Instructions support required */
105 /* Intel L1OM support required */
107 /* Intel K1OM support required */
109 /* Xsave/xrstor New Instructions support required */
111 /* Xsaveopt New Instructions support required */
113 /* AES support required */
115 /* PCLMUL support required */
117 /* FMA support required */
119 /* FMA4 support required */
121 /* XOP support required */
123 /* LWP support required */
125 /* BMI support required */
127 /* TBM support required */
129 /* MOVBE Instruction support required */
131 /* CMPXCHG16B instruction support required. */
133 /* EPT Instructions required */
135 /* RDTSCP Instruction support required */
137 /* FSGSBASE Instructions required */
139 /* RDRND Instructions required */
141 /* F16C Instructions required */
143 /* Intel BMI2 support required */
145 /* LZCNT support required */
147 /* HLE support required */
149 /* RTM support required */
151 /* INVPCID Instructions required */
153 /* VMFUNC Instruction required */
155 /* Intel MPX Instructions required */
157 /* 64bit support available, used by -march= in assembler. */
159 /* RDRSEED instruction required. */
161 /* Multi-presisionn add-carry instructions are required. */
163 /* Supports prefetchw and prefetch instructions. */
165 /* SMAP instructions required. */
167 /* SHA instructions required. */
169 /* VREX support required */
171 /* CLFLUSHOPT instruction required */
173 /* XSAVES/XRSTORS instruction required */
175 /* XSAVEC instruction required */
177 /* PREFETCHWT1 instruction required */
179 /* SE1 instruction required */
181 /* 64bit support required */
183 /* Not supported in the 64bit mode */
185 /* The last bitfield in i386_cpu_flags. */
189 #define CpuNumOfUints \
190 (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
191 #define CpuNumOfBits \
192 (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
194 /* If you get a compiler error for zero width of the unused field,
196 #define CpuUnused (CpuMax + 1)
198 /* We can check if an instruction is available with array instead
200 typedef union i386_cpu_flags
204 unsigned int cpui186
:1;
205 unsigned int cpui286
:1;
206 unsigned int cpui386
:1;
207 unsigned int cpui486
:1;
208 unsigned int cpui586
:1;
209 unsigned int cpui686
:1;
210 unsigned int cpuclflush
:1;
211 unsigned int cpunop
:1;
212 unsigned int cpusyscall
:1;
213 unsigned int cpu8087
:1;
214 unsigned int cpu287
:1;
215 unsigned int cpu387
:1;
216 unsigned int cpu687
:1;
217 unsigned int cpufisttp
:1;
218 unsigned int cpummx
:1;
219 unsigned int cpusse
:1;
220 unsigned int cpusse2
:1;
221 unsigned int cpua3dnow
:1;
222 unsigned int cpua3dnowa
:1;
223 unsigned int cpusse3
:1;
224 unsigned int cpupadlock
:1;
225 unsigned int cpusvme
:1;
226 unsigned int cpuvmx
:1;
227 unsigned int cpusmx
:1;
228 unsigned int cpussse3
:1;
229 unsigned int cpusse4a
:1;
230 unsigned int cpuabm
:1;
231 unsigned int cpusse4_1
:1;
232 unsigned int cpusse4_2
:1;
233 unsigned int cpuavx
:1;
234 unsigned int cpuavx2
:1;
235 unsigned int cpuavx512f
:1;
236 unsigned int cpuavx512cd
:1;
237 unsigned int cpuavx512er
:1;
238 unsigned int cpuavx512pf
:1;
239 unsigned int cpul1om
:1;
240 unsigned int cpuk1om
:1;
241 unsigned int cpuxsave
:1;
242 unsigned int cpuxsaveopt
:1;
243 unsigned int cpuaes
:1;
244 unsigned int cpupclmul
:1;
245 unsigned int cpufma
:1;
246 unsigned int cpufma4
:1;
247 unsigned int cpuxop
:1;
248 unsigned int cpulwp
:1;
249 unsigned int cpubmi
:1;
250 unsigned int cputbm
:1;
251 unsigned int cpumovbe
:1;
252 unsigned int cpucx16
:1;
253 unsigned int cpuept
:1;
254 unsigned int cpurdtscp
:1;
255 unsigned int cpufsgsbase
:1;
256 unsigned int cpurdrnd
:1;
257 unsigned int cpuf16c
:1;
258 unsigned int cpubmi2
:1;
259 unsigned int cpulzcnt
:1;
260 unsigned int cpuhle
:1;
261 unsigned int cpurtm
:1;
262 unsigned int cpuinvpcid
:1;
263 unsigned int cpuvmfunc
:1;
264 unsigned int cpumpx
:1;
265 unsigned int cpulm
:1;
266 unsigned int cpurdseed
:1;
267 unsigned int cpuadx
:1;
268 unsigned int cpuprfchw
:1;
269 unsigned int cpusmap
:1;
270 unsigned int cpusha
:1;
271 unsigned int cpuvrex
:1;
272 unsigned int cpuclflushopt
:1;
273 unsigned int cpuxsaves
:1;
274 unsigned int cpuxsavec
:1;
275 unsigned int cpuprefetchwt1
:1;
276 unsigned int cpuse1
:1;
277 unsigned int cpu64
:1;
278 unsigned int cpuno64
:1;
280 unsigned int unused
:(CpuNumOfBits
- CpuUnused
);
283 unsigned int array
[CpuNumOfUints
];
286 /* Position of opcode_modifier bits. */
290 /* has direction bit. */
292 /* set if operands can be words or dwords encoded the canonical way */
294 /* Skip the current insn and use the next insn in i386-opc.tbl to swap
295 operand in encoding. */
297 /* insn has a modrm byte. */
299 /* register is in low 3 bits of opcode */
301 /* special case for jump insns. */
307 /* special case for intersegment leaps/calls */
309 /* FP insn memory format bit, sized by 0x4 */
311 /* src/dest swap for floats. */
313 /* has float insn direction bit. */
315 /* needs size prefix if in 32-bit mode */
317 /* needs size prefix if in 16-bit mode */
319 /* needs size prefix if in 64-bit mode */
321 /* check register size. */
323 /* instruction ignores operand size prefix and in Intel mode ignores
324 mnemonic size suffix check. */
326 /* default insn size depends on mode */
328 /* b suffix on instruction illegal */
330 /* w suffix on instruction illegal */
332 /* l suffix on instruction illegal */
334 /* s suffix on instruction illegal */
336 /* q suffix on instruction illegal */
338 /* long double suffix on instruction illegal */
340 /* instruction needs FWAIT */
342 /* quick test for string instructions */
344 /* quick test if branch instruction is MPX supported */
346 /* quick test for lockable instructions */
348 /* fake an extra reg operand for clr, imul and special register
349 processing for some instructions. */
351 /* The first operand must be xmm0 */
353 /* An implicit xmm0 as the first operand */
355 /* The HLE prefix is OK:
356 1. With a LOCK prefix.
357 2. With or without a LOCK prefix.
358 3. With a RELEASE (0xf3) prefix.
360 #define HLEPrefixNone 0
361 #define HLEPrefixLock 1
362 #define HLEPrefixAny 2
363 #define HLEPrefixRelease 3
365 /* An instruction on which a "rep" prefix is acceptable. */
367 /* Convert to DWORD */
369 /* Convert to QWORD */
371 /* Address prefix changes operand 0 */
373 /* opcode is a prefix */
375 /* instruction has extension in 8 bit imm */
377 /* instruction don't need Rex64 prefix. */
379 /* instruction require Rex64 prefix. */
381 /* deprecated fp insn, gets a warning */
383 /* insn has VEX prefix:
384 1: 128bit VEX prefix.
385 2: 256bit VEX prefix.
386 3: Scalar VEX prefix.
392 /* How to encode VEX.vvvv:
393 0: VEX.vvvv must be 1111b.
394 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where
395 the content of source registers will be preserved.
396 VEX.DDS. The second register operand is encoded in VEX.vvvv
397 where the content of first source register will be overwritten
399 VEX.NDD2. The second destination register operand is encoded in
400 VEX.vvvv for instructions with 2 destination register operands.
401 For assembler, there are no difference between VEX.NDS, VEX.DDS
403 2. VEX.NDD. Register destination is encoded in VEX.vvvv for
404 instructions with 1 destination register operand.
405 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one
406 of the operands can access a memory location.
412 /* How the VEX.W bit is used:
413 0: Set by the REX.W bit.
414 1: VEX.W0. Should always be 0.
415 2: VEX.W1. Should always be 1.
420 /* VEX opcode prefix:
421 0: VEX 0x0F opcode prefix.
422 1: VEX 0x0F38 opcode prefix.
423 2: VEX 0x0F3A opcode prefix
424 3: XOP 0x08 opcode prefix.
425 4: XOP 0x09 opcode prefix
426 5: XOP 0x0A opcode prefix.
435 /* number of VEX source operands:
436 0: <= 2 source operands.
437 1: 2 XOP source operands.
438 2: 3 source operands.
440 #define XOP2SOURCES 1
441 #define VEX3SOURCES 2
443 /* instruction has VEX 8 bit imm */
445 /* Instruction with vector SIB byte:
446 1: 128bit vector register.
447 2: 256bit vector register.
448 3: 512bit vector register.
454 /* SSE to AVX support required */
456 /* No AVX equivalent */
459 /* insn has EVEX prefix:
460 1: 512bit EVEX prefix.
461 2: 128bit EVEX prefix.
462 3: 256bit EVEX prefix.
463 4: Length-ignored (LIG) EVEX prefix.
471 /* AVX512 masking support:
474 3: Both zeroing and merging masking.
476 #define ZEROING_MASKING 1
477 #define MERGING_MASKING 2
478 #define BOTH_MASKING 3
481 /* Input element size of vector insn:
492 #define NO_BROADCAST 0
493 #define BROADCAST_1TO16 1
494 #define BROADCAST_1TO8 2
497 /* Static rounding control is supported. */
500 /* Supress All Exceptions is supported. */
503 /* Copressed Disp8*N attribute. */
506 /* Default mask isn't allowed. */
509 /* Compatible with old (<= 2.8.1) versions of gcc */
517 /* The last bitfield in i386_opcode_modifier. */
521 typedef struct i386_opcode_modifier
526 unsigned int modrm
:1;
527 unsigned int shortform
:1;
529 unsigned int jumpdword
:1;
530 unsigned int jumpbyte
:1;
531 unsigned int jumpintersegment
:1;
532 unsigned int floatmf
:1;
533 unsigned int floatr
:1;
534 unsigned int floatd
:1;
535 unsigned int size16
:1;
536 unsigned int size32
:1;
537 unsigned int size64
:1;
538 unsigned int checkregsize
:1;
539 unsigned int ignoresize
:1;
540 unsigned int defaultsize
:1;
541 unsigned int no_bsuf
:1;
542 unsigned int no_wsuf
:1;
543 unsigned int no_lsuf
:1;
544 unsigned int no_ssuf
:1;
545 unsigned int no_qsuf
:1;
546 unsigned int no_ldsuf
:1;
547 unsigned int fwait
:1;
548 unsigned int isstring
:1;
549 unsigned int bndprefixok
:1;
550 unsigned int islockable
:1;
551 unsigned int regkludge
:1;
552 unsigned int firstxmm0
:1;
553 unsigned int implicit1stxmm0
:1;
554 unsigned int hleprefixok
:2;
555 unsigned int repprefixok
:1;
556 unsigned int todword
:1;
557 unsigned int toqword
:1;
558 unsigned int addrprefixop0
:1;
559 unsigned int isprefix
:1;
560 unsigned int immext
:1;
561 unsigned int norex64
:1;
562 unsigned int rex64
:1;
565 unsigned int vexvvvv
:2;
567 unsigned int vexopcode
:3;
568 unsigned int vexsources
:2;
569 unsigned int veximmext
:1;
570 unsigned int vecsib
:2;
571 unsigned int sse2avx
:1;
572 unsigned int noavx
:1;
574 unsigned int masking
:2;
575 unsigned int vecesize
:1;
576 unsigned int broadcast
:3;
577 unsigned int staticrounding
:1;
579 unsigned int disp8memshift
:3;
580 unsigned int nodefmask
:1;
581 unsigned int oldgcc
:1;
582 unsigned int attmnemonic
:1;
583 unsigned int attsyntax
:1;
584 unsigned int intelsyntax
:1;
585 } i386_opcode_modifier
;
587 /* Position of operand_type bits. */
599 /* Floating pointer stack register */
607 /* AVX512 registers */
609 /* Vector Mask registers */
611 /* Control register */
617 /* 2 bit segment register */
619 /* 3 bit segment register */
621 /* 1 bit immediate */
623 /* 8 bit immediate */
625 /* 8 bit immediate sign extended */
627 /* 16 bit immediate */
629 /* 32 bit immediate */
631 /* 32 bit immediate sign extended */
633 /* 64 bit immediate */
635 /* 8bit/16bit/32bit displacements are used in different ways,
636 depending on the instruction. For jumps, they specify the
637 size of the PC relative displacement, for instructions with
638 memory operand, they specify the size of the offset relative
639 to the base register, and for instructions with memory offset
640 such as `mov 1234,%al' they specify the size of the offset
641 relative to the segment base. */
642 /* 8 bit displacement */
644 /* 16 bit displacement */
646 /* 32 bit displacement */
648 /* 32 bit signed displacement */
650 /* 64 bit displacement */
652 /* Accumulator %al/%ax/%eax/%rax */
654 /* Floating pointer top stack register %st(0) */
656 /* Register which can be used for base or index in memory operand. */
658 /* Register to hold in/out port addr = dx */
660 /* Register to hold shift count = cl */
662 /* Absolute address for jump. */
664 /* String insn operand with fixed es segment */
666 /* RegMem is for instructions with a modrm byte where the register
667 destination operand should be encoded in the mod and regmem fields.
668 Normally, it will be encoded in the reg field. We add a RegMem
669 flag to the destination register operand to indicate that it should
670 be encoded in the regmem field. */
676 /* WORD memory. 2 byte */
678 /* DWORD memory. 4 byte */
680 /* FWORD memory. 6 byte */
682 /* QWORD memory. 8 byte */
684 /* TBYTE memory. 10 byte */
686 /* XMMWORD memory. */
688 /* YMMWORD memory. */
690 /* ZMMWORD memory. */
692 /* Unspecified memory size. */
694 /* Any memory size. */
697 /* Vector 4 bit immediate. */
700 /* Bound register. */
703 /* Vector 8bit displacement */
706 /* The last bitfield in i386_operand_type. */
710 #define OTNumOfUints \
711 (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
712 #define OTNumOfBits \
713 (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
715 /* If you get a compiler error for zero width of the unused field,
717 #define OTUnused (OTMax + 1)
719 typedef union i386_operand_type
724 unsigned int reg16
:1;
725 unsigned int reg32
:1;
726 unsigned int reg64
:1;
727 unsigned int floatreg
:1;
728 unsigned int regmmx
:1;
729 unsigned int regxmm
:1;
730 unsigned int regymm
:1;
731 unsigned int regzmm
:1;
732 unsigned int regmask
:1;
733 unsigned int control
:1;
734 unsigned int debug
:1;
736 unsigned int sreg2
:1;
737 unsigned int sreg3
:1;
740 unsigned int imm8s
:1;
741 unsigned int imm16
:1;
742 unsigned int imm32
:1;
743 unsigned int imm32s
:1;
744 unsigned int imm64
:1;
745 unsigned int disp8
:1;
746 unsigned int disp16
:1;
747 unsigned int disp32
:1;
748 unsigned int disp32s
:1;
749 unsigned int disp64
:1;
751 unsigned int floatacc
:1;
752 unsigned int baseindex
:1;
753 unsigned int inoutportreg
:1;
754 unsigned int shiftcount
:1;
755 unsigned int jumpabsolute
:1;
756 unsigned int esseg
:1;
757 unsigned int regmem
:1;
761 unsigned int dword
:1;
762 unsigned int fword
:1;
763 unsigned int qword
:1;
764 unsigned int tbyte
:1;
765 unsigned int xmmword
:1;
766 unsigned int ymmword
:1;
767 unsigned int zmmword
:1;
768 unsigned int unspecified
:1;
769 unsigned int anysize
:1;
770 unsigned int vec_imm4
:1;
771 unsigned int regbnd
:1;
772 unsigned int vec_disp8
:1;
774 unsigned int unused
:(OTNumOfBits
- OTUnused
);
777 unsigned int array
[OTNumOfUints
];
780 typedef struct insn_template
782 /* instruction name sans width suffix ("mov" for movl insns) */
785 /* how many operands */
786 unsigned int operands
;
788 /* base_opcode is the fundamental opcode byte without optional
790 unsigned int base_opcode
;
791 #define Opcode_D 0x2 /* Direction bit:
792 set if Reg --> Regmem;
793 unset if Regmem --> Reg. */
794 #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
795 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
797 /* extension_opcode is the 3 bit extension for group <n> insns.
798 This field is also used to store the 8-bit opcode suffix for the
799 AMD 3DNow! instructions.
800 If this template has no extension opcode (the usual case) use None
802 unsigned int extension_opcode
;
803 #define None 0xffff /* If no extension_opcode is possible. */
806 unsigned char opcode_length
;
808 /* cpu feature flags */
809 i386_cpu_flags cpu_flags
;
811 /* the bits in opcode_modifier are used to generate the final opcode from
812 the base_opcode. These bits also are used to detect alternate forms of
813 the same instruction */
814 i386_opcode_modifier opcode_modifier
;
816 /* operand_types[i] describes the type of operand i. This is made
817 by OR'ing together all of the possible type masks. (e.g.
818 'operand_types[i] = Reg|Imm' specifies that operand i can be
819 either a register or an immediate operand. */
820 i386_operand_type operand_types
[MAX_OPERANDS
];
824 extern const insn_template i386_optab
[];
826 /* these are for register name --> number & type hash lookup */
830 i386_operand_type reg_type
;
831 unsigned char reg_flags
;
832 #define RegRex 0x1 /* Extended register. */
833 #define RegRex64 0x2 /* Extended 8 bit register. */
834 #define RegVRex 0x4 /* Extended vector register. */
835 unsigned char reg_num
;
836 #define RegRip ((unsigned char ) ~0)
837 #define RegEip (RegRip - 1)
838 /* EIZ and RIZ are fake index registers. */
839 #define RegEiz (RegEip - 1)
840 #define RegRiz (RegEiz - 1)
841 /* FLAT is a fake segment register (Intel mode). */
842 #define RegFlat ((unsigned char) ~0)
843 signed char dw2_regnum
[2];
844 #define Dw2Inval (-1)
848 /* Entries in i386_regtab. */
851 #define REGNAM_EAX 41
853 extern const reg_entry i386_regtab
[];
854 extern const unsigned int i386_regtab_size
;
859 unsigned int seg_prefix
;
863 extern const seg_entry cs
;
864 extern const seg_entry ds
;
865 extern const seg_entry ss
;
866 extern const seg_entry es
;
867 extern const seg_entry fs
;
868 extern const seg_entry gs
;