1 /* Declarations for Intel 80386 opcode table
2 Copyright (C) 2007-2015 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 #include "opcode/i386.h"
30 /* Position of cpu flags bitfiled. */
34 /* i186 or better required */
36 /* i286 or better required */
38 /* i386 or better required */
40 /* i486 or better required */
42 /* i585 or better required */
44 /* i686 or better required */
46 /* CLFLUSH Instruction support required */
48 /* NOP Instruction support required */
50 /* SYSCALL Instructions support required */
52 /* Floating point support required */
54 /* i287 support required */
56 /* i387 support required */
58 /* i686 and floating point support required */
60 /* SSE3 and floating point support required */
62 /* MMX support required */
64 /* SSE support required */
66 /* SSE2 support required */
68 /* 3dnow! support required */
70 /* 3dnow! Extensions support required */
72 /* SSE3 support required */
74 /* VIA PadLock required */
76 /* AMD Secure Virtual Machine Ext-s required */
78 /* VMX Instructions required */
80 /* SMX Instructions required */
82 /* SSSE3 support required */
84 /* SSE4a support required */
86 /* ABM New Instructions required */
88 /* SSE4.1 support required */
90 /* SSE4.2 support required */
92 /* AVX support required */
94 /* AVX2 support required */
96 /* Intel AVX-512 Foundation Instructions support required */
98 /* Intel AVX-512 Conflict Detection Instructions support required */
100 /* Intel AVX-512 Exponential and Reciprocal Instructions support
103 /* Intel AVX-512 Prefetch Instructions support required */
105 /* Intel AVX-512 VL Instructions support required. */
107 /* Intel AVX-512 DQ Instructions support required. */
109 /* Intel AVX-512 BW Instructions support required. */
111 /* Intel L1OM support required */
113 /* Intel K1OM support required */
115 /* Intel IAMCU support required */
117 /* Xsave/xrstor New Instructions support required */
119 /* Xsaveopt New Instructions support required */
121 /* AES support required */
123 /* PCLMUL support required */
125 /* FMA support required */
127 /* FMA4 support required */
129 /* XOP support required */
131 /* LWP support required */
133 /* BMI support required */
135 /* TBM support required */
137 /* MOVBE Instruction support required */
139 /* CMPXCHG16B instruction support required. */
141 /* EPT Instructions required */
143 /* RDTSCP Instruction support required */
145 /* FSGSBASE Instructions required */
147 /* RDRND Instructions required */
149 /* F16C Instructions required */
151 /* Intel BMI2 support required */
153 /* LZCNT support required */
155 /* HLE support required */
157 /* RTM support required */
159 /* INVPCID Instructions required */
161 /* VMFUNC Instruction required */
163 /* Intel MPX Instructions required */
165 /* 64bit support available, used by -march= in assembler. */
167 /* RDRSEED instruction required. */
169 /* Multi-presisionn add-carry instructions are required. */
171 /* Supports prefetchw and prefetch instructions. */
173 /* SMAP instructions required. */
175 /* SHA instructions required. */
177 /* VREX support required */
179 /* CLFLUSHOPT instruction required */
181 /* XSAVES/XRSTORS instruction required */
183 /* XSAVEC instruction required */
185 /* PREFETCHWT1 instruction required */
187 /* SE1 instruction required */
189 /* CLWB instruction required */
191 /* PCOMMIT instruction required */
193 /* Intel AVX-512 IFMA Instructions support required. */
195 /* Intel AVX-512 VBMI Instructions support required. */
197 /* Clzero instruction required */
199 /* 64bit support required */
201 /* Not supported in the 64bit mode */
203 /* The last bitfield in i386_cpu_flags. */
207 #define CpuNumOfUints \
208 (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
209 #define CpuNumOfBits \
210 (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
212 /* If you get a compiler error for zero width of the unused field,
214 #define CpuUnused (CpuMax + 1)
216 /* We can check if an instruction is available with array instead
218 typedef union i386_cpu_flags
222 unsigned int cpui186
:1;
223 unsigned int cpui286
:1;
224 unsigned int cpui386
:1;
225 unsigned int cpui486
:1;
226 unsigned int cpui586
:1;
227 unsigned int cpui686
:1;
228 unsigned int cpuclflush
:1;
229 unsigned int cpunop
:1;
230 unsigned int cpusyscall
:1;
231 unsigned int cpu8087
:1;
232 unsigned int cpu287
:1;
233 unsigned int cpu387
:1;
234 unsigned int cpu687
:1;
235 unsigned int cpufisttp
:1;
236 unsigned int cpummx
:1;
237 unsigned int cpusse
:1;
238 unsigned int cpusse2
:1;
239 unsigned int cpua3dnow
:1;
240 unsigned int cpua3dnowa
:1;
241 unsigned int cpusse3
:1;
242 unsigned int cpupadlock
:1;
243 unsigned int cpusvme
:1;
244 unsigned int cpuvmx
:1;
245 unsigned int cpusmx
:1;
246 unsigned int cpussse3
:1;
247 unsigned int cpusse4a
:1;
248 unsigned int cpuabm
:1;
249 unsigned int cpusse4_1
:1;
250 unsigned int cpusse4_2
:1;
251 unsigned int cpuavx
:1;
252 unsigned int cpuavx2
:1;
253 unsigned int cpuavx512f
:1;
254 unsigned int cpuavx512cd
:1;
255 unsigned int cpuavx512er
:1;
256 unsigned int cpuavx512pf
:1;
257 unsigned int cpuavx512vl
:1;
258 unsigned int cpuavx512dq
:1;
259 unsigned int cpuavx512bw
:1;
260 unsigned int cpul1om
:1;
261 unsigned int cpuk1om
:1;
262 unsigned int cpuiamcu
:1;
263 unsigned int cpuxsave
:1;
264 unsigned int cpuxsaveopt
:1;
265 unsigned int cpuaes
:1;
266 unsigned int cpupclmul
:1;
267 unsigned int cpufma
:1;
268 unsigned int cpufma4
:1;
269 unsigned int cpuxop
:1;
270 unsigned int cpulwp
:1;
271 unsigned int cpubmi
:1;
272 unsigned int cputbm
:1;
273 unsigned int cpumovbe
:1;
274 unsigned int cpucx16
:1;
275 unsigned int cpuept
:1;
276 unsigned int cpurdtscp
:1;
277 unsigned int cpufsgsbase
:1;
278 unsigned int cpurdrnd
:1;
279 unsigned int cpuf16c
:1;
280 unsigned int cpubmi2
:1;
281 unsigned int cpulzcnt
:1;
282 unsigned int cpuhle
:1;
283 unsigned int cpurtm
:1;
284 unsigned int cpuinvpcid
:1;
285 unsigned int cpuvmfunc
:1;
286 unsigned int cpumpx
:1;
287 unsigned int cpulm
:1;
288 unsigned int cpurdseed
:1;
289 unsigned int cpuadx
:1;
290 unsigned int cpuprfchw
:1;
291 unsigned int cpusmap
:1;
292 unsigned int cpusha
:1;
293 unsigned int cpuvrex
:1;
294 unsigned int cpuclflushopt
:1;
295 unsigned int cpuxsaves
:1;
296 unsigned int cpuxsavec
:1;
297 unsigned int cpuprefetchwt1
:1;
298 unsigned int cpuse1
:1;
299 unsigned int cpuclwb
:1;
300 unsigned int cpupcommit
:1;
301 unsigned int cpuavx512ifma
:1;
302 unsigned int cpuavx512vbmi
:1;
303 unsigned int cpuclzero
:1;
304 unsigned int cpu64
:1;
305 unsigned int cpuno64
:1;
307 unsigned int unused
:(CpuNumOfBits
- CpuUnused
);
310 unsigned int array
[CpuNumOfUints
];
313 /* Position of opcode_modifier bits. */
317 /* has direction bit. */
319 /* set if operands can be words or dwords encoded the canonical way */
321 /* Skip the current insn and use the next insn in i386-opc.tbl to swap
322 operand in encoding. */
324 /* insn has a modrm byte. */
326 /* register is in low 3 bits of opcode */
328 /* special case for jump insns. */
334 /* special case for intersegment leaps/calls */
336 /* FP insn memory format bit, sized by 0x4 */
338 /* src/dest swap for floats. */
340 /* has float insn direction bit. */
342 /* needs size prefix if in 32-bit mode */
344 /* needs size prefix if in 16-bit mode */
346 /* needs size prefix if in 64-bit mode */
348 /* check register size. */
350 /* instruction ignores operand size prefix and in Intel mode ignores
351 mnemonic size suffix check. */
353 /* default insn size depends on mode */
355 /* b suffix on instruction illegal */
357 /* w suffix on instruction illegal */
359 /* l suffix on instruction illegal */
361 /* s suffix on instruction illegal */
363 /* q suffix on instruction illegal */
365 /* long double suffix on instruction illegal */
367 /* instruction needs FWAIT */
369 /* quick test for string instructions */
371 /* quick test if branch instruction is MPX supported */
373 /* quick test for lockable instructions */
375 /* fake an extra reg operand for clr, imul and special register
376 processing for some instructions. */
378 /* The first operand must be xmm0 */
380 /* An implicit xmm0 as the first operand */
382 /* The HLE prefix is OK:
383 1. With a LOCK prefix.
384 2. With or without a LOCK prefix.
385 3. With a RELEASE (0xf3) prefix.
387 #define HLEPrefixNone 0
388 #define HLEPrefixLock 1
389 #define HLEPrefixAny 2
390 #define HLEPrefixRelease 3
392 /* An instruction on which a "rep" prefix is acceptable. */
394 /* Convert to DWORD */
396 /* Convert to QWORD */
398 /* Address prefix changes operand 0 */
400 /* opcode is a prefix */
402 /* instruction has extension in 8 bit imm */
404 /* instruction don't need Rex64 prefix. */
406 /* instruction require Rex64 prefix. */
408 /* deprecated fp insn, gets a warning */
410 /* insn has VEX prefix:
411 1: 128bit VEX prefix.
412 2: 256bit VEX prefix.
413 3: Scalar VEX prefix.
419 /* How to encode VEX.vvvv:
420 0: VEX.vvvv must be 1111b.
421 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where
422 the content of source registers will be preserved.
423 VEX.DDS. The second register operand is encoded in VEX.vvvv
424 where the content of first source register will be overwritten
426 VEX.NDD2. The second destination register operand is encoded in
427 VEX.vvvv for instructions with 2 destination register operands.
428 For assembler, there are no difference between VEX.NDS, VEX.DDS
430 2. VEX.NDD. Register destination is encoded in VEX.vvvv for
431 instructions with 1 destination register operand.
432 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one
433 of the operands can access a memory location.
439 /* How the VEX.W bit is used:
440 0: Set by the REX.W bit.
441 1: VEX.W0. Should always be 0.
442 2: VEX.W1. Should always be 1.
447 /* VEX opcode prefix:
448 0: VEX 0x0F opcode prefix.
449 1: VEX 0x0F38 opcode prefix.
450 2: VEX 0x0F3A opcode prefix
451 3: XOP 0x08 opcode prefix.
452 4: XOP 0x09 opcode prefix
453 5: XOP 0x0A opcode prefix.
462 /* number of VEX source operands:
463 0: <= 2 source operands.
464 1: 2 XOP source operands.
465 2: 3 source operands.
467 #define XOP2SOURCES 1
468 #define VEX3SOURCES 2
470 /* instruction has VEX 8 bit imm */
472 /* Instruction with vector SIB byte:
473 1: 128bit vector register.
474 2: 256bit vector register.
475 3: 512bit vector register.
481 /* SSE to AVX support required */
483 /* No AVX equivalent */
486 /* insn has EVEX prefix:
487 1: 512bit EVEX prefix.
488 2: 128bit EVEX prefix.
489 3: 256bit EVEX prefix.
490 4: Length-ignored (LIG) EVEX prefix.
498 /* AVX512 masking support:
501 3: Both zeroing and merging masking.
503 #define ZEROING_MASKING 1
504 #define MERGING_MASKING 2
505 #define BOTH_MASKING 3
508 /* Input element size of vector insn:
519 #define NO_BROADCAST 0
520 #define BROADCAST_1TO16 1
521 #define BROADCAST_1TO8 2
522 #define BROADCAST_1TO4 3
523 #define BROADCAST_1TO2 4
526 /* Static rounding control is supported. */
529 /* Supress All Exceptions is supported. */
532 /* Copressed Disp8*N attribute. */
535 /* Default mask isn't allowed. */
538 /* Compatible with old (<= 2.8.1) versions of gcc */
546 /* The last bitfield in i386_opcode_modifier. */
550 typedef struct i386_opcode_modifier
555 unsigned int modrm
:1;
556 unsigned int shortform
:1;
558 unsigned int jumpdword
:1;
559 unsigned int jumpbyte
:1;
560 unsigned int jumpintersegment
:1;
561 unsigned int floatmf
:1;
562 unsigned int floatr
:1;
563 unsigned int floatd
:1;
564 unsigned int size16
:1;
565 unsigned int size32
:1;
566 unsigned int size64
:1;
567 unsigned int checkregsize
:1;
568 unsigned int ignoresize
:1;
569 unsigned int defaultsize
:1;
570 unsigned int no_bsuf
:1;
571 unsigned int no_wsuf
:1;
572 unsigned int no_lsuf
:1;
573 unsigned int no_ssuf
:1;
574 unsigned int no_qsuf
:1;
575 unsigned int no_ldsuf
:1;
576 unsigned int fwait
:1;
577 unsigned int isstring
:1;
578 unsigned int bndprefixok
:1;
579 unsigned int islockable
:1;
580 unsigned int regkludge
:1;
581 unsigned int firstxmm0
:1;
582 unsigned int implicit1stxmm0
:1;
583 unsigned int hleprefixok
:2;
584 unsigned int repprefixok
:1;
585 unsigned int todword
:1;
586 unsigned int toqword
:1;
587 unsigned int addrprefixop0
:1;
588 unsigned int isprefix
:1;
589 unsigned int immext
:1;
590 unsigned int norex64
:1;
591 unsigned int rex64
:1;
594 unsigned int vexvvvv
:2;
596 unsigned int vexopcode
:3;
597 unsigned int vexsources
:2;
598 unsigned int veximmext
:1;
599 unsigned int vecsib
:2;
600 unsigned int sse2avx
:1;
601 unsigned int noavx
:1;
603 unsigned int masking
:2;
604 unsigned int vecesize
:1;
605 unsigned int broadcast
:3;
606 unsigned int staticrounding
:1;
608 unsigned int disp8memshift
:3;
609 unsigned int nodefmask
:1;
610 unsigned int oldgcc
:1;
611 unsigned int attmnemonic
:1;
612 unsigned int attsyntax
:1;
613 unsigned int intelsyntax
:1;
614 } i386_opcode_modifier
;
616 /* Position of operand_type bits. */
628 /* Floating pointer stack register */
636 /* AVX512 registers */
638 /* Vector Mask registers */
640 /* Control register */
646 /* 2 bit segment register */
648 /* 3 bit segment register */
650 /* 1 bit immediate */
652 /* 8 bit immediate */
654 /* 8 bit immediate sign extended */
656 /* 16 bit immediate */
658 /* 32 bit immediate */
660 /* 32 bit immediate sign extended */
662 /* 64 bit immediate */
664 /* 8bit/16bit/32bit displacements are used in different ways,
665 depending on the instruction. For jumps, they specify the
666 size of the PC relative displacement, for instructions with
667 memory operand, they specify the size of the offset relative
668 to the base register, and for instructions with memory offset
669 such as `mov 1234,%al' they specify the size of the offset
670 relative to the segment base. */
671 /* 8 bit displacement */
673 /* 16 bit displacement */
675 /* 32 bit displacement */
677 /* 32 bit signed displacement */
679 /* 64 bit displacement */
681 /* Accumulator %al/%ax/%eax/%rax */
683 /* Floating pointer top stack register %st(0) */
685 /* Register which can be used for base or index in memory operand. */
687 /* Register to hold in/out port addr = dx */
689 /* Register to hold shift count = cl */
691 /* Absolute address for jump. */
693 /* String insn operand with fixed es segment */
695 /* RegMem is for instructions with a modrm byte where the register
696 destination operand should be encoded in the mod and regmem fields.
697 Normally, it will be encoded in the reg field. We add a RegMem
698 flag to the destination register operand to indicate that it should
699 be encoded in the regmem field. */
705 /* WORD memory. 2 byte */
707 /* DWORD memory. 4 byte */
709 /* FWORD memory. 6 byte */
711 /* QWORD memory. 8 byte */
713 /* TBYTE memory. 10 byte */
715 /* XMMWORD memory. */
717 /* YMMWORD memory. */
719 /* ZMMWORD memory. */
721 /* Unspecified memory size. */
723 /* Any memory size. */
726 /* Vector 4 bit immediate. */
729 /* Bound register. */
732 /* Vector 8bit displacement */
735 /* The last bitfield in i386_operand_type. */
739 #define OTNumOfUints \
740 (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
741 #define OTNumOfBits \
742 (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
744 /* If you get a compiler error for zero width of the unused field,
746 #define OTUnused (OTMax + 1)
748 typedef union i386_operand_type
753 unsigned int reg16
:1;
754 unsigned int reg32
:1;
755 unsigned int reg64
:1;
756 unsigned int floatreg
:1;
757 unsigned int regmmx
:1;
758 unsigned int regxmm
:1;
759 unsigned int regymm
:1;
760 unsigned int regzmm
:1;
761 unsigned int regmask
:1;
762 unsigned int control
:1;
763 unsigned int debug
:1;
765 unsigned int sreg2
:1;
766 unsigned int sreg3
:1;
769 unsigned int imm8s
:1;
770 unsigned int imm16
:1;
771 unsigned int imm32
:1;
772 unsigned int imm32s
:1;
773 unsigned int imm64
:1;
774 unsigned int disp8
:1;
775 unsigned int disp16
:1;
776 unsigned int disp32
:1;
777 unsigned int disp32s
:1;
778 unsigned int disp64
:1;
780 unsigned int floatacc
:1;
781 unsigned int baseindex
:1;
782 unsigned int inoutportreg
:1;
783 unsigned int shiftcount
:1;
784 unsigned int jumpabsolute
:1;
785 unsigned int esseg
:1;
786 unsigned int regmem
:1;
790 unsigned int dword
:1;
791 unsigned int fword
:1;
792 unsigned int qword
:1;
793 unsigned int tbyte
:1;
794 unsigned int xmmword
:1;
795 unsigned int ymmword
:1;
796 unsigned int zmmword
:1;
797 unsigned int unspecified
:1;
798 unsigned int anysize
:1;
799 unsigned int vec_imm4
:1;
800 unsigned int regbnd
:1;
801 unsigned int vec_disp8
:1;
803 unsigned int unused
:(OTNumOfBits
- OTUnused
);
806 unsigned int array
[OTNumOfUints
];
809 typedef struct insn_template
811 /* instruction name sans width suffix ("mov" for movl insns) */
814 /* how many operands */
815 unsigned int operands
;
817 /* base_opcode is the fundamental opcode byte without optional
819 unsigned int base_opcode
;
820 #define Opcode_D 0x2 /* Direction bit:
821 set if Reg --> Regmem;
822 unset if Regmem --> Reg. */
823 #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
824 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
826 /* extension_opcode is the 3 bit extension for group <n> insns.
827 This field is also used to store the 8-bit opcode suffix for the
828 AMD 3DNow! instructions.
829 If this template has no extension opcode (the usual case) use None
831 unsigned int extension_opcode
;
832 #define None 0xffff /* If no extension_opcode is possible. */
835 unsigned char opcode_length
;
837 /* cpu feature flags */
838 i386_cpu_flags cpu_flags
;
840 /* the bits in opcode_modifier are used to generate the final opcode from
841 the base_opcode. These bits also are used to detect alternate forms of
842 the same instruction */
843 i386_opcode_modifier opcode_modifier
;
845 /* operand_types[i] describes the type of operand i. This is made
846 by OR'ing together all of the possible type masks. (e.g.
847 'operand_types[i] = Reg|Imm' specifies that operand i can be
848 either a register or an immediate operand. */
849 i386_operand_type operand_types
[MAX_OPERANDS
];
853 extern const insn_template i386_optab
[];
855 /* these are for register name --> number & type hash lookup */
859 i386_operand_type reg_type
;
860 unsigned char reg_flags
;
861 #define RegRex 0x1 /* Extended register. */
862 #define RegRex64 0x2 /* Extended 8 bit register. */
863 #define RegVRex 0x4 /* Extended vector register. */
864 unsigned char reg_num
;
865 #define RegRip ((unsigned char ) ~0)
866 #define RegEip (RegRip - 1)
867 /* EIZ and RIZ are fake index registers. */
868 #define RegEiz (RegEip - 1)
869 #define RegRiz (RegEiz - 1)
870 /* FLAT is a fake segment register (Intel mode). */
871 #define RegFlat ((unsigned char) ~0)
872 signed char dw2_regnum
[2];
873 #define Dw2Inval (-1)
877 /* Entries in i386_regtab. */
880 #define REGNAM_EAX 41
882 extern const reg_entry i386_regtab
[];
883 extern const unsigned int i386_regtab_size
;
888 unsigned int seg_prefix
;
892 extern const seg_entry cs
;
893 extern const seg_entry ds
;
894 extern const seg_entry ss
;
895 extern const seg_entry es
;
896 extern const seg_entry fs
;
897 extern const seg_entry gs
;