opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright 2007, 2008, 2009, 2010, 2012
   3    Free Software Foundation, Inc.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  20    02110-1301, USA.  */
  21
  22 #include "opcode/i386.h"
  23 #ifdef HAVE_LIMITS_H
  24 #include <limits.h>
  25 #endif
  26
  27 #ifndef CHAR_BIT
  28 #define CHAR_BIT 8
  29 #endif
  30
  31 /* Position of cpu flags bitfiled.  */
  32
  33 enum
  34 {
  35   /* i186 or better required */
  36   Cpu186 = 0,
  37   /* i286 or better required */
  38   Cpu286,
  39   /* i386 or better required */
  40   Cpu386,
  41   /* i486 or better required */
  42   Cpu486,
  43   /* i585 or better required */
  44   Cpu586,
  45   /* i686 or better required */
  46   Cpu686,
  47   /* CLFLUSH Instruction support required */
  48   CpuClflush,
  49   /* NOP Instruction support required */
  50   CpuNop,
  51   /* SYSCALL Instructions support required */
  52   CpuSYSCALL,
  53   /* Floating point support required */
  54   Cpu8087,
  55   /* i287 support required */
  56   Cpu287,
  57   /* i387 support required */
  58   Cpu387,
  59   /* i686 and floating point support required */
  60   Cpu687,
  61   /* SSE3 and floating point support required */
  62   CpuFISTTP,
  63   /* MMX support required */
  64   CpuMMX,
  65   /* SSE support required */
  66   CpuSSE,
  67   /* SSE2 support required */
  68   CpuSSE2,
  69   /* 3dnow! support required */
  70   Cpu3dnow,
  71   /* 3dnow! Extensions support required */
  72   Cpu3dnowA,
  73   /* SSE3 support required */
  74   CpuSSE3,
  75   /* VIA PadLock required */
  76   CpuPadLock,
  77   /* AMD Secure Virtual Machine Ext-s required */
  78   CpuSVME,
  79   /* VMX Instructions required */
  80   CpuVMX,
  81   /* SMX Instructions required */
  82   CpuSMX,
  83   /* SSSE3 support required */
  84   CpuSSSE3,
  85   /* SSE4a support required */
  86   CpuSSE4a,
  87   /* ABM New Instructions required */
  88   CpuABM,
  89   /* SSE4.1 support required */
  90   CpuSSE4_1,
  91   /* SSE4.2 support required */
  92   CpuSSE4_2,
  93   /* AVX support required */
  94   CpuAVX,
  95   /* AVX2 support required */
  96   CpuAVX2,
  97   /* Intel AVX-512 Foundation Instructions support required */
  98   CpuAVX512F,
  99   /* Intel AVX-512 Conflict Detection Instructions support required */
 100   CpuAVX512CD,
 101   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 102      required */
 103   CpuAVX512ER,
 104   /* Intel AVX-512 Prefetch Instructions support required */
 105   CpuAVX512PF,
 106   /* Intel L1OM support required */
 107   CpuL1OM,
 108   /* Intel K1OM support required */
 109   CpuK1OM,
 110   /* Xsave/xrstor New Instructions support required */
 111   CpuXsave,
 112   /* Xsaveopt New Instructions support required */
 113   CpuXsaveopt,
 114   /* AES support required */
 115   CpuAES,
 116   /* PCLMUL support required */
 117   CpuPCLMUL,
 118   /* FMA support required */
 119   CpuFMA,
 120   /* FMA4 support required */
 121   CpuFMA4,
 122   /* XOP support required */
 123   CpuXOP,
 124   /* LWP support required */
 125   CpuLWP,
 126   /* BMI support required */
 127   CpuBMI,
 128   /* TBM support required */
 129   CpuTBM,
 130   /* MOVBE Instruction support required */
 131   CpuMovbe,
 132   /* CMPXCHG16B instruction support required.  */
 133   CpuCX16,
 134   /* EPT Instructions required */
 135   CpuEPT,
 136   /* RDTSCP Instruction support required */
 137   CpuRdtscp,
 138   /* FSGSBASE Instructions required */
 139   CpuFSGSBase,
 140   /* RDRND Instructions required */
 141   CpuRdRnd,
 142   /* F16C Instructions required */
 143   CpuF16C,
 144   /* Intel BMI2 support required */
 145   CpuBMI2,
 146   /* LZCNT support required */
 147   CpuLZCNT,
 148   /* HLE support required */
 149   CpuHLE,
 150   /* RTM support required */
 151   CpuRTM,
 152   /* INVPCID Instructions required */
 153   CpuINVPCID,
 154   /* VMFUNC Instruction required */
 155   CpuVMFUNC,
 156   /* Intel MPX Instructions required  */
 157   CpuMPX,
 158   /* 64bit support available, used by -march= in assembler.  */
 159   CpuLM,
 160   /* RDRSEED instruction required.  */
 161   CpuRDSEED,
 162   /* Multi-presisionn add-carry instructions are required.  */
 163   CpuADX,
 164   /* Supports prefetchw and prefetch instructions.  */
 165   CpuPRFCHW,
 166   /* SMAP instructions required.  */
 167   CpuSMAP,
 168   /* SHA instructions required.  */
 169   CpuSHA,
 170   /* VREX support required  */
 171   CpuVREX,
 172   /* 64bit support required  */
 173   Cpu64,
 174   /* Not supported in the 64bit mode  */
 175   CpuNo64,
 176   /* The last bitfield in i386_cpu_flags.  */
 177   CpuMax = CpuNo64
 178 };
 179
 180 #define CpuNumOfUints \
 181   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 182 #define CpuNumOfBits \
 183   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 184
 185 /* If you get a compiler error for zero width of the unused field,
 186    comment it out.  */
 187 #define CpuUnused       (CpuMax + 1)
 188
 189 /* We can check if an instruction is available with array instead
 190    of bitfield. */
 191 typedef union i386_cpu_flags
 192 {
 193   struct
 194     {
 195       unsigned int cpui186:1;
 196       unsigned int cpui286:1;
 197       unsigned int cpui386:1;
 198       unsigned int cpui486:1;
 199       unsigned int cpui586:1;
 200       unsigned int cpui686:1;
 201       unsigned int cpuclflush:1;
 202       unsigned int cpunop:1;
 203       unsigned int cpusyscall:1;
 204       unsigned int cpu8087:1;
 205       unsigned int cpu287:1;
 206       unsigned int cpu387:1;
 207       unsigned int cpu687:1;
 208       unsigned int cpufisttp:1;
 209       unsigned int cpummx:1;
 210       unsigned int cpusse:1;
 211       unsigned int cpusse2:1;
 212       unsigned int cpua3dnow:1;
 213       unsigned int cpua3dnowa:1;
 214       unsigned int cpusse3:1;
 215       unsigned int cpupadlock:1;
 216       unsigned int cpusvme:1;
 217       unsigned int cpuvmx:1;
 218       unsigned int cpusmx:1;
 219       unsigned int cpussse3:1;
 220       unsigned int cpusse4a:1;
 221       unsigned int cpuabm:1;
 222       unsigned int cpusse4_1:1;
 223       unsigned int cpusse4_2:1;
 224       unsigned int cpuavx:1;
 225       unsigned int cpuavx2:1;
 226       unsigned int cpuavx512f:1;
 227       unsigned int cpuavx512cd:1;
 228       unsigned int cpuavx512er:1;
 229       unsigned int cpuavx512pf:1;
 230       unsigned int cpul1om:1;
 231       unsigned int cpuk1om:1;
 232       unsigned int cpuxsave:1;
 233       unsigned int cpuxsaveopt:1;
 234       unsigned int cpuaes:1;
 235       unsigned int cpupclmul:1;
 236       unsigned int cpufma:1;
 237       unsigned int cpufma4:1;
 238       unsigned int cpuxop:1;
 239       unsigned int cpulwp:1;
 240       unsigned int cpubmi:1;
 241       unsigned int cputbm:1;
 242       unsigned int cpumovbe:1;
 243       unsigned int cpucx16:1;
 244       unsigned int cpuept:1;
 245       unsigned int cpurdtscp:1;
 246       unsigned int cpufsgsbase:1;
 247       unsigned int cpurdrnd:1;
 248       unsigned int cpuf16c:1;
 249       unsigned int cpubmi2:1;
 250       unsigned int cpulzcnt:1;
 251       unsigned int cpuhle:1;
 252       unsigned int cpurtm:1;
 253       unsigned int cpuinvpcid:1;
 254       unsigned int cpuvmfunc:1;
 255       unsigned int cpumpx:1;
 256       unsigned int cpulm:1;
 257       unsigned int cpurdseed:1;
 258       unsigned int cpuadx:1;
 259       unsigned int cpuprfchw:1;
 260       unsigned int cpusmap:1;
 261       unsigned int cpusha:1;
 262       unsigned int cpuvrex:1;
 263       unsigned int cpu64:1;
 264       unsigned int cpuno64:1;
 265 #ifdef CpuUnused
 266       unsigned int unused:(CpuNumOfBits - CpuUnused);
 267 #endif
 268     } bitfield;
 269   unsigned int array[CpuNumOfUints];
 270 } i386_cpu_flags;
 271
 272 /* Position of opcode_modifier bits.  */
 273
 274 enum
 275 {
 276   /* has direction bit. */
 277   D = 0,
 278   /* set if operands can be words or dwords encoded the canonical way */
 279   W,
 280   /* Skip the current insn and use the next insn in i386-opc.tbl to swap
 281      operand in encoding.  */
 282   S,
 283   /* insn has a modrm byte. */
 284   Modrm,
 285   /* register is in low 3 bits of opcode */
 286   ShortForm,
 287   /* special case for jump insns.  */
 288   Jump,
 289   /* call and jump */
 290   JumpDword,
 291   /* loop and jecxz */
 292   JumpByte,
 293   /* special case for intersegment leaps/calls */
 294   JumpInterSegment,
 295   /* FP insn memory format bit, sized by 0x4 */
 296   FloatMF,
 297   /* src/dest swap for floats. */
 298   FloatR,
 299   /* has float insn direction bit. */
 300   FloatD,
 301   /* needs size prefix if in 32-bit mode */
 302   Size16,
 303   /* needs size prefix if in 16-bit mode */
 304   Size32,
 305   /* needs size prefix if in 64-bit mode */
 306   Size64,
 307   /* check register size.  */
 308   CheckRegSize,
 309   /* instruction ignores operand size prefix and in Intel mode ignores
 310      mnemonic size suffix check.  */
 311   IgnoreSize,
 312   /* default insn size depends on mode */
 313   DefaultSize,
 314   /* b suffix on instruction illegal */
 315   No_bSuf,
 316   /* w suffix on instruction illegal */
 317   No_wSuf,
 318   /* l suffix on instruction illegal */
 319   No_lSuf,
 320   /* s suffix on instruction illegal */
 321   No_sSuf,
 322   /* q suffix on instruction illegal */
 323   No_qSuf,
 324   /* long double suffix on instruction illegal */
 325   No_ldSuf,
 326   /* instruction needs FWAIT */
 327   FWait,
 328   /* quick test for string instructions */
 329   IsString,
 330   /* quick test if branch instruction is MPX supported */
 331   BNDPrefixOk,
 332   /* quick test for lockable instructions */
 333   IsLockable,
 334   /* fake an extra reg operand for clr, imul and special register
 335      processing for some instructions.  */
 336   RegKludge,
 337   /* The first operand must be xmm0 */
 338   FirstXmm0,
 339   /* An implicit xmm0 as the first operand */
 340   Implicit1stXmm0,
 341   /* The HLE prefix is OK:
 342      1. With a LOCK prefix.
 343      2. With or without a LOCK prefix.
 344      3. With a RELEASE (0xf3) prefix.
 345    */
 346 #define HLEPrefixNone           0
 347 #define HLEPrefixLock           1
 348 #define HLEPrefixAny            2
 349 #define HLEPrefixRelease        3
 350   HLEPrefixOk,
 351   /* An instruction on which a "rep" prefix is acceptable.  */
 352   RepPrefixOk,
 353   /* Convert to DWORD */
 354   ToDword,
 355   /* Convert to QWORD */
 356   ToQword,
 357   /* Address prefix changes operand 0 */
 358   AddrPrefixOp0,
 359   /* opcode is a prefix */
 360   IsPrefix,
 361   /* instruction has extension in 8 bit imm */
 362   ImmExt,
 363   /* instruction don't need Rex64 prefix.  */
 364   NoRex64,
 365   /* instruction require Rex64 prefix.  */
 366   Rex64,
 367   /* deprecated fp insn, gets a warning */
 368   Ugh,
 369   /* insn has VEX prefix:
 370         1: 128bit VEX prefix.
 371         2: 256bit VEX prefix.
 372         3: Scalar VEX prefix.
 373    */
 374 #define VEX128          1
 375 #define VEX256          2
 376 #define VEXScalar       3
 377   Vex,
 378   /* How to encode VEX.vvvv:
 379      0: VEX.vvvv must be 1111b.
 380      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 381         the content of source registers will be preserved.
 382         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 383         where the content of first source register will be overwritten
 384         by the result.
 385         VEX.NDD2.  The second destination register operand is encoded in
 386         VEX.vvvv for instructions with 2 destination register operands.
 387         For assembler, there are no difference between VEX.NDS, VEX.DDS
 388         and VEX.NDD2.
 389      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 390      instructions with 1 destination register operand.
 391      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 392         of the operands can access a memory location.
 393    */
 394 #define VEXXDS  1
 395 #define VEXNDD  2
 396 #define VEXLWP  3
 397   VexVVVV,
 398   /* How the VEX.W bit is used:
 399      0: Set by the REX.W bit.
 400      1: VEX.W0.  Should always be 0.
 401      2: VEX.W1.  Should always be 1.
 402    */
 403 #define VEXW0   1
 404 #define VEXW1   2
 405   VexW,
 406   /* VEX opcode prefix:
 407      0: VEX 0x0F opcode prefix.
 408      1: VEX 0x0F38 opcode prefix.
 409      2: VEX 0x0F3A opcode prefix
 410      3: XOP 0x08 opcode prefix.
 411      4: XOP 0x09 opcode prefix
 412      5: XOP 0x0A opcode prefix.
 413    */
 414 #define VEX0F           0
 415 #define VEX0F38         1
 416 #define VEX0F3A         2
 417 #define XOP08           3
 418 #define XOP09           4
 419 #define XOP0A           5
 420   VexOpcode,
 421   /* number of VEX source operands:
 422      0: <= 2 source operands.
 423      1: 2 XOP source operands.
 424      2: 3 source operands.
 425    */
 426 #define XOP2SOURCES     1
 427 #define VEX3SOURCES     2
 428   VexSources,
 429   /* instruction has VEX 8 bit imm */
 430   VexImmExt,
 431   /* Instruction with vector SIB byte:
 432         1: 128bit vector register.
 433         2: 256bit vector register.
 434         3: 512bit vector register.
 435    */
 436 #define VecSIB128       1
 437 #define VecSIB256       2
 438 #define VecSIB512       3
 439   VecSIB,
 440   /* SSE to AVX support required */
 441   SSE2AVX,
 442   /* No AVX equivalent */
 443   NoAVX,
 444
 445   /* insn has EVEX prefix:
 446         1: 512bit EVEX prefix.
 447         2: 128bit EVEX prefix.
 448         3: 256bit EVEX prefix.
 449         4: Length-ignored (LIG) EVEX prefix.
 450    */
 451 #define EVEX512                1
 452 #define EVEX128                2
 453 #define EVEX256                3
 454 #define EVEXLIG                4
 455   EVex,
 456
 457   /* AVX512 masking support:
 458         1: Zeroing-masking.
 459         2: Merging-masking.
 460         3: Both zeroing and merging masking.
 461    */
 462 #define ZEROING_MASKING 1
 463 #define MERGING_MASKING 2
 464 #define BOTH_MASKING    3
 465   Masking,
 466
 467   /* Input element size of vector insn:
 468         0: 32bit.
 469         1: 64bit.
 470    */
 471   VecESize,
 472
 473   /* Broadcast factor.
 474         0: No broadcast.
 475         1: 1to16 broadcast.
 476         2: 1to8 broadcast.
 477    */
 478 #define NO_BROADCAST    0
 479 #define BROADCAST_1TO16 1
 480 #define BROADCAST_1TO8  2
 481   Broadcast,
 482
 483   /* Static rounding control is supported.  */
 484   StaticRounding,
 485
 486   /* Supress All Exceptions is supported.  */
 487   SAE,
 488
 489   /* Copressed Disp8*N attribute.  */
 490   Disp8MemShift,
 491
 492   /* Default mask isn't allowed.  */
 493   NoDefMask,
 494
 495   /* Compatible with old (<= 2.8.1) versions of gcc  */
 496   OldGcc,
 497   /* AT&T mnemonic.  */
 498   ATTMnemonic,
 499   /* AT&T syntax.  */
 500   ATTSyntax,
 501   /* Intel syntax.  */
 502   IntelSyntax,
 503   /* The last bitfield in i386_opcode_modifier.  */
 504   Opcode_Modifier_Max
 505 };
 506
 507 typedef struct i386_opcode_modifier
 508 {
 509   unsigned int d:1;
 510   unsigned int w:1;
 511   unsigned int s:1;
 512   unsigned int modrm:1;
 513   unsigned int shortform:1;
 514   unsigned int jump:1;
 515   unsigned int jumpdword:1;
 516   unsigned int jumpbyte:1;
 517   unsigned int jumpintersegment:1;
 518   unsigned int floatmf:1;
 519   unsigned int floatr:1;
 520   unsigned int floatd:1;
 521   unsigned int size16:1;
 522   unsigned int size32:1;
 523   unsigned int size64:1;
 524   unsigned int checkregsize:1;
 525   unsigned int ignoresize:1;
 526   unsigned int defaultsize:1;
 527   unsigned int no_bsuf:1;
 528   unsigned int no_wsuf:1;
 529   unsigned int no_lsuf:1;
 530   unsigned int no_ssuf:1;
 531   unsigned int no_qsuf:1;
 532   unsigned int no_ldsuf:1;
 533   unsigned int fwait:1;
 534   unsigned int isstring:1;
 535   unsigned int bndprefixok:1;
 536   unsigned int islockable:1;
 537   unsigned int regkludge:1;
 538   unsigned int firstxmm0:1;
 539   unsigned int implicit1stxmm0:1;
 540   unsigned int hleprefixok:2;
 541   unsigned int repprefixok:1;
 542   unsigned int todword:1;
 543   unsigned int toqword:1;
 544   unsigned int addrprefixop0:1;
 545   unsigned int isprefix:1;
 546   unsigned int immext:1;
 547   unsigned int norex64:1;
 548   unsigned int rex64:1;
 549   unsigned int ugh:1;
 550   unsigned int vex:2;
 551   unsigned int vexvvvv:2;
 552   unsigned int vexw:2;
 553   unsigned int vexopcode:3;
 554   unsigned int vexsources:2;
 555   unsigned int veximmext:1;
 556   unsigned int vecsib:2;
 557   unsigned int sse2avx:1;
 558   unsigned int noavx:1;
 559   unsigned int evex:3;
 560   unsigned int masking:2;
 561   unsigned int vecesize:1;
 562   unsigned int broadcast:3;
 563   unsigned int staticrounding:1;
 564   unsigned int sae:1;
 565   unsigned int disp8memshift:3;
 566   unsigned int nodefmask:1;
 567   unsigned int oldgcc:1;
 568   unsigned int attmnemonic:1;
 569   unsigned int attsyntax:1;
 570   unsigned int intelsyntax:1;
 571 } i386_opcode_modifier;
 572
 573 /* Position of operand_type bits.  */
 574
 575 enum
 576 {
 577   /* 8bit register */
 578   Reg8 = 0,
 579   /* 16bit register */
 580   Reg16,
 581   /* 32bit register */
 582   Reg32,
 583   /* 64bit register */
 584   Reg64,
 585   /* Floating pointer stack register */
 586   FloatReg,
 587   /* MMX register */
 588   RegMMX,
 589   /* SSE register */
 590   RegXMM,
 591   /* AVX registers */
 592   RegYMM,
 593   /* AVX512 registers */
 594   RegZMM,
 595   /* Vector Mask registers */
 596   RegMask,
 597   /* Control register */
 598   Control,
 599   /* Debug register */
 600   Debug,
 601   /* Test register */
 602   Test,
 603   /* 2 bit segment register */
 604   SReg2,
 605   /* 3 bit segment register */
 606   SReg3,
 607   /* 1 bit immediate */
 608   Imm1,
 609   /* 8 bit immediate */
 610   Imm8,
 611   /* 8 bit immediate sign extended */
 612   Imm8S,
 613   /* 16 bit immediate */
 614   Imm16,
 615   /* 32 bit immediate */
 616   Imm32,
 617   /* 32 bit immediate sign extended */
 618   Imm32S,
 619   /* 64 bit immediate */
 620   Imm64,
 621   /* 8bit/16bit/32bit displacements are used in different ways,
 622      depending on the instruction.  For jumps, they specify the
 623      size of the PC relative displacement, for instructions with
 624      memory operand, they specify the size of the offset relative
 625      to the base register, and for instructions with memory offset
 626      such as `mov 1234,%al' they specify the size of the offset
 627      relative to the segment base.  */
 628   /* 8 bit displacement */
 629   Disp8,
 630   /* 16 bit displacement */
 631   Disp16,
 632   /* 32 bit displacement */
 633   Disp32,
 634   /* 32 bit signed displacement */
 635   Disp32S,
 636   /* 64 bit displacement */
 637   Disp64,
 638   /* Accumulator %al/%ax/%eax/%rax */
 639   Acc,
 640   /* Floating pointer top stack register %st(0) */
 641   FloatAcc,
 642   /* Register which can be used for base or index in memory operand.  */
 643   BaseIndex,
 644   /* Register to hold in/out port addr = dx */
 645   InOutPortReg,
 646   /* Register to hold shift count = cl */
 647   ShiftCount,
 648   /* Absolute address for jump.  */
 649   JumpAbsolute,
 650   /* String insn operand with fixed es segment */
 651   EsSeg,
 652   /* RegMem is for instructions with a modrm byte where the register
 653      destination operand should be encoded in the mod and regmem fields.
 654      Normally, it will be encoded in the reg field. We add a RegMem
 655      flag to the destination register operand to indicate that it should
 656      be encoded in the regmem field.  */
 657   RegMem,
 658   /* Memory.  */
 659   Mem,
 660   /* BYTE memory. */
 661   Byte,
 662   /* WORD memory. 2 byte */
 663   Word,
 664   /* DWORD memory. 4 byte */
 665   Dword,
 666   /* FWORD memory. 6 byte */
 667   Fword,
 668   /* QWORD memory. 8 byte */
 669   Qword,
 670   /* TBYTE memory. 10 byte */
 671   Tbyte,
 672   /* XMMWORD memory. */
 673   Xmmword,
 674   /* YMMWORD memory. */
 675   Ymmword,
 676   /* ZMMWORD memory.  */
 677   Zmmword,
 678   /* Unspecified memory size.  */
 679   Unspecified,
 680   /* Any memory size.  */
 681   Anysize,
 682
 683   /* Vector 4 bit immediate.  */
 684   Vec_Imm4,
 685
 686   /* Bound register.  */
 687   RegBND,
 688
 689   /* Vector 8bit displacement */
 690   Vec_Disp8,
 691
 692   /* The last bitfield in i386_operand_type.  */
 693   OTMax
 694 };
 695
 696 #define OTNumOfUints \
 697   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 698 #define OTNumOfBits \
 699   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 700
 701 /* If you get a compiler error for zero width of the unused field,
 702    comment it out.  */
 703 #define OTUnused                (OTMax + 1)
 704
 705 typedef union i386_operand_type
 706 {
 707   struct
 708     {
 709       unsigned int reg8:1;
 710       unsigned int reg16:1;
 711       unsigned int reg32:1;
 712       unsigned int reg64:1;
 713       unsigned int floatreg:1;
 714       unsigned int regmmx:1;
 715       unsigned int regxmm:1;
 716       unsigned int regymm:1;
 717       unsigned int regzmm:1;
 718       unsigned int regmask:1;
 719       unsigned int control:1;
 720       unsigned int debug:1;
 721       unsigned int test:1;
 722       unsigned int sreg2:1;
 723       unsigned int sreg3:1;
 724       unsigned int imm1:1;
 725       unsigned int imm8:1;
 726       unsigned int imm8s:1;
 727       unsigned int imm16:1;
 728       unsigned int imm32:1;
 729       unsigned int imm32s:1;
 730       unsigned int imm64:1;
 731       unsigned int disp8:1;
 732       unsigned int disp16:1;
 733       unsigned int disp32:1;
 734       unsigned int disp32s:1;
 735       unsigned int disp64:1;
 736       unsigned int acc:1;
 737       unsigned int floatacc:1;
 738       unsigned int baseindex:1;
 739       unsigned int inoutportreg:1;
 740       unsigned int shiftcount:1;
 741       unsigned int jumpabsolute:1;
 742       unsigned int esseg:1;
 743       unsigned int regmem:1;
 744       unsigned int mem:1;
 745       unsigned int byte:1;
 746       unsigned int word:1;
 747       unsigned int dword:1;
 748       unsigned int fword:1;
 749       unsigned int qword:1;
 750       unsigned int tbyte:1;
 751       unsigned int xmmword:1;
 752       unsigned int ymmword:1;
 753       unsigned int zmmword:1;
 754       unsigned int unspecified:1;
 755       unsigned int anysize:1;
 756       unsigned int vec_imm4:1;
 757       unsigned int regbnd:1;
 758       unsigned int vec_disp8:1;
 759 #ifdef OTUnused
 760       unsigned int unused:(OTNumOfBits - OTUnused);
 761 #endif
 762     } bitfield;
 763   unsigned int array[OTNumOfUints];
 764 } i386_operand_type;
 765
 766 typedef struct insn_template
 767 {
 768   /* instruction name sans width suffix ("mov" for movl insns) */
 769   char *name;
 770
 771   /* how many operands */
 772   unsigned int operands;
 773
 774   /* base_opcode is the fundamental opcode byte without optional
 775      prefix(es).  */
 776   unsigned int base_opcode;
 777 #define Opcode_D        0x2 /* Direction bit:
 778                                set if Reg --> Regmem;
 779                                unset if Regmem --> Reg. */
 780 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 781 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 782
 783   /* extension_opcode is the 3 bit extension for group <n> insns.
 784      This field is also used to store the 8-bit opcode suffix for the
 785      AMD 3DNow! instructions.
 786      If this template has no extension opcode (the usual case) use None
 787      Instructions */
 788   unsigned int extension_opcode;
 789 #define None 0xffff             /* If no extension_opcode is possible.  */
 790
 791   /* Opcode length.  */
 792   unsigned char opcode_length;
 793
 794   /* cpu feature flags */
 795   i386_cpu_flags cpu_flags;
 796
 797   /* the bits in opcode_modifier are used to generate the final opcode from
 798      the base_opcode.  These bits also are used to detect alternate forms of
 799      the same instruction */
 800   i386_opcode_modifier opcode_modifier;
 801
 802   /* operand_types[i] describes the type of operand i.  This is made
 803      by OR'ing together all of the possible type masks.  (e.g.
 804      'operand_types[i] = Reg|Imm' specifies that operand i can be
 805      either a register or an immediate operand.  */
 806   i386_operand_type operand_types[MAX_OPERANDS];
 807 }
 808 insn_template;
 809
 810 extern const insn_template i386_optab[];
 811
 812 /* these are for register name --> number & type hash lookup */
 813 typedef struct
 814 {
 815   char *reg_name;
 816   i386_operand_type reg_type;
 817   unsigned char reg_flags;
 818 #define RegRex      0x1  /* Extended register.  */
 819 #define RegRex64    0x2  /* Extended 8 bit register.  */
 820 #define RegVRex     0x4  /* Extended vector register.  */
 821   unsigned char reg_num;
 822 #define RegRip  ((unsigned char ) ~0)
 823 #define RegEip  (RegRip - 1)
 824 /* EIZ and RIZ are fake index registers.  */
 825 #define RegEiz  (RegEip - 1)
 826 #define RegRiz  (RegEiz - 1)
 827 /* FLAT is a fake segment register (Intel mode).  */
 828 #define RegFlat     ((unsigned char) ~0)
 829   signed char dw2_regnum[2];
 830 #define Dw2Inval (-1)
 831 }
 832 reg_entry;
 833
 834 /* Entries in i386_regtab.  */
 835 #define REGNAM_AL 1
 836 #define REGNAM_AX 25
 837 #define REGNAM_EAX 41
 838
 839 extern const reg_entry i386_regtab[];
 840 extern const unsigned int i386_regtab_size;
 841
 842 typedef struct
 843 {
 844   char *seg_name;
 845   unsigned int seg_prefix;
 846 }
 847 seg_entry;
 848
 849 extern const seg_entry cs;
 850 extern const seg_entry ds;
 851 extern const seg_entry ss;
 852 extern const seg_entry es;
 853 extern const seg_entry fs;
 854 extern const seg_entry gs;