opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2014 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #ifdef HAVE_LIMITS_H
  23 #include <limits.h>
  24 #endif
  25
  26 #ifndef CHAR_BIT
  27 #define CHAR_BIT 8
  28 #endif
  29
  30 /* Position of cpu flags bitfiled.  */
  31
  32 enum
  33 {
  34   /* i186 or better required */
  35   Cpu186 = 0,
  36   /* i286 or better required */
  37   Cpu286,
  38   /* i386 or better required */
  39   Cpu386,
  40   /* i486 or better required */
  41   Cpu486,
  42   /* i585 or better required */
  43   Cpu586,
  44   /* i686 or better required */
  45   Cpu686,
  46   /* CLFLUSH Instruction support required */
  47   CpuClflush,
  48   /* NOP Instruction support required */
  49   CpuNop,
  50   /* SYSCALL Instructions support required */
  51   CpuSYSCALL,
  52   /* Floating point support required */
  53   Cpu8087,
  54   /* i287 support required */
  55   Cpu287,
  56   /* i387 support required */
  57   Cpu387,
  58   /* i686 and floating point support required */
  59   Cpu687,
  60   /* SSE3 and floating point support required */
  61   CpuFISTTP,
  62   /* MMX support required */
  63   CpuMMX,
  64   /* SSE support required */
  65   CpuSSE,
  66   /* SSE2 support required */
  67   CpuSSE2,
  68   /* 3dnow! support required */
  69   Cpu3dnow,
  70   /* 3dnow! Extensions support required */
  71   Cpu3dnowA,
  72   /* SSE3 support required */
  73   CpuSSE3,
  74   /* VIA PadLock required */
  75   CpuPadLock,
  76   /* AMD Secure Virtual Machine Ext-s required */
  77   CpuSVME,
  78   /* VMX Instructions required */
  79   CpuVMX,
  80   /* SMX Instructions required */
  81   CpuSMX,
  82   /* SSSE3 support required */
  83   CpuSSSE3,
  84   /* SSE4a support required */
  85   CpuSSE4a,
  86   /* ABM New Instructions required */
  87   CpuABM,
  88   /* SSE4.1 support required */
  89   CpuSSE4_1,
  90   /* SSE4.2 support required */
  91   CpuSSE4_2,
  92   /* AVX support required */
  93   CpuAVX,
  94   /* AVX2 support required */
  95   CpuAVX2,
  96   /* Intel AVX-512 Foundation Instructions support required */
  97   CpuAVX512F,
  98   /* Intel AVX-512 Conflict Detection Instructions support required */
  99   CpuAVX512CD,
 100   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 101      required */
 102   CpuAVX512ER,
 103   /* Intel AVX-512 Prefetch Instructions support required */
 104   CpuAVX512PF,
 105   /* Intel AVX-512 VL Instructions support required.  */
 106   CpuAVX512VL,
 107   /* Intel AVX-512 DQ Instructions support required.  */
 108   CpuAVX512DQ,
 109   /* Intel AVX-512 BW Instructions support required.  */
 110   CpuAVX512BW,
 111   /* Intel L1OM support required */
 112   CpuL1OM,
 113   /* Intel K1OM support required */
 114   CpuK1OM,
 115   /* Xsave/xrstor New Instructions support required */
 116   CpuXsave,
 117   /* Xsaveopt New Instructions support required */
 118   CpuXsaveopt,
 119   /* AES support required */
 120   CpuAES,
 121   /* PCLMUL support required */
 122   CpuPCLMUL,
 123   /* FMA support required */
 124   CpuFMA,
 125   /* FMA4 support required */
 126   CpuFMA4,
 127   /* XOP support required */
 128   CpuXOP,
 129   /* LWP support required */
 130   CpuLWP,
 131   /* BMI support required */
 132   CpuBMI,
 133   /* TBM support required */
 134   CpuTBM,
 135   /* MOVBE Instruction support required */
 136   CpuMovbe,
 137   /* CMPXCHG16B instruction support required.  */
 138   CpuCX16,
 139   /* EPT Instructions required */
 140   CpuEPT,
 141   /* RDTSCP Instruction support required */
 142   CpuRdtscp,
 143   /* FSGSBASE Instructions required */
 144   CpuFSGSBase,
 145   /* RDRND Instructions required */
 146   CpuRdRnd,
 147   /* F16C Instructions required */
 148   CpuF16C,
 149   /* Intel BMI2 support required */
 150   CpuBMI2,
 151   /* LZCNT support required */
 152   CpuLZCNT,
 153   /* HLE support required */
 154   CpuHLE,
 155   /* RTM support required */
 156   CpuRTM,
 157   /* INVPCID Instructions required */
 158   CpuINVPCID,
 159   /* VMFUNC Instruction required */
 160   CpuVMFUNC,
 161   /* Intel MPX Instructions required  */
 162   CpuMPX,
 163   /* 64bit support available, used by -march= in assembler.  */
 164   CpuLM,
 165   /* RDRSEED instruction required.  */
 166   CpuRDSEED,
 167   /* Multi-presisionn add-carry instructions are required.  */
 168   CpuADX,
 169   /* Supports prefetchw and prefetch instructions.  */
 170   CpuPRFCHW,
 171   /* SMAP instructions required.  */
 172   CpuSMAP,
 173   /* SHA instructions required.  */
 174   CpuSHA,
 175   /* VREX support required  */
 176   CpuVREX,
 177   /* CLFLUSHOPT instruction required */
 178   CpuClflushOpt,
 179   /* XSAVES/XRSTORS instruction required */
 180   CpuXSAVES,
 181   /* XSAVEC instruction required */
 182   CpuXSAVEC,
 183   /* PREFETCHWT1 instruction required */
 184   CpuPREFETCHWT1,
 185   /* SE1 instruction required */
 186   CpuSE1,
 187   /* CLWB instruction required */
 188   CpuCLWB,
 189   /* PCOMMIT instruction required */
 190   CpuPCOMMIT,
 191   /* Intel AVX-512 IFMA Instructions support required.  */
 192   CpuAVX512IFMA,
 193   /* 64bit support required  */
 194   Cpu64,
 195   /* Not supported in the 64bit mode  */
 196   CpuNo64,
 197   /* The last bitfield in i386_cpu_flags.  */
 198   CpuMax = CpuNo64
 199 };
 200
 201 #define CpuNumOfUints \
 202   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 203 #define CpuNumOfBits \
 204   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 205
 206 /* If you get a compiler error for zero width of the unused field,
 207    comment it out.  */
 208 #define CpuUnused       (CpuMax + 1)
 209
 210 /* We can check if an instruction is available with array instead
 211    of bitfield. */
 212 typedef union i386_cpu_flags
 213 {
 214   struct
 215     {
 216       unsigned int cpui186:1;
 217       unsigned int cpui286:1;
 218       unsigned int cpui386:1;
 219       unsigned int cpui486:1;
 220       unsigned int cpui586:1;
 221       unsigned int cpui686:1;
 222       unsigned int cpuclflush:1;
 223       unsigned int cpunop:1;
 224       unsigned int cpusyscall:1;
 225       unsigned int cpu8087:1;
 226       unsigned int cpu287:1;
 227       unsigned int cpu387:1;
 228       unsigned int cpu687:1;
 229       unsigned int cpufisttp:1;
 230       unsigned int cpummx:1;
 231       unsigned int cpusse:1;
 232       unsigned int cpusse2:1;
 233       unsigned int cpua3dnow:1;
 234       unsigned int cpua3dnowa:1;
 235       unsigned int cpusse3:1;
 236       unsigned int cpupadlock:1;
 237       unsigned int cpusvme:1;
 238       unsigned int cpuvmx:1;
 239       unsigned int cpusmx:1;
 240       unsigned int cpussse3:1;
 241       unsigned int cpusse4a:1;
 242       unsigned int cpuabm:1;
 243       unsigned int cpusse4_1:1;
 244       unsigned int cpusse4_2:1;
 245       unsigned int cpuavx:1;
 246       unsigned int cpuavx2:1;
 247       unsigned int cpuavx512f:1;
 248       unsigned int cpuavx512cd:1;
 249       unsigned int cpuavx512er:1;
 250       unsigned int cpuavx512pf:1;
 251       unsigned int cpuavx512vl:1;
 252       unsigned int cpuavx512dq:1;
 253       unsigned int cpuavx512bw:1;
 254       unsigned int cpul1om:1;
 255       unsigned int cpuk1om:1;
 256       unsigned int cpuxsave:1;
 257       unsigned int cpuxsaveopt:1;
 258       unsigned int cpuaes:1;
 259       unsigned int cpupclmul:1;
 260       unsigned int cpufma:1;
 261       unsigned int cpufma4:1;
 262       unsigned int cpuxop:1;
 263       unsigned int cpulwp:1;
 264       unsigned int cpubmi:1;
 265       unsigned int cputbm:1;
 266       unsigned int cpumovbe:1;
 267       unsigned int cpucx16:1;
 268       unsigned int cpuept:1;
 269       unsigned int cpurdtscp:1;
 270       unsigned int cpufsgsbase:1;
 271       unsigned int cpurdrnd:1;
 272       unsigned int cpuf16c:1;
 273       unsigned int cpubmi2:1;
 274       unsigned int cpulzcnt:1;
 275       unsigned int cpuhle:1;
 276       unsigned int cpurtm:1;
 277       unsigned int cpuinvpcid:1;
 278       unsigned int cpuvmfunc:1;
 279       unsigned int cpumpx:1;
 280       unsigned int cpulm:1;
 281       unsigned int cpurdseed:1;
 282       unsigned int cpuadx:1;
 283       unsigned int cpuprfchw:1;
 284       unsigned int cpusmap:1;
 285       unsigned int cpusha:1;
 286       unsigned int cpuvrex:1;
 287       unsigned int cpuclflushopt:1;
 288       unsigned int cpuxsaves:1;
 289       unsigned int cpuxsavec:1;
 290       unsigned int cpuprefetchwt1:1;
 291       unsigned int cpuse1:1;
 292       unsigned int cpuclwb:1;
 293       unsigned int cpupcommit:1;
 294       unsigned int cpuavx512ifma:1;
 295       unsigned int cpu64:1;
 296       unsigned int cpuno64:1;
 297 #ifdef CpuUnused
 298       unsigned int unused:(CpuNumOfBits - CpuUnused);
 299 #endif
 300     } bitfield;
 301   unsigned int array[CpuNumOfUints];
 302 } i386_cpu_flags;
 303
 304 /* Position of opcode_modifier bits.  */
 305
 306 enum
 307 {
 308   /* has direction bit. */
 309   D = 0,
 310   /* set if operands can be words or dwords encoded the canonical way */
 311   W,
 312   /* Skip the current insn and use the next insn in i386-opc.tbl to swap
 313      operand in encoding.  */
 314   S,
 315   /* insn has a modrm byte. */
 316   Modrm,
 317   /* register is in low 3 bits of opcode */
 318   ShortForm,
 319   /* special case for jump insns.  */
 320   Jump,
 321   /* call and jump */
 322   JumpDword,
 323   /* loop and jecxz */
 324   JumpByte,
 325   /* special case for intersegment leaps/calls */
 326   JumpInterSegment,
 327   /* FP insn memory format bit, sized by 0x4 */
 328   FloatMF,
 329   /* src/dest swap for floats. */
 330   FloatR,
 331   /* has float insn direction bit. */
 332   FloatD,
 333   /* needs size prefix if in 32-bit mode */
 334   Size16,
 335   /* needs size prefix if in 16-bit mode */
 336   Size32,
 337   /* needs size prefix if in 64-bit mode */
 338   Size64,
 339   /* check register size.  */
 340   CheckRegSize,
 341   /* instruction ignores operand size prefix and in Intel mode ignores
 342      mnemonic size suffix check.  */
 343   IgnoreSize,
 344   /* default insn size depends on mode */
 345   DefaultSize,
 346   /* b suffix on instruction illegal */
 347   No_bSuf,
 348   /* w suffix on instruction illegal */
 349   No_wSuf,
 350   /* l suffix on instruction illegal */
 351   No_lSuf,
 352   /* s suffix on instruction illegal */
 353   No_sSuf,
 354   /* q suffix on instruction illegal */
 355   No_qSuf,
 356   /* long double suffix on instruction illegal */
 357   No_ldSuf,
 358   /* instruction needs FWAIT */
 359   FWait,
 360   /* quick test for string instructions */
 361   IsString,
 362   /* quick test if branch instruction is MPX supported */
 363   BNDPrefixOk,
 364   /* quick test for lockable instructions */
 365   IsLockable,
 366   /* fake an extra reg operand for clr, imul and special register
 367      processing for some instructions.  */
 368   RegKludge,
 369   /* The first operand must be xmm0 */
 370   FirstXmm0,
 371   /* An implicit xmm0 as the first operand */
 372   Implicit1stXmm0,
 373   /* The HLE prefix is OK:
 374      1. With a LOCK prefix.
 375      2. With or without a LOCK prefix.
 376      3. With a RELEASE (0xf3) prefix.
 377    */
 378 #define HLEPrefixNone           0
 379 #define HLEPrefixLock           1
 380 #define HLEPrefixAny            2
 381 #define HLEPrefixRelease        3
 382   HLEPrefixOk,
 383   /* An instruction on which a "rep" prefix is acceptable.  */
 384   RepPrefixOk,
 385   /* Convert to DWORD */
 386   ToDword,
 387   /* Convert to QWORD */
 388   ToQword,
 389   /* Address prefix changes operand 0 */
 390   AddrPrefixOp0,
 391   /* opcode is a prefix */
 392   IsPrefix,
 393   /* instruction has extension in 8 bit imm */
 394   ImmExt,
 395   /* instruction don't need Rex64 prefix.  */
 396   NoRex64,
 397   /* instruction require Rex64 prefix.  */
 398   Rex64,
 399   /* deprecated fp insn, gets a warning */
 400   Ugh,
 401   /* insn has VEX prefix:
 402         1: 128bit VEX prefix.
 403         2: 256bit VEX prefix.
 404         3: Scalar VEX prefix.
 405    */
 406 #define VEX128          1
 407 #define VEX256          2
 408 #define VEXScalar       3
 409   Vex,
 410   /* How to encode VEX.vvvv:
 411      0: VEX.vvvv must be 1111b.
 412      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 413         the content of source registers will be preserved.
 414         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 415         where the content of first source register will be overwritten
 416         by the result.
 417         VEX.NDD2.  The second destination register operand is encoded in
 418         VEX.vvvv for instructions with 2 destination register operands.
 419         For assembler, there are no difference between VEX.NDS, VEX.DDS
 420         and VEX.NDD2.
 421      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 422      instructions with 1 destination register operand.
 423      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 424         of the operands can access a memory location.
 425    */
 426 #define VEXXDS  1
 427 #define VEXNDD  2
 428 #define VEXLWP  3
 429   VexVVVV,
 430   /* How the VEX.W bit is used:
 431      0: Set by the REX.W bit.
 432      1: VEX.W0.  Should always be 0.
 433      2: VEX.W1.  Should always be 1.
 434    */
 435 #define VEXW0   1
 436 #define VEXW1   2
 437   VexW,
 438   /* VEX opcode prefix:
 439      0: VEX 0x0F opcode prefix.
 440      1: VEX 0x0F38 opcode prefix.
 441      2: VEX 0x0F3A opcode prefix
 442      3: XOP 0x08 opcode prefix.
 443      4: XOP 0x09 opcode prefix
 444      5: XOP 0x0A opcode prefix.
 445    */
 446 #define VEX0F           0
 447 #define VEX0F38         1
 448 #define VEX0F3A         2
 449 #define XOP08           3
 450 #define XOP09           4
 451 #define XOP0A           5
 452   VexOpcode,
 453   /* number of VEX source operands:
 454      0: <= 2 source operands.
 455      1: 2 XOP source operands.
 456      2: 3 source operands.
 457    */
 458 #define XOP2SOURCES     1
 459 #define VEX3SOURCES     2
 460   VexSources,
 461   /* instruction has VEX 8 bit imm */
 462   VexImmExt,
 463   /* Instruction with vector SIB byte:
 464         1: 128bit vector register.
 465         2: 256bit vector register.
 466         3: 512bit vector register.
 467    */
 468 #define VecSIB128       1
 469 #define VecSIB256       2
 470 #define VecSIB512       3
 471   VecSIB,
 472   /* SSE to AVX support required */
 473   SSE2AVX,
 474   /* No AVX equivalent */
 475   NoAVX,
 476
 477   /* insn has EVEX prefix:
 478         1: 512bit EVEX prefix.
 479         2: 128bit EVEX prefix.
 480         3: 256bit EVEX prefix.
 481         4: Length-ignored (LIG) EVEX prefix.
 482    */
 483 #define EVEX512                1
 484 #define EVEX128                2
 485 #define EVEX256                3
 486 #define EVEXLIG                4
 487   EVex,
 488
 489   /* AVX512 masking support:
 490         1: Zeroing-masking.
 491         2: Merging-masking.
 492         3: Both zeroing and merging masking.
 493    */
 494 #define ZEROING_MASKING 1
 495 #define MERGING_MASKING 2
 496 #define BOTH_MASKING    3
 497   Masking,
 498
 499   /* Input element size of vector insn:
 500         0: 32bit.
 501         1: 64bit.
 502    */
 503   VecESize,
 504
 505   /* Broadcast factor.
 506         0: No broadcast.
 507         1: 1to16 broadcast.
 508         2: 1to8 broadcast.
 509    */
 510 #define NO_BROADCAST    0
 511 #define BROADCAST_1TO16 1
 512 #define BROADCAST_1TO8  2
 513 #define BROADCAST_1TO4  3
 514 #define BROADCAST_1TO2  4
 515   Broadcast,
 516
 517   /* Static rounding control is supported.  */
 518   StaticRounding,
 519
 520   /* Supress All Exceptions is supported.  */
 521   SAE,
 522
 523   /* Copressed Disp8*N attribute.  */
 524   Disp8MemShift,
 525
 526   /* Default mask isn't allowed.  */
 527   NoDefMask,
 528
 529   /* Compatible with old (<= 2.8.1) versions of gcc  */
 530   OldGcc,
 531   /* AT&T mnemonic.  */
 532   ATTMnemonic,
 533   /* AT&T syntax.  */
 534   ATTSyntax,
 535   /* Intel syntax.  */
 536   IntelSyntax,
 537   /* The last bitfield in i386_opcode_modifier.  */
 538   Opcode_Modifier_Max
 539 };
 540
 541 typedef struct i386_opcode_modifier
 542 {
 543   unsigned int d:1;
 544   unsigned int w:1;
 545   unsigned int s:1;
 546   unsigned int modrm:1;
 547   unsigned int shortform:1;
 548   unsigned int jump:1;
 549   unsigned int jumpdword:1;
 550   unsigned int jumpbyte:1;
 551   unsigned int jumpintersegment:1;
 552   unsigned int floatmf:1;
 553   unsigned int floatr:1;
 554   unsigned int floatd:1;
 555   unsigned int size16:1;
 556   unsigned int size32:1;
 557   unsigned int size64:1;
 558   unsigned int checkregsize:1;
 559   unsigned int ignoresize:1;
 560   unsigned int defaultsize:1;
 561   unsigned int no_bsuf:1;
 562   unsigned int no_wsuf:1;
 563   unsigned int no_lsuf:1;
 564   unsigned int no_ssuf:1;
 565   unsigned int no_qsuf:1;
 566   unsigned int no_ldsuf:1;
 567   unsigned int fwait:1;
 568   unsigned int isstring:1;
 569   unsigned int bndprefixok:1;
 570   unsigned int islockable:1;
 571   unsigned int regkludge:1;
 572   unsigned int firstxmm0:1;
 573   unsigned int implicit1stxmm0:1;
 574   unsigned int hleprefixok:2;
 575   unsigned int repprefixok:1;
 576   unsigned int todword:1;
 577   unsigned int toqword:1;
 578   unsigned int addrprefixop0:1;
 579   unsigned int isprefix:1;
 580   unsigned int immext:1;
 581   unsigned int norex64:1;
 582   unsigned int rex64:1;
 583   unsigned int ugh:1;
 584   unsigned int vex:2;
 585   unsigned int vexvvvv:2;
 586   unsigned int vexw:2;
 587   unsigned int vexopcode:3;
 588   unsigned int vexsources:2;
 589   unsigned int veximmext:1;
 590   unsigned int vecsib:2;
 591   unsigned int sse2avx:1;
 592   unsigned int noavx:1;
 593   unsigned int evex:3;
 594   unsigned int masking:2;
 595   unsigned int vecesize:1;
 596   unsigned int broadcast:3;
 597   unsigned int staticrounding:1;
 598   unsigned int sae:1;
 599   unsigned int disp8memshift:3;
 600   unsigned int nodefmask:1;
 601   unsigned int oldgcc:1;
 602   unsigned int attmnemonic:1;
 603   unsigned int attsyntax:1;
 604   unsigned int intelsyntax:1;
 605 } i386_opcode_modifier;
 606
 607 /* Position of operand_type bits.  */
 608
 609 enum
 610 {
 611   /* 8bit register */
 612   Reg8 = 0,
 613   /* 16bit register */
 614   Reg16,
 615   /* 32bit register */
 616   Reg32,
 617   /* 64bit register */
 618   Reg64,
 619   /* Floating pointer stack register */
 620   FloatReg,
 621   /* MMX register */
 622   RegMMX,
 623   /* SSE register */
 624   RegXMM,
 625   /* AVX registers */
 626   RegYMM,
 627   /* AVX512 registers */
 628   RegZMM,
 629   /* Vector Mask registers */
 630   RegMask,
 631   /* Control register */
 632   Control,
 633   /* Debug register */
 634   Debug,
 635   /* Test register */
 636   Test,
 637   /* 2 bit segment register */
 638   SReg2,
 639   /* 3 bit segment register */
 640   SReg3,
 641   /* 1 bit immediate */
 642   Imm1,
 643   /* 8 bit immediate */
 644   Imm8,
 645   /* 8 bit immediate sign extended */
 646   Imm8S,
 647   /* 16 bit immediate */
 648   Imm16,
 649   /* 32 bit immediate */
 650   Imm32,
 651   /* 32 bit immediate sign extended */
 652   Imm32S,
 653   /* 64 bit immediate */
 654   Imm64,
 655   /* 8bit/16bit/32bit displacements are used in different ways,
 656      depending on the instruction.  For jumps, they specify the
 657      size of the PC relative displacement, for instructions with
 658      memory operand, they specify the size of the offset relative
 659      to the base register, and for instructions with memory offset
 660      such as `mov 1234,%al' they specify the size of the offset
 661      relative to the segment base.  */
 662   /* 8 bit displacement */
 663   Disp8,
 664   /* 16 bit displacement */
 665   Disp16,
 666   /* 32 bit displacement */
 667   Disp32,
 668   /* 32 bit signed displacement */
 669   Disp32S,
 670   /* 64 bit displacement */
 671   Disp64,
 672   /* Accumulator %al/%ax/%eax/%rax */
 673   Acc,
 674   /* Floating pointer top stack register %st(0) */
 675   FloatAcc,
 676   /* Register which can be used for base or index in memory operand.  */
 677   BaseIndex,
 678   /* Register to hold in/out port addr = dx */
 679   InOutPortReg,
 680   /* Register to hold shift count = cl */
 681   ShiftCount,
 682   /* Absolute address for jump.  */
 683   JumpAbsolute,
 684   /* String insn operand with fixed es segment */
 685   EsSeg,
 686   /* RegMem is for instructions with a modrm byte where the register
 687      destination operand should be encoded in the mod and regmem fields.
 688      Normally, it will be encoded in the reg field. We add a RegMem
 689      flag to the destination register operand to indicate that it should
 690      be encoded in the regmem field.  */
 691   RegMem,
 692   /* Memory.  */
 693   Mem,
 694   /* BYTE memory. */
 695   Byte,
 696   /* WORD memory. 2 byte */
 697   Word,
 698   /* DWORD memory. 4 byte */
 699   Dword,
 700   /* FWORD memory. 6 byte */
 701   Fword,
 702   /* QWORD memory. 8 byte */
 703   Qword,
 704   /* TBYTE memory. 10 byte */
 705   Tbyte,
 706   /* XMMWORD memory. */
 707   Xmmword,
 708   /* YMMWORD memory. */
 709   Ymmword,
 710   /* ZMMWORD memory.  */
 711   Zmmword,
 712   /* Unspecified memory size.  */
 713   Unspecified,
 714   /* Any memory size.  */
 715   Anysize,
 716
 717   /* Vector 4 bit immediate.  */
 718   Vec_Imm4,
 719
 720   /* Bound register.  */
 721   RegBND,
 722
 723   /* Vector 8bit displacement */
 724   Vec_Disp8,
 725
 726   /* The last bitfield in i386_operand_type.  */
 727   OTMax
 728 };
 729
 730 #define OTNumOfUints \
 731   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 732 #define OTNumOfBits \
 733   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 734
 735 /* If you get a compiler error for zero width of the unused field,
 736    comment it out.  */
 737 #define OTUnused                (OTMax + 1)
 738
 739 typedef union i386_operand_type
 740 {
 741   struct
 742     {
 743       unsigned int reg8:1;
 744       unsigned int reg16:1;
 745       unsigned int reg32:1;
 746       unsigned int reg64:1;
 747       unsigned int floatreg:1;
 748       unsigned int regmmx:1;
 749       unsigned int regxmm:1;
 750       unsigned int regymm:1;
 751       unsigned int regzmm:1;
 752       unsigned int regmask:1;
 753       unsigned int control:1;
 754       unsigned int debug:1;
 755       unsigned int test:1;
 756       unsigned int sreg2:1;
 757       unsigned int sreg3:1;
 758       unsigned int imm1:1;
 759       unsigned int imm8:1;
 760       unsigned int imm8s:1;
 761       unsigned int imm16:1;
 762       unsigned int imm32:1;
 763       unsigned int imm32s:1;
 764       unsigned int imm64:1;
 765       unsigned int disp8:1;
 766       unsigned int disp16:1;
 767       unsigned int disp32:1;
 768       unsigned int disp32s:1;
 769       unsigned int disp64:1;
 770       unsigned int acc:1;
 771       unsigned int floatacc:1;
 772       unsigned int baseindex:1;
 773       unsigned int inoutportreg:1;
 774       unsigned int shiftcount:1;
 775       unsigned int jumpabsolute:1;
 776       unsigned int esseg:1;
 777       unsigned int regmem:1;
 778       unsigned int mem:1;
 779       unsigned int byte:1;
 780       unsigned int word:1;
 781       unsigned int dword:1;
 782       unsigned int fword:1;
 783       unsigned int qword:1;
 784       unsigned int tbyte:1;
 785       unsigned int xmmword:1;
 786       unsigned int ymmword:1;
 787       unsigned int zmmword:1;
 788       unsigned int unspecified:1;
 789       unsigned int anysize:1;
 790       unsigned int vec_imm4:1;
 791       unsigned int regbnd:1;
 792       unsigned int vec_disp8:1;
 793 #ifdef OTUnused
 794       unsigned int unused:(OTNumOfBits - OTUnused);
 795 #endif
 796     } bitfield;
 797   unsigned int array[OTNumOfUints];
 798 } i386_operand_type;
 799
 800 typedef struct insn_template
 801 {
 802   /* instruction name sans width suffix ("mov" for movl insns) */
 803   char *name;
 804
 805   /* how many operands */
 806   unsigned int operands;
 807
 808   /* base_opcode is the fundamental opcode byte without optional
 809      prefix(es).  */
 810   unsigned int base_opcode;
 811 #define Opcode_D        0x2 /* Direction bit:
 812                                set if Reg --> Regmem;
 813                                unset if Regmem --> Reg. */
 814 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 815 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 816
 817   /* extension_opcode is the 3 bit extension for group <n> insns.
 818      This field is also used to store the 8-bit opcode suffix for the
 819      AMD 3DNow! instructions.
 820      If this template has no extension opcode (the usual case) use None
 821      Instructions */
 822   unsigned int extension_opcode;
 823 #define None 0xffff             /* If no extension_opcode is possible.  */
 824
 825   /* Opcode length.  */
 826   unsigned char opcode_length;
 827
 828   /* cpu feature flags */
 829   i386_cpu_flags cpu_flags;
 830
 831   /* the bits in opcode_modifier are used to generate the final opcode from
 832      the base_opcode.  These bits also are used to detect alternate forms of
 833      the same instruction */
 834   i386_opcode_modifier opcode_modifier;
 835
 836   /* operand_types[i] describes the type of operand i.  This is made
 837      by OR'ing together all of the possible type masks.  (e.g.
 838      'operand_types[i] = Reg|Imm' specifies that operand i can be
 839      either a register or an immediate operand.  */
 840   i386_operand_type operand_types[MAX_OPERANDS];
 841 }
 842 insn_template;
 843
 844 extern const insn_template i386_optab[];
 845
 846 /* these are for register name --> number & type hash lookup */
 847 typedef struct
 848 {
 849   char *reg_name;
 850   i386_operand_type reg_type;
 851   unsigned char reg_flags;
 852 #define RegRex      0x1  /* Extended register.  */
 853 #define RegRex64    0x2  /* Extended 8 bit register.  */
 854 #define RegVRex     0x4  /* Extended vector register.  */
 855   unsigned char reg_num;
 856 #define RegRip  ((unsigned char ) ~0)
 857 #define RegEip  (RegRip - 1)
 858 /* EIZ and RIZ are fake index registers.  */
 859 #define RegEiz  (RegEip - 1)
 860 #define RegRiz  (RegEiz - 1)
 861 /* FLAT is a fake segment register (Intel mode).  */
 862 #define RegFlat     ((unsigned char) ~0)
 863   signed char dw2_regnum[2];
 864 #define Dw2Inval (-1)
 865 }
 866 reg_entry;
 867
 868 /* Entries in i386_regtab.  */
 869 #define REGNAM_AL 1
 870 #define REGNAM_AX 25
 871 #define REGNAM_EAX 41
 872
 873 extern const reg_entry i386_regtab[];
 874 extern const unsigned int i386_regtab_size;
 875
 876 typedef struct
 877 {
 878   char *seg_name;
 879   unsigned int seg_prefix;
 880 }
 881 seg_entry;
 882
 883 extern const seg_entry cs;
 884 extern const seg_entry ds;
 885 extern const seg_entry ss;
 886 extern const seg_entry es;
 887 extern const seg_entry fs;
 888 extern const seg_entry gs;