opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2018 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #ifdef HAVE_LIMITS_H
  23 #include <limits.h>
  24 #endif
  25
  26 #ifndef CHAR_BIT
  27 #define CHAR_BIT 8
  28 #endif
  29
  30 /* Position of cpu flags bitfiled.  */
  31
  32 enum
  33 {
  34   /* i186 or better required */
  35   Cpu186 = 0,
  36   /* i286 or better required */
  37   Cpu286,
  38   /* i386 or better required */
  39   Cpu386,
  40   /* i486 or better required */
  41   Cpu486,
  42   /* i585 or better required */
  43   Cpu586,
  44   /* i686 or better required */
  45   Cpu686,
  46   /* CLFLUSH Instruction support required */
  47   CpuClflush,
  48   /* NOP Instruction support required */
  49   CpuNop,
  50   /* SYSCALL Instructions support required */
  51   CpuSYSCALL,
  52   /* Floating point support required */
  53   Cpu8087,
  54   /* i287 support required */
  55   Cpu287,
  56   /* i387 support required */
  57   Cpu387,
  58   /* i686 and floating point support required */
  59   Cpu687,
  60   /* SSE3 and floating point support required */
  61   CpuFISTTP,
  62   /* MMX support required */
  63   CpuMMX,
  64   /* SSE support required */
  65   CpuSSE,
  66   /* SSE2 support required */
  67   CpuSSE2,
  68   /* 3dnow! support required */
  69   Cpu3dnow,
  70   /* 3dnow! Extensions support required */
  71   Cpu3dnowA,
  72   /* SSE3 support required */
  73   CpuSSE3,
  74   /* VIA PadLock required */
  75   CpuPadLock,
  76   /* AMD Secure Virtual Machine Ext-s required */
  77   CpuSVME,
  78   /* VMX Instructions required */
  79   CpuVMX,
  80   /* SMX Instructions required */
  81   CpuSMX,
  82   /* SSSE3 support required */
  83   CpuSSSE3,
  84   /* SSE4a support required */
  85   CpuSSE4a,
  86   /* ABM New Instructions required */
  87   CpuABM,
  88   /* SSE4.1 support required */
  89   CpuSSE4_1,
  90   /* SSE4.2 support required */
  91   CpuSSE4_2,
  92   /* AVX support required */
  93   CpuAVX,
  94   /* AVX2 support required */
  95   CpuAVX2,
  96   /* Intel AVX-512 Foundation Instructions support required */
  97   CpuAVX512F,
  98   /* Intel AVX-512 Conflict Detection Instructions support required */
  99   CpuAVX512CD,
 100   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 101      required */
 102   CpuAVX512ER,
 103   /* Intel AVX-512 Prefetch Instructions support required */
 104   CpuAVX512PF,
 105   /* Intel AVX-512 VL Instructions support required.  */
 106   CpuAVX512VL,
 107   /* Intel AVX-512 DQ Instructions support required.  */
 108   CpuAVX512DQ,
 109   /* Intel AVX-512 BW Instructions support required.  */
 110   CpuAVX512BW,
 111   /* Intel L1OM support required */
 112   CpuL1OM,
 113   /* Intel K1OM support required */
 114   CpuK1OM,
 115   /* Intel IAMCU support required */
 116   CpuIAMCU,
 117   /* Xsave/xrstor New Instructions support required */
 118   CpuXsave,
 119   /* Xsaveopt New Instructions support required */
 120   CpuXsaveopt,
 121   /* AES support required */
 122   CpuAES,
 123   /* PCLMUL support required */
 124   CpuPCLMUL,
 125   /* FMA support required */
 126   CpuFMA,
 127   /* FMA4 support required */
 128   CpuFMA4,
 129   /* XOP support required */
 130   CpuXOP,
 131   /* LWP support required */
 132   CpuLWP,
 133   /* BMI support required */
 134   CpuBMI,
 135   /* TBM support required */
 136   CpuTBM,
 137   /* MOVBE Instruction support required */
 138   CpuMovbe,
 139   /* CMPXCHG16B instruction support required.  */
 140   CpuCX16,
 141   /* EPT Instructions required */
 142   CpuEPT,
 143   /* RDTSCP Instruction support required */
 144   CpuRdtscp,
 145   /* FSGSBASE Instructions required */
 146   CpuFSGSBase,
 147   /* RDRND Instructions required */
 148   CpuRdRnd,
 149   /* F16C Instructions required */
 150   CpuF16C,
 151   /* Intel BMI2 support required */
 152   CpuBMI2,
 153   /* LZCNT support required */
 154   CpuLZCNT,
 155   /* HLE support required */
 156   CpuHLE,
 157   /* RTM support required */
 158   CpuRTM,
 159   /* INVPCID Instructions required */
 160   CpuINVPCID,
 161   /* VMFUNC Instruction required */
 162   CpuVMFUNC,
 163   /* Intel MPX Instructions required  */
 164   CpuMPX,
 165   /* 64bit support available, used by -march= in assembler.  */
 166   CpuLM,
 167   /* RDRSEED instruction required.  */
 168   CpuRDSEED,
 169   /* Multi-presisionn add-carry instructions are required.  */
 170   CpuADX,
 171   /* Supports prefetchw and prefetch instructions.  */
 172   CpuPRFCHW,
 173   /* SMAP instructions required.  */
 174   CpuSMAP,
 175   /* SHA instructions required.  */
 176   CpuSHA,
 177   /* VREX support required  */
 178   CpuVREX,
 179   /* CLFLUSHOPT instruction required */
 180   CpuClflushOpt,
 181   /* XSAVES/XRSTORS instruction required */
 182   CpuXSAVES,
 183   /* XSAVEC instruction required */
 184   CpuXSAVEC,
 185   /* PREFETCHWT1 instruction required */
 186   CpuPREFETCHWT1,
 187   /* SE1 instruction required */
 188   CpuSE1,
 189   /* CLWB instruction required */
 190   CpuCLWB,
 191   /* Intel AVX-512 IFMA Instructions support required.  */
 192   CpuAVX512IFMA,
 193   /* Intel AVX-512 VBMI Instructions support required.  */
 194   CpuAVX512VBMI,
 195   /* Intel AVX-512 4FMAPS Instructions support required.  */
 196   CpuAVX512_4FMAPS,
 197   /* Intel AVX-512 4VNNIW Instructions support required.  */
 198   CpuAVX512_4VNNIW,
 199   /* Intel AVX-512 VPOPCNTDQ Instructions support required.  */
 200   CpuAVX512_VPOPCNTDQ,
 201   /* Intel AVX-512 VBMI2 Instructions support required.  */
 202   CpuAVX512_VBMI2,
 203   /* Intel AVX-512 VNNI Instructions support required.  */
 204   CpuAVX512_VNNI,
 205   /* Intel AVX-512 BITALG Instructions support required.  */
 206   CpuAVX512_BITALG,
 207   /* mwaitx instruction required */
 208   CpuMWAITX,
 209   /* Clzero instruction required */
 210   CpuCLZERO,
 211   /* OSPKE instruction required */
 212   CpuOSPKE,
 213   /* RDPID instruction required */
 214   CpuRDPID,
 215   /* PTWRITE instruction required */
 216   CpuPTWRITE,
 217   /* CET instructions support required */
 218   CpuIBT,
 219   CpuSHSTK,
 220   /* GFNI instructions required */
 221   CpuGFNI,
 222   /* VAES instructions required */
 223   CpuVAES,
 224   /* VPCLMULQDQ instructions required */
 225   CpuVPCLMULQDQ,
 226   /* WBNOINVD instructions required */
 227   CpuWBNOINVD,
 228   /* MMX register support required */
 229   CpuRegMMX,
 230   /* XMM register support required */
 231   CpuRegXMM,
 232   /* YMM register support required */
 233   CpuRegYMM,
 234   /* ZMM register support required */
 235   CpuRegZMM,
 236   /* Mask register support required */
 237   CpuRegMask,
 238   /* 64bit support required  */
 239   Cpu64,
 240   /* Not supported in the 64bit mode  */
 241   CpuNo64,
 242   /* The last bitfield in i386_cpu_flags.  */
 243   CpuMax = CpuNo64
 244 };
 245
 246 #define CpuNumOfUints \
 247   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 248 #define CpuNumOfBits \
 249   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 250
 251 /* If you get a compiler error for zero width of the unused field,
 252    comment it out.  */
 253 #define CpuUnused       (CpuMax + 1)
 254
 255 /* We can check if an instruction is available with array instead
 256    of bitfield. */
 257 typedef union i386_cpu_flags
 258 {
 259   struct
 260     {
 261       unsigned int cpui186:1;
 262       unsigned int cpui286:1;
 263       unsigned int cpui386:1;
 264       unsigned int cpui486:1;
 265       unsigned int cpui586:1;
 266       unsigned int cpui686:1;
 267       unsigned int cpuclflush:1;
 268       unsigned int cpunop:1;
 269       unsigned int cpusyscall:1;
 270       unsigned int cpu8087:1;
 271       unsigned int cpu287:1;
 272       unsigned int cpu387:1;
 273       unsigned int cpu687:1;
 274       unsigned int cpufisttp:1;
 275       unsigned int cpummx:1;
 276       unsigned int cpusse:1;
 277       unsigned int cpusse2:1;
 278       unsigned int cpua3dnow:1;
 279       unsigned int cpua3dnowa:1;
 280       unsigned int cpusse3:1;
 281       unsigned int cpupadlock:1;
 282       unsigned int cpusvme:1;
 283       unsigned int cpuvmx:1;
 284       unsigned int cpusmx:1;
 285       unsigned int cpussse3:1;
 286       unsigned int cpusse4a:1;
 287       unsigned int cpuabm:1;
 288       unsigned int cpusse4_1:1;
 289       unsigned int cpusse4_2:1;
 290       unsigned int cpuavx:1;
 291       unsigned int cpuavx2:1;
 292       unsigned int cpuavx512f:1;
 293       unsigned int cpuavx512cd:1;
 294       unsigned int cpuavx512er:1;
 295       unsigned int cpuavx512pf:1;
 296       unsigned int cpuavx512vl:1;
 297       unsigned int cpuavx512dq:1;
 298       unsigned int cpuavx512bw:1;
 299       unsigned int cpul1om:1;
 300       unsigned int cpuk1om:1;
 301       unsigned int cpuiamcu:1;
 302       unsigned int cpuxsave:1;
 303       unsigned int cpuxsaveopt:1;
 304       unsigned int cpuaes:1;
 305       unsigned int cpupclmul:1;
 306       unsigned int cpufma:1;
 307       unsigned int cpufma4:1;
 308       unsigned int cpuxop:1;
 309       unsigned int cpulwp:1;
 310       unsigned int cpubmi:1;
 311       unsigned int cputbm:1;
 312       unsigned int cpumovbe:1;
 313       unsigned int cpucx16:1;
 314       unsigned int cpuept:1;
 315       unsigned int cpurdtscp:1;
 316       unsigned int cpufsgsbase:1;
 317       unsigned int cpurdrnd:1;
 318       unsigned int cpuf16c:1;
 319       unsigned int cpubmi2:1;
 320       unsigned int cpulzcnt:1;
 321       unsigned int cpuhle:1;
 322       unsigned int cpurtm:1;
 323       unsigned int cpuinvpcid:1;
 324       unsigned int cpuvmfunc:1;
 325       unsigned int cpumpx:1;
 326       unsigned int cpulm:1;
 327       unsigned int cpurdseed:1;
 328       unsigned int cpuadx:1;
 329       unsigned int cpuprfchw:1;
 330       unsigned int cpusmap:1;
 331       unsigned int cpusha:1;
 332       unsigned int cpuvrex:1;
 333       unsigned int cpuclflushopt:1;
 334       unsigned int cpuxsaves:1;
 335       unsigned int cpuxsavec:1;
 336       unsigned int cpuprefetchwt1:1;
 337       unsigned int cpuse1:1;
 338       unsigned int cpuclwb:1;
 339       unsigned int cpuavx512ifma:1;
 340       unsigned int cpuavx512vbmi:1;
 341       unsigned int cpuavx512_4fmaps:1;
 342       unsigned int cpuavx512_4vnniw:1;
 343       unsigned int cpuavx512_vpopcntdq:1;
 344       unsigned int cpuavx512_vbmi2:1;
 345       unsigned int cpuavx512_vnni:1;
 346       unsigned int cpuavx512_bitalg:1;
 347       unsigned int cpumwaitx:1;
 348       unsigned int cpuclzero:1;
 349       unsigned int cpuospke:1;
 350       unsigned int cpurdpid:1;
 351       unsigned int cpuptwrite:1;
 352       unsigned int cpuibt:1;
 353       unsigned int cpushstk:1;
 354       unsigned int cpugfni:1;
 355       unsigned int cpuvaes:1;
 356       unsigned int cpuvpclmulqdq:1;
 357       unsigned int cpuwbnoinvd:1;
 358       unsigned int cpuregmmx:1;
 359       unsigned int cpuregxmm:1;
 360       unsigned int cpuregymm:1;
 361       unsigned int cpuregzmm:1;
 362       unsigned int cpuregmask:1;
 363       unsigned int cpu64:1;
 364       unsigned int cpuno64:1;
 365 #ifdef CpuUnused
 366       unsigned int unused:(CpuNumOfBits - CpuUnused);
 367 #endif
 368     } bitfield;
 369   unsigned int array[CpuNumOfUints];
 370 } i386_cpu_flags;
 371
 372 /* Position of opcode_modifier bits.  */
 373
 374 enum
 375 {
 376   /* has direction bit. */
 377   D = 0,
 378   /* set if operands can be words or dwords encoded the canonical way */
 379   W,
 380   /* load form instruction. Must be placed before store form.  */
 381   Load,
 382   /* insn has a modrm byte. */
 383   Modrm,
 384   /* register is in low 3 bits of opcode */
 385   ShortForm,
 386   /* special case for jump insns.  */
 387   Jump,
 388   /* call and jump */
 389   JumpDword,
 390   /* loop and jecxz */
 391   JumpByte,
 392   /* special case for intersegment leaps/calls */
 393   JumpInterSegment,
 394   /* FP insn memory format bit, sized by 0x4 */
 395   FloatMF,
 396   /* src/dest swap for floats. */
 397   FloatR,
 398   /* has float insn direction bit. */
 399   FloatD,
 400   /* needs size prefix if in 32-bit mode */
 401   Size16,
 402   /* needs size prefix if in 16-bit mode */
 403   Size32,
 404   /* needs size prefix if in 64-bit mode */
 405   Size64,
 406   /* check register size.  */
 407   CheckRegSize,
 408   /* instruction ignores operand size prefix and in Intel mode ignores
 409      mnemonic size suffix check.  */
 410   IgnoreSize,
 411   /* default insn size depends on mode */
 412   DefaultSize,
 413   /* b suffix on instruction illegal */
 414   No_bSuf,
 415   /* w suffix on instruction illegal */
 416   No_wSuf,
 417   /* l suffix on instruction illegal */
 418   No_lSuf,
 419   /* s suffix on instruction illegal */
 420   No_sSuf,
 421   /* q suffix on instruction illegal */
 422   No_qSuf,
 423   /* long double suffix on instruction illegal */
 424   No_ldSuf,
 425   /* instruction needs FWAIT */
 426   FWait,
 427   /* quick test for string instructions */
 428   IsString,
 429   /* quick test if branch instruction is MPX supported */
 430   BNDPrefixOk,
 431   /* quick test if NOTRACK prefix is supported */
 432   NoTrackPrefixOk,
 433   /* quick test for lockable instructions */
 434   IsLockable,
 435   /* fake an extra reg operand for clr, imul and special register
 436      processing for some instructions.  */
 437   RegKludge,
 438   /* An implicit xmm0 as the first operand */
 439   Implicit1stXmm0,
 440   /* The HLE prefix is OK:
 441      1. With a LOCK prefix.
 442      2. With or without a LOCK prefix.
 443      3. With a RELEASE (0xf3) prefix.
 444    */
 445 #define HLEPrefixNone           0
 446 #define HLEPrefixLock           1
 447 #define HLEPrefixAny            2
 448 #define HLEPrefixRelease        3
 449   HLEPrefixOk,
 450   /* An instruction on which a "rep" prefix is acceptable.  */
 451   RepPrefixOk,
 452   /* Convert to DWORD */
 453   ToDword,
 454   /* Convert to QWORD */
 455   ToQword,
 456   /* Address prefix changes operand 0 */
 457   AddrPrefixOp0,
 458   /* opcode is a prefix */
 459   IsPrefix,
 460   /* instruction has extension in 8 bit imm */
 461   ImmExt,
 462   /* instruction don't need Rex64 prefix.  */
 463   NoRex64,
 464   /* instruction require Rex64 prefix.  */
 465   Rex64,
 466   /* deprecated fp insn, gets a warning */
 467   Ugh,
 468   /* insn has VEX prefix:
 469         1: 128bit VEX prefix (or operand dependent).
 470         2: 256bit VEX prefix.
 471         3: Scalar VEX prefix.
 472    */
 473 #define VEX128          1
 474 #define VEX256          2
 475 #define VEXScalar       3
 476   Vex,
 477   /* How to encode VEX.vvvv:
 478      0: VEX.vvvv must be 1111b.
 479      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 480         the content of source registers will be preserved.
 481         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 482         where the content of first source register will be overwritten
 483         by the result.
 484         VEX.NDD2.  The second destination register operand is encoded in
 485         VEX.vvvv for instructions with 2 destination register operands.
 486         For assembler, there are no difference between VEX.NDS, VEX.DDS
 487         and VEX.NDD2.
 488      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 489      instructions with 1 destination register operand.
 490      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 491         of the operands can access a memory location.
 492    */
 493 #define VEXXDS  1
 494 #define VEXNDD  2
 495 #define VEXLWP  3
 496   VexVVVV,
 497   /* How the VEX.W bit is used:
 498      0: Set by the REX.W bit.
 499      1: VEX.W0.  Should always be 0.
 500      2: VEX.W1.  Should always be 1.
 501    */
 502 #define VEXW0   1
 503 #define VEXW1   2
 504   VexW,
 505   /* VEX opcode prefix:
 506      0: VEX 0x0F opcode prefix.
 507      1: VEX 0x0F38 opcode prefix.
 508      2: VEX 0x0F3A opcode prefix
 509      3: XOP 0x08 opcode prefix.
 510      4: XOP 0x09 opcode prefix
 511      5: XOP 0x0A opcode prefix.
 512    */
 513 #define VEX0F           0
 514 #define VEX0F38         1
 515 #define VEX0F3A         2
 516 #define XOP08           3
 517 #define XOP09           4
 518 #define XOP0A           5
 519   VexOpcode,
 520   /* number of VEX source operands:
 521      0: <= 2 source operands.
 522      1: 2 XOP source operands.
 523      2: 3 source operands.
 524    */
 525 #define XOP2SOURCES     1
 526 #define VEX3SOURCES     2
 527   VexSources,
 528   /* instruction has VEX 8 bit imm */
 529   VexImmExt,
 530   /* Instruction with vector SIB byte:
 531         1: 128bit vector register.
 532         2: 256bit vector register.
 533         3: 512bit vector register.
 534    */
 535 #define VecSIB128       1
 536 #define VecSIB256       2
 537 #define VecSIB512       3
 538   VecSIB,
 539   /* SSE to AVX support required */
 540   SSE2AVX,
 541   /* No AVX equivalent */
 542   NoAVX,
 543
 544   /* insn has EVEX prefix:
 545         1: 512bit EVEX prefix.
 546         2: 128bit EVEX prefix.
 547         3: 256bit EVEX prefix.
 548         4: Length-ignored (LIG) EVEX prefix.
 549    */
 550 #define EVEX512                1
 551 #define EVEX128                2
 552 #define EVEX256                3
 553 #define EVEXLIG                4
 554   EVex,
 555
 556   /* AVX512 masking support:
 557         1: Zeroing-masking.
 558         2: Merging-masking.
 559         3: Both zeroing and merging masking.
 560    */
 561 #define ZEROING_MASKING 1
 562 #define MERGING_MASKING 2
 563 #define BOTH_MASKING    3
 564   Masking,
 565
 566   /* Input element size of vector insn:
 567         0: 32bit.
 568         1: 64bit.
 569    */
 570   VecESize,
 571
 572   /* Broadcast factor.
 573         0: No broadcast.
 574         1: 1to16 broadcast.
 575         2: 1to8 broadcast.
 576    */
 577 #define NO_BROADCAST    0
 578 #define BROADCAST_1TO16 1
 579 #define BROADCAST_1TO8  2
 580 #define BROADCAST_1TO4  3
 581 #define BROADCAST_1TO2  4
 582   Broadcast,
 583
 584   /* Static rounding control is supported.  */
 585   StaticRounding,
 586
 587   /* Supress All Exceptions is supported.  */
 588   SAE,
 589
 590   /* Copressed Disp8*N attribute.  */
 591   Disp8MemShift,
 592
 593   /* Default mask isn't allowed.  */
 594   NoDefMask,
 595
 596   /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
 597      It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
 598    */
 599   ImplicitQuadGroup,
 600
 601   /* Compatible with old (<= 2.8.1) versions of gcc  */
 602   OldGcc,
 603   /* AT&T mnemonic.  */
 604   ATTMnemonic,
 605   /* AT&T syntax.  */
 606   ATTSyntax,
 607   /* Intel syntax.  */
 608   IntelSyntax,
 609   /* AMD64.  */
 610   AMD64,
 611   /* Intel64.  */
 612   Intel64,
 613   /* The last bitfield in i386_opcode_modifier.  */
 614   Opcode_Modifier_Max
 615 };
 616
 617 typedef struct i386_opcode_modifier
 618 {
 619   unsigned int d:1;
 620   unsigned int w:1;
 621   unsigned int load:1;
 622   unsigned int modrm:1;
 623   unsigned int shortform:1;
 624   unsigned int jump:1;
 625   unsigned int jumpdword:1;
 626   unsigned int jumpbyte:1;
 627   unsigned int jumpintersegment:1;
 628   unsigned int floatmf:1;
 629   unsigned int floatr:1;
 630   unsigned int floatd:1;
 631   unsigned int size16:1;
 632   unsigned int size32:1;
 633   unsigned int size64:1;
 634   unsigned int checkregsize:1;
 635   unsigned int ignoresize:1;
 636   unsigned int defaultsize:1;
 637   unsigned int no_bsuf:1;
 638   unsigned int no_wsuf:1;
 639   unsigned int no_lsuf:1;
 640   unsigned int no_ssuf:1;
 641   unsigned int no_qsuf:1;
 642   unsigned int no_ldsuf:1;
 643   unsigned int fwait:1;
 644   unsigned int isstring:1;
 645   unsigned int bndprefixok:1;
 646   unsigned int notrackprefixok:1;
 647   unsigned int islockable:1;
 648   unsigned int regkludge:1;
 649   unsigned int implicit1stxmm0:1;
 650   unsigned int hleprefixok:2;
 651   unsigned int repprefixok:1;
 652   unsigned int todword:1;
 653   unsigned int toqword:1;
 654   unsigned int addrprefixop0:1;
 655   unsigned int isprefix:1;
 656   unsigned int immext:1;
 657   unsigned int norex64:1;
 658   unsigned int rex64:1;
 659   unsigned int ugh:1;
 660   unsigned int vex:2;
 661   unsigned int vexvvvv:2;
 662   unsigned int vexw:2;
 663   unsigned int vexopcode:3;
 664   unsigned int vexsources:2;
 665   unsigned int veximmext:1;
 666   unsigned int vecsib:2;
 667   unsigned int sse2avx:1;
 668   unsigned int noavx:1;
 669   unsigned int evex:3;
 670   unsigned int masking:2;
 671   unsigned int vecesize:1;
 672   unsigned int broadcast:3;
 673   unsigned int staticrounding:1;
 674   unsigned int sae:1;
 675   unsigned int disp8memshift:3;
 676   unsigned int nodefmask:1;
 677   unsigned int implicitquadgroup:1;
 678   unsigned int oldgcc:1;
 679   unsigned int attmnemonic:1;
 680   unsigned int attsyntax:1;
 681   unsigned int intelsyntax:1;
 682   unsigned int amd64:1;
 683   unsigned int intel64:1;
 684 } i386_opcode_modifier;
 685
 686 /* Position of operand_type bits.  */
 687
 688 enum
 689 {
 690   /* Register (qualified by Byte, Word, etc) */
 691   Reg = 0,
 692   /* MMX register */
 693   RegMMX,
 694   /* Vector registers */
 695   RegSIMD,
 696   /* Vector Mask registers */
 697   RegMask,
 698   /* Control register */
 699   Control,
 700   /* Debug register */
 701   Debug,
 702   /* Test register */
 703   Test,
 704   /* 2 bit segment register */
 705   SReg2,
 706   /* 3 bit segment register */
 707   SReg3,
 708   /* 1 bit immediate */
 709   Imm1,
 710   /* 8 bit immediate */
 711   Imm8,
 712   /* 8 bit immediate sign extended */
 713   Imm8S,
 714   /* 16 bit immediate */
 715   Imm16,
 716   /* 32 bit immediate */
 717   Imm32,
 718   /* 32 bit immediate sign extended */
 719   Imm32S,
 720   /* 64 bit immediate */
 721   Imm64,
 722   /* 8bit/16bit/32bit displacements are used in different ways,
 723      depending on the instruction.  For jumps, they specify the
 724      size of the PC relative displacement, for instructions with
 725      memory operand, they specify the size of the offset relative
 726      to the base register, and for instructions with memory offset
 727      such as `mov 1234,%al' they specify the size of the offset
 728      relative to the segment base.  */
 729   /* 8 bit displacement */
 730   Disp8,
 731   /* 16 bit displacement */
 732   Disp16,
 733   /* 32 bit displacement */
 734   Disp32,
 735   /* 32 bit signed displacement */
 736   Disp32S,
 737   /* 64 bit displacement */
 738   Disp64,
 739   /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
 740   Acc,
 741   /* Register which can be used for base or index in memory operand.  */
 742   BaseIndex,
 743   /* Register to hold in/out port addr = dx */
 744   InOutPortReg,
 745   /* Register to hold shift count = cl */
 746   ShiftCount,
 747   /* Absolute address for jump.  */
 748   JumpAbsolute,
 749   /* String insn operand with fixed es segment */
 750   EsSeg,
 751   /* RegMem is for instructions with a modrm byte where the register
 752      destination operand should be encoded in the mod and regmem fields.
 753      Normally, it will be encoded in the reg field. We add a RegMem
 754      flag to the destination register operand to indicate that it should
 755      be encoded in the regmem field.  */
 756   RegMem,
 757   /* Memory.  */
 758   Mem,
 759   /* BYTE memory. */
 760   Byte,
 761   /* WORD memory. 2 byte */
 762   Word,
 763   /* DWORD memory. 4 byte */
 764   Dword,
 765   /* FWORD memory. 6 byte */
 766   Fword,
 767   /* QWORD memory. 8 byte */
 768   Qword,
 769   /* TBYTE memory. 10 byte */
 770   Tbyte,
 771   /* XMMWORD memory. */
 772   Xmmword,
 773   /* YMMWORD memory. */
 774   Ymmword,
 775   /* ZMMWORD memory.  */
 776   Zmmword,
 777   /* Unspecified memory size.  */
 778   Unspecified,
 779   /* Any memory size.  */
 780   Anysize,
 781
 782   /* Vector 4 bit immediate.  */
 783   Vec_Imm4,
 784
 785   /* Bound register.  */
 786   RegBND,
 787
 788   /* The last bitfield in i386_operand_type.  */
 789   OTMax
 790 };
 791
 792 #define OTNumOfUints \
 793   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 794 #define OTNumOfBits \
 795   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 796
 797 /* If you get a compiler error for zero width of the unused field,
 798    comment it out.  */
 799 #define OTUnused                (OTMax + 1)
 800
 801 typedef union i386_operand_type
 802 {
 803   struct
 804     {
 805       unsigned int reg:1;
 806       unsigned int regmmx:1;
 807       unsigned int regsimd:1;
 808       unsigned int regmask:1;
 809       unsigned int control:1;
 810       unsigned int debug:1;
 811       unsigned int test:1;
 812       unsigned int sreg2:1;
 813       unsigned int sreg3:1;
 814       unsigned int imm1:1;
 815       unsigned int imm8:1;
 816       unsigned int imm8s:1;
 817       unsigned int imm16:1;
 818       unsigned int imm32:1;
 819       unsigned int imm32s:1;
 820       unsigned int imm64:1;
 821       unsigned int disp8:1;
 822       unsigned int disp16:1;
 823       unsigned int disp32:1;
 824       unsigned int disp32s:1;
 825       unsigned int disp64:1;
 826       unsigned int acc:1;
 827       unsigned int baseindex:1;
 828       unsigned int inoutportreg:1;
 829       unsigned int shiftcount:1;
 830       unsigned int jumpabsolute:1;
 831       unsigned int esseg:1;
 832       unsigned int regmem:1;
 833       unsigned int mem:1;
 834       unsigned int byte:1;
 835       unsigned int word:1;
 836       unsigned int dword:1;
 837       unsigned int fword:1;
 838       unsigned int qword:1;
 839       unsigned int tbyte:1;
 840       unsigned int xmmword:1;
 841       unsigned int ymmword:1;
 842       unsigned int zmmword:1;
 843       unsigned int unspecified:1;
 844       unsigned int anysize:1;
 845       unsigned int vec_imm4:1;
 846       unsigned int regbnd:1;
 847 #ifdef OTUnused
 848       unsigned int unused:(OTNumOfBits - OTUnused);
 849 #endif
 850     } bitfield;
 851   unsigned int array[OTNumOfUints];
 852 } i386_operand_type;
 853
 854 typedef struct insn_template
 855 {
 856   /* instruction name sans width suffix ("mov" for movl insns) */
 857   char *name;
 858
 859   /* how many operands */
 860   unsigned int operands;
 861
 862   /* base_opcode is the fundamental opcode byte without optional
 863      prefix(es).  */
 864   unsigned int base_opcode;
 865 #define Opcode_D        0x2 /* Direction bit:
 866                                set if Reg --> Regmem;
 867                                unset if Regmem --> Reg. */
 868 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 869 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 870
 871   /* extension_opcode is the 3 bit extension for group <n> insns.
 872      This field is also used to store the 8-bit opcode suffix for the
 873      AMD 3DNow! instructions.
 874      If this template has no extension opcode (the usual case) use None
 875      Instructions */
 876   unsigned int extension_opcode;
 877 #define None 0xffff             /* If no extension_opcode is possible.  */
 878
 879   /* Opcode length.  */
 880   unsigned char opcode_length;
 881
 882   /* cpu feature flags */
 883   i386_cpu_flags cpu_flags;
 884
 885   /* the bits in opcode_modifier are used to generate the final opcode from
 886      the base_opcode.  These bits also are used to detect alternate forms of
 887      the same instruction */
 888   i386_opcode_modifier opcode_modifier;
 889
 890   /* operand_types[i] describes the type of operand i.  This is made
 891      by OR'ing together all of the possible type masks.  (e.g.
 892      'operand_types[i] = Reg|Imm' specifies that operand i can be
 893      either a register or an immediate operand.  */
 894   i386_operand_type operand_types[MAX_OPERANDS];
 895 }
 896 insn_template;
 897
 898 extern const insn_template i386_optab[];
 899
 900 /* these are for register name --> number & type hash lookup */
 901 typedef struct
 902 {
 903   char *reg_name;
 904   i386_operand_type reg_type;
 905   unsigned char reg_flags;
 906 #define RegRex      0x1  /* Extended register.  */
 907 #define RegRex64    0x2  /* Extended 8 bit register.  */
 908 #define RegVRex     0x4  /* Extended vector register.  */
 909   unsigned char reg_num;
 910 #define RegRip  ((unsigned char ) ~0)
 911 #define RegEip  (RegRip - 1)
 912 /* EIZ and RIZ are fake index registers.  */
 913 #define RegEiz  (RegEip - 1)
 914 #define RegRiz  (RegEiz - 1)
 915 /* FLAT is a fake segment register (Intel mode).  */
 916 #define RegFlat     ((unsigned char) ~0)
 917   signed char dw2_regnum[2];
 918 #define Dw2Inval (-1)
 919 }
 920 reg_entry;
 921
 922 /* Entries in i386_regtab.  */
 923 #define REGNAM_AL 1
 924 #define REGNAM_AX 25
 925 #define REGNAM_EAX 41
 926
 927 extern const reg_entry i386_regtab[];
 928 extern const unsigned int i386_regtab_size;
 929
 930 typedef struct
 931 {
 932   char *seg_name;
 933   unsigned int seg_prefix;
 934 }
 935 seg_entry;
 936
 937 extern const seg_entry cs;
 938 extern const seg_entry ds;
 939 extern const seg_entry ss;
 940 extern const seg_entry es;
 941 extern const seg_entry fs;
 942 extern const seg_entry gs;