opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2018 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #ifdef HAVE_LIMITS_H
  23 #include <limits.h>
  24 #endif
  25
  26 #ifndef CHAR_BIT
  27 #define CHAR_BIT 8
  28 #endif
  29
  30 /* Position of cpu flags bitfiled.  */
  31
  32 enum
  33 {
  34   /* i186 or better required */
  35   Cpu186 = 0,
  36   /* i286 or better required */
  37   Cpu286,
  38   /* i386 or better required */
  39   Cpu386,
  40   /* i486 or better required */
  41   Cpu486,
  42   /* i585 or better required */
  43   Cpu586,
  44   /* i686 or better required */
  45   Cpu686,
  46   /* CLFLUSH Instruction support required */
  47   CpuClflush,
  48   /* NOP Instruction support required */
  49   CpuNop,
  50   /* SYSCALL Instructions support required */
  51   CpuSYSCALL,
  52   /* Floating point support required */
  53   Cpu8087,
  54   /* i287 support required */
  55   Cpu287,
  56   /* i387 support required */
  57   Cpu387,
  58   /* i686 and floating point support required */
  59   Cpu687,
  60   /* SSE3 and floating point support required */
  61   CpuFISTTP,
  62   /* MMX support required */
  63   CpuMMX,
  64   /* SSE support required */
  65   CpuSSE,
  66   /* SSE2 support required */
  67   CpuSSE2,
  68   /* 3dnow! support required */
  69   Cpu3dnow,
  70   /* 3dnow! Extensions support required */
  71   Cpu3dnowA,
  72   /* SSE3 support required */
  73   CpuSSE3,
  74   /* VIA PadLock required */
  75   CpuPadLock,
  76   /* AMD Secure Virtual Machine Ext-s required */
  77   CpuSVME,
  78   /* VMX Instructions required */
  79   CpuVMX,
  80   /* SMX Instructions required */
  81   CpuSMX,
  82   /* SSSE3 support required */
  83   CpuSSSE3,
  84   /* SSE4a support required */
  85   CpuSSE4a,
  86   /* ABM New Instructions required */
  87   CpuABM,
  88   /* SSE4.1 support required */
  89   CpuSSE4_1,
  90   /* SSE4.2 support required */
  91   CpuSSE4_2,
  92   /* AVX support required */
  93   CpuAVX,
  94   /* AVX2 support required */
  95   CpuAVX2,
  96   /* Intel AVX-512 Foundation Instructions support required */
  97   CpuAVX512F,
  98   /* Intel AVX-512 Conflict Detection Instructions support required */
  99   CpuAVX512CD,
 100   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 101      required */
 102   CpuAVX512ER,
 103   /* Intel AVX-512 Prefetch Instructions support required */
 104   CpuAVX512PF,
 105   /* Intel AVX-512 VL Instructions support required.  */
 106   CpuAVX512VL,
 107   /* Intel AVX-512 DQ Instructions support required.  */
 108   CpuAVX512DQ,
 109   /* Intel AVX-512 BW Instructions support required.  */
 110   CpuAVX512BW,
 111   /* Intel L1OM support required */
 112   CpuL1OM,
 113   /* Intel K1OM support required */
 114   CpuK1OM,
 115   /* Intel IAMCU support required */
 116   CpuIAMCU,
 117   /* Xsave/xrstor New Instructions support required */
 118   CpuXsave,
 119   /* Xsaveopt New Instructions support required */
 120   CpuXsaveopt,
 121   /* AES support required */
 122   CpuAES,
 123   /* PCLMUL support required */
 124   CpuPCLMUL,
 125   /* FMA support required */
 126   CpuFMA,
 127   /* FMA4 support required */
 128   CpuFMA4,
 129   /* XOP support required */
 130   CpuXOP,
 131   /* LWP support required */
 132   CpuLWP,
 133   /* BMI support required */
 134   CpuBMI,
 135   /* TBM support required */
 136   CpuTBM,
 137   /* MOVBE Instruction support required */
 138   CpuMovbe,
 139   /* CMPXCHG16B instruction support required.  */
 140   CpuCX16,
 141   /* EPT Instructions required */
 142   CpuEPT,
 143   /* RDTSCP Instruction support required */
 144   CpuRdtscp,
 145   /* FSGSBASE Instructions required */
 146   CpuFSGSBase,
 147   /* RDRND Instructions required */
 148   CpuRdRnd,
 149   /* F16C Instructions required */
 150   CpuF16C,
 151   /* Intel BMI2 support required */
 152   CpuBMI2,
 153   /* LZCNT support required */
 154   CpuLZCNT,
 155   /* HLE support required */
 156   CpuHLE,
 157   /* RTM support required */
 158   CpuRTM,
 159   /* INVPCID Instructions required */
 160   CpuINVPCID,
 161   /* VMFUNC Instruction required */
 162   CpuVMFUNC,
 163   /* Intel MPX Instructions required  */
 164   CpuMPX,
 165   /* 64bit support available, used by -march= in assembler.  */
 166   CpuLM,
 167   /* RDRSEED instruction required.  */
 168   CpuRDSEED,
 169   /* Multi-presisionn add-carry instructions are required.  */
 170   CpuADX,
 171   /* Supports prefetchw and prefetch instructions.  */
 172   CpuPRFCHW,
 173   /* SMAP instructions required.  */
 174   CpuSMAP,
 175   /* SHA instructions required.  */
 176   CpuSHA,
 177   /* VREX support required  */
 178   CpuVREX,
 179   /* CLFLUSHOPT instruction required */
 180   CpuClflushOpt,
 181   /* XSAVES/XRSTORS instruction required */
 182   CpuXSAVES,
 183   /* XSAVEC instruction required */
 184   CpuXSAVEC,
 185   /* PREFETCHWT1 instruction required */
 186   CpuPREFETCHWT1,
 187   /* SE1 instruction required */
 188   CpuSE1,
 189   /* CLWB instruction required */
 190   CpuCLWB,
 191   /* Intel AVX-512 IFMA Instructions support required.  */
 192   CpuAVX512IFMA,
 193   /* Intel AVX-512 VBMI Instructions support required.  */
 194   CpuAVX512VBMI,
 195   /* Intel AVX-512 4FMAPS Instructions support required.  */
 196   CpuAVX512_4FMAPS,
 197   /* Intel AVX-512 4VNNIW Instructions support required.  */
 198   CpuAVX512_4VNNIW,
 199   /* Intel AVX-512 VPOPCNTDQ Instructions support required.  */
 200   CpuAVX512_VPOPCNTDQ,
 201   /* Intel AVX-512 VBMI2 Instructions support required.  */
 202   CpuAVX512_VBMI2,
 203   /* Intel AVX-512 VNNI Instructions support required.  */
 204   CpuAVX512_VNNI,
 205   /* Intel AVX-512 BITALG Instructions support required.  */
 206   CpuAVX512_BITALG,
 207   /* mwaitx instruction required */
 208   CpuMWAITX,
 209   /* Clzero instruction required */
 210   CpuCLZERO,
 211   /* OSPKE instruction required */
 212   CpuOSPKE,
 213   /* RDPID instruction required */
 214   CpuRDPID,
 215   /* PTWRITE instruction required */
 216   CpuPTWRITE,
 217   /* CET instructions support required */
 218   CpuIBT,
 219   CpuSHSTK,
 220   /* GFNI instructions required */
 221   CpuGFNI,
 222   /* VAES instructions required */
 223   CpuVAES,
 224   /* VPCLMULQDQ instructions required */
 225   CpuVPCLMULQDQ,
 226   /* WBNOINVD instructions required */
 227   CpuWBNOINVD,
 228   /* PCONFIG instructions required */
 229   CpuPCONFIG,
 230   /* WAITPKG instructions required */
 231   CpuWAITPKG,
 232   /* CLDEMOTE instruction required */
 233   CpuCLDEMOTE,
 234   /* MOVDIRI instruction support required */
 235   CpuMOVDIRI,
 236   /* MOVDIRR64B instruction required */
 237   CpuMOVDIR64B,
 238   /* 64bit support required  */
 239   Cpu64,
 240   /* Not supported in the 64bit mode  */
 241   CpuNo64,
 242   /* The last bitfield in i386_cpu_flags.  */
 243   CpuMax = CpuNo64
 244 };
 245
 246 #define CpuNumOfUints \
 247   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 248 #define CpuNumOfBits \
 249   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 250
 251 /* If you get a compiler error for zero width of the unused field,
 252    comment it out.  */
 253 #define CpuUnused       (CpuMax + 1)
 254
 255 /* We can check if an instruction is available with array instead
 256    of bitfield. */
 257 typedef union i386_cpu_flags
 258 {
 259   struct
 260     {
 261       unsigned int cpui186:1;
 262       unsigned int cpui286:1;
 263       unsigned int cpui386:1;
 264       unsigned int cpui486:1;
 265       unsigned int cpui586:1;
 266       unsigned int cpui686:1;
 267       unsigned int cpuclflush:1;
 268       unsigned int cpunop:1;
 269       unsigned int cpusyscall:1;
 270       unsigned int cpu8087:1;
 271       unsigned int cpu287:1;
 272       unsigned int cpu387:1;
 273       unsigned int cpu687:1;
 274       unsigned int cpufisttp:1;
 275       unsigned int cpummx:1;
 276       unsigned int cpusse:1;
 277       unsigned int cpusse2:1;
 278       unsigned int cpua3dnow:1;
 279       unsigned int cpua3dnowa:1;
 280       unsigned int cpusse3:1;
 281       unsigned int cpupadlock:1;
 282       unsigned int cpusvme:1;
 283       unsigned int cpuvmx:1;
 284       unsigned int cpusmx:1;
 285       unsigned int cpussse3:1;
 286       unsigned int cpusse4a:1;
 287       unsigned int cpuabm:1;
 288       unsigned int cpusse4_1:1;
 289       unsigned int cpusse4_2:1;
 290       unsigned int cpuavx:1;
 291       unsigned int cpuavx2:1;
 292       unsigned int cpuavx512f:1;
 293       unsigned int cpuavx512cd:1;
 294       unsigned int cpuavx512er:1;
 295       unsigned int cpuavx512pf:1;
 296       unsigned int cpuavx512vl:1;
 297       unsigned int cpuavx512dq:1;
 298       unsigned int cpuavx512bw:1;
 299       unsigned int cpul1om:1;
 300       unsigned int cpuk1om:1;
 301       unsigned int cpuiamcu:1;
 302       unsigned int cpuxsave:1;
 303       unsigned int cpuxsaveopt:1;
 304       unsigned int cpuaes:1;
 305       unsigned int cpupclmul:1;
 306       unsigned int cpufma:1;
 307       unsigned int cpufma4:1;
 308       unsigned int cpuxop:1;
 309       unsigned int cpulwp:1;
 310       unsigned int cpubmi:1;
 311       unsigned int cputbm:1;
 312       unsigned int cpumovbe:1;
 313       unsigned int cpucx16:1;
 314       unsigned int cpuept:1;
 315       unsigned int cpurdtscp:1;
 316       unsigned int cpufsgsbase:1;
 317       unsigned int cpurdrnd:1;
 318       unsigned int cpuf16c:1;
 319       unsigned int cpubmi2:1;
 320       unsigned int cpulzcnt:1;
 321       unsigned int cpuhle:1;
 322       unsigned int cpurtm:1;
 323       unsigned int cpuinvpcid:1;
 324       unsigned int cpuvmfunc:1;
 325       unsigned int cpumpx:1;
 326       unsigned int cpulm:1;
 327       unsigned int cpurdseed:1;
 328       unsigned int cpuadx:1;
 329       unsigned int cpuprfchw:1;
 330       unsigned int cpusmap:1;
 331       unsigned int cpusha:1;
 332       unsigned int cpuvrex:1;
 333       unsigned int cpuclflushopt:1;
 334       unsigned int cpuxsaves:1;
 335       unsigned int cpuxsavec:1;
 336       unsigned int cpuprefetchwt1:1;
 337       unsigned int cpuse1:1;
 338       unsigned int cpuclwb:1;
 339       unsigned int cpuavx512ifma:1;
 340       unsigned int cpuavx512vbmi:1;
 341       unsigned int cpuavx512_4fmaps:1;
 342       unsigned int cpuavx512_4vnniw:1;
 343       unsigned int cpuavx512_vpopcntdq:1;
 344       unsigned int cpuavx512_vbmi2:1;
 345       unsigned int cpuavx512_vnni:1;
 346       unsigned int cpuavx512_bitalg:1;
 347       unsigned int cpumwaitx:1;
 348       unsigned int cpuclzero:1;
 349       unsigned int cpuospke:1;
 350       unsigned int cpurdpid:1;
 351       unsigned int cpuptwrite:1;
 352       unsigned int cpuibt:1;
 353       unsigned int cpushstk:1;
 354       unsigned int cpugfni:1;
 355       unsigned int cpuvaes:1;
 356       unsigned int cpuvpclmulqdq:1;
 357       unsigned int cpuwbnoinvd:1;
 358       unsigned int cpupconfig:1;
 359       unsigned int cpuwaitpkg:1;
 360       unsigned int cpucldemote:1;
 361       unsigned int cpumovdiri:1;
 362       unsigned int cpumovdir64b:1;
 363       unsigned int cpu64:1;
 364       unsigned int cpuno64:1;
 365 #ifdef CpuUnused
 366       unsigned int unused:(CpuNumOfBits - CpuUnused);
 367 #endif
 368     } bitfield;
 369   unsigned int array[CpuNumOfUints];
 370 } i386_cpu_flags;
 371
 372 /* Position of opcode_modifier bits.  */
 373
 374 enum
 375 {
 376   /* has direction bit. */
 377   D = 0,
 378   /* set if operands can be words or dwords encoded the canonical way */
 379   W,
 380   /* load form instruction. Must be placed before store form.  */
 381   Load,
 382   /* insn has a modrm byte. */
 383   Modrm,
 384   /* register is in low 3 bits of opcode */
 385   ShortForm,
 386   /* special case for jump insns.  */
 387   Jump,
 388   /* call and jump */
 389   JumpDword,
 390   /* loop and jecxz */
 391   JumpByte,
 392   /* special case for intersegment leaps/calls */
 393   JumpInterSegment,
 394   /* FP insn memory format bit, sized by 0x4 */
 395   FloatMF,
 396   /* src/dest swap for floats. */
 397   FloatR,
 398   /* needs size prefix if in 32-bit mode */
 399   Size16,
 400   /* needs size prefix if in 16-bit mode */
 401   Size32,
 402   /* needs size prefix if in 64-bit mode */
 403   Size64,
 404   /* check register size.  */
 405   CheckRegSize,
 406   /* instruction ignores operand size prefix and in Intel mode ignores
 407      mnemonic size suffix check.  */
 408   IgnoreSize,
 409   /* default insn size depends on mode */
 410   DefaultSize,
 411   /* b suffix on instruction illegal */
 412   No_bSuf,
 413   /* w suffix on instruction illegal */
 414   No_wSuf,
 415   /* l suffix on instruction illegal */
 416   No_lSuf,
 417   /* s suffix on instruction illegal */
 418   No_sSuf,
 419   /* q suffix on instruction illegal */
 420   No_qSuf,
 421   /* long double suffix on instruction illegal */
 422   No_ldSuf,
 423   /* instruction needs FWAIT */
 424   FWait,
 425   /* quick test for string instructions */
 426   IsString,
 427   /* quick test if branch instruction is MPX supported */
 428   BNDPrefixOk,
 429   /* quick test if NOTRACK prefix is supported */
 430   NoTrackPrefixOk,
 431   /* quick test for lockable instructions */
 432   IsLockable,
 433   /* fake an extra reg operand for clr, imul and special register
 434      processing for some instructions.  */
 435   RegKludge,
 436   /* An implicit xmm0 as the first operand */
 437   Implicit1stXmm0,
 438   /* The HLE prefix is OK:
 439      1. With a LOCK prefix.
 440      2. With or without a LOCK prefix.
 441      3. With a RELEASE (0xf3) prefix.
 442    */
 443 #define HLEPrefixNone           0
 444 #define HLEPrefixLock           1
 445 #define HLEPrefixAny            2
 446 #define HLEPrefixRelease        3
 447   HLEPrefixOk,
 448   /* An instruction on which a "rep" prefix is acceptable.  */
 449   RepPrefixOk,
 450   /* Convert to DWORD */
 451   ToDword,
 452   /* Convert to QWORD */
 453   ToQword,
 454   /* Address prefix changes register operand */
 455   AddrPrefixOpReg,
 456   /* opcode is a prefix */
 457   IsPrefix,
 458   /* instruction has extension in 8 bit imm */
 459   ImmExt,
 460   /* instruction don't need Rex64 prefix.  */
 461   NoRex64,
 462   /* instruction require Rex64 prefix.  */
 463   Rex64,
 464   /* deprecated fp insn, gets a warning */
 465   Ugh,
 466   /* insn has VEX prefix:
 467         1: 128bit VEX prefix (or operand dependent).
 468         2: 256bit VEX prefix.
 469         3: Scalar VEX prefix.
 470    */
 471 #define VEX128          1
 472 #define VEX256          2
 473 #define VEXScalar       3
 474   Vex,
 475   /* How to encode VEX.vvvv:
 476      0: VEX.vvvv must be 1111b.
 477      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 478         the content of source registers will be preserved.
 479         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 480         where the content of first source register will be overwritten
 481         by the result.
 482         VEX.NDD2.  The second destination register operand is encoded in
 483         VEX.vvvv for instructions with 2 destination register operands.
 484         For assembler, there are no difference between VEX.NDS, VEX.DDS
 485         and VEX.NDD2.
 486      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 487      instructions with 1 destination register operand.
 488      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 489         of the operands can access a memory location.
 490    */
 491 #define VEXXDS  1
 492 #define VEXNDD  2
 493 #define VEXLWP  3
 494   VexVVVV,
 495   /* How the VEX.W bit is used:
 496      0: Set by the REX.W bit.
 497      1: VEX.W0.  Should always be 0.
 498      2: VEX.W1.  Should always be 1.
 499    */
 500 #define VEXW0   1
 501 #define VEXW1   2
 502   VexW,
 503   /* VEX opcode prefix:
 504      0: VEX 0x0F opcode prefix.
 505      1: VEX 0x0F38 opcode prefix.
 506      2: VEX 0x0F3A opcode prefix
 507      3: XOP 0x08 opcode prefix.
 508      4: XOP 0x09 opcode prefix
 509      5: XOP 0x0A opcode prefix.
 510    */
 511 #define VEX0F           0
 512 #define VEX0F38         1
 513 #define VEX0F3A         2
 514 #define XOP08           3
 515 #define XOP09           4
 516 #define XOP0A           5
 517   VexOpcode,
 518   /* number of VEX source operands:
 519      0: <= 2 source operands.
 520      1: 2 XOP source operands.
 521      2: 3 source operands.
 522    */
 523 #define XOP2SOURCES     1
 524 #define VEX3SOURCES     2
 525   VexSources,
 526   /* Instruction with vector SIB byte:
 527         1: 128bit vector register.
 528         2: 256bit vector register.
 529         3: 512bit vector register.
 530    */
 531 #define VecSIB128       1
 532 #define VecSIB256       2
 533 #define VecSIB512       3
 534   VecSIB,
 535   /* SSE to AVX support required */
 536   SSE2AVX,
 537   /* No AVX equivalent */
 538   NoAVX,
 539
 540   /* insn has EVEX prefix:
 541         1: 512bit EVEX prefix.
 542         2: 128bit EVEX prefix.
 543         3: 256bit EVEX prefix.
 544         4: Length-ignored (LIG) EVEX prefix.
 545         5: Length determined from actual operands.
 546    */
 547 #define EVEX512                1
 548 #define EVEX128                2
 549 #define EVEX256                3
 550 #define EVEXLIG                4
 551 #define EVEXDYN                5
 552   EVex,
 553
 554   /* AVX512 masking support:
 555         1: Zeroing-masking.
 556         2: Merging-masking.
 557         3: Both zeroing and merging masking.
 558    */
 559 #define ZEROING_MASKING 1
 560 #define MERGING_MASKING 2
 561 #define BOTH_MASKING    3
 562   Masking,
 563
 564   /* AVX512 broadcast support.  The number of bytes to broadcast is
 565      1 << (Broadcast - 1):
 566         1: Byte broadcast.
 567         2: Word broadcast.
 568         3: Dword broadcast.
 569         4: Qword broadcast.
 570    */
 571 #define BYTE_BROADCAST  1
 572 #define WORD_BROADCAST  2
 573 #define DWORD_BROADCAST 3
 574 #define QWORD_BROADCAST 4
 575   Broadcast,
 576
 577   /* Static rounding control is supported.  */
 578   StaticRounding,
 579
 580   /* Supress All Exceptions is supported.  */
 581   SAE,
 582
 583   /* Compressed Disp8*N attribute.  */
 584 #define DISP8_SHIFT_VL 7
 585   Disp8MemShift,
 586
 587   /* Default mask isn't allowed.  */
 588   NoDefMask,
 589
 590   /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
 591      It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
 592    */
 593   ImplicitQuadGroup,
 594
 595   /* Support encoding optimization.  */
 596   Optimize,
 597
 598   /* AT&T mnemonic.  */
 599   ATTMnemonic,
 600   /* AT&T syntax.  */
 601   ATTSyntax,
 602   /* Intel syntax.  */
 603   IntelSyntax,
 604   /* AMD64.  */
 605   AMD64,
 606   /* Intel64.  */
 607   Intel64,
 608   /* The last bitfield in i386_opcode_modifier.  */
 609   Opcode_Modifier_Max
 610 };
 611
 612 typedef struct i386_opcode_modifier
 613 {
 614   unsigned int d:1;
 615   unsigned int w:1;
 616   unsigned int load:1;
 617   unsigned int modrm:1;
 618   unsigned int shortform:1;
 619   unsigned int jump:1;
 620   unsigned int jumpdword:1;
 621   unsigned int jumpbyte:1;
 622   unsigned int jumpintersegment:1;
 623   unsigned int floatmf:1;
 624   unsigned int floatr:1;
 625   unsigned int size16:1;
 626   unsigned int size32:1;
 627   unsigned int size64:1;
 628   unsigned int checkregsize:1;
 629   unsigned int ignoresize:1;
 630   unsigned int defaultsize:1;
 631   unsigned int no_bsuf:1;
 632   unsigned int no_wsuf:1;
 633   unsigned int no_lsuf:1;
 634   unsigned int no_ssuf:1;
 635   unsigned int no_qsuf:1;
 636   unsigned int no_ldsuf:1;
 637   unsigned int fwait:1;
 638   unsigned int isstring:1;
 639   unsigned int bndprefixok:1;
 640   unsigned int notrackprefixok:1;
 641   unsigned int islockable:1;
 642   unsigned int regkludge:1;
 643   unsigned int implicit1stxmm0:1;
 644   unsigned int hleprefixok:2;
 645   unsigned int repprefixok:1;
 646   unsigned int todword:1;
 647   unsigned int toqword:1;
 648   unsigned int addrprefixopreg:1;
 649   unsigned int isprefix:1;
 650   unsigned int immext:1;
 651   unsigned int norex64:1;
 652   unsigned int rex64:1;
 653   unsigned int ugh:1;
 654   unsigned int vex:2;
 655   unsigned int vexvvvv:2;
 656   unsigned int vexw:2;
 657   unsigned int vexopcode:3;
 658   unsigned int vexsources:2;
 659   unsigned int vecsib:2;
 660   unsigned int sse2avx:1;
 661   unsigned int noavx:1;
 662   unsigned int evex:3;
 663   unsigned int masking:2;
 664   unsigned int broadcast:3;
 665   unsigned int staticrounding:1;
 666   unsigned int sae:1;
 667   unsigned int disp8memshift:3;
 668   unsigned int nodefmask:1;
 669   unsigned int implicitquadgroup:1;
 670   unsigned int optimize:1;
 671   unsigned int attmnemonic:1;
 672   unsigned int attsyntax:1;
 673   unsigned int intelsyntax:1;
 674   unsigned int amd64:1;
 675   unsigned int intel64:1;
 676 } i386_opcode_modifier;
 677
 678 /* Position of operand_type bits.  */
 679
 680 enum
 681 {
 682   /* Register (qualified by Byte, Word, etc) */
 683   Reg = 0,
 684   /* MMX register */
 685   RegMMX,
 686   /* Vector registers */
 687   RegSIMD,
 688   /* Vector Mask registers */
 689   RegMask,
 690   /* Control register */
 691   Control,
 692   /* Debug register */
 693   Debug,
 694   /* Test register */
 695   Test,
 696   /* 2 bit segment register */
 697   SReg2,
 698   /* 3 bit segment register */
 699   SReg3,
 700   /* 1 bit immediate */
 701   Imm1,
 702   /* 8 bit immediate */
 703   Imm8,
 704   /* 8 bit immediate sign extended */
 705   Imm8S,
 706   /* 16 bit immediate */
 707   Imm16,
 708   /* 32 bit immediate */
 709   Imm32,
 710   /* 32 bit immediate sign extended */
 711   Imm32S,
 712   /* 64 bit immediate */
 713   Imm64,
 714   /* 8bit/16bit/32bit displacements are used in different ways,
 715      depending on the instruction.  For jumps, they specify the
 716      size of the PC relative displacement, for instructions with
 717      memory operand, they specify the size of the offset relative
 718      to the base register, and for instructions with memory offset
 719      such as `mov 1234,%al' they specify the size of the offset
 720      relative to the segment base.  */
 721   /* 8 bit displacement */
 722   Disp8,
 723   /* 16 bit displacement */
 724   Disp16,
 725   /* 32 bit displacement */
 726   Disp32,
 727   /* 32 bit signed displacement */
 728   Disp32S,
 729   /* 64 bit displacement */
 730   Disp64,
 731   /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
 732   Acc,
 733   /* Register which can be used for base or index in memory operand.  */
 734   BaseIndex,
 735   /* Register to hold in/out port addr = dx */
 736   InOutPortReg,
 737   /* Register to hold shift count = cl */
 738   ShiftCount,
 739   /* Absolute address for jump.  */
 740   JumpAbsolute,
 741   /* String insn operand with fixed es segment */
 742   EsSeg,
 743   /* RegMem is for instructions with a modrm byte where the register
 744      destination operand should be encoded in the mod and regmem fields.
 745      Normally, it will be encoded in the reg field. We add a RegMem
 746      flag to the destination register operand to indicate that it should
 747      be encoded in the regmem field.  */
 748   RegMem,
 749   /* Memory.  */
 750   Mem,
 751   /* BYTE size. */
 752   Byte,
 753   /* WORD size. 2 byte */
 754   Word,
 755   /* DWORD size. 4 byte */
 756   Dword,
 757   /* FWORD size. 6 byte */
 758   Fword,
 759   /* QWORD size. 8 byte */
 760   Qword,
 761   /* TBYTE size. 10 byte */
 762   Tbyte,
 763   /* XMMWORD size. */
 764   Xmmword,
 765   /* YMMWORD size. */
 766   Ymmword,
 767   /* ZMMWORD size.  */
 768   Zmmword,
 769   /* Unspecified memory size.  */
 770   Unspecified,
 771   /* Any memory size.  */
 772   Anysize,
 773
 774   /* Vector 4 bit immediate.  */
 775   Vec_Imm4,
 776
 777   /* Bound register.  */
 778   RegBND,
 779
 780   /* The number of bitfields in i386_operand_type.  */
 781   OTNum
 782 };
 783
 784 #define OTNumOfUints \
 785   ((OTNum - 1) / sizeof (unsigned int) / CHAR_BIT + 1)
 786 #define OTNumOfBits \
 787   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 788
 789 /* If you get a compiler error for zero width of the unused field,
 790    comment it out.  */
 791 #define OTUnused                OTNum
 792
 793 typedef union i386_operand_type
 794 {
 795   struct
 796     {
 797       unsigned int reg:1;
 798       unsigned int regmmx:1;
 799       unsigned int regsimd:1;
 800       unsigned int regmask:1;
 801       unsigned int control:1;
 802       unsigned int debug:1;
 803       unsigned int test:1;
 804       unsigned int sreg2:1;
 805       unsigned int sreg3:1;
 806       unsigned int imm1:1;
 807       unsigned int imm8:1;
 808       unsigned int imm8s:1;
 809       unsigned int imm16:1;
 810       unsigned int imm32:1;
 811       unsigned int imm32s:1;
 812       unsigned int imm64:1;
 813       unsigned int disp8:1;
 814       unsigned int disp16:1;
 815       unsigned int disp32:1;
 816       unsigned int disp32s:1;
 817       unsigned int disp64:1;
 818       unsigned int acc:1;
 819       unsigned int baseindex:1;
 820       unsigned int inoutportreg:1;
 821       unsigned int shiftcount:1;
 822       unsigned int jumpabsolute:1;
 823       unsigned int esseg:1;
 824       unsigned int regmem:1;
 825       unsigned int mem:1;
 826       unsigned int byte:1;
 827       unsigned int word:1;
 828       unsigned int dword:1;
 829       unsigned int fword:1;
 830       unsigned int qword:1;
 831       unsigned int tbyte:1;
 832       unsigned int xmmword:1;
 833       unsigned int ymmword:1;
 834       unsigned int zmmword:1;
 835       unsigned int unspecified:1;
 836       unsigned int anysize:1;
 837       unsigned int vec_imm4:1;
 838       unsigned int regbnd:1;
 839 #ifdef OTUnused
 840       unsigned int unused:(OTNumOfBits - OTUnused);
 841 #endif
 842     } bitfield;
 843   unsigned int array[OTNumOfUints];
 844 } i386_operand_type;
 845
 846 typedef struct insn_template
 847 {
 848   /* instruction name sans width suffix ("mov" for movl insns) */
 849   char *name;
 850
 851   /* how many operands */
 852   unsigned int operands;
 853
 854   /* base_opcode is the fundamental opcode byte without optional
 855      prefix(es).  */
 856   unsigned int base_opcode;
 857 #define Opcode_D        0x2 /* Direction bit:
 858                                set if Reg --> Regmem;
 859                                unset if Regmem --> Reg. */
 860 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 861 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 862
 863   /* extension_opcode is the 3 bit extension for group <n> insns.
 864      This field is also used to store the 8-bit opcode suffix for the
 865      AMD 3DNow! instructions.
 866      If this template has no extension opcode (the usual case) use None
 867      Instructions */
 868   unsigned int extension_opcode;
 869 #define None 0xffff             /* If no extension_opcode is possible.  */
 870
 871   /* Opcode length.  */
 872   unsigned char opcode_length;
 873
 874   /* cpu feature flags */
 875   i386_cpu_flags cpu_flags;
 876
 877   /* the bits in opcode_modifier are used to generate the final opcode from
 878      the base_opcode.  These bits also are used to detect alternate forms of
 879      the same instruction */
 880   i386_opcode_modifier opcode_modifier;
 881
 882   /* operand_types[i] describes the type of operand i.  This is made
 883      by OR'ing together all of the possible type masks.  (e.g.
 884      'operand_types[i] = Reg|Imm' specifies that operand i can be
 885      either a register or an immediate operand.  */
 886   i386_operand_type operand_types[MAX_OPERANDS];
 887 }
 888 insn_template;
 889
 890 extern const insn_template i386_optab[];
 891
 892 /* these are for register name --> number & type hash lookup */
 893 typedef struct
 894 {
 895   char *reg_name;
 896   i386_operand_type reg_type;
 897   unsigned char reg_flags;
 898 #define RegRex      0x1  /* Extended register.  */
 899 #define RegRex64    0x2  /* Extended 8 bit register.  */
 900 #define RegVRex     0x4  /* Extended vector register.  */
 901   unsigned char reg_num;
 902 #define RegRip  ((unsigned char ) ~0)
 903 #define RegEip  (RegRip - 1)
 904 /* EIZ and RIZ are fake index registers.  */
 905 #define RegEiz  (RegEip - 1)
 906 #define RegRiz  (RegEiz - 1)
 907 /* FLAT is a fake segment register (Intel mode).  */
 908 #define RegFlat     ((unsigned char) ~0)
 909   signed char dw2_regnum[2];
 910 #define Dw2Inval (-1)
 911 }
 912 reg_entry;
 913
 914 /* Entries in i386_regtab.  */
 915 #define REGNAM_AL 1
 916 #define REGNAM_AX 25
 917 #define REGNAM_EAX 41
 918
 919 extern const reg_entry i386_regtab[];
 920 extern const unsigned int i386_regtab_size;
 921
 922 typedef struct
 923 {
 924   char *seg_name;
 925   unsigned int seg_prefix;
 926 }
 927 seg_entry;
 928
 929 extern const seg_entry cs;
 930 extern const seg_entry ds;
 931 extern const seg_entry ss;
 932 extern const seg_entry es;
 933 extern const seg_entry fs;
 934 extern const seg_entry gs;