opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2019 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #ifdef HAVE_LIMITS_H
  23 #include <limits.h>
  24 #endif
  25
  26 #ifndef CHAR_BIT
  27 #define CHAR_BIT 8
  28 #endif
  29
  30 /* Position of cpu flags bitfiled.  */
  31
  32 enum
  33 {
  34   /* i186 or better required */
  35   Cpu186 = 0,
  36   /* i286 or better required */
  37   Cpu286,
  38   /* i386 or better required */
  39   Cpu386,
  40   /* i486 or better required */
  41   Cpu486,
  42   /* i585 or better required */
  43   Cpu586,
  44   /* i686 or better required */
  45   Cpu686,
  46   /* CMOV Instruction support required */
  47   CpuCMOV,
  48   /* FXSR Instruction support required */
  49   CpuFXSR,
  50   /* CLFLUSH Instruction support required */
  51   CpuClflush,
  52   /* NOP Instruction support required */
  53   CpuNop,
  54   /* SYSCALL Instructions support required */
  55   CpuSYSCALL,
  56   /* Floating point support required */
  57   Cpu8087,
  58   /* i287 support required */
  59   Cpu287,
  60   /* i387 support required */
  61   Cpu387,
  62   /* i686 and floating point support required */
  63   Cpu687,
  64   /* SSE3 and floating point support required */
  65   CpuFISTTP,
  66   /* MMX support required */
  67   CpuMMX,
  68   /* SSE support required */
  69   CpuSSE,
  70   /* SSE2 support required */
  71   CpuSSE2,
  72   /* 3dnow! support required */
  73   Cpu3dnow,
  74   /* 3dnow! Extensions support required */
  75   Cpu3dnowA,
  76   /* SSE3 support required */
  77   CpuSSE3,
  78   /* VIA PadLock required */
  79   CpuPadLock,
  80   /* AMD Secure Virtual Machine Ext-s required */
  81   CpuSVME,
  82   /* VMX Instructions required */
  83   CpuVMX,
  84   /* SMX Instructions required */
  85   CpuSMX,
  86   /* SSSE3 support required */
  87   CpuSSSE3,
  88   /* SSE4a support required */
  89   CpuSSE4a,
  90   /* ABM New Instructions required */
  91   CpuABM,
  92   /* SSE4.1 support required */
  93   CpuSSE4_1,
  94   /* SSE4.2 support required */
  95   CpuSSE4_2,
  96   /* AVX support required */
  97   CpuAVX,
  98   /* AVX2 support required */
  99   CpuAVX2,
 100   /* Intel AVX-512 Foundation Instructions support required */
 101   CpuAVX512F,
 102   /* Intel AVX-512 Conflict Detection Instructions support required */
 103   CpuAVX512CD,
 104   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 105      required */
 106   CpuAVX512ER,
 107   /* Intel AVX-512 Prefetch Instructions support required */
 108   CpuAVX512PF,
 109   /* Intel AVX-512 VL Instructions support required.  */
 110   CpuAVX512VL,
 111   /* Intel AVX-512 DQ Instructions support required.  */
 112   CpuAVX512DQ,
 113   /* Intel AVX-512 BW Instructions support required.  */
 114   CpuAVX512BW,
 115   /* Intel L1OM support required */
 116   CpuL1OM,
 117   /* Intel K1OM support required */
 118   CpuK1OM,
 119   /* Intel IAMCU support required */
 120   CpuIAMCU,
 121   /* Xsave/xrstor New Instructions support required */
 122   CpuXsave,
 123   /* Xsaveopt New Instructions support required */
 124   CpuXsaveopt,
 125   /* AES support required */
 126   CpuAES,
 127   /* PCLMUL support required */
 128   CpuPCLMUL,
 129   /* FMA support required */
 130   CpuFMA,
 131   /* FMA4 support required */
 132   CpuFMA4,
 133   /* XOP support required */
 134   CpuXOP,
 135   /* LWP support required */
 136   CpuLWP,
 137   /* BMI support required */
 138   CpuBMI,
 139   /* TBM support required */
 140   CpuTBM,
 141   /* MOVBE Instruction support required */
 142   CpuMovbe,
 143   /* CMPXCHG16B instruction support required.  */
 144   CpuCX16,
 145   /* EPT Instructions required */
 146   CpuEPT,
 147   /* RDTSCP Instruction support required */
 148   CpuRdtscp,
 149   /* FSGSBASE Instructions required */
 150   CpuFSGSBase,
 151   /* RDRND Instructions required */
 152   CpuRdRnd,
 153   /* F16C Instructions required */
 154   CpuF16C,
 155   /* Intel BMI2 support required */
 156   CpuBMI2,
 157   /* LZCNT support required */
 158   CpuLZCNT,
 159   /* HLE support required */
 160   CpuHLE,
 161   /* RTM support required */
 162   CpuRTM,
 163   /* INVPCID Instructions required */
 164   CpuINVPCID,
 165   /* VMFUNC Instruction required */
 166   CpuVMFUNC,
 167   /* Intel MPX Instructions required  */
 168   CpuMPX,
 169   /* 64bit support available, used by -march= in assembler.  */
 170   CpuLM,
 171   /* RDRSEED instruction required.  */
 172   CpuRDSEED,
 173   /* Multi-presisionn add-carry instructions are required.  */
 174   CpuADX,
 175   /* Supports prefetchw and prefetch instructions.  */
 176   CpuPRFCHW,
 177   /* SMAP instructions required.  */
 178   CpuSMAP,
 179   /* SHA instructions required.  */
 180   CpuSHA,
 181   /* CLFLUSHOPT instruction required */
 182   CpuClflushOpt,
 183   /* XSAVES/XRSTORS instruction required */
 184   CpuXSAVES,
 185   /* XSAVEC instruction required */
 186   CpuXSAVEC,
 187   /* PREFETCHWT1 instruction required */
 188   CpuPREFETCHWT1,
 189   /* SE1 instruction required */
 190   CpuSE1,
 191   /* CLWB instruction required */
 192   CpuCLWB,
 193   /* Intel AVX-512 IFMA Instructions support required.  */
 194   CpuAVX512IFMA,
 195   /* Intel AVX-512 VBMI Instructions support required.  */
 196   CpuAVX512VBMI,
 197   /* Intel AVX-512 4FMAPS Instructions support required.  */
 198   CpuAVX512_4FMAPS,
 199   /* Intel AVX-512 4VNNIW Instructions support required.  */
 200   CpuAVX512_4VNNIW,
 201   /* Intel AVX-512 VPOPCNTDQ Instructions support required.  */
 202   CpuAVX512_VPOPCNTDQ,
 203   /* Intel AVX-512 VBMI2 Instructions support required.  */
 204   CpuAVX512_VBMI2,
 205   /* Intel AVX-512 VNNI Instructions support required.  */
 206   CpuAVX512_VNNI,
 207   /* Intel AVX-512 BITALG Instructions support required.  */
 208   CpuAVX512_BITALG,
 209   /* Intel AVX-512 BF16 Instructions support required.  */
 210   CpuAVX512_BF16,
 211   /* mwaitx instruction required */
 212   CpuMWAITX,
 213   /* Clzero instruction required */
 214   CpuCLZERO,
 215   /* OSPKE instruction required */
 216   CpuOSPKE,
 217   /* RDPID instruction required */
 218   CpuRDPID,
 219   /* PTWRITE instruction required */
 220   CpuPTWRITE,
 221   /* CET instructions support required */
 222   CpuIBT,
 223   CpuSHSTK,
 224   /* GFNI instructions required */
 225   CpuGFNI,
 226   /* VAES instructions required */
 227   CpuVAES,
 228   /* VPCLMULQDQ instructions required */
 229   CpuVPCLMULQDQ,
 230   /* WBNOINVD instructions required */
 231   CpuWBNOINVD,
 232   /* PCONFIG instructions required */
 233   CpuPCONFIG,
 234   /* WAITPKG instructions required */
 235   CpuWAITPKG,
 236   /* CLDEMOTE instruction required */
 237   CpuCLDEMOTE,
 238   /* MOVDIRI instruction support required */
 239   CpuMOVDIRI,
 240   /* MOVDIRR64B instruction required */
 241   CpuMOVDIR64B,
 242   /* ENQCMD instruction required */
 243   CpuENQCMD,
 244   /* 64bit support required  */
 245   Cpu64,
 246   /* Not supported in the 64bit mode  */
 247   CpuNo64,
 248   /* The last bitfield in i386_cpu_flags.  */
 249   CpuMax = CpuNo64
 250 };
 251
 252 #define CpuNumOfUints \
 253   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 254 #define CpuNumOfBits \
 255   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 256
 257 /* If you get a compiler error for zero width of the unused field,
 258    comment it out.  */
 259 #define CpuUnused       (CpuMax + 1)
 260
 261 /* We can check if an instruction is available with array instead
 262    of bitfield. */
 263 typedef union i386_cpu_flags
 264 {
 265   struct
 266     {
 267       unsigned int cpui186:1;
 268       unsigned int cpui286:1;
 269       unsigned int cpui386:1;
 270       unsigned int cpui486:1;
 271       unsigned int cpui586:1;
 272       unsigned int cpui686:1;
 273       unsigned int cpucmov:1;
 274       unsigned int cpufxsr:1;
 275       unsigned int cpuclflush:1;
 276       unsigned int cpunop:1;
 277       unsigned int cpusyscall:1;
 278       unsigned int cpu8087:1;
 279       unsigned int cpu287:1;
 280       unsigned int cpu387:1;
 281       unsigned int cpu687:1;
 282       unsigned int cpufisttp:1;
 283       unsigned int cpummx:1;
 284       unsigned int cpusse:1;
 285       unsigned int cpusse2:1;
 286       unsigned int cpua3dnow:1;
 287       unsigned int cpua3dnowa:1;
 288       unsigned int cpusse3:1;
 289       unsigned int cpupadlock:1;
 290       unsigned int cpusvme:1;
 291       unsigned int cpuvmx:1;
 292       unsigned int cpusmx:1;
 293       unsigned int cpussse3:1;
 294       unsigned int cpusse4a:1;
 295       unsigned int cpuabm:1;
 296       unsigned int cpusse4_1:1;
 297       unsigned int cpusse4_2:1;
 298       unsigned int cpuavx:1;
 299       unsigned int cpuavx2:1;
 300       unsigned int cpuavx512f:1;
 301       unsigned int cpuavx512cd:1;
 302       unsigned int cpuavx512er:1;
 303       unsigned int cpuavx512pf:1;
 304       unsigned int cpuavx512vl:1;
 305       unsigned int cpuavx512dq:1;
 306       unsigned int cpuavx512bw:1;
 307       unsigned int cpul1om:1;
 308       unsigned int cpuk1om:1;
 309       unsigned int cpuiamcu:1;
 310       unsigned int cpuxsave:1;
 311       unsigned int cpuxsaveopt:1;
 312       unsigned int cpuaes:1;
 313       unsigned int cpupclmul:1;
 314       unsigned int cpufma:1;
 315       unsigned int cpufma4:1;
 316       unsigned int cpuxop:1;
 317       unsigned int cpulwp:1;
 318       unsigned int cpubmi:1;
 319       unsigned int cputbm:1;
 320       unsigned int cpumovbe:1;
 321       unsigned int cpucx16:1;
 322       unsigned int cpuept:1;
 323       unsigned int cpurdtscp:1;
 324       unsigned int cpufsgsbase:1;
 325       unsigned int cpurdrnd:1;
 326       unsigned int cpuf16c:1;
 327       unsigned int cpubmi2:1;
 328       unsigned int cpulzcnt:1;
 329       unsigned int cpuhle:1;
 330       unsigned int cpurtm:1;
 331       unsigned int cpuinvpcid:1;
 332       unsigned int cpuvmfunc:1;
 333       unsigned int cpumpx:1;
 334       unsigned int cpulm:1;
 335       unsigned int cpurdseed:1;
 336       unsigned int cpuadx:1;
 337       unsigned int cpuprfchw:1;
 338       unsigned int cpusmap:1;
 339       unsigned int cpusha:1;
 340       unsigned int cpuclflushopt:1;
 341       unsigned int cpuxsaves:1;
 342       unsigned int cpuxsavec:1;
 343       unsigned int cpuprefetchwt1:1;
 344       unsigned int cpuse1:1;
 345       unsigned int cpuclwb:1;
 346       unsigned int cpuavx512ifma:1;
 347       unsigned int cpuavx512vbmi:1;
 348       unsigned int cpuavx512_4fmaps:1;
 349       unsigned int cpuavx512_4vnniw:1;
 350       unsigned int cpuavx512_vpopcntdq:1;
 351       unsigned int cpuavx512_vbmi2:1;
 352       unsigned int cpuavx512_vnni:1;
 353       unsigned int cpuavx512_bitalg:1;
 354       unsigned int cpuavx512_bf16:1;
 355       unsigned int cpumwaitx:1;
 356       unsigned int cpuclzero:1;
 357       unsigned int cpuospke:1;
 358       unsigned int cpurdpid:1;
 359       unsigned int cpuptwrite:1;
 360       unsigned int cpuibt:1;
 361       unsigned int cpushstk:1;
 362       unsigned int cpugfni:1;
 363       unsigned int cpuvaes:1;
 364       unsigned int cpuvpclmulqdq:1;
 365       unsigned int cpuwbnoinvd:1;
 366       unsigned int cpupconfig:1;
 367       unsigned int cpuwaitpkg:1;
 368       unsigned int cpucldemote:1;
 369       unsigned int cpumovdiri:1;
 370       unsigned int cpumovdir64b:1;
 371       unsigned int cpuenqcmd:1;
 372       unsigned int cpu64:1;
 373       unsigned int cpuno64:1;
 374 #ifdef CpuUnused
 375       unsigned int unused:(CpuNumOfBits - CpuUnused);
 376 #endif
 377     } bitfield;
 378   unsigned int array[CpuNumOfUints];
 379 } i386_cpu_flags;
 380
 381 /* Position of opcode_modifier bits.  */
 382
 383 enum
 384 {
 385   /* has direction bit. */
 386   D = 0,
 387   /* set if operands can be words or dwords encoded the canonical way */
 388   W,
 389   /* load form instruction. Must be placed before store form.  */
 390   Load,
 391   /* insn has a modrm byte. */
 392   Modrm,
 393   /* register is in low 3 bits of opcode */
 394   ShortForm,
 395   /* special case for jump insns.  */
 396   Jump,
 397   /* call and jump */
 398   JumpDword,
 399   /* loop and jecxz */
 400   JumpByte,
 401   /* special case for intersegment leaps/calls */
 402   JumpInterSegment,
 403   /* FP insn memory format bit, sized by 0x4 */
 404   FloatMF,
 405   /* src/dest swap for floats. */
 406   FloatR,
 407   /* needs size prefix if in 32-bit mode */
 408 #define SIZE16 1
 409   /* needs size prefix if in 16-bit mode */
 410 #define SIZE32 2
 411   /* needs size prefix if in 64-bit mode */
 412 #define SIZE64 3
 413   Size,
 414   /* check register size.  */
 415   CheckRegSize,
 416   /* instruction ignores operand size prefix and in Intel mode ignores
 417      mnemonic size suffix check.  */
 418   IgnoreSize,
 419   /* default insn size depends on mode */
 420   DefaultSize,
 421   /* b suffix on instruction illegal */
 422   No_bSuf,
 423   /* w suffix on instruction illegal */
 424   No_wSuf,
 425   /* l suffix on instruction illegal */
 426   No_lSuf,
 427   /* s suffix on instruction illegal */
 428   No_sSuf,
 429   /* q suffix on instruction illegal */
 430   No_qSuf,
 431   /* long double suffix on instruction illegal */
 432   No_ldSuf,
 433   /* instruction needs FWAIT */
 434   FWait,
 435   /* quick test for string instructions */
 436   IsString,
 437   /* quick test if branch instruction is MPX supported */
 438   BNDPrefixOk,
 439   /* quick test if NOTRACK prefix is supported */
 440   NoTrackPrefixOk,
 441   /* quick test for lockable instructions */
 442   IsLockable,
 443   /* fake an extra reg operand for clr, imul and special register
 444      processing for some instructions.  */
 445   RegKludge,
 446   /* An implicit xmm0 as the first operand */
 447   Implicit1stXmm0,
 448   /* The HLE prefix is OK:
 449      1. With a LOCK prefix.
 450      2. With or without a LOCK prefix.
 451      3. With a RELEASE (0xf3) prefix.
 452    */
 453 #define HLEPrefixNone           0
 454 #define HLEPrefixLock           1
 455 #define HLEPrefixAny            2
 456 #define HLEPrefixRelease        3
 457   HLEPrefixOk,
 458   /* An instruction on which a "rep" prefix is acceptable.  */
 459   RepPrefixOk,
 460   /* Convert to DWORD */
 461   ToDword,
 462   /* Convert to QWORD */
 463   ToQword,
 464   /* Address prefix changes register operand */
 465   AddrPrefixOpReg,
 466   /* opcode is a prefix */
 467   IsPrefix,
 468   /* instruction has extension in 8 bit imm */
 469   ImmExt,
 470   /* instruction don't need Rex64 prefix.  */
 471   NoRex64,
 472   /* instruction require Rex64 prefix.  */
 473   Rex64,
 474   /* deprecated fp insn, gets a warning */
 475   Ugh,
 476   /* insn has VEX prefix:
 477         1: 128bit VEX prefix (or operand dependent).
 478         2: 256bit VEX prefix.
 479         3: Scalar VEX prefix.
 480    */
 481 #define VEX128          1
 482 #define VEX256          2
 483 #define VEXScalar       3
 484   Vex,
 485   /* How to encode VEX.vvvv:
 486      0: VEX.vvvv must be 1111b.
 487      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 488         the content of source registers will be preserved.
 489         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 490         where the content of first source register will be overwritten
 491         by the result.
 492         VEX.NDD2.  The second destination register operand is encoded in
 493         VEX.vvvv for instructions with 2 destination register operands.
 494         For assembler, there are no difference between VEX.NDS, VEX.DDS
 495         and VEX.NDD2.
 496      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 497      instructions with 1 destination register operand.
 498      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 499         of the operands can access a memory location.
 500    */
 501 #define VEXXDS  1
 502 #define VEXNDD  2
 503 #define VEXLWP  3
 504   VexVVVV,
 505   /* How the VEX.W bit is used:
 506      0: Set by the REX.W bit.
 507      1: VEX.W0.  Should always be 0.
 508      2: VEX.W1.  Should always be 1.
 509      3: VEX.WIG. The VEX.W bit is ignored.
 510    */
 511 #define VEXW0   1
 512 #define VEXW1   2
 513 #define VEXWIG  3
 514   VexW,
 515   /* VEX opcode prefix:
 516      0: VEX 0x0F opcode prefix.
 517      1: VEX 0x0F38 opcode prefix.
 518      2: VEX 0x0F3A opcode prefix
 519      3: XOP 0x08 opcode prefix.
 520      4: XOP 0x09 opcode prefix
 521      5: XOP 0x0A opcode prefix.
 522    */
 523 #define VEX0F           0
 524 #define VEX0F38         1
 525 #define VEX0F3A         2
 526 #define XOP08           3
 527 #define XOP09           4
 528 #define XOP0A           5
 529   VexOpcode,
 530   /* number of VEX source operands:
 531      0: <= 2 source operands.
 532      1: 2 XOP source operands.
 533      2: 3 source operands.
 534    */
 535 #define XOP2SOURCES     1
 536 #define VEX3SOURCES     2
 537   VexSources,
 538   /* Instruction with vector SIB byte:
 539         1: 128bit vector register.
 540         2: 256bit vector register.
 541         3: 512bit vector register.
 542    */
 543 #define VecSIB128       1
 544 #define VecSIB256       2
 545 #define VecSIB512       3
 546   VecSIB,
 547   /* SSE to AVX support required */
 548   SSE2AVX,
 549   /* No AVX equivalent */
 550   NoAVX,
 551
 552   /* insn has EVEX prefix:
 553         1: 512bit EVEX prefix.
 554         2: 128bit EVEX prefix.
 555         3: 256bit EVEX prefix.
 556         4: Length-ignored (LIG) EVEX prefix.
 557         5: Length determined from actual operands.
 558    */
 559 #define EVEX512                1
 560 #define EVEX128                2
 561 #define EVEX256                3
 562 #define EVEXLIG                4
 563 #define EVEXDYN                5
 564   EVex,
 565
 566   /* AVX512 masking support:
 567         1: Zeroing or merging masking depending on operands.
 568         2: Merging-masking.
 569         3: Both zeroing and merging masking.
 570    */
 571 #define DYNAMIC_MASKING 1
 572 #define MERGING_MASKING 2
 573 #define BOTH_MASKING    3
 574   Masking,
 575
 576   /* AVX512 broadcast support.  The number of bytes to broadcast is
 577      1 << (Broadcast - 1):
 578         1: Byte broadcast.
 579         2: Word broadcast.
 580         3: Dword broadcast.
 581         4: Qword broadcast.
 582    */
 583 #define BYTE_BROADCAST  1
 584 #define WORD_BROADCAST  2
 585 #define DWORD_BROADCAST 3
 586 #define QWORD_BROADCAST 4
 587   Broadcast,
 588
 589   /* Static rounding control is supported.  */
 590   StaticRounding,
 591
 592   /* Supress All Exceptions is supported.  */
 593   SAE,
 594
 595   /* Compressed Disp8*N attribute.  */
 596 #define DISP8_SHIFT_VL 7
 597   Disp8MemShift,
 598
 599   /* Default mask isn't allowed.  */
 600   NoDefMask,
 601
 602   /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
 603      It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
 604    */
 605   ImplicitQuadGroup,
 606
 607   /* Support encoding optimization.  */
 608   Optimize,
 609
 610   /* AT&T mnemonic.  */
 611   ATTMnemonic,
 612   /* AT&T syntax.  */
 613   ATTSyntax,
 614   /* Intel syntax.  */
 615   IntelSyntax,
 616   /* AMD64.  */
 617   AMD64,
 618   /* Intel64.  */
 619   Intel64,
 620   /* The last bitfield in i386_opcode_modifier.  */
 621   Opcode_Modifier_Max
 622 };
 623
 624 typedef struct i386_opcode_modifier
 625 {
 626   unsigned int d:1;
 627   unsigned int w:1;
 628   unsigned int load:1;
 629   unsigned int modrm:1;
 630   unsigned int shortform:1;
 631   unsigned int jump:1;
 632   unsigned int jumpdword:1;
 633   unsigned int jumpbyte:1;
 634   unsigned int jumpintersegment:1;
 635   unsigned int floatmf:1;
 636   unsigned int floatr:1;
 637   unsigned int size:2;
 638   unsigned int checkregsize:1;
 639   unsigned int ignoresize:1;
 640   unsigned int defaultsize:1;
 641   unsigned int no_bsuf:1;
 642   unsigned int no_wsuf:1;
 643   unsigned int no_lsuf:1;
 644   unsigned int no_ssuf:1;
 645   unsigned int no_qsuf:1;
 646   unsigned int no_ldsuf:1;
 647   unsigned int fwait:1;
 648   unsigned int isstring:1;
 649   unsigned int bndprefixok:1;
 650   unsigned int notrackprefixok:1;
 651   unsigned int islockable:1;
 652   unsigned int regkludge:1;
 653   unsigned int implicit1stxmm0:1;
 654   unsigned int hleprefixok:2;
 655   unsigned int repprefixok:1;
 656   unsigned int todword:1;
 657   unsigned int toqword:1;
 658   unsigned int addrprefixopreg:1;
 659   unsigned int isprefix:1;
 660   unsigned int immext:1;
 661   unsigned int norex64:1;
 662   unsigned int rex64:1;
 663   unsigned int ugh:1;
 664   unsigned int vex:2;
 665   unsigned int vexvvvv:2;
 666   unsigned int vexw:2;
 667   unsigned int vexopcode:3;
 668   unsigned int vexsources:2;
 669   unsigned int vecsib:2;
 670   unsigned int sse2avx:1;
 671   unsigned int noavx:1;
 672   unsigned int evex:3;
 673   unsigned int masking:2;
 674   unsigned int broadcast:3;
 675   unsigned int staticrounding:1;
 676   unsigned int sae:1;
 677   unsigned int disp8memshift:3;
 678   unsigned int nodefmask:1;
 679   unsigned int implicitquadgroup:1;
 680   unsigned int optimize:1;
 681   unsigned int attmnemonic:1;
 682   unsigned int attsyntax:1;
 683   unsigned int intelsyntax:1;
 684   unsigned int amd64:1;
 685   unsigned int intel64:1;
 686 } i386_opcode_modifier;
 687
 688 /* Position of operand_type bits.  */
 689
 690 enum
 691 {
 692   /* Register (qualified by Byte, Word, etc) */
 693   Reg = 0,
 694   /* MMX register */
 695   RegMMX,
 696   /* Vector registers */
 697   RegSIMD,
 698   /* Vector Mask registers */
 699   RegMask,
 700   /* Control register */
 701   Control,
 702   /* Debug register */
 703   Debug,
 704   /* Test register */
 705   Test,
 706   /* 2 bit segment register */
 707   SReg2,
 708   /* 3 bit segment register */
 709   SReg3,
 710   /* 1 bit immediate */
 711   Imm1,
 712   /* 8 bit immediate */
 713   Imm8,
 714   /* 8 bit immediate sign extended */
 715   Imm8S,
 716   /* 16 bit immediate */
 717   Imm16,
 718   /* 32 bit immediate */
 719   Imm32,
 720   /* 32 bit immediate sign extended */
 721   Imm32S,
 722   /* 64 bit immediate */
 723   Imm64,
 724   /* 8bit/16bit/32bit displacements are used in different ways,
 725      depending on the instruction.  For jumps, they specify the
 726      size of the PC relative displacement, for instructions with
 727      memory operand, they specify the size of the offset relative
 728      to the base register, and for instructions with memory offset
 729      such as `mov 1234,%al' they specify the size of the offset
 730      relative to the segment base.  */
 731   /* 8 bit displacement */
 732   Disp8,
 733   /* 16 bit displacement */
 734   Disp16,
 735   /* 32 bit displacement */
 736   Disp32,
 737   /* 32 bit signed displacement */
 738   Disp32S,
 739   /* 64 bit displacement */
 740   Disp64,
 741   /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
 742   Acc,
 743   /* Register which can be used for base or index in memory operand.  */
 744   BaseIndex,
 745   /* Register to hold in/out port addr = dx */
 746   InOutPortReg,
 747   /* Register to hold shift count = cl */
 748   ShiftCount,
 749   /* Absolute address for jump.  */
 750   JumpAbsolute,
 751   /* String insn operand with fixed es segment */
 752   EsSeg,
 753   /* RegMem is for instructions with a modrm byte where the register
 754      destination operand should be encoded in the mod and regmem fields.
 755      Normally, it will be encoded in the reg field. We add a RegMem
 756      flag to the destination register operand to indicate that it should
 757      be encoded in the regmem field.  */
 758   RegMem,
 759   /* Memory.  */
 760   Mem,
 761   /* BYTE size. */
 762   Byte,
 763   /* WORD size. 2 byte */
 764   Word,
 765   /* DWORD size. 4 byte */
 766   Dword,
 767   /* FWORD size. 6 byte */
 768   Fword,
 769   /* QWORD size. 8 byte */
 770   Qword,
 771   /* TBYTE size. 10 byte */
 772   Tbyte,
 773   /* XMMWORD size. */
 774   Xmmword,
 775   /* YMMWORD size. */
 776   Ymmword,
 777   /* ZMMWORD size.  */
 778   Zmmword,
 779   /* Unspecified memory size.  */
 780   Unspecified,
 781   /* Any memory size.  */
 782   Anysize,
 783
 784   /* Vector 4 bit immediate.  */
 785   Vec_Imm4,
 786
 787   /* Bound register.  */
 788   RegBND,
 789
 790   /* The number of bitfields in i386_operand_type.  */
 791   OTNum
 792 };
 793
 794 #define OTNumOfUints \
 795   ((OTNum - 1) / sizeof (unsigned int) / CHAR_BIT + 1)
 796 #define OTNumOfBits \
 797   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 798
 799 /* If you get a compiler error for zero width of the unused field,
 800    comment it out.  */
 801 #define OTUnused                OTNum
 802
 803 typedef union i386_operand_type
 804 {
 805   struct
 806     {
 807       unsigned int reg:1;
 808       unsigned int regmmx:1;
 809       unsigned int regsimd:1;
 810       unsigned int regmask:1;
 811       unsigned int control:1;
 812       unsigned int debug:1;
 813       unsigned int test:1;
 814       unsigned int sreg2:1;
 815       unsigned int sreg3:1;
 816       unsigned int imm1:1;
 817       unsigned int imm8:1;
 818       unsigned int imm8s:1;
 819       unsigned int imm16:1;
 820       unsigned int imm32:1;
 821       unsigned int imm32s:1;
 822       unsigned int imm64:1;
 823       unsigned int disp8:1;
 824       unsigned int disp16:1;
 825       unsigned int disp32:1;
 826       unsigned int disp32s:1;
 827       unsigned int disp64:1;
 828       unsigned int acc:1;
 829       unsigned int baseindex:1;
 830       unsigned int inoutportreg:1;
 831       unsigned int shiftcount:1;
 832       unsigned int jumpabsolute:1;
 833       unsigned int esseg:1;
 834       unsigned int regmem:1;
 835       unsigned int byte:1;
 836       unsigned int word:1;
 837       unsigned int dword:1;
 838       unsigned int fword:1;
 839       unsigned int qword:1;
 840       unsigned int tbyte:1;
 841       unsigned int xmmword:1;
 842       unsigned int ymmword:1;
 843       unsigned int zmmword:1;
 844       unsigned int unspecified:1;
 845       unsigned int anysize:1;
 846       unsigned int vec_imm4:1;
 847       unsigned int regbnd:1;
 848 #ifdef OTUnused
 849       unsigned int unused:(OTNumOfBits - OTUnused);
 850 #endif
 851     } bitfield;
 852   unsigned int array[OTNumOfUints];
 853 } i386_operand_type;
 854
 855 typedef struct insn_template
 856 {
 857   /* instruction name sans width suffix ("mov" for movl insns) */
 858   char *name;
 859
 860   /* how many operands */
 861   unsigned int operands;
 862
 863   /* base_opcode is the fundamental opcode byte without optional
 864      prefix(es).  */
 865   unsigned int base_opcode;
 866 #define Opcode_D        0x2 /* Direction bit:
 867                                set if Reg --> Regmem;
 868                                unset if Regmem --> Reg. */
 869 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 870 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 871 #define Opcode_SIMD_FloatD 0x1 /* Direction bit for SIMD fp insns. */
 872 #define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */
 873
 874   /* extension_opcode is the 3 bit extension for group <n> insns.
 875      This field is also used to store the 8-bit opcode suffix for the
 876      AMD 3DNow! instructions.
 877      If this template has no extension opcode (the usual case) use None
 878      Instructions */
 879   unsigned int extension_opcode;
 880 #define None 0xffff             /* If no extension_opcode is possible.  */
 881
 882   /* Opcode length.  */
 883   unsigned char opcode_length;
 884
 885   /* cpu feature flags */
 886   i386_cpu_flags cpu_flags;
 887
 888   /* the bits in opcode_modifier are used to generate the final opcode from
 889      the base_opcode.  These bits also are used to detect alternate forms of
 890      the same instruction */
 891   i386_opcode_modifier opcode_modifier;
 892
 893   /* operand_types[i] describes the type of operand i.  This is made
 894      by OR'ing together all of the possible type masks.  (e.g.
 895      'operand_types[i] = Reg|Imm' specifies that operand i can be
 896      either a register or an immediate operand.  */
 897   i386_operand_type operand_types[MAX_OPERANDS];
 898 }
 899 insn_template;
 900
 901 extern const insn_template i386_optab[];
 902
 903 /* these are for register name --> number & type hash lookup */
 904 typedef struct
 905 {
 906   char *reg_name;
 907   i386_operand_type reg_type;
 908   unsigned char reg_flags;
 909 #define RegRex      0x1  /* Extended register.  */
 910 #define RegRex64    0x2  /* Extended 8 bit register.  */
 911 #define RegVRex     0x4  /* Extended vector register.  */
 912   unsigned char reg_num;
 913 #define RegIP   ((unsigned char ) ~0)
 914 /* EIZ and RIZ are fake index registers.  */
 915 #define RegIZ   (RegIP - 1)
 916 /* FLAT is a fake segment register (Intel mode).  */
 917 #define RegFlat     ((unsigned char) ~0)
 918   signed char dw2_regnum[2];
 919 #define Dw2Inval (-1)
 920 }
 921 reg_entry;
 922
 923 /* Entries in i386_regtab.  */
 924 #define REGNAM_AL 1
 925 #define REGNAM_AX 25
 926 #define REGNAM_EAX 41
 927
 928 extern const reg_entry i386_regtab[];
 929 extern const unsigned int i386_regtab_size;
 930
 931 typedef struct
 932 {
 933   char *seg_name;
 934   unsigned int seg_prefix;
 935 }
 936 seg_entry;
 937
 938 extern const seg_entry cs;
 939 extern const seg_entry ds;
 940 extern const seg_entry ss;
 941 extern const seg_entry es;
 942 extern const seg_entry fs;
 943 extern const seg_entry gs;