opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2017 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #ifdef HAVE_LIMITS_H
  23 #include <limits.h>
  24 #endif
  25
  26 #ifndef CHAR_BIT
  27 #define CHAR_BIT 8
  28 #endif
  29
  30 /* Position of cpu flags bitfiled.  */
  31
  32 enum
  33 {
  34   /* i186 or better required */
  35   Cpu186 = 0,
  36   /* i286 or better required */
  37   Cpu286,
  38   /* i386 or better required */
  39   Cpu386,
  40   /* i486 or better required */
  41   Cpu486,
  42   /* i585 or better required */
  43   Cpu586,
  44   /* i686 or better required */
  45   Cpu686,
  46   /* CLFLUSH Instruction support required */
  47   CpuClflush,
  48   /* NOP Instruction support required */
  49   CpuNop,
  50   /* SYSCALL Instructions support required */
  51   CpuSYSCALL,
  52   /* Floating point support required */
  53   Cpu8087,
  54   /* i287 support required */
  55   Cpu287,
  56   /* i387 support required */
  57   Cpu387,
  58   /* i686 and floating point support required */
  59   Cpu687,
  60   /* SSE3 and floating point support required */
  61   CpuFISTTP,
  62   /* MMX support required */
  63   CpuMMX,
  64   /* SSE support required */
  65   CpuSSE,
  66   /* SSE2 support required */
  67   CpuSSE2,
  68   /* 3dnow! support required */
  69   Cpu3dnow,
  70   /* 3dnow! Extensions support required */
  71   Cpu3dnowA,
  72   /* SSE3 support required */
  73   CpuSSE3,
  74   /* VIA PadLock required */
  75   CpuPadLock,
  76   /* AMD Secure Virtual Machine Ext-s required */
  77   CpuSVME,
  78   /* VMX Instructions required */
  79   CpuVMX,
  80   /* SMX Instructions required */
  81   CpuSMX,
  82   /* SSSE3 support required */
  83   CpuSSSE3,
  84   /* SSE4a support required */
  85   CpuSSE4a,
  86   /* ABM New Instructions required */
  87   CpuABM,
  88   /* SSE4.1 support required */
  89   CpuSSE4_1,
  90   /* SSE4.2 support required */
  91   CpuSSE4_2,
  92   /* AVX support required */
  93   CpuAVX,
  94   /* AVX2 support required */
  95   CpuAVX2,
  96   /* Intel AVX-512 Foundation Instructions support required */
  97   CpuAVX512F,
  98   /* Intel AVX-512 Conflict Detection Instructions support required */
  99   CpuAVX512CD,
 100   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 101      required */
 102   CpuAVX512ER,
 103   /* Intel AVX-512 Prefetch Instructions support required */
 104   CpuAVX512PF,
 105   /* Intel AVX-512 VL Instructions support required.  */
 106   CpuAVX512VL,
 107   /* Intel AVX-512 DQ Instructions support required.  */
 108   CpuAVX512DQ,
 109   /* Intel AVX-512 BW Instructions support required.  */
 110   CpuAVX512BW,
 111   /* Intel L1OM support required */
 112   CpuL1OM,
 113   /* Intel K1OM support required */
 114   CpuK1OM,
 115   /* Intel IAMCU support required */
 116   CpuIAMCU,
 117   /* Xsave/xrstor New Instructions support required */
 118   CpuXsave,
 119   /* Xsaveopt New Instructions support required */
 120   CpuXsaveopt,
 121   /* AES support required */
 122   CpuAES,
 123   /* PCLMUL support required */
 124   CpuPCLMUL,
 125   /* FMA support required */
 126   CpuFMA,
 127   /* FMA4 support required */
 128   CpuFMA4,
 129   /* XOP support required */
 130   CpuXOP,
 131   /* LWP support required */
 132   CpuLWP,
 133   /* BMI support required */
 134   CpuBMI,
 135   /* TBM support required */
 136   CpuTBM,
 137   /* MOVBE Instruction support required */
 138   CpuMovbe,
 139   /* CMPXCHG16B instruction support required.  */
 140   CpuCX16,
 141   /* EPT Instructions required */
 142   CpuEPT,
 143   /* RDTSCP Instruction support required */
 144   CpuRdtscp,
 145   /* FSGSBASE Instructions required */
 146   CpuFSGSBase,
 147   /* RDRND Instructions required */
 148   CpuRdRnd,
 149   /* F16C Instructions required */
 150   CpuF16C,
 151   /* Intel BMI2 support required */
 152   CpuBMI2,
 153   /* LZCNT support required */
 154   CpuLZCNT,
 155   /* HLE support required */
 156   CpuHLE,
 157   /* RTM support required */
 158   CpuRTM,
 159   /* INVPCID Instructions required */
 160   CpuINVPCID,
 161   /* VMFUNC Instruction required */
 162   CpuVMFUNC,
 163   /* Intel MPX Instructions required  */
 164   CpuMPX,
 165   /* 64bit support available, used by -march= in assembler.  */
 166   CpuLM,
 167   /* RDRSEED instruction required.  */
 168   CpuRDSEED,
 169   /* Multi-presisionn add-carry instructions are required.  */
 170   CpuADX,
 171   /* Supports prefetchw and prefetch instructions.  */
 172   CpuPRFCHW,
 173   /* SMAP instructions required.  */
 174   CpuSMAP,
 175   /* SHA instructions required.  */
 176   CpuSHA,
 177   /* VREX support required  */
 178   CpuVREX,
 179   /* CLFLUSHOPT instruction required */
 180   CpuClflushOpt,
 181   /* XSAVES/XRSTORS instruction required */
 182   CpuXSAVES,
 183   /* XSAVEC instruction required */
 184   CpuXSAVEC,
 185   /* PREFETCHWT1 instruction required */
 186   CpuPREFETCHWT1,
 187   /* SE1 instruction required */
 188   CpuSE1,
 189   /* CLWB instruction required */
 190   CpuCLWB,
 191   /* Intel AVX-512 IFMA Instructions support required.  */
 192   CpuAVX512IFMA,
 193   /* Intel AVX-512 VBMI Instructions support required.  */
 194   CpuAVX512VBMI,
 195   /* Intel AVX-512 4FMAPS Instructions support required.  */
 196   CpuAVX512_4FMAPS,
 197   /* Intel AVX-512 4VNNIW Instructions support required.  */
 198   CpuAVX512_4VNNIW,
 199   /* Intel AVX-512 VPOPCNTDQ Instructions support required.  */
 200   CpuAVX512_VPOPCNTDQ,
 201   /* mwaitx instruction required */
 202   CpuMWAITX,
 203   /* Clzero instruction required */
 204   CpuCLZERO,
 205   /* OSPKE instruction required */
 206   CpuOSPKE,
 207   /* RDPID instruction required */
 208   CpuRDPID,
 209   /* PTWRITE instruction required */
 210   CpuPTWRITE,
 211   /* CET instruction support required */
 212   CpuCET,
 213   /* MMX register support required */
 214   CpuRegMMX,
 215   /* XMM register support required */
 216   CpuRegXMM,
 217   /* YMM register support required */
 218   CpuRegYMM,
 219   /* ZMM register support required */
 220   CpuRegZMM,
 221   /* Mask register support required */
 222   CpuRegMask,
 223   /* 64bit support required  */
 224   Cpu64,
 225   /* Not supported in the 64bit mode  */
 226   CpuNo64,
 227   /* The last bitfield in i386_cpu_flags.  */
 228   CpuMax = CpuNo64
 229 };
 230
 231 #define CpuNumOfUints \
 232   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 233 #define CpuNumOfBits \
 234   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 235
 236 /* If you get a compiler error for zero width of the unused field,
 237    comment it out.  */
 238 #if 0
 239 #define CpuUnused       (CpuMax + 1)
 240 #endif
 241
 242 /* We can check if an instruction is available with array instead
 243    of bitfield. */
 244 typedef union i386_cpu_flags
 245 {
 246   struct
 247     {
 248       unsigned int cpui186:1;
 249       unsigned int cpui286:1;
 250       unsigned int cpui386:1;
 251       unsigned int cpui486:1;
 252       unsigned int cpui586:1;
 253       unsigned int cpui686:1;
 254       unsigned int cpuclflush:1;
 255       unsigned int cpunop:1;
 256       unsigned int cpusyscall:1;
 257       unsigned int cpu8087:1;
 258       unsigned int cpu287:1;
 259       unsigned int cpu387:1;
 260       unsigned int cpu687:1;
 261       unsigned int cpufisttp:1;
 262       unsigned int cpummx:1;
 263       unsigned int cpusse:1;
 264       unsigned int cpusse2:1;
 265       unsigned int cpua3dnow:1;
 266       unsigned int cpua3dnowa:1;
 267       unsigned int cpusse3:1;
 268       unsigned int cpupadlock:1;
 269       unsigned int cpusvme:1;
 270       unsigned int cpuvmx:1;
 271       unsigned int cpusmx:1;
 272       unsigned int cpussse3:1;
 273       unsigned int cpusse4a:1;
 274       unsigned int cpuabm:1;
 275       unsigned int cpusse4_1:1;
 276       unsigned int cpusse4_2:1;
 277       unsigned int cpuavx:1;
 278       unsigned int cpuavx2:1;
 279       unsigned int cpuavx512f:1;
 280       unsigned int cpuavx512cd:1;
 281       unsigned int cpuavx512er:1;
 282       unsigned int cpuavx512pf:1;
 283       unsigned int cpuavx512vl:1;
 284       unsigned int cpuavx512dq:1;
 285       unsigned int cpuavx512bw:1;
 286       unsigned int cpul1om:1;
 287       unsigned int cpuk1om:1;
 288       unsigned int cpuiamcu:1;
 289       unsigned int cpuxsave:1;
 290       unsigned int cpuxsaveopt:1;
 291       unsigned int cpuaes:1;
 292       unsigned int cpupclmul:1;
 293       unsigned int cpufma:1;
 294       unsigned int cpufma4:1;
 295       unsigned int cpuxop:1;
 296       unsigned int cpulwp:1;
 297       unsigned int cpubmi:1;
 298       unsigned int cputbm:1;
 299       unsigned int cpumovbe:1;
 300       unsigned int cpucx16:1;
 301       unsigned int cpuept:1;
 302       unsigned int cpurdtscp:1;
 303       unsigned int cpufsgsbase:1;
 304       unsigned int cpurdrnd:1;
 305       unsigned int cpuf16c:1;
 306       unsigned int cpubmi2:1;
 307       unsigned int cpulzcnt:1;
 308       unsigned int cpuhle:1;
 309       unsigned int cpurtm:1;
 310       unsigned int cpuinvpcid:1;
 311       unsigned int cpuvmfunc:1;
 312       unsigned int cpumpx:1;
 313       unsigned int cpulm:1;
 314       unsigned int cpurdseed:1;
 315       unsigned int cpuadx:1;
 316       unsigned int cpuprfchw:1;
 317       unsigned int cpusmap:1;
 318       unsigned int cpusha:1;
 319       unsigned int cpuvrex:1;
 320       unsigned int cpuclflushopt:1;
 321       unsigned int cpuxsaves:1;
 322       unsigned int cpuxsavec:1;
 323       unsigned int cpuprefetchwt1:1;
 324       unsigned int cpuse1:1;
 325       unsigned int cpuclwb:1;
 326       unsigned int cpuavx512ifma:1;
 327       unsigned int cpuavx512vbmi:1;
 328       unsigned int cpuavx512_4fmaps:1;
 329       unsigned int cpuavx512_4vnniw:1;
 330       unsigned int cpuavx512_vpopcntdq:1;
 331       unsigned int cpumwaitx:1;
 332       unsigned int cpuclzero:1;
 333       unsigned int cpuospke:1;
 334       unsigned int cpurdpid:1;
 335       unsigned int cpuptwrite:1;
 336       unsigned int cpucet:1;
 337       unsigned int cpuregmmx:1;
 338       unsigned int cpuregxmm:1;
 339       unsigned int cpuregymm:1;
 340       unsigned int cpuregzmm:1;
 341       unsigned int cpuregmask:1;
 342       unsigned int cpu64:1;
 343       unsigned int cpuno64:1;
 344 #ifdef CpuUnused
 345       unsigned int unused:(CpuNumOfBits - CpuUnused);
 346 #endif
 347     } bitfield;
 348   unsigned int array[CpuNumOfUints];
 349 } i386_cpu_flags;
 350
 351 /* Position of opcode_modifier bits.  */
 352
 353 enum
 354 {
 355   /* has direction bit. */
 356   D = 0,
 357   /* set if operands can be words or dwords encoded the canonical way */
 358   W,
 359   /* Skip the current insn and use the next insn in i386-opc.tbl to swap
 360      operand in encoding.  */
 361   S,
 362   /* insn has a modrm byte. */
 363   Modrm,
 364   /* register is in low 3 bits of opcode */
 365   ShortForm,
 366   /* special case for jump insns.  */
 367   Jump,
 368   /* call and jump */
 369   JumpDword,
 370   /* loop and jecxz */
 371   JumpByte,
 372   /* special case for intersegment leaps/calls */
 373   JumpInterSegment,
 374   /* FP insn memory format bit, sized by 0x4 */
 375   FloatMF,
 376   /* src/dest swap for floats. */
 377   FloatR,
 378   /* has float insn direction bit. */
 379   FloatD,
 380   /* needs size prefix if in 32-bit mode */
 381   Size16,
 382   /* needs size prefix if in 16-bit mode */
 383   Size32,
 384   /* needs size prefix if in 64-bit mode */
 385   Size64,
 386   /* check register size.  */
 387   CheckRegSize,
 388   /* instruction ignores operand size prefix and in Intel mode ignores
 389      mnemonic size suffix check.  */
 390   IgnoreSize,
 391   /* default insn size depends on mode */
 392   DefaultSize,
 393   /* b suffix on instruction illegal */
 394   No_bSuf,
 395   /* w suffix on instruction illegal */
 396   No_wSuf,
 397   /* l suffix on instruction illegal */
 398   No_lSuf,
 399   /* s suffix on instruction illegal */
 400   No_sSuf,
 401   /* q suffix on instruction illegal */
 402   No_qSuf,
 403   /* long double suffix on instruction illegal */
 404   No_ldSuf,
 405   /* instruction needs FWAIT */
 406   FWait,
 407   /* quick test for string instructions */
 408   IsString,
 409   /* quick test if branch instruction is MPX supported */
 410   BNDPrefixOk,
 411   /* quick test for lockable instructions */
 412   IsLockable,
 413   /* fake an extra reg operand for clr, imul and special register
 414      processing for some instructions.  */
 415   RegKludge,
 416   /* The first operand must be xmm0 */
 417   FirstXmm0,
 418   /* An implicit xmm0 as the first operand */
 419   Implicit1stXmm0,
 420   /* The HLE prefix is OK:
 421      1. With a LOCK prefix.
 422      2. With or without a LOCK prefix.
 423      3. With a RELEASE (0xf3) prefix.
 424    */
 425 #define HLEPrefixNone           0
 426 #define HLEPrefixLock           1
 427 #define HLEPrefixAny            2
 428 #define HLEPrefixRelease        3
 429   HLEPrefixOk,
 430   /* An instruction on which a "rep" prefix is acceptable.  */
 431   RepPrefixOk,
 432   /* Convert to DWORD */
 433   ToDword,
 434   /* Convert to QWORD */
 435   ToQword,
 436   /* Address prefix changes operand 0 */
 437   AddrPrefixOp0,
 438   /* opcode is a prefix */
 439   IsPrefix,
 440   /* instruction has extension in 8 bit imm */
 441   ImmExt,
 442   /* instruction don't need Rex64 prefix.  */
 443   NoRex64,
 444   /* instruction require Rex64 prefix.  */
 445   Rex64,
 446   /* deprecated fp insn, gets a warning */
 447   Ugh,
 448   /* insn has VEX prefix:
 449         1: 128bit VEX prefix.
 450         2: 256bit VEX prefix.
 451         3: Scalar VEX prefix.
 452    */
 453 #define VEX128          1
 454 #define VEX256          2
 455 #define VEXScalar       3
 456   Vex,
 457   /* How to encode VEX.vvvv:
 458      0: VEX.vvvv must be 1111b.
 459      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 460         the content of source registers will be preserved.
 461         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 462         where the content of first source register will be overwritten
 463         by the result.
 464         VEX.NDD2.  The second destination register operand is encoded in
 465         VEX.vvvv for instructions with 2 destination register operands.
 466         For assembler, there are no difference between VEX.NDS, VEX.DDS
 467         and VEX.NDD2.
 468      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 469      instructions with 1 destination register operand.
 470      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 471         of the operands can access a memory location.
 472    */
 473 #define VEXXDS  1
 474 #define VEXNDD  2
 475 #define VEXLWP  3
 476   VexVVVV,
 477   /* How the VEX.W bit is used:
 478      0: Set by the REX.W bit.
 479      1: VEX.W0.  Should always be 0.
 480      2: VEX.W1.  Should always be 1.
 481    */
 482 #define VEXW0   1
 483 #define VEXW1   2
 484   VexW,
 485   /* VEX opcode prefix:
 486      0: VEX 0x0F opcode prefix.
 487      1: VEX 0x0F38 opcode prefix.
 488      2: VEX 0x0F3A opcode prefix
 489      3: XOP 0x08 opcode prefix.
 490      4: XOP 0x09 opcode prefix
 491      5: XOP 0x0A opcode prefix.
 492    */
 493 #define VEX0F           0
 494 #define VEX0F38         1
 495 #define VEX0F3A         2
 496 #define XOP08           3
 497 #define XOP09           4
 498 #define XOP0A           5
 499   VexOpcode,
 500   /* number of VEX source operands:
 501      0: <= 2 source operands.
 502      1: 2 XOP source operands.
 503      2: 3 source operands.
 504    */
 505 #define XOP2SOURCES     1
 506 #define VEX3SOURCES     2
 507   VexSources,
 508   /* instruction has VEX 8 bit imm */
 509   VexImmExt,
 510   /* Instruction with vector SIB byte:
 511         1: 128bit vector register.
 512         2: 256bit vector register.
 513         3: 512bit vector register.
 514    */
 515 #define VecSIB128       1
 516 #define VecSIB256       2
 517 #define VecSIB512       3
 518   VecSIB,
 519   /* SSE to AVX support required */
 520   SSE2AVX,
 521   /* No AVX equivalent */
 522   NoAVX,
 523
 524   /* insn has EVEX prefix:
 525         1: 512bit EVEX prefix.
 526         2: 128bit EVEX prefix.
 527         3: 256bit EVEX prefix.
 528         4: Length-ignored (LIG) EVEX prefix.
 529    */
 530 #define EVEX512                1
 531 #define EVEX128                2
 532 #define EVEX256                3
 533 #define EVEXLIG                4
 534   EVex,
 535
 536   /* AVX512 masking support:
 537         1: Zeroing-masking.
 538         2: Merging-masking.
 539         3: Both zeroing and merging masking.
 540    */
 541 #define ZEROING_MASKING 1
 542 #define MERGING_MASKING 2
 543 #define BOTH_MASKING    3
 544   Masking,
 545
 546   /* Input element size of vector insn:
 547         0: 32bit.
 548         1: 64bit.
 549    */
 550   VecESize,
 551
 552   /* Broadcast factor.
 553         0: No broadcast.
 554         1: 1to16 broadcast.
 555         2: 1to8 broadcast.
 556    */
 557 #define NO_BROADCAST    0
 558 #define BROADCAST_1TO16 1
 559 #define BROADCAST_1TO8  2
 560 #define BROADCAST_1TO4  3
 561 #define BROADCAST_1TO2  4
 562   Broadcast,
 563
 564   /* Static rounding control is supported.  */
 565   StaticRounding,
 566
 567   /* Supress All Exceptions is supported.  */
 568   SAE,
 569
 570   /* Copressed Disp8*N attribute.  */
 571   Disp8MemShift,
 572
 573   /* Default mask isn't allowed.  */
 574   NoDefMask,
 575
 576   /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
 577      It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
 578    */
 579   ImplicitQuadGroup,
 580
 581   /* Compatible with old (<= 2.8.1) versions of gcc  */
 582   OldGcc,
 583   /* AT&T mnemonic.  */
 584   ATTMnemonic,
 585   /* AT&T syntax.  */
 586   ATTSyntax,
 587   /* Intel syntax.  */
 588   IntelSyntax,
 589   /* AMD64.  */
 590   AMD64,
 591   /* Intel64.  */
 592   Intel64,
 593   /* The last bitfield in i386_opcode_modifier.  */
 594   Opcode_Modifier_Max
 595 };
 596
 597 typedef struct i386_opcode_modifier
 598 {
 599   unsigned int d:1;
 600   unsigned int w:1;
 601   unsigned int s:1;
 602   unsigned int modrm:1;
 603   unsigned int shortform:1;
 604   unsigned int jump:1;
 605   unsigned int jumpdword:1;
 606   unsigned int jumpbyte:1;
 607   unsigned int jumpintersegment:1;
 608   unsigned int floatmf:1;
 609   unsigned int floatr:1;
 610   unsigned int floatd:1;
 611   unsigned int size16:1;
 612   unsigned int size32:1;
 613   unsigned int size64:1;
 614   unsigned int checkregsize:1;
 615   unsigned int ignoresize:1;
 616   unsigned int defaultsize:1;
 617   unsigned int no_bsuf:1;
 618   unsigned int no_wsuf:1;
 619   unsigned int no_lsuf:1;
 620   unsigned int no_ssuf:1;
 621   unsigned int no_qsuf:1;
 622   unsigned int no_ldsuf:1;
 623   unsigned int fwait:1;
 624   unsigned int isstring:1;
 625   unsigned int bndprefixok:1;
 626   unsigned int islockable:1;
 627   unsigned int regkludge:1;
 628   unsigned int firstxmm0:1;
 629   unsigned int implicit1stxmm0:1;
 630   unsigned int hleprefixok:2;
 631   unsigned int repprefixok:1;
 632   unsigned int todword:1;
 633   unsigned int toqword:1;
 634   unsigned int addrprefixop0:1;
 635   unsigned int isprefix:1;
 636   unsigned int immext:1;
 637   unsigned int norex64:1;
 638   unsigned int rex64:1;
 639   unsigned int ugh:1;
 640   unsigned int vex:2;
 641   unsigned int vexvvvv:2;
 642   unsigned int vexw:2;
 643   unsigned int vexopcode:3;
 644   unsigned int vexsources:2;
 645   unsigned int veximmext:1;
 646   unsigned int vecsib:2;
 647   unsigned int sse2avx:1;
 648   unsigned int noavx:1;
 649   unsigned int evex:3;
 650   unsigned int masking:2;
 651   unsigned int vecesize:1;
 652   unsigned int broadcast:3;
 653   unsigned int staticrounding:1;
 654   unsigned int sae:1;
 655   unsigned int disp8memshift:3;
 656   unsigned int nodefmask:1;
 657   unsigned int implicitquadgroup:1;
 658   unsigned int oldgcc:1;
 659   unsigned int attmnemonic:1;
 660   unsigned int attsyntax:1;
 661   unsigned int intelsyntax:1;
 662   unsigned int amd64:1;
 663   unsigned int intel64:1;
 664 } i386_opcode_modifier;
 665
 666 /* Position of operand_type bits.  */
 667
 668 enum
 669 {
 670   /* 8bit register */
 671   Reg8 = 0,
 672   /* 16bit register */
 673   Reg16,
 674   /* 32bit register */
 675   Reg32,
 676   /* 64bit register */
 677   Reg64,
 678   /* Floating pointer stack register */
 679   FloatReg,
 680   /* MMX register */
 681   RegMMX,
 682   /* SSE register */
 683   RegXMM,
 684   /* AVX registers */
 685   RegYMM,
 686   /* AVX512 registers */
 687   RegZMM,
 688   /* Vector Mask registers */
 689   RegMask,
 690   /* Control register */
 691   Control,
 692   /* Debug register */
 693   Debug,
 694   /* Test register */
 695   Test,
 696   /* 2 bit segment register */
 697   SReg2,
 698   /* 3 bit segment register */
 699   SReg3,
 700   /* 1 bit immediate */
 701   Imm1,
 702   /* 8 bit immediate */
 703   Imm8,
 704   /* 8 bit immediate sign extended */
 705   Imm8S,
 706   /* 16 bit immediate */
 707   Imm16,
 708   /* 32 bit immediate */
 709   Imm32,
 710   /* 32 bit immediate sign extended */
 711   Imm32S,
 712   /* 64 bit immediate */
 713   Imm64,
 714   /* 8bit/16bit/32bit displacements are used in different ways,
 715      depending on the instruction.  For jumps, they specify the
 716      size of the PC relative displacement, for instructions with
 717      memory operand, they specify the size of the offset relative
 718      to the base register, and for instructions with memory offset
 719      such as `mov 1234,%al' they specify the size of the offset
 720      relative to the segment base.  */
 721   /* 8 bit displacement */
 722   Disp8,
 723   /* 16 bit displacement */
 724   Disp16,
 725   /* 32 bit displacement */
 726   Disp32,
 727   /* 32 bit signed displacement */
 728   Disp32S,
 729   /* 64 bit displacement */
 730   Disp64,
 731   /* Accumulator %al/%ax/%eax/%rax */
 732   Acc,
 733   /* Floating pointer top stack register %st(0) */
 734   FloatAcc,
 735   /* Register which can be used for base or index in memory operand.  */
 736   BaseIndex,
 737   /* Register to hold in/out port addr = dx */
 738   InOutPortReg,
 739   /* Register to hold shift count = cl */
 740   ShiftCount,
 741   /* Absolute address for jump.  */
 742   JumpAbsolute,
 743   /* String insn operand with fixed es segment */
 744   EsSeg,
 745   /* RegMem is for instructions with a modrm byte where the register
 746      destination operand should be encoded in the mod and regmem fields.
 747      Normally, it will be encoded in the reg field. We add a RegMem
 748      flag to the destination register operand to indicate that it should
 749      be encoded in the regmem field.  */
 750   RegMem,
 751   /* Memory.  */
 752   Mem,
 753   /* BYTE memory. */
 754   Byte,
 755   /* WORD memory. 2 byte */
 756   Word,
 757   /* DWORD memory. 4 byte */
 758   Dword,
 759   /* FWORD memory. 6 byte */
 760   Fword,
 761   /* QWORD memory. 8 byte */
 762   Qword,
 763   /* TBYTE memory. 10 byte */
 764   Tbyte,
 765   /* XMMWORD memory. */
 766   Xmmword,
 767   /* YMMWORD memory. */
 768   Ymmword,
 769   /* ZMMWORD memory.  */
 770   Zmmword,
 771   /* Unspecified memory size.  */
 772   Unspecified,
 773   /* Any memory size.  */
 774   Anysize,
 775
 776   /* Vector 4 bit immediate.  */
 777   Vec_Imm4,
 778
 779   /* Bound register.  */
 780   RegBND,
 781
 782   /* Vector 8bit displacement */
 783   Vec_Disp8,
 784
 785   /* The last bitfield in i386_operand_type.  */
 786   OTMax
 787 };
 788
 789 #define OTNumOfUints \
 790   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 791 #define OTNumOfBits \
 792   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 793
 794 /* If you get a compiler error for zero width of the unused field,
 795    comment it out.  */
 796 #define OTUnused                (OTMax + 1)
 797
 798 typedef union i386_operand_type
 799 {
 800   struct
 801     {
 802       unsigned int reg8:1;
 803       unsigned int reg16:1;
 804       unsigned int reg32:1;
 805       unsigned int reg64:1;
 806       unsigned int floatreg:1;
 807       unsigned int regmmx:1;
 808       unsigned int regxmm:1;
 809       unsigned int regymm:1;
 810       unsigned int regzmm:1;
 811       unsigned int regmask:1;
 812       unsigned int control:1;
 813       unsigned int debug:1;
 814       unsigned int test:1;
 815       unsigned int sreg2:1;
 816       unsigned int sreg3:1;
 817       unsigned int imm1:1;
 818       unsigned int imm8:1;
 819       unsigned int imm8s:1;
 820       unsigned int imm16:1;
 821       unsigned int imm32:1;
 822       unsigned int imm32s:1;
 823       unsigned int imm64:1;
 824       unsigned int disp8:1;
 825       unsigned int disp16:1;
 826       unsigned int disp32:1;
 827       unsigned int disp32s:1;
 828       unsigned int disp64:1;
 829       unsigned int acc:1;
 830       unsigned int floatacc:1;
 831       unsigned int baseindex:1;
 832       unsigned int inoutportreg:1;
 833       unsigned int shiftcount:1;
 834       unsigned int jumpabsolute:1;
 835       unsigned int esseg:1;
 836       unsigned int regmem:1;
 837       unsigned int mem:1;
 838       unsigned int byte:1;
 839       unsigned int word:1;
 840       unsigned int dword:1;
 841       unsigned int fword:1;
 842       unsigned int qword:1;
 843       unsigned int tbyte:1;
 844       unsigned int xmmword:1;
 845       unsigned int ymmword:1;
 846       unsigned int zmmword:1;
 847       unsigned int unspecified:1;
 848       unsigned int anysize:1;
 849       unsigned int vec_imm4:1;
 850       unsigned int regbnd:1;
 851       unsigned int vec_disp8:1;
 852 #ifdef OTUnused
 853       unsigned int unused:(OTNumOfBits - OTUnused);
 854 #endif
 855     } bitfield;
 856   unsigned int array[OTNumOfUints];
 857 } i386_operand_type;
 858
 859 typedef struct insn_template
 860 {
 861   /* instruction name sans width suffix ("mov" for movl insns) */
 862   char *name;
 863
 864   /* how many operands */
 865   unsigned int operands;
 866
 867   /* base_opcode is the fundamental opcode byte without optional
 868      prefix(es).  */
 869   unsigned int base_opcode;
 870 #define Opcode_D        0x2 /* Direction bit:
 871                                set if Reg --> Regmem;
 872                                unset if Regmem --> Reg. */
 873 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 874 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 875
 876   /* extension_opcode is the 3 bit extension for group <n> insns.
 877      This field is also used to store the 8-bit opcode suffix for the
 878      AMD 3DNow! instructions.
 879      If this template has no extension opcode (the usual case) use None
 880      Instructions */
 881   unsigned int extension_opcode;
 882 #define None 0xffff             /* If no extension_opcode is possible.  */
 883
 884   /* Opcode length.  */
 885   unsigned char opcode_length;
 886
 887   /* cpu feature flags */
 888   i386_cpu_flags cpu_flags;
 889
 890   /* the bits in opcode_modifier are used to generate the final opcode from
 891      the base_opcode.  These bits also are used to detect alternate forms of
 892      the same instruction */
 893   i386_opcode_modifier opcode_modifier;
 894
 895   /* operand_types[i] describes the type of operand i.  This is made
 896      by OR'ing together all of the possible type masks.  (e.g.
 897      'operand_types[i] = Reg|Imm' specifies that operand i can be
 898      either a register or an immediate operand.  */
 899   i386_operand_type operand_types[MAX_OPERANDS];
 900 }
 901 insn_template;
 902
 903 extern const insn_template i386_optab[];
 904
 905 /* these are for register name --> number & type hash lookup */
 906 typedef struct
 907 {
 908   char *reg_name;
 909   i386_operand_type reg_type;
 910   unsigned char reg_flags;
 911 #define RegRex      0x1  /* Extended register.  */
 912 #define RegRex64    0x2  /* Extended 8 bit register.  */
 913 #define RegVRex     0x4  /* Extended vector register.  */
 914   unsigned char reg_num;
 915 #define RegRip  ((unsigned char ) ~0)
 916 #define RegEip  (RegRip - 1)
 917 /* EIZ and RIZ are fake index registers.  */
 918 #define RegEiz  (RegEip - 1)
 919 #define RegRiz  (RegEiz - 1)
 920 /* FLAT is a fake segment register (Intel mode).  */
 921 #define RegFlat     ((unsigned char) ~0)
 922   signed char dw2_regnum[2];
 923 #define Dw2Inval (-1)
 924 }
 925 reg_entry;
 926
 927 /* Entries in i386_regtab.  */
 928 #define REGNAM_AL 1
 929 #define REGNAM_AX 25
 930 #define REGNAM_EAX 41
 931
 932 extern const reg_entry i386_regtab[];
 933 extern const unsigned int i386_regtab_size;
 934
 935 typedef struct
 936 {
 937   char *seg_name;
 938   unsigned int seg_prefix;
 939 }
 940 seg_entry;
 941
 942 extern const seg_entry cs;
 943 extern const seg_entry ds;
 944 extern const seg_entry ss;
 945 extern const seg_entry es;
 946 extern const seg_entry fs;
 947 extern const seg_entry gs;