opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2014 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #ifdef HAVE_LIMITS_H
  23 #include <limits.h>
  24 #endif
  25
  26 #ifndef CHAR_BIT
  27 #define CHAR_BIT 8
  28 #endif
  29
  30 /* Position of cpu flags bitfiled.  */
  31
  32 enum
  33 {
  34   /* i186 or better required */
  35   Cpu186 = 0,
  36   /* i286 or better required */
  37   Cpu286,
  38   /* i386 or better required */
  39   Cpu386,
  40   /* i486 or better required */
  41   Cpu486,
  42   /* i585 or better required */
  43   Cpu586,
  44   /* i686 or better required */
  45   Cpu686,
  46   /* CLFLUSH Instruction support required */
  47   CpuClflush,
  48   /* NOP Instruction support required */
  49   CpuNop,
  50   /* SYSCALL Instructions support required */
  51   CpuSYSCALL,
  52   /* Floating point support required */
  53   Cpu8087,
  54   /* i287 support required */
  55   Cpu287,
  56   /* i387 support required */
  57   Cpu387,
  58   /* i686 and floating point support required */
  59   Cpu687,
  60   /* SSE3 and floating point support required */
  61   CpuFISTTP,
  62   /* MMX support required */
  63   CpuMMX,
  64   /* SSE support required */
  65   CpuSSE,
  66   /* SSE2 support required */
  67   CpuSSE2,
  68   /* 3dnow! support required */
  69   Cpu3dnow,
  70   /* 3dnow! Extensions support required */
  71   Cpu3dnowA,
  72   /* SSE3 support required */
  73   CpuSSE3,
  74   /* VIA PadLock required */
  75   CpuPadLock,
  76   /* AMD Secure Virtual Machine Ext-s required */
  77   CpuSVME,
  78   /* VMX Instructions required */
  79   CpuVMX,
  80   /* SMX Instructions required */
  81   CpuSMX,
  82   /* SSSE3 support required */
  83   CpuSSSE3,
  84   /* SSE4a support required */
  85   CpuSSE4a,
  86   /* ABM New Instructions required */
  87   CpuABM,
  88   /* SSE4.1 support required */
  89   CpuSSE4_1,
  90   /* SSE4.2 support required */
  91   CpuSSE4_2,
  92   /* AVX support required */
  93   CpuAVX,
  94   /* AVX2 support required */
  95   CpuAVX2,
  96   /* Intel AVX-512 Foundation Instructions support required */
  97   CpuAVX512F,
  98   /* Intel AVX-512 Conflict Detection Instructions support required */
  99   CpuAVX512CD,
 100   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 101      required */
 102   CpuAVX512ER,
 103   /* Intel AVX-512 Prefetch Instructions support required */
 104   CpuAVX512PF,
 105   /* Intel AVX-512 VL Instructions support required.  */
 106   CpuAVX512VL,
 107   /* Intel AVX-512 DQ Instructions support required.  */
 108   CpuAVX512DQ,
 109   /* Intel AVX-512 BW Instructions support required.  */
 110   CpuAVX512BW,
 111   /* Intel L1OM support required */
 112   CpuL1OM,
 113   /* Intel K1OM support required */
 114   CpuK1OM,
 115   /* Xsave/xrstor New Instructions support required */
 116   CpuXsave,
 117   /* Xsaveopt New Instructions support required */
 118   CpuXsaveopt,
 119   /* AES support required */
 120   CpuAES,
 121   /* PCLMUL support required */
 122   CpuPCLMUL,
 123   /* FMA support required */
 124   CpuFMA,
 125   /* FMA4 support required */
 126   CpuFMA4,
 127   /* XOP support required */
 128   CpuXOP,
 129   /* LWP support required */
 130   CpuLWP,
 131   /* BMI support required */
 132   CpuBMI,
 133   /* TBM support required */
 134   CpuTBM,
 135   /* MOVBE Instruction support required */
 136   CpuMovbe,
 137   /* CMPXCHG16B instruction support required.  */
 138   CpuCX16,
 139   /* EPT Instructions required */
 140   CpuEPT,
 141   /* RDTSCP Instruction support required */
 142   CpuRdtscp,
 143   /* FSGSBASE Instructions required */
 144   CpuFSGSBase,
 145   /* RDRND Instructions required */
 146   CpuRdRnd,
 147   /* F16C Instructions required */
 148   CpuF16C,
 149   /* Intel BMI2 support required */
 150   CpuBMI2,
 151   /* LZCNT support required */
 152   CpuLZCNT,
 153   /* HLE support required */
 154   CpuHLE,
 155   /* RTM support required */
 156   CpuRTM,
 157   /* INVPCID Instructions required */
 158   CpuINVPCID,
 159   /* VMFUNC Instruction required */
 160   CpuVMFUNC,
 161   /* Intel MPX Instructions required  */
 162   CpuMPX,
 163   /* 64bit support available, used by -march= in assembler.  */
 164   CpuLM,
 165   /* RDRSEED instruction required.  */
 166   CpuRDSEED,
 167   /* Multi-presisionn add-carry instructions are required.  */
 168   CpuADX,
 169   /* Supports prefetchw and prefetch instructions.  */
 170   CpuPRFCHW,
 171   /* SMAP instructions required.  */
 172   CpuSMAP,
 173   /* SHA instructions required.  */
 174   CpuSHA,
 175   /* VREX support required  */
 176   CpuVREX,
 177   /* CLFLUSHOPT instruction required */
 178   CpuClflushOpt,
 179   /* XSAVES/XRSTORS instruction required */
 180   CpuXSAVES,
 181   /* XSAVEC instruction required */
 182   CpuXSAVEC,
 183   /* PREFETCHWT1 instruction required */
 184   CpuPREFETCHWT1,
 185   /* SE1 instruction required */
 186   CpuSE1,
 187   /* 64bit support required  */
 188   Cpu64,
 189   /* Not supported in the 64bit mode  */
 190   CpuNo64,
 191   /* The last bitfield in i386_cpu_flags.  */
 192   CpuMax = CpuNo64
 193 };
 194
 195 #define CpuNumOfUints \
 196   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 197 #define CpuNumOfBits \
 198   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 199
 200 /* If you get a compiler error for zero width of the unused field,
 201    comment it out.  */
 202 #define CpuUnused       (CpuMax + 1)
 203
 204 /* We can check if an instruction is available with array instead
 205    of bitfield. */
 206 typedef union i386_cpu_flags
 207 {
 208   struct
 209     {
 210       unsigned int cpui186:1;
 211       unsigned int cpui286:1;
 212       unsigned int cpui386:1;
 213       unsigned int cpui486:1;
 214       unsigned int cpui586:1;
 215       unsigned int cpui686:1;
 216       unsigned int cpuclflush:1;
 217       unsigned int cpunop:1;
 218       unsigned int cpusyscall:1;
 219       unsigned int cpu8087:1;
 220       unsigned int cpu287:1;
 221       unsigned int cpu387:1;
 222       unsigned int cpu687:1;
 223       unsigned int cpufisttp:1;
 224       unsigned int cpummx:1;
 225       unsigned int cpusse:1;
 226       unsigned int cpusse2:1;
 227       unsigned int cpua3dnow:1;
 228       unsigned int cpua3dnowa:1;
 229       unsigned int cpusse3:1;
 230       unsigned int cpupadlock:1;
 231       unsigned int cpusvme:1;
 232       unsigned int cpuvmx:1;
 233       unsigned int cpusmx:1;
 234       unsigned int cpussse3:1;
 235       unsigned int cpusse4a:1;
 236       unsigned int cpuabm:1;
 237       unsigned int cpusse4_1:1;
 238       unsigned int cpusse4_2:1;
 239       unsigned int cpuavx:1;
 240       unsigned int cpuavx2:1;
 241       unsigned int cpuavx512f:1;
 242       unsigned int cpuavx512cd:1;
 243       unsigned int cpuavx512er:1;
 244       unsigned int cpuavx512pf:1;
 245       unsigned int cpuavx512vl:1;
 246       unsigned int cpuavx512dq:1;
 247       unsigned int cpuavx512bw:1;
 248       unsigned int cpul1om:1;
 249       unsigned int cpuk1om:1;
 250       unsigned int cpuxsave:1;
 251       unsigned int cpuxsaveopt:1;
 252       unsigned int cpuaes:1;
 253       unsigned int cpupclmul:1;
 254       unsigned int cpufma:1;
 255       unsigned int cpufma4:1;
 256       unsigned int cpuxop:1;
 257       unsigned int cpulwp:1;
 258       unsigned int cpubmi:1;
 259       unsigned int cputbm:1;
 260       unsigned int cpumovbe:1;
 261       unsigned int cpucx16:1;
 262       unsigned int cpuept:1;
 263       unsigned int cpurdtscp:1;
 264       unsigned int cpufsgsbase:1;
 265       unsigned int cpurdrnd:1;
 266       unsigned int cpuf16c:1;
 267       unsigned int cpubmi2:1;
 268       unsigned int cpulzcnt:1;
 269       unsigned int cpuhle:1;
 270       unsigned int cpurtm:1;
 271       unsigned int cpuinvpcid:1;
 272       unsigned int cpuvmfunc:1;
 273       unsigned int cpumpx:1;
 274       unsigned int cpulm:1;
 275       unsigned int cpurdseed:1;
 276       unsigned int cpuadx:1;
 277       unsigned int cpuprfchw:1;
 278       unsigned int cpusmap:1;
 279       unsigned int cpusha:1;
 280       unsigned int cpuvrex:1;
 281       unsigned int cpuclflushopt:1;
 282       unsigned int cpuxsaves:1;
 283       unsigned int cpuxsavec:1;
 284       unsigned int cpuprefetchwt1:1;
 285       unsigned int cpuse1:1;
 286       unsigned int cpu64:1;
 287       unsigned int cpuno64:1;
 288 #ifdef CpuUnused
 289       unsigned int unused:(CpuNumOfBits - CpuUnused);
 290 #endif
 291     } bitfield;
 292   unsigned int array[CpuNumOfUints];
 293 } i386_cpu_flags;
 294
 295 /* Position of opcode_modifier bits.  */
 296
 297 enum
 298 {
 299   /* has direction bit. */
 300   D = 0,
 301   /* set if operands can be words or dwords encoded the canonical way */
 302   W,
 303   /* Skip the current insn and use the next insn in i386-opc.tbl to swap
 304      operand in encoding.  */
 305   S,
 306   /* insn has a modrm byte. */
 307   Modrm,
 308   /* register is in low 3 bits of opcode */
 309   ShortForm,
 310   /* special case for jump insns.  */
 311   Jump,
 312   /* call and jump */
 313   JumpDword,
 314   /* loop and jecxz */
 315   JumpByte,
 316   /* special case for intersegment leaps/calls */
 317   JumpInterSegment,
 318   /* FP insn memory format bit, sized by 0x4 */
 319   FloatMF,
 320   /* src/dest swap for floats. */
 321   FloatR,
 322   /* has float insn direction bit. */
 323   FloatD,
 324   /* needs size prefix if in 32-bit mode */
 325   Size16,
 326   /* needs size prefix if in 16-bit mode */
 327   Size32,
 328   /* needs size prefix if in 64-bit mode */
 329   Size64,
 330   /* check register size.  */
 331   CheckRegSize,
 332   /* instruction ignores operand size prefix and in Intel mode ignores
 333      mnemonic size suffix check.  */
 334   IgnoreSize,
 335   /* default insn size depends on mode */
 336   DefaultSize,
 337   /* b suffix on instruction illegal */
 338   No_bSuf,
 339   /* w suffix on instruction illegal */
 340   No_wSuf,
 341   /* l suffix on instruction illegal */
 342   No_lSuf,
 343   /* s suffix on instruction illegal */
 344   No_sSuf,
 345   /* q suffix on instruction illegal */
 346   No_qSuf,
 347   /* long double suffix on instruction illegal */
 348   No_ldSuf,
 349   /* instruction needs FWAIT */
 350   FWait,
 351   /* quick test for string instructions */
 352   IsString,
 353   /* quick test if branch instruction is MPX supported */
 354   BNDPrefixOk,
 355   /* quick test for lockable instructions */
 356   IsLockable,
 357   /* fake an extra reg operand for clr, imul and special register
 358      processing for some instructions.  */
 359   RegKludge,
 360   /* The first operand must be xmm0 */
 361   FirstXmm0,
 362   /* An implicit xmm0 as the first operand */
 363   Implicit1stXmm0,
 364   /* The HLE prefix is OK:
 365      1. With a LOCK prefix.
 366      2. With or without a LOCK prefix.
 367      3. With a RELEASE (0xf3) prefix.
 368    */
 369 #define HLEPrefixNone           0
 370 #define HLEPrefixLock           1
 371 #define HLEPrefixAny            2
 372 #define HLEPrefixRelease        3
 373   HLEPrefixOk,
 374   /* An instruction on which a "rep" prefix is acceptable.  */
 375   RepPrefixOk,
 376   /* Convert to DWORD */
 377   ToDword,
 378   /* Convert to QWORD */
 379   ToQword,
 380   /* Address prefix changes operand 0 */
 381   AddrPrefixOp0,
 382   /* opcode is a prefix */
 383   IsPrefix,
 384   /* instruction has extension in 8 bit imm */
 385   ImmExt,
 386   /* instruction don't need Rex64 prefix.  */
 387   NoRex64,
 388   /* instruction require Rex64 prefix.  */
 389   Rex64,
 390   /* deprecated fp insn, gets a warning */
 391   Ugh,
 392   /* insn has VEX prefix:
 393         1: 128bit VEX prefix.
 394         2: 256bit VEX prefix.
 395         3: Scalar VEX prefix.
 396    */
 397 #define VEX128          1
 398 #define VEX256          2
 399 #define VEXScalar       3
 400   Vex,
 401   /* How to encode VEX.vvvv:
 402      0: VEX.vvvv must be 1111b.
 403      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 404         the content of source registers will be preserved.
 405         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 406         where the content of first source register will be overwritten
 407         by the result.
 408         VEX.NDD2.  The second destination register operand is encoded in
 409         VEX.vvvv for instructions with 2 destination register operands.
 410         For assembler, there are no difference between VEX.NDS, VEX.DDS
 411         and VEX.NDD2.
 412      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 413      instructions with 1 destination register operand.
 414      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 415         of the operands can access a memory location.
 416    */
 417 #define VEXXDS  1
 418 #define VEXNDD  2
 419 #define VEXLWP  3
 420   VexVVVV,
 421   /* How the VEX.W bit is used:
 422      0: Set by the REX.W bit.
 423      1: VEX.W0.  Should always be 0.
 424      2: VEX.W1.  Should always be 1.
 425    */
 426 #define VEXW0   1
 427 #define VEXW1   2
 428   VexW,
 429   /* VEX opcode prefix:
 430      0: VEX 0x0F opcode prefix.
 431      1: VEX 0x0F38 opcode prefix.
 432      2: VEX 0x0F3A opcode prefix
 433      3: XOP 0x08 opcode prefix.
 434      4: XOP 0x09 opcode prefix
 435      5: XOP 0x0A opcode prefix.
 436    */
 437 #define VEX0F           0
 438 #define VEX0F38         1
 439 #define VEX0F3A         2
 440 #define XOP08           3
 441 #define XOP09           4
 442 #define XOP0A           5
 443   VexOpcode,
 444   /* number of VEX source operands:
 445      0: <= 2 source operands.
 446      1: 2 XOP source operands.
 447      2: 3 source operands.
 448    */
 449 #define XOP2SOURCES     1
 450 #define VEX3SOURCES     2
 451   VexSources,
 452   /* instruction has VEX 8 bit imm */
 453   VexImmExt,
 454   /* Instruction with vector SIB byte:
 455         1: 128bit vector register.
 456         2: 256bit vector register.
 457         3: 512bit vector register.
 458    */
 459 #define VecSIB128       1
 460 #define VecSIB256       2
 461 #define VecSIB512       3
 462   VecSIB,
 463   /* SSE to AVX support required */
 464   SSE2AVX,
 465   /* No AVX equivalent */
 466   NoAVX,
 467
 468   /* insn has EVEX prefix:
 469         1: 512bit EVEX prefix.
 470         2: 128bit EVEX prefix.
 471         3: 256bit EVEX prefix.
 472         4: Length-ignored (LIG) EVEX prefix.
 473    */
 474 #define EVEX512                1
 475 #define EVEX128                2
 476 #define EVEX256                3
 477 #define EVEXLIG                4
 478   EVex,
 479
 480   /* AVX512 masking support:
 481         1: Zeroing-masking.
 482         2: Merging-masking.
 483         3: Both zeroing and merging masking.
 484    */
 485 #define ZEROING_MASKING 1
 486 #define MERGING_MASKING 2
 487 #define BOTH_MASKING    3
 488   Masking,
 489
 490   /* Input element size of vector insn:
 491         0: 32bit.
 492         1: 64bit.
 493    */
 494   VecESize,
 495
 496   /* Broadcast factor.
 497         0: No broadcast.
 498         1: 1to16 broadcast.
 499         2: 1to8 broadcast.
 500    */
 501 #define NO_BROADCAST    0
 502 #define BROADCAST_1TO16 1
 503 #define BROADCAST_1TO8  2
 504 #define BROADCAST_1TO4  3
 505 #define BROADCAST_1TO2  4
 506   Broadcast,
 507
 508   /* Static rounding control is supported.  */
 509   StaticRounding,
 510
 511   /* Supress All Exceptions is supported.  */
 512   SAE,
 513
 514   /* Copressed Disp8*N attribute.  */
 515   Disp8MemShift,
 516
 517   /* Default mask isn't allowed.  */
 518   NoDefMask,
 519
 520   /* Compatible with old (<= 2.8.1) versions of gcc  */
 521   OldGcc,
 522   /* AT&T mnemonic.  */
 523   ATTMnemonic,
 524   /* AT&T syntax.  */
 525   ATTSyntax,
 526   /* Intel syntax.  */
 527   IntelSyntax,
 528   /* The last bitfield in i386_opcode_modifier.  */
 529   Opcode_Modifier_Max
 530 };
 531
 532 typedef struct i386_opcode_modifier
 533 {
 534   unsigned int d:1;
 535   unsigned int w:1;
 536   unsigned int s:1;
 537   unsigned int modrm:1;
 538   unsigned int shortform:1;
 539   unsigned int jump:1;
 540   unsigned int jumpdword:1;
 541   unsigned int jumpbyte:1;
 542   unsigned int jumpintersegment:1;
 543   unsigned int floatmf:1;
 544   unsigned int floatr:1;
 545   unsigned int floatd:1;
 546   unsigned int size16:1;
 547   unsigned int size32:1;
 548   unsigned int size64:1;
 549   unsigned int checkregsize:1;
 550   unsigned int ignoresize:1;
 551   unsigned int defaultsize:1;
 552   unsigned int no_bsuf:1;
 553   unsigned int no_wsuf:1;
 554   unsigned int no_lsuf:1;
 555   unsigned int no_ssuf:1;
 556   unsigned int no_qsuf:1;
 557   unsigned int no_ldsuf:1;
 558   unsigned int fwait:1;
 559   unsigned int isstring:1;
 560   unsigned int bndprefixok:1;
 561   unsigned int islockable:1;
 562   unsigned int regkludge:1;
 563   unsigned int firstxmm0:1;
 564   unsigned int implicit1stxmm0:1;
 565   unsigned int hleprefixok:2;
 566   unsigned int repprefixok:1;
 567   unsigned int todword:1;
 568   unsigned int toqword:1;
 569   unsigned int addrprefixop0:1;
 570   unsigned int isprefix:1;
 571   unsigned int immext:1;
 572   unsigned int norex64:1;
 573   unsigned int rex64:1;
 574   unsigned int ugh:1;
 575   unsigned int vex:2;
 576   unsigned int vexvvvv:2;
 577   unsigned int vexw:2;
 578   unsigned int vexopcode:3;
 579   unsigned int vexsources:2;
 580   unsigned int veximmext:1;
 581   unsigned int vecsib:2;
 582   unsigned int sse2avx:1;
 583   unsigned int noavx:1;
 584   unsigned int evex:3;
 585   unsigned int masking:2;
 586   unsigned int vecesize:1;
 587   unsigned int broadcast:3;
 588   unsigned int staticrounding:1;
 589   unsigned int sae:1;
 590   unsigned int disp8memshift:3;
 591   unsigned int nodefmask:1;
 592   unsigned int oldgcc:1;
 593   unsigned int attmnemonic:1;
 594   unsigned int attsyntax:1;
 595   unsigned int intelsyntax:1;
 596 } i386_opcode_modifier;
 597
 598 /* Position of operand_type bits.  */
 599
 600 enum
 601 {
 602   /* 8bit register */
 603   Reg8 = 0,
 604   /* 16bit register */
 605   Reg16,
 606   /* 32bit register */
 607   Reg32,
 608   /* 64bit register */
 609   Reg64,
 610   /* Floating pointer stack register */
 611   FloatReg,
 612   /* MMX register */
 613   RegMMX,
 614   /* SSE register */
 615   RegXMM,
 616   /* AVX registers */
 617   RegYMM,
 618   /* AVX512 registers */
 619   RegZMM,
 620   /* Vector Mask registers */
 621   RegMask,
 622   /* Control register */
 623   Control,
 624   /* Debug register */
 625   Debug,
 626   /* Test register */
 627   Test,
 628   /* 2 bit segment register */
 629   SReg2,
 630   /* 3 bit segment register */
 631   SReg3,
 632   /* 1 bit immediate */
 633   Imm1,
 634   /* 8 bit immediate */
 635   Imm8,
 636   /* 8 bit immediate sign extended */
 637   Imm8S,
 638   /* 16 bit immediate */
 639   Imm16,
 640   /* 32 bit immediate */
 641   Imm32,
 642   /* 32 bit immediate sign extended */
 643   Imm32S,
 644   /* 64 bit immediate */
 645   Imm64,
 646   /* 8bit/16bit/32bit displacements are used in different ways,
 647      depending on the instruction.  For jumps, they specify the
 648      size of the PC relative displacement, for instructions with
 649      memory operand, they specify the size of the offset relative
 650      to the base register, and for instructions with memory offset
 651      such as `mov 1234,%al' they specify the size of the offset
 652      relative to the segment base.  */
 653   /* 8 bit displacement */
 654   Disp8,
 655   /* 16 bit displacement */
 656   Disp16,
 657   /* 32 bit displacement */
 658   Disp32,
 659   /* 32 bit signed displacement */
 660   Disp32S,
 661   /* 64 bit displacement */
 662   Disp64,
 663   /* Accumulator %al/%ax/%eax/%rax */
 664   Acc,
 665   /* Floating pointer top stack register %st(0) */
 666   FloatAcc,
 667   /* Register which can be used for base or index in memory operand.  */
 668   BaseIndex,
 669   /* Register to hold in/out port addr = dx */
 670   InOutPortReg,
 671   /* Register to hold shift count = cl */
 672   ShiftCount,
 673   /* Absolute address for jump.  */
 674   JumpAbsolute,
 675   /* String insn operand with fixed es segment */
 676   EsSeg,
 677   /* RegMem is for instructions with a modrm byte where the register
 678      destination operand should be encoded in the mod and regmem fields.
 679      Normally, it will be encoded in the reg field. We add a RegMem
 680      flag to the destination register operand to indicate that it should
 681      be encoded in the regmem field.  */
 682   RegMem,
 683   /* Memory.  */
 684   Mem,
 685   /* BYTE memory. */
 686   Byte,
 687   /* WORD memory. 2 byte */
 688   Word,
 689   /* DWORD memory. 4 byte */
 690   Dword,
 691   /* FWORD memory. 6 byte */
 692   Fword,
 693   /* QWORD memory. 8 byte */
 694   Qword,
 695   /* TBYTE memory. 10 byte */
 696   Tbyte,
 697   /* XMMWORD memory. */
 698   Xmmword,
 699   /* YMMWORD memory. */
 700   Ymmword,
 701   /* ZMMWORD memory.  */
 702   Zmmword,
 703   /* Unspecified memory size.  */
 704   Unspecified,
 705   /* Any memory size.  */
 706   Anysize,
 707
 708   /* Vector 4 bit immediate.  */
 709   Vec_Imm4,
 710
 711   /* Bound register.  */
 712   RegBND,
 713
 714   /* Vector 8bit displacement */
 715   Vec_Disp8,
 716
 717   /* The last bitfield in i386_operand_type.  */
 718   OTMax
 719 };
 720
 721 #define OTNumOfUints \
 722   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 723 #define OTNumOfBits \
 724   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 725
 726 /* If you get a compiler error for zero width of the unused field,
 727    comment it out.  */
 728 #define OTUnused                (OTMax + 1)
 729
 730 typedef union i386_operand_type
 731 {
 732   struct
 733     {
 734       unsigned int reg8:1;
 735       unsigned int reg16:1;
 736       unsigned int reg32:1;
 737       unsigned int reg64:1;
 738       unsigned int floatreg:1;
 739       unsigned int regmmx:1;
 740       unsigned int regxmm:1;
 741       unsigned int regymm:1;
 742       unsigned int regzmm:1;
 743       unsigned int regmask:1;
 744       unsigned int control:1;
 745       unsigned int debug:1;
 746       unsigned int test:1;
 747       unsigned int sreg2:1;
 748       unsigned int sreg3:1;
 749       unsigned int imm1:1;
 750       unsigned int imm8:1;
 751       unsigned int imm8s:1;
 752       unsigned int imm16:1;
 753       unsigned int imm32:1;
 754       unsigned int imm32s:1;
 755       unsigned int imm64:1;
 756       unsigned int disp8:1;
 757       unsigned int disp16:1;
 758       unsigned int disp32:1;
 759       unsigned int disp32s:1;
 760       unsigned int disp64:1;
 761       unsigned int acc:1;
 762       unsigned int floatacc:1;
 763       unsigned int baseindex:1;
 764       unsigned int inoutportreg:1;
 765       unsigned int shiftcount:1;
 766       unsigned int jumpabsolute:1;
 767       unsigned int esseg:1;
 768       unsigned int regmem:1;
 769       unsigned int mem:1;
 770       unsigned int byte:1;
 771       unsigned int word:1;
 772       unsigned int dword:1;
 773       unsigned int fword:1;
 774       unsigned int qword:1;
 775       unsigned int tbyte:1;
 776       unsigned int xmmword:1;
 777       unsigned int ymmword:1;
 778       unsigned int zmmword:1;
 779       unsigned int unspecified:1;
 780       unsigned int anysize:1;
 781       unsigned int vec_imm4:1;
 782       unsigned int regbnd:1;
 783       unsigned int vec_disp8:1;
 784 #ifdef OTUnused
 785       unsigned int unused:(OTNumOfBits - OTUnused);
 786 #endif
 787     } bitfield;
 788   unsigned int array[OTNumOfUints];
 789 } i386_operand_type;
 790
 791 typedef struct insn_template
 792 {
 793   /* instruction name sans width suffix ("mov" for movl insns) */
 794   char *name;
 795
 796   /* how many operands */
 797   unsigned int operands;
 798
 799   /* base_opcode is the fundamental opcode byte without optional
 800      prefix(es).  */
 801   unsigned int base_opcode;
 802 #define Opcode_D        0x2 /* Direction bit:
 803                                set if Reg --> Regmem;
 804                                unset if Regmem --> Reg. */
 805 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 806 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 807
 808   /* extension_opcode is the 3 bit extension for group <n> insns.
 809      This field is also used to store the 8-bit opcode suffix for the
 810      AMD 3DNow! instructions.
 811      If this template has no extension opcode (the usual case) use None
 812      Instructions */
 813   unsigned int extension_opcode;
 814 #define None 0xffff             /* If no extension_opcode is possible.  */
 815
 816   /* Opcode length.  */
 817   unsigned char opcode_length;
 818
 819   /* cpu feature flags */
 820   i386_cpu_flags cpu_flags;
 821
 822   /* the bits in opcode_modifier are used to generate the final opcode from
 823      the base_opcode.  These bits also are used to detect alternate forms of
 824      the same instruction */
 825   i386_opcode_modifier opcode_modifier;
 826
 827   /* operand_types[i] describes the type of operand i.  This is made
 828      by OR'ing together all of the possible type masks.  (e.g.
 829      'operand_types[i] = Reg|Imm' specifies that operand i can be
 830      either a register or an immediate operand.  */
 831   i386_operand_type operand_types[MAX_OPERANDS];
 832 }
 833 insn_template;
 834
 835 extern const insn_template i386_optab[];
 836
 837 /* these are for register name --> number & type hash lookup */
 838 typedef struct
 839 {
 840   char *reg_name;
 841   i386_operand_type reg_type;
 842   unsigned char reg_flags;
 843 #define RegRex      0x1  /* Extended register.  */
 844 #define RegRex64    0x2  /* Extended 8 bit register.  */
 845 #define RegVRex     0x4  /* Extended vector register.  */
 846   unsigned char reg_num;
 847 #define RegRip  ((unsigned char ) ~0)
 848 #define RegEip  (RegRip - 1)
 849 /* EIZ and RIZ are fake index registers.  */
 850 #define RegEiz  (RegEip - 1)
 851 #define RegRiz  (RegEiz - 1)
 852 /* FLAT is a fake segment register (Intel mode).  */
 853 #define RegFlat     ((unsigned char) ~0)
 854   signed char dw2_regnum[2];
 855 #define Dw2Inval (-1)
 856 }
 857 reg_entry;
 858
 859 /* Entries in i386_regtab.  */
 860 #define REGNAM_AL 1
 861 #define REGNAM_AX 25
 862 #define REGNAM_EAX 41
 863
 864 extern const reg_entry i386_regtab[];
 865 extern const unsigned int i386_regtab_size;
 866
 867 typedef struct
 868 {
 869   char *seg_name;
 870   unsigned int seg_prefix;
 871 }
 872 seg_entry;
 873
 874 extern const seg_entry cs;
 875 extern const seg_entry ds;
 876 extern const seg_entry ss;
 877 extern const seg_entry es;
 878 extern const seg_entry fs;
 879 extern const seg_entry gs;