opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2014 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #ifdef HAVE_LIMITS_H
  23 #include <limits.h>
  24 #endif
  25
  26 #ifndef CHAR_BIT
  27 #define CHAR_BIT 8
  28 #endif
  29
  30 /* Position of cpu flags bitfiled.  */
  31
  32 enum
  33 {
  34   /* i186 or better required */
  35   Cpu186 = 0,
  36   /* i286 or better required */
  37   Cpu286,
  38   /* i386 or better required */
  39   Cpu386,
  40   /* i486 or better required */
  41   Cpu486,
  42   /* i585 or better required */
  43   Cpu586,
  44   /* i686 or better required */
  45   Cpu686,
  46   /* CLFLUSH Instruction support required */
  47   CpuClflush,
  48   /* NOP Instruction support required */
  49   CpuNop,
  50   /* SYSCALL Instructions support required */
  51   CpuSYSCALL,
  52   /* Floating point support required */
  53   Cpu8087,
  54   /* i287 support required */
  55   Cpu287,
  56   /* i387 support required */
  57   Cpu387,
  58   /* i686 and floating point support required */
  59   Cpu687,
  60   /* SSE3 and floating point support required */
  61   CpuFISTTP,
  62   /* MMX support required */
  63   CpuMMX,
  64   /* SSE support required */
  65   CpuSSE,
  66   /* SSE2 support required */
  67   CpuSSE2,
  68   /* 3dnow! support required */
  69   Cpu3dnow,
  70   /* 3dnow! Extensions support required */
  71   Cpu3dnowA,
  72   /* SSE3 support required */
  73   CpuSSE3,
  74   /* VIA PadLock required */
  75   CpuPadLock,
  76   /* AMD Secure Virtual Machine Ext-s required */
  77   CpuSVME,
  78   /* VMX Instructions required */
  79   CpuVMX,
  80   /* SMX Instructions required */
  81   CpuSMX,
  82   /* SSSE3 support required */
  83   CpuSSSE3,
  84   /* SSE4a support required */
  85   CpuSSE4a,
  86   /* ABM New Instructions required */
  87   CpuABM,
  88   /* SSE4.1 support required */
  89   CpuSSE4_1,
  90   /* SSE4.2 support required */
  91   CpuSSE4_2,
  92   /* AVX support required */
  93   CpuAVX,
  94   /* AVX2 support required */
  95   CpuAVX2,
  96   /* Intel AVX-512 Foundation Instructions support required */
  97   CpuAVX512F,
  98   /* Intel AVX-512 Conflict Detection Instructions support required */
  99   CpuAVX512CD,
 100   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 101      required */
 102   CpuAVX512ER,
 103   /* Intel AVX-512 Prefetch Instructions support required */
 104   CpuAVX512PF,
 105   /* Intel AVX-512 VL Instructions support required.  */
 106   CpuAVX512VL,
 107   /* Intel L1OM support required */
 108   CpuL1OM,
 109   /* Intel K1OM support required */
 110   CpuK1OM,
 111   /* Xsave/xrstor New Instructions support required */
 112   CpuXsave,
 113   /* Xsaveopt New Instructions support required */
 114   CpuXsaveopt,
 115   /* AES support required */
 116   CpuAES,
 117   /* PCLMUL support required */
 118   CpuPCLMUL,
 119   /* FMA support required */
 120   CpuFMA,
 121   /* FMA4 support required */
 122   CpuFMA4,
 123   /* XOP support required */
 124   CpuXOP,
 125   /* LWP support required */
 126   CpuLWP,
 127   /* BMI support required */
 128   CpuBMI,
 129   /* TBM support required */
 130   CpuTBM,
 131   /* MOVBE Instruction support required */
 132   CpuMovbe,
 133   /* CMPXCHG16B instruction support required.  */
 134   CpuCX16,
 135   /* EPT Instructions required */
 136   CpuEPT,
 137   /* RDTSCP Instruction support required */
 138   CpuRdtscp,
 139   /* FSGSBASE Instructions required */
 140   CpuFSGSBase,
 141   /* RDRND Instructions required */
 142   CpuRdRnd,
 143   /* F16C Instructions required */
 144   CpuF16C,
 145   /* Intel BMI2 support required */
 146   CpuBMI2,
 147   /* LZCNT support required */
 148   CpuLZCNT,
 149   /* HLE support required */
 150   CpuHLE,
 151   /* RTM support required */
 152   CpuRTM,
 153   /* INVPCID Instructions required */
 154   CpuINVPCID,
 155   /* VMFUNC Instruction required */
 156   CpuVMFUNC,
 157   /* Intel MPX Instructions required  */
 158   CpuMPX,
 159   /* 64bit support available, used by -march= in assembler.  */
 160   CpuLM,
 161   /* RDRSEED instruction required.  */
 162   CpuRDSEED,
 163   /* Multi-presisionn add-carry instructions are required.  */
 164   CpuADX,
 165   /* Supports prefetchw and prefetch instructions.  */
 166   CpuPRFCHW,
 167   /* SMAP instructions required.  */
 168   CpuSMAP,
 169   /* SHA instructions required.  */
 170   CpuSHA,
 171   /* VREX support required  */
 172   CpuVREX,
 173   /* CLFLUSHOPT instruction required */
 174   CpuClflushOpt,
 175   /* XSAVES/XRSTORS instruction required */
 176   CpuXSAVES,
 177   /* XSAVEC instruction required */
 178   CpuXSAVEC,
 179   /* PREFETCHWT1 instruction required */
 180   CpuPREFETCHWT1,
 181   /* SE1 instruction required */
 182   CpuSE1,
 183   /* 64bit support required  */
 184   Cpu64,
 185   /* Not supported in the 64bit mode  */
 186   CpuNo64,
 187   /* The last bitfield in i386_cpu_flags.  */
 188   CpuMax = CpuNo64
 189 };
 190
 191 #define CpuNumOfUints \
 192   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 193 #define CpuNumOfBits \
 194   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 195
 196 /* If you get a compiler error for zero width of the unused field,
 197    comment it out.  */
 198 #define CpuUnused       (CpuMax + 1)
 199
 200 /* We can check if an instruction is available with array instead
 201    of bitfield. */
 202 typedef union i386_cpu_flags
 203 {
 204   struct
 205     {
 206       unsigned int cpui186:1;
 207       unsigned int cpui286:1;
 208       unsigned int cpui386:1;
 209       unsigned int cpui486:1;
 210       unsigned int cpui586:1;
 211       unsigned int cpui686:1;
 212       unsigned int cpuclflush:1;
 213       unsigned int cpunop:1;
 214       unsigned int cpusyscall:1;
 215       unsigned int cpu8087:1;
 216       unsigned int cpu287:1;
 217       unsigned int cpu387:1;
 218       unsigned int cpu687:1;
 219       unsigned int cpufisttp:1;
 220       unsigned int cpummx:1;
 221       unsigned int cpusse:1;
 222       unsigned int cpusse2:1;
 223       unsigned int cpua3dnow:1;
 224       unsigned int cpua3dnowa:1;
 225       unsigned int cpusse3:1;
 226       unsigned int cpupadlock:1;
 227       unsigned int cpusvme:1;
 228       unsigned int cpuvmx:1;
 229       unsigned int cpusmx:1;
 230       unsigned int cpussse3:1;
 231       unsigned int cpusse4a:1;
 232       unsigned int cpuabm:1;
 233       unsigned int cpusse4_1:1;
 234       unsigned int cpusse4_2:1;
 235       unsigned int cpuavx:1;
 236       unsigned int cpuavx2:1;
 237       unsigned int cpuavx512f:1;
 238       unsigned int cpuavx512cd:1;
 239       unsigned int cpuavx512er:1;
 240       unsigned int cpuavx512pf:1;
 241       unsigned int cpuavx512vl:1;
 242       unsigned int cpul1om:1;
 243       unsigned int cpuk1om:1;
 244       unsigned int cpuxsave:1;
 245       unsigned int cpuxsaveopt:1;
 246       unsigned int cpuaes:1;
 247       unsigned int cpupclmul:1;
 248       unsigned int cpufma:1;
 249       unsigned int cpufma4:1;
 250       unsigned int cpuxop:1;
 251       unsigned int cpulwp:1;
 252       unsigned int cpubmi:1;
 253       unsigned int cputbm:1;
 254       unsigned int cpumovbe:1;
 255       unsigned int cpucx16:1;
 256       unsigned int cpuept:1;
 257       unsigned int cpurdtscp:1;
 258       unsigned int cpufsgsbase:1;
 259       unsigned int cpurdrnd:1;
 260       unsigned int cpuf16c:1;
 261       unsigned int cpubmi2:1;
 262       unsigned int cpulzcnt:1;
 263       unsigned int cpuhle:1;
 264       unsigned int cpurtm:1;
 265       unsigned int cpuinvpcid:1;
 266       unsigned int cpuvmfunc:1;
 267       unsigned int cpumpx:1;
 268       unsigned int cpulm:1;
 269       unsigned int cpurdseed:1;
 270       unsigned int cpuadx:1;
 271       unsigned int cpuprfchw:1;
 272       unsigned int cpusmap:1;
 273       unsigned int cpusha:1;
 274       unsigned int cpuvrex:1;
 275       unsigned int cpuclflushopt:1;
 276       unsigned int cpuxsaves:1;
 277       unsigned int cpuxsavec:1;
 278       unsigned int cpuprefetchwt1:1;
 279       unsigned int cpuse1:1;
 280       unsigned int cpu64:1;
 281       unsigned int cpuno64:1;
 282 #ifdef CpuUnused
 283       unsigned int unused:(CpuNumOfBits - CpuUnused);
 284 #endif
 285     } bitfield;
 286   unsigned int array[CpuNumOfUints];
 287 } i386_cpu_flags;
 288
 289 /* Position of opcode_modifier bits.  */
 290
 291 enum
 292 {
 293   /* has direction bit. */
 294   D = 0,
 295   /* set if operands can be words or dwords encoded the canonical way */
 296   W,
 297   /* Skip the current insn and use the next insn in i386-opc.tbl to swap
 298      operand in encoding.  */
 299   S,
 300   /* insn has a modrm byte. */
 301   Modrm,
 302   /* register is in low 3 bits of opcode */
 303   ShortForm,
 304   /* special case for jump insns.  */
 305   Jump,
 306   /* call and jump */
 307   JumpDword,
 308   /* loop and jecxz */
 309   JumpByte,
 310   /* special case for intersegment leaps/calls */
 311   JumpInterSegment,
 312   /* FP insn memory format bit, sized by 0x4 */
 313   FloatMF,
 314   /* src/dest swap for floats. */
 315   FloatR,
 316   /* has float insn direction bit. */
 317   FloatD,
 318   /* needs size prefix if in 32-bit mode */
 319   Size16,
 320   /* needs size prefix if in 16-bit mode */
 321   Size32,
 322   /* needs size prefix if in 64-bit mode */
 323   Size64,
 324   /* check register size.  */
 325   CheckRegSize,
 326   /* instruction ignores operand size prefix and in Intel mode ignores
 327      mnemonic size suffix check.  */
 328   IgnoreSize,
 329   /* default insn size depends on mode */
 330   DefaultSize,
 331   /* b suffix on instruction illegal */
 332   No_bSuf,
 333   /* w suffix on instruction illegal */
 334   No_wSuf,
 335   /* l suffix on instruction illegal */
 336   No_lSuf,
 337   /* s suffix on instruction illegal */
 338   No_sSuf,
 339   /* q suffix on instruction illegal */
 340   No_qSuf,
 341   /* long double suffix on instruction illegal */
 342   No_ldSuf,
 343   /* instruction needs FWAIT */
 344   FWait,
 345   /* quick test for string instructions */
 346   IsString,
 347   /* quick test if branch instruction is MPX supported */
 348   BNDPrefixOk,
 349   /* quick test for lockable instructions */
 350   IsLockable,
 351   /* fake an extra reg operand for clr, imul and special register
 352      processing for some instructions.  */
 353   RegKludge,
 354   /* The first operand must be xmm0 */
 355   FirstXmm0,
 356   /* An implicit xmm0 as the first operand */
 357   Implicit1stXmm0,
 358   /* The HLE prefix is OK:
 359      1. With a LOCK prefix.
 360      2. With or without a LOCK prefix.
 361      3. With a RELEASE (0xf3) prefix.
 362    */
 363 #define HLEPrefixNone           0
 364 #define HLEPrefixLock           1
 365 #define HLEPrefixAny            2
 366 #define HLEPrefixRelease        3
 367   HLEPrefixOk,
 368   /* An instruction on which a "rep" prefix is acceptable.  */
 369   RepPrefixOk,
 370   /* Convert to DWORD */
 371   ToDword,
 372   /* Convert to QWORD */
 373   ToQword,
 374   /* Address prefix changes operand 0 */
 375   AddrPrefixOp0,
 376   /* opcode is a prefix */
 377   IsPrefix,
 378   /* instruction has extension in 8 bit imm */
 379   ImmExt,
 380   /* instruction don't need Rex64 prefix.  */
 381   NoRex64,
 382   /* instruction require Rex64 prefix.  */
 383   Rex64,
 384   /* deprecated fp insn, gets a warning */
 385   Ugh,
 386   /* insn has VEX prefix:
 387         1: 128bit VEX prefix.
 388         2: 256bit VEX prefix.
 389         3: Scalar VEX prefix.
 390    */
 391 #define VEX128          1
 392 #define VEX256          2
 393 #define VEXScalar       3
 394   Vex,
 395   /* How to encode VEX.vvvv:
 396      0: VEX.vvvv must be 1111b.
 397      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 398         the content of source registers will be preserved.
 399         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 400         where the content of first source register will be overwritten
 401         by the result.
 402         VEX.NDD2.  The second destination register operand is encoded in
 403         VEX.vvvv for instructions with 2 destination register operands.
 404         For assembler, there are no difference between VEX.NDS, VEX.DDS
 405         and VEX.NDD2.
 406      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 407      instructions with 1 destination register operand.
 408      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 409         of the operands can access a memory location.
 410    */
 411 #define VEXXDS  1
 412 #define VEXNDD  2
 413 #define VEXLWP  3
 414   VexVVVV,
 415   /* How the VEX.W bit is used:
 416      0: Set by the REX.W bit.
 417      1: VEX.W0.  Should always be 0.
 418      2: VEX.W1.  Should always be 1.
 419    */
 420 #define VEXW0   1
 421 #define VEXW1   2
 422   VexW,
 423   /* VEX opcode prefix:
 424      0: VEX 0x0F opcode prefix.
 425      1: VEX 0x0F38 opcode prefix.
 426      2: VEX 0x0F3A opcode prefix
 427      3: XOP 0x08 opcode prefix.
 428      4: XOP 0x09 opcode prefix
 429      5: XOP 0x0A opcode prefix.
 430    */
 431 #define VEX0F           0
 432 #define VEX0F38         1
 433 #define VEX0F3A         2
 434 #define XOP08           3
 435 #define XOP09           4
 436 #define XOP0A           5
 437   VexOpcode,
 438   /* number of VEX source operands:
 439      0: <= 2 source operands.
 440      1: 2 XOP source operands.
 441      2: 3 source operands.
 442    */
 443 #define XOP2SOURCES     1
 444 #define VEX3SOURCES     2
 445   VexSources,
 446   /* instruction has VEX 8 bit imm */
 447   VexImmExt,
 448   /* Instruction with vector SIB byte:
 449         1: 128bit vector register.
 450         2: 256bit vector register.
 451         3: 512bit vector register.
 452    */
 453 #define VecSIB128       1
 454 #define VecSIB256       2
 455 #define VecSIB512       3
 456   VecSIB,
 457   /* SSE to AVX support required */
 458   SSE2AVX,
 459   /* No AVX equivalent */
 460   NoAVX,
 461
 462   /* insn has EVEX prefix:
 463         1: 512bit EVEX prefix.
 464         2: 128bit EVEX prefix.
 465         3: 256bit EVEX prefix.
 466         4: Length-ignored (LIG) EVEX prefix.
 467    */
 468 #define EVEX512                1
 469 #define EVEX128                2
 470 #define EVEX256                3
 471 #define EVEXLIG                4
 472   EVex,
 473
 474   /* AVX512 masking support:
 475         1: Zeroing-masking.
 476         2: Merging-masking.
 477         3: Both zeroing and merging masking.
 478    */
 479 #define ZEROING_MASKING 1
 480 #define MERGING_MASKING 2
 481 #define BOTH_MASKING    3
 482   Masking,
 483
 484   /* Input element size of vector insn:
 485         0: 32bit.
 486         1: 64bit.
 487    */
 488   VecESize,
 489
 490   /* Broadcast factor.
 491         0: No broadcast.
 492         1: 1to16 broadcast.
 493         2: 1to8 broadcast.
 494    */
 495 #define NO_BROADCAST    0
 496 #define BROADCAST_1TO16 1
 497 #define BROADCAST_1TO8  2
 498 #define BROADCAST_1TO4  3
 499 #define BROADCAST_1TO2  4
 500   Broadcast,
 501
 502   /* Static rounding control is supported.  */
 503   StaticRounding,
 504
 505   /* Supress All Exceptions is supported.  */
 506   SAE,
 507
 508   /* Copressed Disp8*N attribute.  */
 509   Disp8MemShift,
 510
 511   /* Default mask isn't allowed.  */
 512   NoDefMask,
 513
 514   /* Compatible with old (<= 2.8.1) versions of gcc  */
 515   OldGcc,
 516   /* AT&T mnemonic.  */
 517   ATTMnemonic,
 518   /* AT&T syntax.  */
 519   ATTSyntax,
 520   /* Intel syntax.  */
 521   IntelSyntax,
 522   /* The last bitfield in i386_opcode_modifier.  */
 523   Opcode_Modifier_Max
 524 };
 525
 526 typedef struct i386_opcode_modifier
 527 {
 528   unsigned int d:1;
 529   unsigned int w:1;
 530   unsigned int s:1;
 531   unsigned int modrm:1;
 532   unsigned int shortform:1;
 533   unsigned int jump:1;
 534   unsigned int jumpdword:1;
 535   unsigned int jumpbyte:1;
 536   unsigned int jumpintersegment:1;
 537   unsigned int floatmf:1;
 538   unsigned int floatr:1;
 539   unsigned int floatd:1;
 540   unsigned int size16:1;
 541   unsigned int size32:1;
 542   unsigned int size64:1;
 543   unsigned int checkregsize:1;
 544   unsigned int ignoresize:1;
 545   unsigned int defaultsize:1;
 546   unsigned int no_bsuf:1;
 547   unsigned int no_wsuf:1;
 548   unsigned int no_lsuf:1;
 549   unsigned int no_ssuf:1;
 550   unsigned int no_qsuf:1;
 551   unsigned int no_ldsuf:1;
 552   unsigned int fwait:1;
 553   unsigned int isstring:1;
 554   unsigned int bndprefixok:1;
 555   unsigned int islockable:1;
 556   unsigned int regkludge:1;
 557   unsigned int firstxmm0:1;
 558   unsigned int implicit1stxmm0:1;
 559   unsigned int hleprefixok:2;
 560   unsigned int repprefixok:1;
 561   unsigned int todword:1;
 562   unsigned int toqword:1;
 563   unsigned int addrprefixop0:1;
 564   unsigned int isprefix:1;
 565   unsigned int immext:1;
 566   unsigned int norex64:1;
 567   unsigned int rex64:1;
 568   unsigned int ugh:1;
 569   unsigned int vex:2;
 570   unsigned int vexvvvv:2;
 571   unsigned int vexw:2;
 572   unsigned int vexopcode:3;
 573   unsigned int vexsources:2;
 574   unsigned int veximmext:1;
 575   unsigned int vecsib:2;
 576   unsigned int sse2avx:1;
 577   unsigned int noavx:1;
 578   unsigned int evex:3;
 579   unsigned int masking:2;
 580   unsigned int vecesize:1;
 581   unsigned int broadcast:3;
 582   unsigned int staticrounding:1;
 583   unsigned int sae:1;
 584   unsigned int disp8memshift:3;
 585   unsigned int nodefmask:1;
 586   unsigned int oldgcc:1;
 587   unsigned int attmnemonic:1;
 588   unsigned int attsyntax:1;
 589   unsigned int intelsyntax:1;
 590 } i386_opcode_modifier;
 591
 592 /* Position of operand_type bits.  */
 593
 594 enum
 595 {
 596   /* 8bit register */
 597   Reg8 = 0,
 598   /* 16bit register */
 599   Reg16,
 600   /* 32bit register */
 601   Reg32,
 602   /* 64bit register */
 603   Reg64,
 604   /* Floating pointer stack register */
 605   FloatReg,
 606   /* MMX register */
 607   RegMMX,
 608   /* SSE register */
 609   RegXMM,
 610   /* AVX registers */
 611   RegYMM,
 612   /* AVX512 registers */
 613   RegZMM,
 614   /* Vector Mask registers */
 615   RegMask,
 616   /* Control register */
 617   Control,
 618   /* Debug register */
 619   Debug,
 620   /* Test register */
 621   Test,
 622   /* 2 bit segment register */
 623   SReg2,
 624   /* 3 bit segment register */
 625   SReg3,
 626   /* 1 bit immediate */
 627   Imm1,
 628   /* 8 bit immediate */
 629   Imm8,
 630   /* 8 bit immediate sign extended */
 631   Imm8S,
 632   /* 16 bit immediate */
 633   Imm16,
 634   /* 32 bit immediate */
 635   Imm32,
 636   /* 32 bit immediate sign extended */
 637   Imm32S,
 638   /* 64 bit immediate */
 639   Imm64,
 640   /* 8bit/16bit/32bit displacements are used in different ways,
 641      depending on the instruction.  For jumps, they specify the
 642      size of the PC relative displacement, for instructions with
 643      memory operand, they specify the size of the offset relative
 644      to the base register, and for instructions with memory offset
 645      such as `mov 1234,%al' they specify the size of the offset
 646      relative to the segment base.  */
 647   /* 8 bit displacement */
 648   Disp8,
 649   /* 16 bit displacement */
 650   Disp16,
 651   /* 32 bit displacement */
 652   Disp32,
 653   /* 32 bit signed displacement */
 654   Disp32S,
 655   /* 64 bit displacement */
 656   Disp64,
 657   /* Accumulator %al/%ax/%eax/%rax */
 658   Acc,
 659   /* Floating pointer top stack register %st(0) */
 660   FloatAcc,
 661   /* Register which can be used for base or index in memory operand.  */
 662   BaseIndex,
 663   /* Register to hold in/out port addr = dx */
 664   InOutPortReg,
 665   /* Register to hold shift count = cl */
 666   ShiftCount,
 667   /* Absolute address for jump.  */
 668   JumpAbsolute,
 669   /* String insn operand with fixed es segment */
 670   EsSeg,
 671   /* RegMem is for instructions with a modrm byte where the register
 672      destination operand should be encoded in the mod and regmem fields.
 673      Normally, it will be encoded in the reg field. We add a RegMem
 674      flag to the destination register operand to indicate that it should
 675      be encoded in the regmem field.  */
 676   RegMem,
 677   /* Memory.  */
 678   Mem,
 679   /* BYTE memory. */
 680   Byte,
 681   /* WORD memory. 2 byte */
 682   Word,
 683   /* DWORD memory. 4 byte */
 684   Dword,
 685   /* FWORD memory. 6 byte */
 686   Fword,
 687   /* QWORD memory. 8 byte */
 688   Qword,
 689   /* TBYTE memory. 10 byte */
 690   Tbyte,
 691   /* XMMWORD memory. */
 692   Xmmword,
 693   /* YMMWORD memory. */
 694   Ymmword,
 695   /* ZMMWORD memory.  */
 696   Zmmword,
 697   /* Unspecified memory size.  */
 698   Unspecified,
 699   /* Any memory size.  */
 700   Anysize,
 701
 702   /* Vector 4 bit immediate.  */
 703   Vec_Imm4,
 704
 705   /* Bound register.  */
 706   RegBND,
 707
 708   /* Vector 8bit displacement */
 709   Vec_Disp8,
 710
 711   /* The last bitfield in i386_operand_type.  */
 712   OTMax
 713 };
 714
 715 #define OTNumOfUints \
 716   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 717 #define OTNumOfBits \
 718   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 719
 720 /* If you get a compiler error for zero width of the unused field,
 721    comment it out.  */
 722 #define OTUnused                (OTMax + 1)
 723
 724 typedef union i386_operand_type
 725 {
 726   struct
 727     {
 728       unsigned int reg8:1;
 729       unsigned int reg16:1;
 730       unsigned int reg32:1;
 731       unsigned int reg64:1;
 732       unsigned int floatreg:1;
 733       unsigned int regmmx:1;
 734       unsigned int regxmm:1;
 735       unsigned int regymm:1;
 736       unsigned int regzmm:1;
 737       unsigned int regmask:1;
 738       unsigned int control:1;
 739       unsigned int debug:1;
 740       unsigned int test:1;
 741       unsigned int sreg2:1;
 742       unsigned int sreg3:1;
 743       unsigned int imm1:1;
 744       unsigned int imm8:1;
 745       unsigned int imm8s:1;
 746       unsigned int imm16:1;
 747       unsigned int imm32:1;
 748       unsigned int imm32s:1;
 749       unsigned int imm64:1;
 750       unsigned int disp8:1;
 751       unsigned int disp16:1;
 752       unsigned int disp32:1;
 753       unsigned int disp32s:1;
 754       unsigned int disp64:1;
 755       unsigned int acc:1;
 756       unsigned int floatacc:1;
 757       unsigned int baseindex:1;
 758       unsigned int inoutportreg:1;
 759       unsigned int shiftcount:1;
 760       unsigned int jumpabsolute:1;
 761       unsigned int esseg:1;
 762       unsigned int regmem:1;
 763       unsigned int mem:1;
 764       unsigned int byte:1;
 765       unsigned int word:1;
 766       unsigned int dword:1;
 767       unsigned int fword:1;
 768       unsigned int qword:1;
 769       unsigned int tbyte:1;
 770       unsigned int xmmword:1;
 771       unsigned int ymmword:1;
 772       unsigned int zmmword:1;
 773       unsigned int unspecified:1;
 774       unsigned int anysize:1;
 775       unsigned int vec_imm4:1;
 776       unsigned int regbnd:1;
 777       unsigned int vec_disp8:1;
 778 #ifdef OTUnused
 779       unsigned int unused:(OTNumOfBits - OTUnused);
 780 #endif
 781     } bitfield;
 782   unsigned int array[OTNumOfUints];
 783 } i386_operand_type;
 784
 785 typedef struct insn_template
 786 {
 787   /* instruction name sans width suffix ("mov" for movl insns) */
 788   char *name;
 789
 790   /* how many operands */
 791   unsigned int operands;
 792
 793   /* base_opcode is the fundamental opcode byte without optional
 794      prefix(es).  */
 795   unsigned int base_opcode;
 796 #define Opcode_D        0x2 /* Direction bit:
 797                                set if Reg --> Regmem;
 798                                unset if Regmem --> Reg. */
 799 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 800 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 801
 802   /* extension_opcode is the 3 bit extension for group <n> insns.
 803      This field is also used to store the 8-bit opcode suffix for the
 804      AMD 3DNow! instructions.
 805      If this template has no extension opcode (the usual case) use None
 806      Instructions */
 807   unsigned int extension_opcode;
 808 #define None 0xffff             /* If no extension_opcode is possible.  */
 809
 810   /* Opcode length.  */
 811   unsigned char opcode_length;
 812
 813   /* cpu feature flags */
 814   i386_cpu_flags cpu_flags;
 815
 816   /* the bits in opcode_modifier are used to generate the final opcode from
 817      the base_opcode.  These bits also are used to detect alternate forms of
 818      the same instruction */
 819   i386_opcode_modifier opcode_modifier;
 820
 821   /* operand_types[i] describes the type of operand i.  This is made
 822      by OR'ing together all of the possible type masks.  (e.g.
 823      'operand_types[i] = Reg|Imm' specifies that operand i can be
 824      either a register or an immediate operand.  */
 825   i386_operand_type operand_types[MAX_OPERANDS];
 826 }
 827 insn_template;
 828
 829 extern const insn_template i386_optab[];
 830
 831 /* these are for register name --> number & type hash lookup */
 832 typedef struct
 833 {
 834   char *reg_name;
 835   i386_operand_type reg_type;
 836   unsigned char reg_flags;
 837 #define RegRex      0x1  /* Extended register.  */
 838 #define RegRex64    0x2  /* Extended 8 bit register.  */
 839 #define RegVRex     0x4  /* Extended vector register.  */
 840   unsigned char reg_num;
 841 #define RegRip  ((unsigned char ) ~0)
 842 #define RegEip  (RegRip - 1)
 843 /* EIZ and RIZ are fake index registers.  */
 844 #define RegEiz  (RegEip - 1)
 845 #define RegRiz  (RegEiz - 1)
 846 /* FLAT is a fake segment register (Intel mode).  */
 847 #define RegFlat     ((unsigned char) ~0)
 848   signed char dw2_regnum[2];
 849 #define Dw2Inval (-1)
 850 }
 851 reg_entry;
 852
 853 /* Entries in i386_regtab.  */
 854 #define REGNAM_AL 1
 855 #define REGNAM_AX 25
 856 #define REGNAM_EAX 41
 857
 858 extern const reg_entry i386_regtab[];
 859 extern const unsigned int i386_regtab_size;
 860
 861 typedef struct
 862 {
 863   char *seg_name;
 864   unsigned int seg_prefix;
 865 }
 866 seg_entry;
 867
 868 extern const seg_entry cs;
 869 extern const seg_entry ds;
 870 extern const seg_entry ss;
 871 extern const seg_entry es;
 872 extern const seg_entry fs;
 873 extern const seg_entry gs;