opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2018 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #ifdef HAVE_LIMITS_H
  23 #include <limits.h>
  24 #endif
  25
  26 #ifndef CHAR_BIT
  27 #define CHAR_BIT 8
  28 #endif
  29
  30 /* Position of cpu flags bitfiled.  */
  31
  32 enum
  33 {
  34   /* i186 or better required */
  35   Cpu186 = 0,
  36   /* i286 or better required */
  37   Cpu286,
  38   /* i386 or better required */
  39   Cpu386,
  40   /* i486 or better required */
  41   Cpu486,
  42   /* i585 or better required */
  43   Cpu586,
  44   /* i686 or better required */
  45   Cpu686,
  46   /* CLFLUSH Instruction support required */
  47   CpuClflush,
  48   /* NOP Instruction support required */
  49   CpuNop,
  50   /* SYSCALL Instructions support required */
  51   CpuSYSCALL,
  52   /* Floating point support required */
  53   Cpu8087,
  54   /* i287 support required */
  55   Cpu287,
  56   /* i387 support required */
  57   Cpu387,
  58   /* i686 and floating point support required */
  59   Cpu687,
  60   /* SSE3 and floating point support required */
  61   CpuFISTTP,
  62   /* MMX support required */
  63   CpuMMX,
  64   /* SSE support required */
  65   CpuSSE,
  66   /* SSE2 support required */
  67   CpuSSE2,
  68   /* 3dnow! support required */
  69   Cpu3dnow,
  70   /* 3dnow! Extensions support required */
  71   Cpu3dnowA,
  72   /* SSE3 support required */
  73   CpuSSE3,
  74   /* VIA PadLock required */
  75   CpuPadLock,
  76   /* AMD Secure Virtual Machine Ext-s required */
  77   CpuSVME,
  78   /* VMX Instructions required */
  79   CpuVMX,
  80   /* SMX Instructions required */
  81   CpuSMX,
  82   /* SSSE3 support required */
  83   CpuSSSE3,
  84   /* SSE4a support required */
  85   CpuSSE4a,
  86   /* ABM New Instructions required */
  87   CpuABM,
  88   /* SSE4.1 support required */
  89   CpuSSE4_1,
  90   /* SSE4.2 support required */
  91   CpuSSE4_2,
  92   /* AVX support required */
  93   CpuAVX,
  94   /* AVX2 support required */
  95   CpuAVX2,
  96   /* Intel AVX-512 Foundation Instructions support required */
  97   CpuAVX512F,
  98   /* Intel AVX-512 Conflict Detection Instructions support required */
  99   CpuAVX512CD,
 100   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 101      required */
 102   CpuAVX512ER,
 103   /* Intel AVX-512 Prefetch Instructions support required */
 104   CpuAVX512PF,
 105   /* Intel AVX-512 VL Instructions support required.  */
 106   CpuAVX512VL,
 107   /* Intel AVX-512 DQ Instructions support required.  */
 108   CpuAVX512DQ,
 109   /* Intel AVX-512 BW Instructions support required.  */
 110   CpuAVX512BW,
 111   /* Intel L1OM support required */
 112   CpuL1OM,
 113   /* Intel K1OM support required */
 114   CpuK1OM,
 115   /* Intel IAMCU support required */
 116   CpuIAMCU,
 117   /* Xsave/xrstor New Instructions support required */
 118   CpuXsave,
 119   /* Xsaveopt New Instructions support required */
 120   CpuXsaveopt,
 121   /* AES support required */
 122   CpuAES,
 123   /* PCLMUL support required */
 124   CpuPCLMUL,
 125   /* FMA support required */
 126   CpuFMA,
 127   /* FMA4 support required */
 128   CpuFMA4,
 129   /* XOP support required */
 130   CpuXOP,
 131   /* LWP support required */
 132   CpuLWP,
 133   /* BMI support required */
 134   CpuBMI,
 135   /* TBM support required */
 136   CpuTBM,
 137   /* MOVBE Instruction support required */
 138   CpuMovbe,
 139   /* CMPXCHG16B instruction support required.  */
 140   CpuCX16,
 141   /* EPT Instructions required */
 142   CpuEPT,
 143   /* RDTSCP Instruction support required */
 144   CpuRdtscp,
 145   /* FSGSBASE Instructions required */
 146   CpuFSGSBase,
 147   /* RDRND Instructions required */
 148   CpuRdRnd,
 149   /* F16C Instructions required */
 150   CpuF16C,
 151   /* Intel BMI2 support required */
 152   CpuBMI2,
 153   /* LZCNT support required */
 154   CpuLZCNT,
 155   /* HLE support required */
 156   CpuHLE,
 157   /* RTM support required */
 158   CpuRTM,
 159   /* INVPCID Instructions required */
 160   CpuINVPCID,
 161   /* VMFUNC Instruction required */
 162   CpuVMFUNC,
 163   /* Intel MPX Instructions required  */
 164   CpuMPX,
 165   /* 64bit support available, used by -march= in assembler.  */
 166   CpuLM,
 167   /* RDRSEED instruction required.  */
 168   CpuRDSEED,
 169   /* Multi-presisionn add-carry instructions are required.  */
 170   CpuADX,
 171   /* Supports prefetchw and prefetch instructions.  */
 172   CpuPRFCHW,
 173   /* SMAP instructions required.  */
 174   CpuSMAP,
 175   /* SHA instructions required.  */
 176   CpuSHA,
 177   /* VREX support required  */
 178   CpuVREX,
 179   /* CLFLUSHOPT instruction required */
 180   CpuClflushOpt,
 181   /* XSAVES/XRSTORS instruction required */
 182   CpuXSAVES,
 183   /* XSAVEC instruction required */
 184   CpuXSAVEC,
 185   /* PREFETCHWT1 instruction required */
 186   CpuPREFETCHWT1,
 187   /* SE1 instruction required */
 188   CpuSE1,
 189   /* CLWB instruction required */
 190   CpuCLWB,
 191   /* Intel AVX-512 IFMA Instructions support required.  */
 192   CpuAVX512IFMA,
 193   /* Intel AVX-512 VBMI Instructions support required.  */
 194   CpuAVX512VBMI,
 195   /* Intel AVX-512 4FMAPS Instructions support required.  */
 196   CpuAVX512_4FMAPS,
 197   /* Intel AVX-512 4VNNIW Instructions support required.  */
 198   CpuAVX512_4VNNIW,
 199   /* Intel AVX-512 VPOPCNTDQ Instructions support required.  */
 200   CpuAVX512_VPOPCNTDQ,
 201   /* Intel AVX-512 VBMI2 Instructions support required.  */
 202   CpuAVX512_VBMI2,
 203   /* Intel AVX-512 VNNI Instructions support required.  */
 204   CpuAVX512_VNNI,
 205   /* Intel AVX-512 BITALG Instructions support required.  */
 206   CpuAVX512_BITALG,
 207   /* mwaitx instruction required */
 208   CpuMWAITX,
 209   /* Clzero instruction required */
 210   CpuCLZERO,
 211   /* OSPKE instruction required */
 212   CpuOSPKE,
 213   /* RDPID instruction required */
 214   CpuRDPID,
 215   /* PTWRITE instruction required */
 216   CpuPTWRITE,
 217   /* CET instructions support required */
 218   CpuIBT,
 219   CpuSHSTK,
 220   /* GFNI instructions required */
 221   CpuGFNI,
 222   /* VAES instructions required */
 223   CpuVAES,
 224   /* VPCLMULQDQ instructions required */
 225   CpuVPCLMULQDQ,
 226   /* WBNOINVD instructions required */
 227   CpuWBNOINVD,
 228   /* PCONFIG instructions required */
 229   CpuPCONFIG,
 230   /* MMX register support required */
 231   CpuRegMMX,
 232   /* XMM register support required */
 233   CpuRegXMM,
 234   /* YMM register support required */
 235   CpuRegYMM,
 236   /* ZMM register support required */
 237   CpuRegZMM,
 238   /* Mask register support required */
 239   CpuRegMask,
 240   /* 64bit support required  */
 241   Cpu64,
 242   /* Not supported in the 64bit mode  */
 243   CpuNo64,
 244   /* The last bitfield in i386_cpu_flags.  */
 245   CpuMax = CpuNo64
 246 };
 247
 248 #define CpuNumOfUints \
 249   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 250 #define CpuNumOfBits \
 251   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 252
 253 /* If you get a compiler error for zero width of the unused field,
 254    comment it out.  */
 255 #define CpuUnused       (CpuMax + 1)
 256
 257 /* We can check if an instruction is available with array instead
 258    of bitfield. */
 259 typedef union i386_cpu_flags
 260 {
 261   struct
 262     {
 263       unsigned int cpui186:1;
 264       unsigned int cpui286:1;
 265       unsigned int cpui386:1;
 266       unsigned int cpui486:1;
 267       unsigned int cpui586:1;
 268       unsigned int cpui686:1;
 269       unsigned int cpuclflush:1;
 270       unsigned int cpunop:1;
 271       unsigned int cpusyscall:1;
 272       unsigned int cpu8087:1;
 273       unsigned int cpu287:1;
 274       unsigned int cpu387:1;
 275       unsigned int cpu687:1;
 276       unsigned int cpufisttp:1;
 277       unsigned int cpummx:1;
 278       unsigned int cpusse:1;
 279       unsigned int cpusse2:1;
 280       unsigned int cpua3dnow:1;
 281       unsigned int cpua3dnowa:1;
 282       unsigned int cpusse3:1;
 283       unsigned int cpupadlock:1;
 284       unsigned int cpusvme:1;
 285       unsigned int cpuvmx:1;
 286       unsigned int cpusmx:1;
 287       unsigned int cpussse3:1;
 288       unsigned int cpusse4a:1;
 289       unsigned int cpuabm:1;
 290       unsigned int cpusse4_1:1;
 291       unsigned int cpusse4_2:1;
 292       unsigned int cpuavx:1;
 293       unsigned int cpuavx2:1;
 294       unsigned int cpuavx512f:1;
 295       unsigned int cpuavx512cd:1;
 296       unsigned int cpuavx512er:1;
 297       unsigned int cpuavx512pf:1;
 298       unsigned int cpuavx512vl:1;
 299       unsigned int cpuavx512dq:1;
 300       unsigned int cpuavx512bw:1;
 301       unsigned int cpul1om:1;
 302       unsigned int cpuk1om:1;
 303       unsigned int cpuiamcu:1;
 304       unsigned int cpuxsave:1;
 305       unsigned int cpuxsaveopt:1;
 306       unsigned int cpuaes:1;
 307       unsigned int cpupclmul:1;
 308       unsigned int cpufma:1;
 309       unsigned int cpufma4:1;
 310       unsigned int cpuxop:1;
 311       unsigned int cpulwp:1;
 312       unsigned int cpubmi:1;
 313       unsigned int cputbm:1;
 314       unsigned int cpumovbe:1;
 315       unsigned int cpucx16:1;
 316       unsigned int cpuept:1;
 317       unsigned int cpurdtscp:1;
 318       unsigned int cpufsgsbase:1;
 319       unsigned int cpurdrnd:1;
 320       unsigned int cpuf16c:1;
 321       unsigned int cpubmi2:1;
 322       unsigned int cpulzcnt:1;
 323       unsigned int cpuhle:1;
 324       unsigned int cpurtm:1;
 325       unsigned int cpuinvpcid:1;
 326       unsigned int cpuvmfunc:1;
 327       unsigned int cpumpx:1;
 328       unsigned int cpulm:1;
 329       unsigned int cpurdseed:1;
 330       unsigned int cpuadx:1;
 331       unsigned int cpuprfchw:1;
 332       unsigned int cpusmap:1;
 333       unsigned int cpusha:1;
 334       unsigned int cpuvrex:1;
 335       unsigned int cpuclflushopt:1;
 336       unsigned int cpuxsaves:1;
 337       unsigned int cpuxsavec:1;
 338       unsigned int cpuprefetchwt1:1;
 339       unsigned int cpuse1:1;
 340       unsigned int cpuclwb:1;
 341       unsigned int cpuavx512ifma:1;
 342       unsigned int cpuavx512vbmi:1;
 343       unsigned int cpuavx512_4fmaps:1;
 344       unsigned int cpuavx512_4vnniw:1;
 345       unsigned int cpuavx512_vpopcntdq:1;
 346       unsigned int cpuavx512_vbmi2:1;
 347       unsigned int cpuavx512_vnni:1;
 348       unsigned int cpuavx512_bitalg:1;
 349       unsigned int cpumwaitx:1;
 350       unsigned int cpuclzero:1;
 351       unsigned int cpuospke:1;
 352       unsigned int cpurdpid:1;
 353       unsigned int cpuptwrite:1;
 354       unsigned int cpuibt:1;
 355       unsigned int cpushstk:1;
 356       unsigned int cpugfni:1;
 357       unsigned int cpuvaes:1;
 358       unsigned int cpuvpclmulqdq:1;
 359       unsigned int cpuwbnoinvd:1;
 360       unsigned int cpupconfig:1;
 361       unsigned int cpuregmmx:1;
 362       unsigned int cpuregxmm:1;
 363       unsigned int cpuregymm:1;
 364       unsigned int cpuregzmm:1;
 365       unsigned int cpuregmask:1;
 366       unsigned int cpu64:1;
 367       unsigned int cpuno64:1;
 368 #ifdef CpuUnused
 369       unsigned int unused:(CpuNumOfBits - CpuUnused);
 370 #endif
 371     } bitfield;
 372   unsigned int array[CpuNumOfUints];
 373 } i386_cpu_flags;
 374
 375 /* Position of opcode_modifier bits.  */
 376
 377 enum
 378 {
 379   /* has direction bit. */
 380   D = 0,
 381   /* set if operands can be words or dwords encoded the canonical way */
 382   W,
 383   /* load form instruction. Must be placed before store form.  */
 384   Load,
 385   /* insn has a modrm byte. */
 386   Modrm,
 387   /* register is in low 3 bits of opcode */
 388   ShortForm,
 389   /* special case for jump insns.  */
 390   Jump,
 391   /* call and jump */
 392   JumpDword,
 393   /* loop and jecxz */
 394   JumpByte,
 395   /* special case for intersegment leaps/calls */
 396   JumpInterSegment,
 397   /* FP insn memory format bit, sized by 0x4 */
 398   FloatMF,
 399   /* src/dest swap for floats. */
 400   FloatR,
 401   /* has float insn direction bit. */
 402   FloatD,
 403   /* needs size prefix if in 32-bit mode */
 404   Size16,
 405   /* needs size prefix if in 16-bit mode */
 406   Size32,
 407   /* needs size prefix if in 64-bit mode */
 408   Size64,
 409   /* check register size.  */
 410   CheckRegSize,
 411   /* instruction ignores operand size prefix and in Intel mode ignores
 412      mnemonic size suffix check.  */
 413   IgnoreSize,
 414   /* default insn size depends on mode */
 415   DefaultSize,
 416   /* b suffix on instruction illegal */
 417   No_bSuf,
 418   /* w suffix on instruction illegal */
 419   No_wSuf,
 420   /* l suffix on instruction illegal */
 421   No_lSuf,
 422   /* s suffix on instruction illegal */
 423   No_sSuf,
 424   /* q suffix on instruction illegal */
 425   No_qSuf,
 426   /* long double suffix on instruction illegal */
 427   No_ldSuf,
 428   /* instruction needs FWAIT */
 429   FWait,
 430   /* quick test for string instructions */
 431   IsString,
 432   /* quick test if branch instruction is MPX supported */
 433   BNDPrefixOk,
 434   /* quick test if NOTRACK prefix is supported */
 435   NoTrackPrefixOk,
 436   /* quick test for lockable instructions */
 437   IsLockable,
 438   /* fake an extra reg operand for clr, imul and special register
 439      processing for some instructions.  */
 440   RegKludge,
 441   /* An implicit xmm0 as the first operand */
 442   Implicit1stXmm0,
 443   /* The HLE prefix is OK:
 444      1. With a LOCK prefix.
 445      2. With or without a LOCK prefix.
 446      3. With a RELEASE (0xf3) prefix.
 447    */
 448 #define HLEPrefixNone           0
 449 #define HLEPrefixLock           1
 450 #define HLEPrefixAny            2
 451 #define HLEPrefixRelease        3
 452   HLEPrefixOk,
 453   /* An instruction on which a "rep" prefix is acceptable.  */
 454   RepPrefixOk,
 455   /* Convert to DWORD */
 456   ToDword,
 457   /* Convert to QWORD */
 458   ToQword,
 459   /* Address prefix changes operand 0 */
 460   AddrPrefixOp0,
 461   /* opcode is a prefix */
 462   IsPrefix,
 463   /* instruction has extension in 8 bit imm */
 464   ImmExt,
 465   /* instruction don't need Rex64 prefix.  */
 466   NoRex64,
 467   /* instruction require Rex64 prefix.  */
 468   Rex64,
 469   /* deprecated fp insn, gets a warning */
 470   Ugh,
 471   /* insn has VEX prefix:
 472         1: 128bit VEX prefix (or operand dependent).
 473         2: 256bit VEX prefix.
 474         3: Scalar VEX prefix.
 475    */
 476 #define VEX128          1
 477 #define VEX256          2
 478 #define VEXScalar       3
 479   Vex,
 480   /* How to encode VEX.vvvv:
 481      0: VEX.vvvv must be 1111b.
 482      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 483         the content of source registers will be preserved.
 484         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 485         where the content of first source register will be overwritten
 486         by the result.
 487         VEX.NDD2.  The second destination register operand is encoded in
 488         VEX.vvvv for instructions with 2 destination register operands.
 489         For assembler, there are no difference between VEX.NDS, VEX.DDS
 490         and VEX.NDD2.
 491      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 492      instructions with 1 destination register operand.
 493      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 494         of the operands can access a memory location.
 495    */
 496 #define VEXXDS  1
 497 #define VEXNDD  2
 498 #define VEXLWP  3
 499   VexVVVV,
 500   /* How the VEX.W bit is used:
 501      0: Set by the REX.W bit.
 502      1: VEX.W0.  Should always be 0.
 503      2: VEX.W1.  Should always be 1.
 504    */
 505 #define VEXW0   1
 506 #define VEXW1   2
 507   VexW,
 508   /* VEX opcode prefix:
 509      0: VEX 0x0F opcode prefix.
 510      1: VEX 0x0F38 opcode prefix.
 511      2: VEX 0x0F3A opcode prefix
 512      3: XOP 0x08 opcode prefix.
 513      4: XOP 0x09 opcode prefix
 514      5: XOP 0x0A opcode prefix.
 515    */
 516 #define VEX0F           0
 517 #define VEX0F38         1
 518 #define VEX0F3A         2
 519 #define XOP08           3
 520 #define XOP09           4
 521 #define XOP0A           5
 522   VexOpcode,
 523   /* number of VEX source operands:
 524      0: <= 2 source operands.
 525      1: 2 XOP source operands.
 526      2: 3 source operands.
 527    */
 528 #define XOP2SOURCES     1
 529 #define VEX3SOURCES     2
 530   VexSources,
 531   /* instruction has VEX 8 bit imm */
 532   VexImmExt,
 533   /* Instruction with vector SIB byte:
 534         1: 128bit vector register.
 535         2: 256bit vector register.
 536         3: 512bit vector register.
 537    */
 538 #define VecSIB128       1
 539 #define VecSIB256       2
 540 #define VecSIB512       3
 541   VecSIB,
 542   /* SSE to AVX support required */
 543   SSE2AVX,
 544   /* No AVX equivalent */
 545   NoAVX,
 546
 547   /* insn has EVEX prefix:
 548         1: 512bit EVEX prefix.
 549         2: 128bit EVEX prefix.
 550         3: 256bit EVEX prefix.
 551         4: Length-ignored (LIG) EVEX prefix.
 552    */
 553 #define EVEX512                1
 554 #define EVEX128                2
 555 #define EVEX256                3
 556 #define EVEXLIG                4
 557   EVex,
 558
 559   /* AVX512 masking support:
 560         1: Zeroing-masking.
 561         2: Merging-masking.
 562         3: Both zeroing and merging masking.
 563    */
 564 #define ZEROING_MASKING 1
 565 #define MERGING_MASKING 2
 566 #define BOTH_MASKING    3
 567   Masking,
 568
 569   /* Input element size of vector insn:
 570         0: 32bit.
 571         1: 64bit.
 572    */
 573   VecESize,
 574
 575   /* Broadcast factor.
 576         0: No broadcast.
 577         1: 1to16 broadcast.
 578         2: 1to8 broadcast.
 579    */
 580 #define NO_BROADCAST    0
 581 #define BROADCAST_1TO16 1
 582 #define BROADCAST_1TO8  2
 583 #define BROADCAST_1TO4  3
 584 #define BROADCAST_1TO2  4
 585   Broadcast,
 586
 587   /* Static rounding control is supported.  */
 588   StaticRounding,
 589
 590   /* Supress All Exceptions is supported.  */
 591   SAE,
 592
 593   /* Copressed Disp8*N attribute.  */
 594   Disp8MemShift,
 595
 596   /* Default mask isn't allowed.  */
 597   NoDefMask,
 598
 599   /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
 600      It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
 601    */
 602   ImplicitQuadGroup,
 603
 604   /* Support encoding optimization.  */
 605   Optimize,
 606
 607   /* Compatible with old (<= 2.8.1) versions of gcc  */
 608   OldGcc,
 609   /* AT&T mnemonic.  */
 610   ATTMnemonic,
 611   /* AT&T syntax.  */
 612   ATTSyntax,
 613   /* Intel syntax.  */
 614   IntelSyntax,
 615   /* AMD64.  */
 616   AMD64,
 617   /* Intel64.  */
 618   Intel64,
 619   /* The last bitfield in i386_opcode_modifier.  */
 620   Opcode_Modifier_Max
 621 };
 622
 623 typedef struct i386_opcode_modifier
 624 {
 625   unsigned int d:1;
 626   unsigned int w:1;
 627   unsigned int load:1;
 628   unsigned int modrm:1;
 629   unsigned int shortform:1;
 630   unsigned int jump:1;
 631   unsigned int jumpdword:1;
 632   unsigned int jumpbyte:1;
 633   unsigned int jumpintersegment:1;
 634   unsigned int floatmf:1;
 635   unsigned int floatr:1;
 636   unsigned int floatd:1;
 637   unsigned int size16:1;
 638   unsigned int size32:1;
 639   unsigned int size64:1;
 640   unsigned int checkregsize:1;
 641   unsigned int ignoresize:1;
 642   unsigned int defaultsize:1;
 643   unsigned int no_bsuf:1;
 644   unsigned int no_wsuf:1;
 645   unsigned int no_lsuf:1;
 646   unsigned int no_ssuf:1;
 647   unsigned int no_qsuf:1;
 648   unsigned int no_ldsuf:1;
 649   unsigned int fwait:1;
 650   unsigned int isstring:1;
 651   unsigned int bndprefixok:1;
 652   unsigned int notrackprefixok:1;
 653   unsigned int islockable:1;
 654   unsigned int regkludge:1;
 655   unsigned int implicit1stxmm0:1;
 656   unsigned int hleprefixok:2;
 657   unsigned int repprefixok:1;
 658   unsigned int todword:1;
 659   unsigned int toqword:1;
 660   unsigned int addrprefixop0:1;
 661   unsigned int isprefix:1;
 662   unsigned int immext:1;
 663   unsigned int norex64:1;
 664   unsigned int rex64:1;
 665   unsigned int ugh:1;
 666   unsigned int vex:2;
 667   unsigned int vexvvvv:2;
 668   unsigned int vexw:2;
 669   unsigned int vexopcode:3;
 670   unsigned int vexsources:2;
 671   unsigned int veximmext:1;
 672   unsigned int vecsib:2;
 673   unsigned int sse2avx:1;
 674   unsigned int noavx:1;
 675   unsigned int evex:3;
 676   unsigned int masking:2;
 677   unsigned int vecesize:1;
 678   unsigned int broadcast:3;
 679   unsigned int staticrounding:1;
 680   unsigned int sae:1;
 681   unsigned int disp8memshift:3;
 682   unsigned int nodefmask:1;
 683   unsigned int implicitquadgroup:1;
 684   unsigned int optimize:1;
 685   unsigned int oldgcc:1;
 686   unsigned int attmnemonic:1;
 687   unsigned int attsyntax:1;
 688   unsigned int intelsyntax:1;
 689   unsigned int amd64:1;
 690   unsigned int intel64:1;
 691 } i386_opcode_modifier;
 692
 693 /* Position of operand_type bits.  */
 694
 695 enum
 696 {
 697   /* Register (qualified by Byte, Word, etc) */
 698   Reg = 0,
 699   /* MMX register */
 700   RegMMX,
 701   /* Vector registers */
 702   RegSIMD,
 703   /* Vector Mask registers */
 704   RegMask,
 705   /* Control register */
 706   Control,
 707   /* Debug register */
 708   Debug,
 709   /* Test register */
 710   Test,
 711   /* 2 bit segment register */
 712   SReg2,
 713   /* 3 bit segment register */
 714   SReg3,
 715   /* 1 bit immediate */
 716   Imm1,
 717   /* 8 bit immediate */
 718   Imm8,
 719   /* 8 bit immediate sign extended */
 720   Imm8S,
 721   /* 16 bit immediate */
 722   Imm16,
 723   /* 32 bit immediate */
 724   Imm32,
 725   /* 32 bit immediate sign extended */
 726   Imm32S,
 727   /* 64 bit immediate */
 728   Imm64,
 729   /* 8bit/16bit/32bit displacements are used in different ways,
 730      depending on the instruction.  For jumps, they specify the
 731      size of the PC relative displacement, for instructions with
 732      memory operand, they specify the size of the offset relative
 733      to the base register, and for instructions with memory offset
 734      such as `mov 1234,%al' they specify the size of the offset
 735      relative to the segment base.  */
 736   /* 8 bit displacement */
 737   Disp8,
 738   /* 16 bit displacement */
 739   Disp16,
 740   /* 32 bit displacement */
 741   Disp32,
 742   /* 32 bit signed displacement */
 743   Disp32S,
 744   /* 64 bit displacement */
 745   Disp64,
 746   /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
 747   Acc,
 748   /* Register which can be used for base or index in memory operand.  */
 749   BaseIndex,
 750   /* Register to hold in/out port addr = dx */
 751   InOutPortReg,
 752   /* Register to hold shift count = cl */
 753   ShiftCount,
 754   /* Absolute address for jump.  */
 755   JumpAbsolute,
 756   /* String insn operand with fixed es segment */
 757   EsSeg,
 758   /* RegMem is for instructions with a modrm byte where the register
 759      destination operand should be encoded in the mod and regmem fields.
 760      Normally, it will be encoded in the reg field. We add a RegMem
 761      flag to the destination register operand to indicate that it should
 762      be encoded in the regmem field.  */
 763   RegMem,
 764   /* Memory.  */
 765   Mem,
 766   /* BYTE memory. */
 767   Byte,
 768   /* WORD memory. 2 byte */
 769   Word,
 770   /* DWORD memory. 4 byte */
 771   Dword,
 772   /* FWORD memory. 6 byte */
 773   Fword,
 774   /* QWORD memory. 8 byte */
 775   Qword,
 776   /* TBYTE memory. 10 byte */
 777   Tbyte,
 778   /* XMMWORD memory. */
 779   Xmmword,
 780   /* YMMWORD memory. */
 781   Ymmword,
 782   /* ZMMWORD memory.  */
 783   Zmmword,
 784   /* Unspecified memory size.  */
 785   Unspecified,
 786   /* Any memory size.  */
 787   Anysize,
 788
 789   /* Vector 4 bit immediate.  */
 790   Vec_Imm4,
 791
 792   /* Bound register.  */
 793   RegBND,
 794
 795   /* The last bitfield in i386_operand_type.  */
 796   OTMax
 797 };
 798
 799 #define OTNumOfUints \
 800   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 801 #define OTNumOfBits \
 802   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 803
 804 /* If you get a compiler error for zero width of the unused field,
 805    comment it out.  */
 806 #define OTUnused                (OTMax + 1)
 807
 808 typedef union i386_operand_type
 809 {
 810   struct
 811     {
 812       unsigned int reg:1;
 813       unsigned int regmmx:1;
 814       unsigned int regsimd:1;
 815       unsigned int regmask:1;
 816       unsigned int control:1;
 817       unsigned int debug:1;
 818       unsigned int test:1;
 819       unsigned int sreg2:1;
 820       unsigned int sreg3:1;
 821       unsigned int imm1:1;
 822       unsigned int imm8:1;
 823       unsigned int imm8s:1;
 824       unsigned int imm16:1;
 825       unsigned int imm32:1;
 826       unsigned int imm32s:1;
 827       unsigned int imm64:1;
 828       unsigned int disp8:1;
 829       unsigned int disp16:1;
 830       unsigned int disp32:1;
 831       unsigned int disp32s:1;
 832       unsigned int disp64:1;
 833       unsigned int acc:1;
 834       unsigned int baseindex:1;
 835       unsigned int inoutportreg:1;
 836       unsigned int shiftcount:1;
 837       unsigned int jumpabsolute:1;
 838       unsigned int esseg:1;
 839       unsigned int regmem:1;
 840       unsigned int mem:1;
 841       unsigned int byte:1;
 842       unsigned int word:1;
 843       unsigned int dword:1;
 844       unsigned int fword:1;
 845       unsigned int qword:1;
 846       unsigned int tbyte:1;
 847       unsigned int xmmword:1;
 848       unsigned int ymmword:1;
 849       unsigned int zmmword:1;
 850       unsigned int unspecified:1;
 851       unsigned int anysize:1;
 852       unsigned int vec_imm4:1;
 853       unsigned int regbnd:1;
 854 #ifdef OTUnused
 855       unsigned int unused:(OTNumOfBits - OTUnused);
 856 #endif
 857     } bitfield;
 858   unsigned int array[OTNumOfUints];
 859 } i386_operand_type;
 860
 861 typedef struct insn_template
 862 {
 863   /* instruction name sans width suffix ("mov" for movl insns) */
 864   char *name;
 865
 866   /* how many operands */
 867   unsigned int operands;
 868
 869   /* base_opcode is the fundamental opcode byte without optional
 870      prefix(es).  */
 871   unsigned int base_opcode;
 872 #define Opcode_D        0x2 /* Direction bit:
 873                                set if Reg --> Regmem;
 874                                unset if Regmem --> Reg. */
 875 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 876 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 877
 878   /* extension_opcode is the 3 bit extension for group <n> insns.
 879      This field is also used to store the 8-bit opcode suffix for the
 880      AMD 3DNow! instructions.
 881      If this template has no extension opcode (the usual case) use None
 882      Instructions */
 883   unsigned int extension_opcode;
 884 #define None 0xffff             /* If no extension_opcode is possible.  */
 885
 886   /* Opcode length.  */
 887   unsigned char opcode_length;
 888
 889   /* cpu feature flags */
 890   i386_cpu_flags cpu_flags;
 891
 892   /* the bits in opcode_modifier are used to generate the final opcode from
 893      the base_opcode.  These bits also are used to detect alternate forms of
 894      the same instruction */
 895   i386_opcode_modifier opcode_modifier;
 896
 897   /* operand_types[i] describes the type of operand i.  This is made
 898      by OR'ing together all of the possible type masks.  (e.g.
 899      'operand_types[i] = Reg|Imm' specifies that operand i can be
 900      either a register or an immediate operand.  */
 901   i386_operand_type operand_types[MAX_OPERANDS];
 902 }
 903 insn_template;
 904
 905 extern const insn_template i386_optab[];
 906
 907 /* these are for register name --> number & type hash lookup */
 908 typedef struct
 909 {
 910   char *reg_name;
 911   i386_operand_type reg_type;
 912   unsigned char reg_flags;
 913 #define RegRex      0x1  /* Extended register.  */
 914 #define RegRex64    0x2  /* Extended 8 bit register.  */
 915 #define RegVRex     0x4  /* Extended vector register.  */
 916   unsigned char reg_num;
 917 #define RegRip  ((unsigned char ) ~0)
 918 #define RegEip  (RegRip - 1)
 919 /* EIZ and RIZ are fake index registers.  */
 920 #define RegEiz  (RegEip - 1)
 921 #define RegRiz  (RegEiz - 1)
 922 /* FLAT is a fake segment register (Intel mode).  */
 923 #define RegFlat     ((unsigned char) ~0)
 924   signed char dw2_regnum[2];
 925 #define Dw2Inval (-1)
 926 }
 927 reg_entry;
 928
 929 /* Entries in i386_regtab.  */
 930 #define REGNAM_AL 1
 931 #define REGNAM_AX 25
 932 #define REGNAM_EAX 41
 933
 934 extern const reg_entry i386_regtab[];
 935 extern const unsigned int i386_regtab_size;
 936
 937 typedef struct
 938 {
 939   char *seg_name;
 940   unsigned int seg_prefix;
 941 }
 942 seg_entry;
 943
 944 extern const seg_entry cs;
 945 extern const seg_entry ds;
 946 extern const seg_entry ss;
 947 extern const seg_entry es;
 948 extern const seg_entry fs;
 949 extern const seg_entry gs;