opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2014 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #ifdef HAVE_LIMITS_H
  23 #include <limits.h>
  24 #endif
  25
  26 #ifndef CHAR_BIT
  27 #define CHAR_BIT 8
  28 #endif
  29
  30 /* Position of cpu flags bitfiled.  */
  31
  32 enum
  33 {
  34   /* i186 or better required */
  35   Cpu186 = 0,
  36   /* i286 or better required */
  37   Cpu286,
  38   /* i386 or better required */
  39   Cpu386,
  40   /* i486 or better required */
  41   Cpu486,
  42   /* i585 or better required */
  43   Cpu586,
  44   /* i686 or better required */
  45   Cpu686,
  46   /* CLFLUSH Instruction support required */
  47   CpuClflush,
  48   /* NOP Instruction support required */
  49   CpuNop,
  50   /* SYSCALL Instructions support required */
  51   CpuSYSCALL,
  52   /* Floating point support required */
  53   Cpu8087,
  54   /* i287 support required */
  55   Cpu287,
  56   /* i387 support required */
  57   Cpu387,
  58   /* i686 and floating point support required */
  59   Cpu687,
  60   /* SSE3 and floating point support required */
  61   CpuFISTTP,
  62   /* MMX support required */
  63   CpuMMX,
  64   /* SSE support required */
  65   CpuSSE,
  66   /* SSE2 support required */
  67   CpuSSE2,
  68   /* 3dnow! support required */
  69   Cpu3dnow,
  70   /* 3dnow! Extensions support required */
  71   Cpu3dnowA,
  72   /* SSE3 support required */
  73   CpuSSE3,
  74   /* VIA PadLock required */
  75   CpuPadLock,
  76   /* AMD Secure Virtual Machine Ext-s required */
  77   CpuSVME,
  78   /* VMX Instructions required */
  79   CpuVMX,
  80   /* SMX Instructions required */
  81   CpuSMX,
  82   /* SSSE3 support required */
  83   CpuSSSE3,
  84   /* SSE4a support required */
  85   CpuSSE4a,
  86   /* ABM New Instructions required */
  87   CpuABM,
  88   /* SSE4.1 support required */
  89   CpuSSE4_1,
  90   /* SSE4.2 support required */
  91   CpuSSE4_2,
  92   /* AVX support required */
  93   CpuAVX,
  94   /* AVX2 support required */
  95   CpuAVX2,
  96   /* Intel AVX-512 Foundation Instructions support required */
  97   CpuAVX512F,
  98   /* Intel AVX-512 Conflict Detection Instructions support required */
  99   CpuAVX512CD,
 100   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 101      required */
 102   CpuAVX512ER,
 103   /* Intel AVX-512 Prefetch Instructions support required */
 104   CpuAVX512PF,
 105   /* Intel AVX-512 VL Instructions support required.  */
 106   CpuAVX512VL,
 107   /* Intel AVX-512 DQ Instructions support required.  */
 108   CpuAVX512DQ,
 109   /* Intel AVX-512 BW Instructions support required.  */
 110   CpuAVX512BW,
 111   /* Intel L1OM support required */
 112   CpuL1OM,
 113   /* Intel K1OM support required */
 114   CpuK1OM,
 115   /* Xsave/xrstor New Instructions support required */
 116   CpuXsave,
 117   /* Xsaveopt New Instructions support required */
 118   CpuXsaveopt,
 119   /* AES support required */
 120   CpuAES,
 121   /* PCLMUL support required */
 122   CpuPCLMUL,
 123   /* FMA support required */
 124   CpuFMA,
 125   /* FMA4 support required */
 126   CpuFMA4,
 127   /* XOP support required */
 128   CpuXOP,
 129   /* LWP support required */
 130   CpuLWP,
 131   /* BMI support required */
 132   CpuBMI,
 133   /* TBM support required */
 134   CpuTBM,
 135   /* MOVBE Instruction support required */
 136   CpuMovbe,
 137   /* CMPXCHG16B instruction support required.  */
 138   CpuCX16,
 139   /* EPT Instructions required */
 140   CpuEPT,
 141   /* RDTSCP Instruction support required */
 142   CpuRdtscp,
 143   /* FSGSBASE Instructions required */
 144   CpuFSGSBase,
 145   /* RDRND Instructions required */
 146   CpuRdRnd,
 147   /* F16C Instructions required */
 148   CpuF16C,
 149   /* Intel BMI2 support required */
 150   CpuBMI2,
 151   /* LZCNT support required */
 152   CpuLZCNT,
 153   /* HLE support required */
 154   CpuHLE,
 155   /* RTM support required */
 156   CpuRTM,
 157   /* INVPCID Instructions required */
 158   CpuINVPCID,
 159   /* VMFUNC Instruction required */
 160   CpuVMFUNC,
 161   /* Intel MPX Instructions required  */
 162   CpuMPX,
 163   /* 64bit support available, used by -march= in assembler.  */
 164   CpuLM,
 165   /* RDRSEED instruction required.  */
 166   CpuRDSEED,
 167   /* Multi-presisionn add-carry instructions are required.  */
 168   CpuADX,
 169   /* Supports prefetchw and prefetch instructions.  */
 170   CpuPRFCHW,
 171   /* SMAP instructions required.  */
 172   CpuSMAP,
 173   /* SHA instructions required.  */
 174   CpuSHA,
 175   /* VREX support required  */
 176   CpuVREX,
 177   /* CLFLUSHOPT instruction required */
 178   CpuClflushOpt,
 179   /* XSAVES/XRSTORS instruction required */
 180   CpuXSAVES,
 181   /* XSAVEC instruction required */
 182   CpuXSAVEC,
 183   /* PREFETCHWT1 instruction required */
 184   CpuPREFETCHWT1,
 185   /* SE1 instruction required */
 186   CpuSE1,
 187   /* CLWB instruction required */
 188   CpuCLWB,
 189   /* 64bit support required  */
 190   Cpu64,
 191   /* Not supported in the 64bit mode  */
 192   CpuNo64,
 193   /* The last bitfield in i386_cpu_flags.  */
 194   CpuMax = CpuNo64
 195 };
 196
 197 #define CpuNumOfUints \
 198   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 199 #define CpuNumOfBits \
 200   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 201
 202 /* If you get a compiler error for zero width of the unused field,
 203    comment it out.  */
 204 #define CpuUnused       (CpuMax + 1)
 205
 206 /* We can check if an instruction is available with array instead
 207    of bitfield. */
 208 typedef union i386_cpu_flags
 209 {
 210   struct
 211     {
 212       unsigned int cpui186:1;
 213       unsigned int cpui286:1;
 214       unsigned int cpui386:1;
 215       unsigned int cpui486:1;
 216       unsigned int cpui586:1;
 217       unsigned int cpui686:1;
 218       unsigned int cpuclflush:1;
 219       unsigned int cpunop:1;
 220       unsigned int cpusyscall:1;
 221       unsigned int cpu8087:1;
 222       unsigned int cpu287:1;
 223       unsigned int cpu387:1;
 224       unsigned int cpu687:1;
 225       unsigned int cpufisttp:1;
 226       unsigned int cpummx:1;
 227       unsigned int cpusse:1;
 228       unsigned int cpusse2:1;
 229       unsigned int cpua3dnow:1;
 230       unsigned int cpua3dnowa:1;
 231       unsigned int cpusse3:1;
 232       unsigned int cpupadlock:1;
 233       unsigned int cpusvme:1;
 234       unsigned int cpuvmx:1;
 235       unsigned int cpusmx:1;
 236       unsigned int cpussse3:1;
 237       unsigned int cpusse4a:1;
 238       unsigned int cpuabm:1;
 239       unsigned int cpusse4_1:1;
 240       unsigned int cpusse4_2:1;
 241       unsigned int cpuavx:1;
 242       unsigned int cpuavx2:1;
 243       unsigned int cpuavx512f:1;
 244       unsigned int cpuavx512cd:1;
 245       unsigned int cpuavx512er:1;
 246       unsigned int cpuavx512pf:1;
 247       unsigned int cpuavx512vl:1;
 248       unsigned int cpuavx512dq:1;
 249       unsigned int cpuavx512bw:1;
 250       unsigned int cpul1om:1;
 251       unsigned int cpuk1om:1;
 252       unsigned int cpuxsave:1;
 253       unsigned int cpuxsaveopt:1;
 254       unsigned int cpuaes:1;
 255       unsigned int cpupclmul:1;
 256       unsigned int cpufma:1;
 257       unsigned int cpufma4:1;
 258       unsigned int cpuxop:1;
 259       unsigned int cpulwp:1;
 260       unsigned int cpubmi:1;
 261       unsigned int cputbm:1;
 262       unsigned int cpumovbe:1;
 263       unsigned int cpucx16:1;
 264       unsigned int cpuept:1;
 265       unsigned int cpurdtscp:1;
 266       unsigned int cpufsgsbase:1;
 267       unsigned int cpurdrnd:1;
 268       unsigned int cpuf16c:1;
 269       unsigned int cpubmi2:1;
 270       unsigned int cpulzcnt:1;
 271       unsigned int cpuhle:1;
 272       unsigned int cpurtm:1;
 273       unsigned int cpuinvpcid:1;
 274       unsigned int cpuvmfunc:1;
 275       unsigned int cpumpx:1;
 276       unsigned int cpulm:1;
 277       unsigned int cpurdseed:1;
 278       unsigned int cpuadx:1;
 279       unsigned int cpuprfchw:1;
 280       unsigned int cpusmap:1;
 281       unsigned int cpusha:1;
 282       unsigned int cpuvrex:1;
 283       unsigned int cpuclflushopt:1;
 284       unsigned int cpuxsaves:1;
 285       unsigned int cpuxsavec:1;
 286       unsigned int cpuprefetchwt1:1;
 287       unsigned int cpuse1:1;
 288       unsigned int cpuclwb:1;
 289       unsigned int cpu64:1;
 290       unsigned int cpuno64:1;
 291 #ifdef CpuUnused
 292       unsigned int unused:(CpuNumOfBits - CpuUnused);
 293 #endif
 294     } bitfield;
 295   unsigned int array[CpuNumOfUints];
 296 } i386_cpu_flags;
 297
 298 /* Position of opcode_modifier bits.  */
 299
 300 enum
 301 {
 302   /* has direction bit. */
 303   D = 0,
 304   /* set if operands can be words or dwords encoded the canonical way */
 305   W,
 306   /* Skip the current insn and use the next insn in i386-opc.tbl to swap
 307      operand in encoding.  */
 308   S,
 309   /* insn has a modrm byte. */
 310   Modrm,
 311   /* register is in low 3 bits of opcode */
 312   ShortForm,
 313   /* special case for jump insns.  */
 314   Jump,
 315   /* call and jump */
 316   JumpDword,
 317   /* loop and jecxz */
 318   JumpByte,
 319   /* special case for intersegment leaps/calls */
 320   JumpInterSegment,
 321   /* FP insn memory format bit, sized by 0x4 */
 322   FloatMF,
 323   /* src/dest swap for floats. */
 324   FloatR,
 325   /* has float insn direction bit. */
 326   FloatD,
 327   /* needs size prefix if in 32-bit mode */
 328   Size16,
 329   /* needs size prefix if in 16-bit mode */
 330   Size32,
 331   /* needs size prefix if in 64-bit mode */
 332   Size64,
 333   /* check register size.  */
 334   CheckRegSize,
 335   /* instruction ignores operand size prefix and in Intel mode ignores
 336      mnemonic size suffix check.  */
 337   IgnoreSize,
 338   /* default insn size depends on mode */
 339   DefaultSize,
 340   /* b suffix on instruction illegal */
 341   No_bSuf,
 342   /* w suffix on instruction illegal */
 343   No_wSuf,
 344   /* l suffix on instruction illegal */
 345   No_lSuf,
 346   /* s suffix on instruction illegal */
 347   No_sSuf,
 348   /* q suffix on instruction illegal */
 349   No_qSuf,
 350   /* long double suffix on instruction illegal */
 351   No_ldSuf,
 352   /* instruction needs FWAIT */
 353   FWait,
 354   /* quick test for string instructions */
 355   IsString,
 356   /* quick test if branch instruction is MPX supported */
 357   BNDPrefixOk,
 358   /* quick test for lockable instructions */
 359   IsLockable,
 360   /* fake an extra reg operand for clr, imul and special register
 361      processing for some instructions.  */
 362   RegKludge,
 363   /* The first operand must be xmm0 */
 364   FirstXmm0,
 365   /* An implicit xmm0 as the first operand */
 366   Implicit1stXmm0,
 367   /* The HLE prefix is OK:
 368      1. With a LOCK prefix.
 369      2. With or without a LOCK prefix.
 370      3. With a RELEASE (0xf3) prefix.
 371    */
 372 #define HLEPrefixNone           0
 373 #define HLEPrefixLock           1
 374 #define HLEPrefixAny            2
 375 #define HLEPrefixRelease        3
 376   HLEPrefixOk,
 377   /* An instruction on which a "rep" prefix is acceptable.  */
 378   RepPrefixOk,
 379   /* Convert to DWORD */
 380   ToDword,
 381   /* Convert to QWORD */
 382   ToQword,
 383   /* Address prefix changes operand 0 */
 384   AddrPrefixOp0,
 385   /* opcode is a prefix */
 386   IsPrefix,
 387   /* instruction has extension in 8 bit imm */
 388   ImmExt,
 389   /* instruction don't need Rex64 prefix.  */
 390   NoRex64,
 391   /* instruction require Rex64 prefix.  */
 392   Rex64,
 393   /* deprecated fp insn, gets a warning */
 394   Ugh,
 395   /* insn has VEX prefix:
 396         1: 128bit VEX prefix.
 397         2: 256bit VEX prefix.
 398         3: Scalar VEX prefix.
 399    */
 400 #define VEX128          1
 401 #define VEX256          2
 402 #define VEXScalar       3
 403   Vex,
 404   /* How to encode VEX.vvvv:
 405      0: VEX.vvvv must be 1111b.
 406      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 407         the content of source registers will be preserved.
 408         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 409         where the content of first source register will be overwritten
 410         by the result.
 411         VEX.NDD2.  The second destination register operand is encoded in
 412         VEX.vvvv for instructions with 2 destination register operands.
 413         For assembler, there are no difference between VEX.NDS, VEX.DDS
 414         and VEX.NDD2.
 415      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 416      instructions with 1 destination register operand.
 417      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 418         of the operands can access a memory location.
 419    */
 420 #define VEXXDS  1
 421 #define VEXNDD  2
 422 #define VEXLWP  3
 423   VexVVVV,
 424   /* How the VEX.W bit is used:
 425      0: Set by the REX.W bit.
 426      1: VEX.W0.  Should always be 0.
 427      2: VEX.W1.  Should always be 1.
 428    */
 429 #define VEXW0   1
 430 #define VEXW1   2
 431   VexW,
 432   /* VEX opcode prefix:
 433      0: VEX 0x0F opcode prefix.
 434      1: VEX 0x0F38 opcode prefix.
 435      2: VEX 0x0F3A opcode prefix
 436      3: XOP 0x08 opcode prefix.
 437      4: XOP 0x09 opcode prefix
 438      5: XOP 0x0A opcode prefix.
 439    */
 440 #define VEX0F           0
 441 #define VEX0F38         1
 442 #define VEX0F3A         2
 443 #define XOP08           3
 444 #define XOP09           4
 445 #define XOP0A           5
 446   VexOpcode,
 447   /* number of VEX source operands:
 448      0: <= 2 source operands.
 449      1: 2 XOP source operands.
 450      2: 3 source operands.
 451    */
 452 #define XOP2SOURCES     1
 453 #define VEX3SOURCES     2
 454   VexSources,
 455   /* instruction has VEX 8 bit imm */
 456   VexImmExt,
 457   /* Instruction with vector SIB byte:
 458         1: 128bit vector register.
 459         2: 256bit vector register.
 460         3: 512bit vector register.
 461    */
 462 #define VecSIB128       1
 463 #define VecSIB256       2
 464 #define VecSIB512       3
 465   VecSIB,
 466   /* SSE to AVX support required */
 467   SSE2AVX,
 468   /* No AVX equivalent */
 469   NoAVX,
 470
 471   /* insn has EVEX prefix:
 472         1: 512bit EVEX prefix.
 473         2: 128bit EVEX prefix.
 474         3: 256bit EVEX prefix.
 475         4: Length-ignored (LIG) EVEX prefix.
 476    */
 477 #define EVEX512                1
 478 #define EVEX128                2
 479 #define EVEX256                3
 480 #define EVEXLIG                4
 481   EVex,
 482
 483   /* AVX512 masking support:
 484         1: Zeroing-masking.
 485         2: Merging-masking.
 486         3: Both zeroing and merging masking.
 487    */
 488 #define ZEROING_MASKING 1
 489 #define MERGING_MASKING 2
 490 #define BOTH_MASKING    3
 491   Masking,
 492
 493   /* Input element size of vector insn:
 494         0: 32bit.
 495         1: 64bit.
 496    */
 497   VecESize,
 498
 499   /* Broadcast factor.
 500         0: No broadcast.
 501         1: 1to16 broadcast.
 502         2: 1to8 broadcast.
 503    */
 504 #define NO_BROADCAST    0
 505 #define BROADCAST_1TO16 1
 506 #define BROADCAST_1TO8  2
 507 #define BROADCAST_1TO4  3
 508 #define BROADCAST_1TO2  4
 509   Broadcast,
 510
 511   /* Static rounding control is supported.  */
 512   StaticRounding,
 513
 514   /* Supress All Exceptions is supported.  */
 515   SAE,
 516
 517   /* Copressed Disp8*N attribute.  */
 518   Disp8MemShift,
 519
 520   /* Default mask isn't allowed.  */
 521   NoDefMask,
 522
 523   /* Compatible with old (<= 2.8.1) versions of gcc  */
 524   OldGcc,
 525   /* AT&T mnemonic.  */
 526   ATTMnemonic,
 527   /* AT&T syntax.  */
 528   ATTSyntax,
 529   /* Intel syntax.  */
 530   IntelSyntax,
 531   /* The last bitfield in i386_opcode_modifier.  */
 532   Opcode_Modifier_Max
 533 };
 534
 535 typedef struct i386_opcode_modifier
 536 {
 537   unsigned int d:1;
 538   unsigned int w:1;
 539   unsigned int s:1;
 540   unsigned int modrm:1;
 541   unsigned int shortform:1;
 542   unsigned int jump:1;
 543   unsigned int jumpdword:1;
 544   unsigned int jumpbyte:1;
 545   unsigned int jumpintersegment:1;
 546   unsigned int floatmf:1;
 547   unsigned int floatr:1;
 548   unsigned int floatd:1;
 549   unsigned int size16:1;
 550   unsigned int size32:1;
 551   unsigned int size64:1;
 552   unsigned int checkregsize:1;
 553   unsigned int ignoresize:1;
 554   unsigned int defaultsize:1;
 555   unsigned int no_bsuf:1;
 556   unsigned int no_wsuf:1;
 557   unsigned int no_lsuf:1;
 558   unsigned int no_ssuf:1;
 559   unsigned int no_qsuf:1;
 560   unsigned int no_ldsuf:1;
 561   unsigned int fwait:1;
 562   unsigned int isstring:1;
 563   unsigned int bndprefixok:1;
 564   unsigned int islockable:1;
 565   unsigned int regkludge:1;
 566   unsigned int firstxmm0:1;
 567   unsigned int implicit1stxmm0:1;
 568   unsigned int hleprefixok:2;
 569   unsigned int repprefixok:1;
 570   unsigned int todword:1;
 571   unsigned int toqword:1;
 572   unsigned int addrprefixop0:1;
 573   unsigned int isprefix:1;
 574   unsigned int immext:1;
 575   unsigned int norex64:1;
 576   unsigned int rex64:1;
 577   unsigned int ugh:1;
 578   unsigned int vex:2;
 579   unsigned int vexvvvv:2;
 580   unsigned int vexw:2;
 581   unsigned int vexopcode:3;
 582   unsigned int vexsources:2;
 583   unsigned int veximmext:1;
 584   unsigned int vecsib:2;
 585   unsigned int sse2avx:1;
 586   unsigned int noavx:1;
 587   unsigned int evex:3;
 588   unsigned int masking:2;
 589   unsigned int vecesize:1;
 590   unsigned int broadcast:3;
 591   unsigned int staticrounding:1;
 592   unsigned int sae:1;
 593   unsigned int disp8memshift:3;
 594   unsigned int nodefmask:1;
 595   unsigned int oldgcc:1;
 596   unsigned int attmnemonic:1;
 597   unsigned int attsyntax:1;
 598   unsigned int intelsyntax:1;
 599 } i386_opcode_modifier;
 600
 601 /* Position of operand_type bits.  */
 602
 603 enum
 604 {
 605   /* 8bit register */
 606   Reg8 = 0,
 607   /* 16bit register */
 608   Reg16,
 609   /* 32bit register */
 610   Reg32,
 611   /* 64bit register */
 612   Reg64,
 613   /* Floating pointer stack register */
 614   FloatReg,
 615   /* MMX register */
 616   RegMMX,
 617   /* SSE register */
 618   RegXMM,
 619   /* AVX registers */
 620   RegYMM,
 621   /* AVX512 registers */
 622   RegZMM,
 623   /* Vector Mask registers */
 624   RegMask,
 625   /* Control register */
 626   Control,
 627   /* Debug register */
 628   Debug,
 629   /* Test register */
 630   Test,
 631   /* 2 bit segment register */
 632   SReg2,
 633   /* 3 bit segment register */
 634   SReg3,
 635   /* 1 bit immediate */
 636   Imm1,
 637   /* 8 bit immediate */
 638   Imm8,
 639   /* 8 bit immediate sign extended */
 640   Imm8S,
 641   /* 16 bit immediate */
 642   Imm16,
 643   /* 32 bit immediate */
 644   Imm32,
 645   /* 32 bit immediate sign extended */
 646   Imm32S,
 647   /* 64 bit immediate */
 648   Imm64,
 649   /* 8bit/16bit/32bit displacements are used in different ways,
 650      depending on the instruction.  For jumps, they specify the
 651      size of the PC relative displacement, for instructions with
 652      memory operand, they specify the size of the offset relative
 653      to the base register, and for instructions with memory offset
 654      such as `mov 1234,%al' they specify the size of the offset
 655      relative to the segment base.  */
 656   /* 8 bit displacement */
 657   Disp8,
 658   /* 16 bit displacement */
 659   Disp16,
 660   /* 32 bit displacement */
 661   Disp32,
 662   /* 32 bit signed displacement */
 663   Disp32S,
 664   /* 64 bit displacement */
 665   Disp64,
 666   /* Accumulator %al/%ax/%eax/%rax */
 667   Acc,
 668   /* Floating pointer top stack register %st(0) */
 669   FloatAcc,
 670   /* Register which can be used for base or index in memory operand.  */
 671   BaseIndex,
 672   /* Register to hold in/out port addr = dx */
 673   InOutPortReg,
 674   /* Register to hold shift count = cl */
 675   ShiftCount,
 676   /* Absolute address for jump.  */
 677   JumpAbsolute,
 678   /* String insn operand with fixed es segment */
 679   EsSeg,
 680   /* RegMem is for instructions with a modrm byte where the register
 681      destination operand should be encoded in the mod and regmem fields.
 682      Normally, it will be encoded in the reg field. We add a RegMem
 683      flag to the destination register operand to indicate that it should
 684      be encoded in the regmem field.  */
 685   RegMem,
 686   /* Memory.  */
 687   Mem,
 688   /* BYTE memory. */
 689   Byte,
 690   /* WORD memory. 2 byte */
 691   Word,
 692   /* DWORD memory. 4 byte */
 693   Dword,
 694   /* FWORD memory. 6 byte */
 695   Fword,
 696   /* QWORD memory. 8 byte */
 697   Qword,
 698   /* TBYTE memory. 10 byte */
 699   Tbyte,
 700   /* XMMWORD memory. */
 701   Xmmword,
 702   /* YMMWORD memory. */
 703   Ymmword,
 704   /* ZMMWORD memory.  */
 705   Zmmword,
 706   /* Unspecified memory size.  */
 707   Unspecified,
 708   /* Any memory size.  */
 709   Anysize,
 710
 711   /* Vector 4 bit immediate.  */
 712   Vec_Imm4,
 713
 714   /* Bound register.  */
 715   RegBND,
 716
 717   /* Vector 8bit displacement */
 718   Vec_Disp8,
 719
 720   /* The last bitfield in i386_operand_type.  */
 721   OTMax
 722 };
 723
 724 #define OTNumOfUints \
 725   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 726 #define OTNumOfBits \
 727   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 728
 729 /* If you get a compiler error for zero width of the unused field,
 730    comment it out.  */
 731 #define OTUnused                (OTMax + 1)
 732
 733 typedef union i386_operand_type
 734 {
 735   struct
 736     {
 737       unsigned int reg8:1;
 738       unsigned int reg16:1;
 739       unsigned int reg32:1;
 740       unsigned int reg64:1;
 741       unsigned int floatreg:1;
 742       unsigned int regmmx:1;
 743       unsigned int regxmm:1;
 744       unsigned int regymm:1;
 745       unsigned int regzmm:1;
 746       unsigned int regmask:1;
 747       unsigned int control:1;
 748       unsigned int debug:1;
 749       unsigned int test:1;
 750       unsigned int sreg2:1;
 751       unsigned int sreg3:1;
 752       unsigned int imm1:1;
 753       unsigned int imm8:1;
 754       unsigned int imm8s:1;
 755       unsigned int imm16:1;
 756       unsigned int imm32:1;
 757       unsigned int imm32s:1;
 758       unsigned int imm64:1;
 759       unsigned int disp8:1;
 760       unsigned int disp16:1;
 761       unsigned int disp32:1;
 762       unsigned int disp32s:1;
 763       unsigned int disp64:1;
 764       unsigned int acc:1;
 765       unsigned int floatacc:1;
 766       unsigned int baseindex:1;
 767       unsigned int inoutportreg:1;
 768       unsigned int shiftcount:1;
 769       unsigned int jumpabsolute:1;
 770       unsigned int esseg:1;
 771       unsigned int regmem:1;
 772       unsigned int mem:1;
 773       unsigned int byte:1;
 774       unsigned int word:1;
 775       unsigned int dword:1;
 776       unsigned int fword:1;
 777       unsigned int qword:1;
 778       unsigned int tbyte:1;
 779       unsigned int xmmword:1;
 780       unsigned int ymmword:1;
 781       unsigned int zmmword:1;
 782       unsigned int unspecified:1;
 783       unsigned int anysize:1;
 784       unsigned int vec_imm4:1;
 785       unsigned int regbnd:1;
 786       unsigned int vec_disp8:1;
 787 #ifdef OTUnused
 788       unsigned int unused:(OTNumOfBits - OTUnused);
 789 #endif
 790     } bitfield;
 791   unsigned int array[OTNumOfUints];
 792 } i386_operand_type;
 793
 794 typedef struct insn_template
 795 {
 796   /* instruction name sans width suffix ("mov" for movl insns) */
 797   char *name;
 798
 799   /* how many operands */
 800   unsigned int operands;
 801
 802   /* base_opcode is the fundamental opcode byte without optional
 803      prefix(es).  */
 804   unsigned int base_opcode;
 805 #define Opcode_D        0x2 /* Direction bit:
 806                                set if Reg --> Regmem;
 807                                unset if Regmem --> Reg. */
 808 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 809 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 810
 811   /* extension_opcode is the 3 bit extension for group <n> insns.
 812      This field is also used to store the 8-bit opcode suffix for the
 813      AMD 3DNow! instructions.
 814      If this template has no extension opcode (the usual case) use None
 815      Instructions */
 816   unsigned int extension_opcode;
 817 #define None 0xffff             /* If no extension_opcode is possible.  */
 818
 819   /* Opcode length.  */
 820   unsigned char opcode_length;
 821
 822   /* cpu feature flags */
 823   i386_cpu_flags cpu_flags;
 824
 825   /* the bits in opcode_modifier are used to generate the final opcode from
 826      the base_opcode.  These bits also are used to detect alternate forms of
 827      the same instruction */
 828   i386_opcode_modifier opcode_modifier;
 829
 830   /* operand_types[i] describes the type of operand i.  This is made
 831      by OR'ing together all of the possible type masks.  (e.g.
 832      'operand_types[i] = Reg|Imm' specifies that operand i can be
 833      either a register or an immediate operand.  */
 834   i386_operand_type operand_types[MAX_OPERANDS];
 835 }
 836 insn_template;
 837
 838 extern const insn_template i386_optab[];
 839
 840 /* these are for register name --> number & type hash lookup */
 841 typedef struct
 842 {
 843   char *reg_name;
 844   i386_operand_type reg_type;
 845   unsigned char reg_flags;
 846 #define RegRex      0x1  /* Extended register.  */
 847 #define RegRex64    0x2  /* Extended 8 bit register.  */
 848 #define RegVRex     0x4  /* Extended vector register.  */
 849   unsigned char reg_num;
 850 #define RegRip  ((unsigned char ) ~0)
 851 #define RegEip  (RegRip - 1)
 852 /* EIZ and RIZ are fake index registers.  */
 853 #define RegEiz  (RegEip - 1)
 854 #define RegRiz  (RegEiz - 1)
 855 /* FLAT is a fake segment register (Intel mode).  */
 856 #define RegFlat     ((unsigned char) ~0)
 857   signed char dw2_regnum[2];
 858 #define Dw2Inval (-1)
 859 }
 860 reg_entry;
 861
 862 /* Entries in i386_regtab.  */
 863 #define REGNAM_AL 1
 864 #define REGNAM_AX 25
 865 #define REGNAM_EAX 41
 866
 867 extern const reg_entry i386_regtab[];
 868 extern const unsigned int i386_regtab_size;
 869
 870 typedef struct
 871 {
 872   char *seg_name;
 873   unsigned int seg_prefix;
 874 }
 875 seg_entry;
 876
 877 extern const seg_entry cs;
 878 extern const seg_entry ds;
 879 extern const seg_entry ss;
 880 extern const seg_entry es;
 881 extern const seg_entry fs;
 882 extern const seg_entry gs;