opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2018 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #ifdef HAVE_LIMITS_H
  23 #include <limits.h>
  24 #endif
  25
  26 #ifndef CHAR_BIT
  27 #define CHAR_BIT 8
  28 #endif
  29
  30 /* Position of cpu flags bitfiled.  */
  31
  32 enum
  33 {
  34   /* i186 or better required */
  35   Cpu186 = 0,
  36   /* i286 or better required */
  37   Cpu286,
  38   /* i386 or better required */
  39   Cpu386,
  40   /* i486 or better required */
  41   Cpu486,
  42   /* i585 or better required */
  43   Cpu586,
  44   /* i686 or better required */
  45   Cpu686,
  46   /* CLFLUSH Instruction support required */
  47   CpuClflush,
  48   /* NOP Instruction support required */
  49   CpuNop,
  50   /* SYSCALL Instructions support required */
  51   CpuSYSCALL,
  52   /* Floating point support required */
  53   Cpu8087,
  54   /* i287 support required */
  55   Cpu287,
  56   /* i387 support required */
  57   Cpu387,
  58   /* i686 and floating point support required */
  59   Cpu687,
  60   /* SSE3 and floating point support required */
  61   CpuFISTTP,
  62   /* MMX support required */
  63   CpuMMX,
  64   /* SSE support required */
  65   CpuSSE,
  66   /* SSE2 support required */
  67   CpuSSE2,
  68   /* 3dnow! support required */
  69   Cpu3dnow,
  70   /* 3dnow! Extensions support required */
  71   Cpu3dnowA,
  72   /* SSE3 support required */
  73   CpuSSE3,
  74   /* VIA PadLock required */
  75   CpuPadLock,
  76   /* AMD Secure Virtual Machine Ext-s required */
  77   CpuSVME,
  78   /* VMX Instructions required */
  79   CpuVMX,
  80   /* SMX Instructions required */
  81   CpuSMX,
  82   /* SSSE3 support required */
  83   CpuSSSE3,
  84   /* SSE4a support required */
  85   CpuSSE4a,
  86   /* ABM New Instructions required */
  87   CpuABM,
  88   /* SSE4.1 support required */
  89   CpuSSE4_1,
  90   /* SSE4.2 support required */
  91   CpuSSE4_2,
  92   /* AVX support required */
  93   CpuAVX,
  94   /* AVX2 support required */
  95   CpuAVX2,
  96   /* Intel AVX-512 Foundation Instructions support required */
  97   CpuAVX512F,
  98   /* Intel AVX-512 Conflict Detection Instructions support required */
  99   CpuAVX512CD,
 100   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 101      required */
 102   CpuAVX512ER,
 103   /* Intel AVX-512 Prefetch Instructions support required */
 104   CpuAVX512PF,
 105   /* Intel AVX-512 VL Instructions support required.  */
 106   CpuAVX512VL,
 107   /* Intel AVX-512 DQ Instructions support required.  */
 108   CpuAVX512DQ,
 109   /* Intel AVX-512 BW Instructions support required.  */
 110   CpuAVX512BW,
 111   /* Intel L1OM support required */
 112   CpuL1OM,
 113   /* Intel K1OM support required */
 114   CpuK1OM,
 115   /* Intel IAMCU support required */
 116   CpuIAMCU,
 117   /* Xsave/xrstor New Instructions support required */
 118   CpuXsave,
 119   /* Xsaveopt New Instructions support required */
 120   CpuXsaveopt,
 121   /* AES support required */
 122   CpuAES,
 123   /* PCLMUL support required */
 124   CpuPCLMUL,
 125   /* FMA support required */
 126   CpuFMA,
 127   /* FMA4 support required */
 128   CpuFMA4,
 129   /* XOP support required */
 130   CpuXOP,
 131   /* LWP support required */
 132   CpuLWP,
 133   /* BMI support required */
 134   CpuBMI,
 135   /* TBM support required */
 136   CpuTBM,
 137   /* MOVBE Instruction support required */
 138   CpuMovbe,
 139   /* CMPXCHG16B instruction support required.  */
 140   CpuCX16,
 141   /* EPT Instructions required */
 142   CpuEPT,
 143   /* RDTSCP Instruction support required */
 144   CpuRdtscp,
 145   /* FSGSBASE Instructions required */
 146   CpuFSGSBase,
 147   /* RDRND Instructions required */
 148   CpuRdRnd,
 149   /* F16C Instructions required */
 150   CpuF16C,
 151   /* Intel BMI2 support required */
 152   CpuBMI2,
 153   /* LZCNT support required */
 154   CpuLZCNT,
 155   /* HLE support required */
 156   CpuHLE,
 157   /* RTM support required */
 158   CpuRTM,
 159   /* INVPCID Instructions required */
 160   CpuINVPCID,
 161   /* VMFUNC Instruction required */
 162   CpuVMFUNC,
 163   /* Intel MPX Instructions required  */
 164   CpuMPX,
 165   /* 64bit support available, used by -march= in assembler.  */
 166   CpuLM,
 167   /* RDRSEED instruction required.  */
 168   CpuRDSEED,
 169   /* Multi-presisionn add-carry instructions are required.  */
 170   CpuADX,
 171   /* Supports prefetchw and prefetch instructions.  */
 172   CpuPRFCHW,
 173   /* SMAP instructions required.  */
 174   CpuSMAP,
 175   /* SHA instructions required.  */
 176   CpuSHA,
 177   /* VREX support required  */
 178   CpuVREX,
 179   /* CLFLUSHOPT instruction required */
 180   CpuClflushOpt,
 181   /* XSAVES/XRSTORS instruction required */
 182   CpuXSAVES,
 183   /* XSAVEC instruction required */
 184   CpuXSAVEC,
 185   /* PREFETCHWT1 instruction required */
 186   CpuPREFETCHWT1,
 187   /* SE1 instruction required */
 188   CpuSE1,
 189   /* CLWB instruction required */
 190   CpuCLWB,
 191   /* Intel AVX-512 IFMA Instructions support required.  */
 192   CpuAVX512IFMA,
 193   /* Intel AVX-512 VBMI Instructions support required.  */
 194   CpuAVX512VBMI,
 195   /* Intel AVX-512 4FMAPS Instructions support required.  */
 196   CpuAVX512_4FMAPS,
 197   /* Intel AVX-512 4VNNIW Instructions support required.  */
 198   CpuAVX512_4VNNIW,
 199   /* Intel AVX-512 VPOPCNTDQ Instructions support required.  */
 200   CpuAVX512_VPOPCNTDQ,
 201   /* Intel AVX-512 VBMI2 Instructions support required.  */
 202   CpuAVX512_VBMI2,
 203   /* Intel AVX-512 VNNI Instructions support required.  */
 204   CpuAVX512_VNNI,
 205   /* Intel AVX-512 BITALG Instructions support required.  */
 206   CpuAVX512_BITALG,
 207   /* mwaitx instruction required */
 208   CpuMWAITX,
 209   /* Clzero instruction required */
 210   CpuCLZERO,
 211   /* OSPKE instruction required */
 212   CpuOSPKE,
 213   /* RDPID instruction required */
 214   CpuRDPID,
 215   /* PTWRITE instruction required */
 216   CpuPTWRITE,
 217   /* CET instructions support required */
 218   CpuIBT,
 219   CpuSHSTK,
 220   /* GFNI instructions required */
 221   CpuGFNI,
 222   /* VAES instructions required */
 223   CpuVAES,
 224   /* VPCLMULQDQ instructions required */
 225   CpuVPCLMULQDQ,
 226   /* WBNOINVD instructions required */
 227   CpuWBNOINVD,
 228   /* PCONFIG instructions required */
 229   CpuPCONFIG,
 230   /* WAITPKG instructions required */
 231   CpuWAITPKG,
 232   /* MMX register support required */
 233   CpuRegMMX,
 234   /* XMM register support required */
 235   CpuRegXMM,
 236   /* YMM register support required */
 237   CpuRegYMM,
 238   /* ZMM register support required */
 239   CpuRegZMM,
 240   /* Mask register support required */
 241   CpuRegMask,
 242   /* 64bit support required  */
 243   Cpu64,
 244   /* Not supported in the 64bit mode  */
 245   CpuNo64,
 246   /* The last bitfield in i386_cpu_flags.  */
 247   CpuMax = CpuNo64
 248 };
 249
 250 #define CpuNumOfUints \
 251   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 252 #define CpuNumOfBits \
 253   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 254
 255 /* If you get a compiler error for zero width of the unused field,
 256    comment it out.  */
 257 #define CpuUnused       (CpuMax + 1)
 258
 259 /* We can check if an instruction is available with array instead
 260    of bitfield. */
 261 typedef union i386_cpu_flags
 262 {
 263   struct
 264     {
 265       unsigned int cpui186:1;
 266       unsigned int cpui286:1;
 267       unsigned int cpui386:1;
 268       unsigned int cpui486:1;
 269       unsigned int cpui586:1;
 270       unsigned int cpui686:1;
 271       unsigned int cpuclflush:1;
 272       unsigned int cpunop:1;
 273       unsigned int cpusyscall:1;
 274       unsigned int cpu8087:1;
 275       unsigned int cpu287:1;
 276       unsigned int cpu387:1;
 277       unsigned int cpu687:1;
 278       unsigned int cpufisttp:1;
 279       unsigned int cpummx:1;
 280       unsigned int cpusse:1;
 281       unsigned int cpusse2:1;
 282       unsigned int cpua3dnow:1;
 283       unsigned int cpua3dnowa:1;
 284       unsigned int cpusse3:1;
 285       unsigned int cpupadlock:1;
 286       unsigned int cpusvme:1;
 287       unsigned int cpuvmx:1;
 288       unsigned int cpusmx:1;
 289       unsigned int cpussse3:1;
 290       unsigned int cpusse4a:1;
 291       unsigned int cpuabm:1;
 292       unsigned int cpusse4_1:1;
 293       unsigned int cpusse4_2:1;
 294       unsigned int cpuavx:1;
 295       unsigned int cpuavx2:1;
 296       unsigned int cpuavx512f:1;
 297       unsigned int cpuavx512cd:1;
 298       unsigned int cpuavx512er:1;
 299       unsigned int cpuavx512pf:1;
 300       unsigned int cpuavx512vl:1;
 301       unsigned int cpuavx512dq:1;
 302       unsigned int cpuavx512bw:1;
 303       unsigned int cpul1om:1;
 304       unsigned int cpuk1om:1;
 305       unsigned int cpuiamcu:1;
 306       unsigned int cpuxsave:1;
 307       unsigned int cpuxsaveopt:1;
 308       unsigned int cpuaes:1;
 309       unsigned int cpupclmul:1;
 310       unsigned int cpufma:1;
 311       unsigned int cpufma4:1;
 312       unsigned int cpuxop:1;
 313       unsigned int cpulwp:1;
 314       unsigned int cpubmi:1;
 315       unsigned int cputbm:1;
 316       unsigned int cpumovbe:1;
 317       unsigned int cpucx16:1;
 318       unsigned int cpuept:1;
 319       unsigned int cpurdtscp:1;
 320       unsigned int cpufsgsbase:1;
 321       unsigned int cpurdrnd:1;
 322       unsigned int cpuf16c:1;
 323       unsigned int cpubmi2:1;
 324       unsigned int cpulzcnt:1;
 325       unsigned int cpuhle:1;
 326       unsigned int cpurtm:1;
 327       unsigned int cpuinvpcid:1;
 328       unsigned int cpuvmfunc:1;
 329       unsigned int cpumpx:1;
 330       unsigned int cpulm:1;
 331       unsigned int cpurdseed:1;
 332       unsigned int cpuadx:1;
 333       unsigned int cpuprfchw:1;
 334       unsigned int cpusmap:1;
 335       unsigned int cpusha:1;
 336       unsigned int cpuvrex:1;
 337       unsigned int cpuclflushopt:1;
 338       unsigned int cpuxsaves:1;
 339       unsigned int cpuxsavec:1;
 340       unsigned int cpuprefetchwt1:1;
 341       unsigned int cpuse1:1;
 342       unsigned int cpuclwb:1;
 343       unsigned int cpuavx512ifma:1;
 344       unsigned int cpuavx512vbmi:1;
 345       unsigned int cpuavx512_4fmaps:1;
 346       unsigned int cpuavx512_4vnniw:1;
 347       unsigned int cpuavx512_vpopcntdq:1;
 348       unsigned int cpuavx512_vbmi2:1;
 349       unsigned int cpuavx512_vnni:1;
 350       unsigned int cpuavx512_bitalg:1;
 351       unsigned int cpumwaitx:1;
 352       unsigned int cpuclzero:1;
 353       unsigned int cpuospke:1;
 354       unsigned int cpurdpid:1;
 355       unsigned int cpuptwrite:1;
 356       unsigned int cpuibt:1;
 357       unsigned int cpushstk:1;
 358       unsigned int cpugfni:1;
 359       unsigned int cpuvaes:1;
 360       unsigned int cpuvpclmulqdq:1;
 361       unsigned int cpuwbnoinvd:1;
 362       unsigned int cpupconfig:1;
 363       unsigned int cpuwaitpkg:1;
 364       unsigned int cpuregmmx:1;
 365       unsigned int cpuregxmm:1;
 366       unsigned int cpuregymm:1;
 367       unsigned int cpuregzmm:1;
 368       unsigned int cpuregmask:1;
 369       unsigned int cpu64:1;
 370       unsigned int cpuno64:1;
 371 #ifdef CpuUnused
 372       unsigned int unused:(CpuNumOfBits - CpuUnused);
 373 #endif
 374     } bitfield;
 375   unsigned int array[CpuNumOfUints];
 376 } i386_cpu_flags;
 377
 378 /* Position of opcode_modifier bits.  */
 379
 380 enum
 381 {
 382   /* has direction bit. */
 383   D = 0,
 384   /* set if operands can be words or dwords encoded the canonical way */
 385   W,
 386   /* load form instruction. Must be placed before store form.  */
 387   Load,
 388   /* insn has a modrm byte. */
 389   Modrm,
 390   /* register is in low 3 bits of opcode */
 391   ShortForm,
 392   /* special case for jump insns.  */
 393   Jump,
 394   /* call and jump */
 395   JumpDword,
 396   /* loop and jecxz */
 397   JumpByte,
 398   /* special case for intersegment leaps/calls */
 399   JumpInterSegment,
 400   /* FP insn memory format bit, sized by 0x4 */
 401   FloatMF,
 402   /* src/dest swap for floats. */
 403   FloatR,
 404   /* needs size prefix if in 32-bit mode */
 405   Size16,
 406   /* needs size prefix if in 16-bit mode */
 407   Size32,
 408   /* needs size prefix if in 64-bit mode */
 409   Size64,
 410   /* check register size.  */
 411   CheckRegSize,
 412   /* instruction ignores operand size prefix and in Intel mode ignores
 413      mnemonic size suffix check.  */
 414   IgnoreSize,
 415   /* default insn size depends on mode */
 416   DefaultSize,
 417   /* b suffix on instruction illegal */
 418   No_bSuf,
 419   /* w suffix on instruction illegal */
 420   No_wSuf,
 421   /* l suffix on instruction illegal */
 422   No_lSuf,
 423   /* s suffix on instruction illegal */
 424   No_sSuf,
 425   /* q suffix on instruction illegal */
 426   No_qSuf,
 427   /* long double suffix on instruction illegal */
 428   No_ldSuf,
 429   /* instruction needs FWAIT */
 430   FWait,
 431   /* quick test for string instructions */
 432   IsString,
 433   /* quick test if branch instruction is MPX supported */
 434   BNDPrefixOk,
 435   /* quick test if NOTRACK prefix is supported */
 436   NoTrackPrefixOk,
 437   /* quick test for lockable instructions */
 438   IsLockable,
 439   /* fake an extra reg operand for clr, imul and special register
 440      processing for some instructions.  */
 441   RegKludge,
 442   /* An implicit xmm0 as the first operand */
 443   Implicit1stXmm0,
 444   /* The HLE prefix is OK:
 445      1. With a LOCK prefix.
 446      2. With or without a LOCK prefix.
 447      3. With a RELEASE (0xf3) prefix.
 448    */
 449 #define HLEPrefixNone           0
 450 #define HLEPrefixLock           1
 451 #define HLEPrefixAny            2
 452 #define HLEPrefixRelease        3
 453   HLEPrefixOk,
 454   /* An instruction on which a "rep" prefix is acceptable.  */
 455   RepPrefixOk,
 456   /* Convert to DWORD */
 457   ToDword,
 458   /* Convert to QWORD */
 459   ToQword,
 460   /* Address prefix changes operand 0 */
 461   AddrPrefixOp0,
 462   /* opcode is a prefix */
 463   IsPrefix,
 464   /* instruction has extension in 8 bit imm */
 465   ImmExt,
 466   /* instruction don't need Rex64 prefix.  */
 467   NoRex64,
 468   /* instruction require Rex64 prefix.  */
 469   Rex64,
 470   /* deprecated fp insn, gets a warning */
 471   Ugh,
 472   /* insn has VEX prefix:
 473         1: 128bit VEX prefix (or operand dependent).
 474         2: 256bit VEX prefix.
 475         3: Scalar VEX prefix.
 476    */
 477 #define VEX128          1
 478 #define VEX256          2
 479 #define VEXScalar       3
 480   Vex,
 481   /* How to encode VEX.vvvv:
 482      0: VEX.vvvv must be 1111b.
 483      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 484         the content of source registers will be preserved.
 485         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 486         where the content of first source register will be overwritten
 487         by the result.
 488         VEX.NDD2.  The second destination register operand is encoded in
 489         VEX.vvvv for instructions with 2 destination register operands.
 490         For assembler, there are no difference between VEX.NDS, VEX.DDS
 491         and VEX.NDD2.
 492      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 493      instructions with 1 destination register operand.
 494      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 495         of the operands can access a memory location.
 496    */
 497 #define VEXXDS  1
 498 #define VEXNDD  2
 499 #define VEXLWP  3
 500   VexVVVV,
 501   /* How the VEX.W bit is used:
 502      0: Set by the REX.W bit.
 503      1: VEX.W0.  Should always be 0.
 504      2: VEX.W1.  Should always be 1.
 505    */
 506 #define VEXW0   1
 507 #define VEXW1   2
 508   VexW,
 509   /* VEX opcode prefix:
 510      0: VEX 0x0F opcode prefix.
 511      1: VEX 0x0F38 opcode prefix.
 512      2: VEX 0x0F3A opcode prefix
 513      3: XOP 0x08 opcode prefix.
 514      4: XOP 0x09 opcode prefix
 515      5: XOP 0x0A opcode prefix.
 516    */
 517 #define VEX0F           0
 518 #define VEX0F38         1
 519 #define VEX0F3A         2
 520 #define XOP08           3
 521 #define XOP09           4
 522 #define XOP0A           5
 523   VexOpcode,
 524   /* number of VEX source operands:
 525      0: <= 2 source operands.
 526      1: 2 XOP source operands.
 527      2: 3 source operands.
 528    */
 529 #define XOP2SOURCES     1
 530 #define VEX3SOURCES     2
 531   VexSources,
 532   /* instruction has VEX 8 bit imm */
 533   VexImmExt,
 534   /* Instruction with vector SIB byte:
 535         1: 128bit vector register.
 536         2: 256bit vector register.
 537         3: 512bit vector register.
 538    */
 539 #define VecSIB128       1
 540 #define VecSIB256       2
 541 #define VecSIB512       3
 542   VecSIB,
 543   /* SSE to AVX support required */
 544   SSE2AVX,
 545   /* No AVX equivalent */
 546   NoAVX,
 547
 548   /* insn has EVEX prefix:
 549         1: 512bit EVEX prefix.
 550         2: 128bit EVEX prefix.
 551         3: 256bit EVEX prefix.
 552         4: Length-ignored (LIG) EVEX prefix.
 553         5: Length determined from actual operands.
 554    */
 555 #define EVEX512                1
 556 #define EVEX128                2
 557 #define EVEX256                3
 558 #define EVEXLIG                4
 559 #define EVEXDYN                5
 560   EVex,
 561
 562   /* AVX512 masking support:
 563         1: Zeroing-masking.
 564         2: Merging-masking.
 565         3: Both zeroing and merging masking.
 566    */
 567 #define ZEROING_MASKING 1
 568 #define MERGING_MASKING 2
 569 #define BOTH_MASKING    3
 570   Masking,
 571
 572   Broadcast,
 573
 574   /* Static rounding control is supported.  */
 575   StaticRounding,
 576
 577   /* Supress All Exceptions is supported.  */
 578   SAE,
 579
 580   /* Copressed Disp8*N attribute.  */
 581   Disp8MemShift,
 582
 583   /* Default mask isn't allowed.  */
 584   NoDefMask,
 585
 586   /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
 587      It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
 588    */
 589   ImplicitQuadGroup,
 590
 591   /* Support encoding optimization.  */
 592   Optimize,
 593
 594   /* AT&T mnemonic.  */
 595   ATTMnemonic,
 596   /* AT&T syntax.  */
 597   ATTSyntax,
 598   /* Intel syntax.  */
 599   IntelSyntax,
 600   /* AMD64.  */
 601   AMD64,
 602   /* Intel64.  */
 603   Intel64,
 604   /* The last bitfield in i386_opcode_modifier.  */
 605   Opcode_Modifier_Max
 606 };
 607
 608 typedef struct i386_opcode_modifier
 609 {
 610   unsigned int d:1;
 611   unsigned int w:1;
 612   unsigned int load:1;
 613   unsigned int modrm:1;
 614   unsigned int shortform:1;
 615   unsigned int jump:1;
 616   unsigned int jumpdword:1;
 617   unsigned int jumpbyte:1;
 618   unsigned int jumpintersegment:1;
 619   unsigned int floatmf:1;
 620   unsigned int floatr:1;
 621   unsigned int size16:1;
 622   unsigned int size32:1;
 623   unsigned int size64:1;
 624   unsigned int checkregsize:1;
 625   unsigned int ignoresize:1;
 626   unsigned int defaultsize:1;
 627   unsigned int no_bsuf:1;
 628   unsigned int no_wsuf:1;
 629   unsigned int no_lsuf:1;
 630   unsigned int no_ssuf:1;
 631   unsigned int no_qsuf:1;
 632   unsigned int no_ldsuf:1;
 633   unsigned int fwait:1;
 634   unsigned int isstring:1;
 635   unsigned int bndprefixok:1;
 636   unsigned int notrackprefixok:1;
 637   unsigned int islockable:1;
 638   unsigned int regkludge:1;
 639   unsigned int implicit1stxmm0:1;
 640   unsigned int hleprefixok:2;
 641   unsigned int repprefixok:1;
 642   unsigned int todword:1;
 643   unsigned int toqword:1;
 644   unsigned int addrprefixop0:1;
 645   unsigned int isprefix:1;
 646   unsigned int immext:1;
 647   unsigned int norex64:1;
 648   unsigned int rex64:1;
 649   unsigned int ugh:1;
 650   unsigned int vex:2;
 651   unsigned int vexvvvv:2;
 652   unsigned int vexw:2;
 653   unsigned int vexopcode:3;
 654   unsigned int vexsources:2;
 655   unsigned int veximmext:1;
 656   unsigned int vecsib:2;
 657   unsigned int sse2avx:1;
 658   unsigned int noavx:1;
 659   unsigned int evex:3;
 660   unsigned int masking:2;
 661   unsigned int broadcast:1;
 662   unsigned int staticrounding:1;
 663   unsigned int sae:1;
 664   unsigned int disp8memshift:3;
 665   unsigned int nodefmask:1;
 666   unsigned int implicitquadgroup:1;
 667   unsigned int optimize:1;
 668   unsigned int attmnemonic:1;
 669   unsigned int attsyntax:1;
 670   unsigned int intelsyntax:1;
 671   unsigned int amd64:1;
 672   unsigned int intel64:1;
 673 } i386_opcode_modifier;
 674
 675 /* Position of operand_type bits.  */
 676
 677 enum
 678 {
 679   /* Register (qualified by Byte, Word, etc) */
 680   Reg = 0,
 681   /* MMX register */
 682   RegMMX,
 683   /* Vector registers */
 684   RegSIMD,
 685   /* Vector Mask registers */
 686   RegMask,
 687   /* Control register */
 688   Control,
 689   /* Debug register */
 690   Debug,
 691   /* Test register */
 692   Test,
 693   /* 2 bit segment register */
 694   SReg2,
 695   /* 3 bit segment register */
 696   SReg3,
 697   /* 1 bit immediate */
 698   Imm1,
 699   /* 8 bit immediate */
 700   Imm8,
 701   /* 8 bit immediate sign extended */
 702   Imm8S,
 703   /* 16 bit immediate */
 704   Imm16,
 705   /* 32 bit immediate */
 706   Imm32,
 707   /* 32 bit immediate sign extended */
 708   Imm32S,
 709   /* 64 bit immediate */
 710   Imm64,
 711   /* 8bit/16bit/32bit displacements are used in different ways,
 712      depending on the instruction.  For jumps, they specify the
 713      size of the PC relative displacement, for instructions with
 714      memory operand, they specify the size of the offset relative
 715      to the base register, and for instructions with memory offset
 716      such as `mov 1234,%al' they specify the size of the offset
 717      relative to the segment base.  */
 718   /* 8 bit displacement */
 719   Disp8,
 720   /* 16 bit displacement */
 721   Disp16,
 722   /* 32 bit displacement */
 723   Disp32,
 724   /* 32 bit signed displacement */
 725   Disp32S,
 726   /* 64 bit displacement */
 727   Disp64,
 728   /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
 729   Acc,
 730   /* Register which can be used for base or index in memory operand.  */
 731   BaseIndex,
 732   /* Register to hold in/out port addr = dx */
 733   InOutPortReg,
 734   /* Register to hold shift count = cl */
 735   ShiftCount,
 736   /* Absolute address for jump.  */
 737   JumpAbsolute,
 738   /* String insn operand with fixed es segment */
 739   EsSeg,
 740   /* RegMem is for instructions with a modrm byte where the register
 741      destination operand should be encoded in the mod and regmem fields.
 742      Normally, it will be encoded in the reg field. We add a RegMem
 743      flag to the destination register operand to indicate that it should
 744      be encoded in the regmem field.  */
 745   RegMem,
 746   /* Memory.  */
 747   Mem,
 748   /* BYTE memory. */
 749   Byte,
 750   /* WORD memory. 2 byte */
 751   Word,
 752   /* DWORD memory. 4 byte */
 753   Dword,
 754   /* FWORD memory. 6 byte */
 755   Fword,
 756   /* QWORD memory. 8 byte */
 757   Qword,
 758   /* TBYTE memory. 10 byte */
 759   Tbyte,
 760   /* XMMWORD memory. */
 761   Xmmword,
 762   /* YMMWORD memory. */
 763   Ymmword,
 764   /* ZMMWORD memory.  */
 765   Zmmword,
 766   /* Unspecified memory size.  */
 767   Unspecified,
 768   /* Any memory size.  */
 769   Anysize,
 770
 771   /* Vector 4 bit immediate.  */
 772   Vec_Imm4,
 773
 774   /* Bound register.  */
 775   RegBND,
 776
 777   /* The last bitfield in i386_operand_type.  */
 778   OTMax
 779 };
 780
 781 #define OTNumOfUints \
 782   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 783 #define OTNumOfBits \
 784   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 785
 786 /* If you get a compiler error for zero width of the unused field,
 787    comment it out.  */
 788 #define OTUnused                (OTMax + 1)
 789
 790 typedef union i386_operand_type
 791 {
 792   struct
 793     {
 794       unsigned int reg:1;
 795       unsigned int regmmx:1;
 796       unsigned int regsimd:1;
 797       unsigned int regmask:1;
 798       unsigned int control:1;
 799       unsigned int debug:1;
 800       unsigned int test:1;
 801       unsigned int sreg2:1;
 802       unsigned int sreg3:1;
 803       unsigned int imm1:1;
 804       unsigned int imm8:1;
 805       unsigned int imm8s:1;
 806       unsigned int imm16:1;
 807       unsigned int imm32:1;
 808       unsigned int imm32s:1;
 809       unsigned int imm64:1;
 810       unsigned int disp8:1;
 811       unsigned int disp16:1;
 812       unsigned int disp32:1;
 813       unsigned int disp32s:1;
 814       unsigned int disp64:1;
 815       unsigned int acc:1;
 816       unsigned int baseindex:1;
 817       unsigned int inoutportreg:1;
 818       unsigned int shiftcount:1;
 819       unsigned int jumpabsolute:1;
 820       unsigned int esseg:1;
 821       unsigned int regmem:1;
 822       unsigned int mem:1;
 823       unsigned int byte:1;
 824       unsigned int word:1;
 825       unsigned int dword:1;
 826       unsigned int fword:1;
 827       unsigned int qword:1;
 828       unsigned int tbyte:1;
 829       unsigned int xmmword:1;
 830       unsigned int ymmword:1;
 831       unsigned int zmmword:1;
 832       unsigned int unspecified:1;
 833       unsigned int anysize:1;
 834       unsigned int vec_imm4:1;
 835       unsigned int regbnd:1;
 836 #ifdef OTUnused
 837       unsigned int unused:(OTNumOfBits - OTUnused);
 838 #endif
 839     } bitfield;
 840   unsigned int array[OTNumOfUints];
 841 } i386_operand_type;
 842
 843 typedef struct insn_template
 844 {
 845   /* instruction name sans width suffix ("mov" for movl insns) */
 846   char *name;
 847
 848   /* how many operands */
 849   unsigned int operands;
 850
 851   /* base_opcode is the fundamental opcode byte without optional
 852      prefix(es).  */
 853   unsigned int base_opcode;
 854 #define Opcode_D        0x2 /* Direction bit:
 855                                set if Reg --> Regmem;
 856                                unset if Regmem --> Reg. */
 857 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 858 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 859
 860   /* extension_opcode is the 3 bit extension for group <n> insns.
 861      This field is also used to store the 8-bit opcode suffix for the
 862      AMD 3DNow! instructions.
 863      If this template has no extension opcode (the usual case) use None
 864      Instructions */
 865   unsigned int extension_opcode;
 866 #define None 0xffff             /* If no extension_opcode is possible.  */
 867
 868   /* Opcode length.  */
 869   unsigned char opcode_length;
 870
 871   /* cpu feature flags */
 872   i386_cpu_flags cpu_flags;
 873
 874   /* the bits in opcode_modifier are used to generate the final opcode from
 875      the base_opcode.  These bits also are used to detect alternate forms of
 876      the same instruction */
 877   i386_opcode_modifier opcode_modifier;
 878
 879   /* operand_types[i] describes the type of operand i.  This is made
 880      by OR'ing together all of the possible type masks.  (e.g.
 881      'operand_types[i] = Reg|Imm' specifies that operand i can be
 882      either a register or an immediate operand.  */
 883   i386_operand_type operand_types[MAX_OPERANDS];
 884 }
 885 insn_template;
 886
 887 extern const insn_template i386_optab[];
 888
 889 /* these are for register name --> number & type hash lookup */
 890 typedef struct
 891 {
 892   char *reg_name;
 893   i386_operand_type reg_type;
 894   unsigned char reg_flags;
 895 #define RegRex      0x1  /* Extended register.  */
 896 #define RegRex64    0x2  /* Extended 8 bit register.  */
 897 #define RegVRex     0x4  /* Extended vector register.  */
 898   unsigned char reg_num;
 899 #define RegRip  ((unsigned char ) ~0)
 900 #define RegEip  (RegRip - 1)
 901 /* EIZ and RIZ are fake index registers.  */
 902 #define RegEiz  (RegEip - 1)
 903 #define RegRiz  (RegEiz - 1)
 904 /* FLAT is a fake segment register (Intel mode).  */
 905 #define RegFlat     ((unsigned char) ~0)
 906   signed char dw2_regnum[2];
 907 #define Dw2Inval (-1)
 908 }
 909 reg_entry;
 910
 911 /* Entries in i386_regtab.  */
 912 #define REGNAM_AL 1
 913 #define REGNAM_AX 25
 914 #define REGNAM_EAX 41
 915
 916 extern const reg_entry i386_regtab[];
 917 extern const unsigned int i386_regtab_size;
 918
 919 typedef struct
 920 {
 921   char *seg_name;
 922   unsigned int seg_prefix;
 923 }
 924 seg_entry;
 925
 926 extern const seg_entry cs;
 927 extern const seg_entry ds;
 928 extern const seg_entry ss;
 929 extern const seg_entry es;
 930 extern const seg_entry fs;
 931 extern const seg_entry gs;