opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2016 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #ifdef HAVE_LIMITS_H
  23 #include <limits.h>
  24 #endif
  25
  26 #ifndef CHAR_BIT
  27 #define CHAR_BIT 8
  28 #endif
  29
  30 /* Position of cpu flags bitfiled.  */
  31
  32 enum
  33 {
  34   /* i186 or better required */
  35   Cpu186 = 0,
  36   /* i286 or better required */
  37   Cpu286,
  38   /* i386 or better required */
  39   Cpu386,
  40   /* i486 or better required */
  41   Cpu486,
  42   /* i585 or better required */
  43   Cpu586,
  44   /* i686 or better required */
  45   Cpu686,
  46   /* CLFLUSH Instruction support required */
  47   CpuClflush,
  48   /* NOP Instruction support required */
  49   CpuNop,
  50   /* SYSCALL Instructions support required */
  51   CpuSYSCALL,
  52   /* Floating point support required */
  53   Cpu8087,
  54   /* i287 support required */
  55   Cpu287,
  56   /* i387 support required */
  57   Cpu387,
  58   /* i686 and floating point support required */
  59   Cpu687,
  60   /* SSE3 and floating point support required */
  61   CpuFISTTP,
  62   /* MMX support required */
  63   CpuMMX,
  64   /* SSE support required */
  65   CpuSSE,
  66   /* SSE2 support required */
  67   CpuSSE2,
  68   /* 3dnow! support required */
  69   Cpu3dnow,
  70   /* 3dnow! Extensions support required */
  71   Cpu3dnowA,
  72   /* SSE3 support required */
  73   CpuSSE3,
  74   /* VIA PadLock required */
  75   CpuPadLock,
  76   /* AMD Secure Virtual Machine Ext-s required */
  77   CpuSVME,
  78   /* VMX Instructions required */
  79   CpuVMX,
  80   /* SMX Instructions required */
  81   CpuSMX,
  82   /* SSSE3 support required */
  83   CpuSSSE3,
  84   /* SSE4a support required */
  85   CpuSSE4a,
  86   /* ABM New Instructions required */
  87   CpuABM,
  88   /* SSE4.1 support required */
  89   CpuSSE4_1,
  90   /* SSE4.2 support required */
  91   CpuSSE4_2,
  92   /* AVX support required */
  93   CpuAVX,
  94   /* AVX2 support required */
  95   CpuAVX2,
  96   /* Intel AVX-512 Foundation Instructions support required */
  97   CpuAVX512F,
  98   /* Intel AVX-512 Conflict Detection Instructions support required */
  99   CpuAVX512CD,
 100   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 101      required */
 102   CpuAVX512ER,
 103   /* Intel AVX-512 Prefetch Instructions support required */
 104   CpuAVX512PF,
 105   /* Intel AVX-512 VL Instructions support required.  */
 106   CpuAVX512VL,
 107   /* Intel AVX-512 DQ Instructions support required.  */
 108   CpuAVX512DQ,
 109   /* Intel AVX-512 BW Instructions support required.  */
 110   CpuAVX512BW,
 111   /* Intel L1OM support required */
 112   CpuL1OM,
 113   /* Intel K1OM support required */
 114   CpuK1OM,
 115   /* Intel IAMCU support required */
 116   CpuIAMCU,
 117   /* Xsave/xrstor New Instructions support required */
 118   CpuXsave,
 119   /* Xsaveopt New Instructions support required */
 120   CpuXsaveopt,
 121   /* AES support required */
 122   CpuAES,
 123   /* PCLMUL support required */
 124   CpuPCLMUL,
 125   /* FMA support required */
 126   CpuFMA,
 127   /* FMA4 support required */
 128   CpuFMA4,
 129   /* XOP support required */
 130   CpuXOP,
 131   /* LWP support required */
 132   CpuLWP,
 133   /* BMI support required */
 134   CpuBMI,
 135   /* TBM support required */
 136   CpuTBM,
 137   /* MOVBE Instruction support required */
 138   CpuMovbe,
 139   /* CMPXCHG16B instruction support required.  */
 140   CpuCX16,
 141   /* EPT Instructions required */
 142   CpuEPT,
 143   /* RDTSCP Instruction support required */
 144   CpuRdtscp,
 145   /* FSGSBASE Instructions required */
 146   CpuFSGSBase,
 147   /* RDRND Instructions required */
 148   CpuRdRnd,
 149   /* F16C Instructions required */
 150   CpuF16C,
 151   /* Intel BMI2 support required */
 152   CpuBMI2,
 153   /* LZCNT support required */
 154   CpuLZCNT,
 155   /* HLE support required */
 156   CpuHLE,
 157   /* RTM support required */
 158   CpuRTM,
 159   /* INVPCID Instructions required */
 160   CpuINVPCID,
 161   /* VMFUNC Instruction required */
 162   CpuVMFUNC,
 163   /* Intel MPX Instructions required  */
 164   CpuMPX,
 165   /* 64bit support available, used by -march= in assembler.  */
 166   CpuLM,
 167   /* RDRSEED instruction required.  */
 168   CpuRDSEED,
 169   /* Multi-presisionn add-carry instructions are required.  */
 170   CpuADX,
 171   /* Supports prefetchw and prefetch instructions.  */
 172   CpuPRFCHW,
 173   /* SMAP instructions required.  */
 174   CpuSMAP,
 175   /* SHA instructions required.  */
 176   CpuSHA,
 177   /* VREX support required  */
 178   CpuVREX,
 179   /* CLFLUSHOPT instruction required */
 180   CpuClflushOpt,
 181   /* XSAVES/XRSTORS instruction required */
 182   CpuXSAVES,
 183   /* XSAVEC instruction required */
 184   CpuXSAVEC,
 185   /* PREFETCHWT1 instruction required */
 186   CpuPREFETCHWT1,
 187   /* SE1 instruction required */
 188   CpuSE1,
 189   /* CLWB instruction required */
 190   CpuCLWB,
 191   /* PCOMMIT instruction required */
 192   CpuPCOMMIT,
 193   /* Intel AVX-512 IFMA Instructions support required.  */
 194   CpuAVX512IFMA,
 195   /* Intel AVX-512 VBMI Instructions support required.  */
 196   CpuAVX512VBMI,
 197   /* mwaitx instruction required */
 198   CpuMWAITX,
 199   /* Clzero instruction required */
 200   CpuCLZERO,
 201   /* OSPKE instruction required */
 202   CpuOSPKE,
 203   /* RDPID instruction required */
 204   CpuRDPID,
 205   /* 64bit support required  */
 206   Cpu64,
 207   /* Not supported in the 64bit mode  */
 208   CpuNo64,
 209   /* The last bitfield in i386_cpu_flags.  */
 210   CpuMax = CpuNo64
 211 };
 212
 213 #define CpuNumOfUints \
 214   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 215 #define CpuNumOfBits \
 216   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 217
 218 /* If you get a compiler error for zero width of the unused field,
 219    comment it out.  */
 220 #define CpuUnused       (CpuMax + 1)
 221
 222 /* We can check if an instruction is available with array instead
 223    of bitfield. */
 224 typedef union i386_cpu_flags
 225 {
 226   struct
 227     {
 228       unsigned int cpui186:1;
 229       unsigned int cpui286:1;
 230       unsigned int cpui386:1;
 231       unsigned int cpui486:1;
 232       unsigned int cpui586:1;
 233       unsigned int cpui686:1;
 234       unsigned int cpuclflush:1;
 235       unsigned int cpunop:1;
 236       unsigned int cpusyscall:1;
 237       unsigned int cpu8087:1;
 238       unsigned int cpu287:1;
 239       unsigned int cpu387:1;
 240       unsigned int cpu687:1;
 241       unsigned int cpufisttp:1;
 242       unsigned int cpummx:1;
 243       unsigned int cpusse:1;
 244       unsigned int cpusse2:1;
 245       unsigned int cpua3dnow:1;
 246       unsigned int cpua3dnowa:1;
 247       unsigned int cpusse3:1;
 248       unsigned int cpupadlock:1;
 249       unsigned int cpusvme:1;
 250       unsigned int cpuvmx:1;
 251       unsigned int cpusmx:1;
 252       unsigned int cpussse3:1;
 253       unsigned int cpusse4a:1;
 254       unsigned int cpuabm:1;
 255       unsigned int cpusse4_1:1;
 256       unsigned int cpusse4_2:1;
 257       unsigned int cpuavx:1;
 258       unsigned int cpuavx2:1;
 259       unsigned int cpuavx512f:1;
 260       unsigned int cpuavx512cd:1;
 261       unsigned int cpuavx512er:1;
 262       unsigned int cpuavx512pf:1;
 263       unsigned int cpuavx512vl:1;
 264       unsigned int cpuavx512dq:1;
 265       unsigned int cpuavx512bw:1;
 266       unsigned int cpul1om:1;
 267       unsigned int cpuk1om:1;
 268       unsigned int cpuiamcu:1;
 269       unsigned int cpuxsave:1;
 270       unsigned int cpuxsaveopt:1;
 271       unsigned int cpuaes:1;
 272       unsigned int cpupclmul:1;
 273       unsigned int cpufma:1;
 274       unsigned int cpufma4:1;
 275       unsigned int cpuxop:1;
 276       unsigned int cpulwp:1;
 277       unsigned int cpubmi:1;
 278       unsigned int cputbm:1;
 279       unsigned int cpumovbe:1;
 280       unsigned int cpucx16:1;
 281       unsigned int cpuept:1;
 282       unsigned int cpurdtscp:1;
 283       unsigned int cpufsgsbase:1;
 284       unsigned int cpurdrnd:1;
 285       unsigned int cpuf16c:1;
 286       unsigned int cpubmi2:1;
 287       unsigned int cpulzcnt:1;
 288       unsigned int cpuhle:1;
 289       unsigned int cpurtm:1;
 290       unsigned int cpuinvpcid:1;
 291       unsigned int cpuvmfunc:1;
 292       unsigned int cpumpx:1;
 293       unsigned int cpulm:1;
 294       unsigned int cpurdseed:1;
 295       unsigned int cpuadx:1;
 296       unsigned int cpuprfchw:1;
 297       unsigned int cpusmap:1;
 298       unsigned int cpusha:1;
 299       unsigned int cpuvrex:1;
 300       unsigned int cpuclflushopt:1;
 301       unsigned int cpuxsaves:1;
 302       unsigned int cpuxsavec:1;
 303       unsigned int cpuprefetchwt1:1;
 304       unsigned int cpuse1:1;
 305       unsigned int cpuclwb:1;
 306       unsigned int cpupcommit:1;
 307       unsigned int cpuavx512ifma:1;
 308       unsigned int cpuavx512vbmi:1;
 309       unsigned int cpumwaitx:1;
 310       unsigned int cpuclzero:1;
 311       unsigned int cpuospke:1;
 312       unsigned int cpurdpid:1;
 313       unsigned int cpu64:1;
 314       unsigned int cpuno64:1;
 315 #ifdef CpuUnused
 316       unsigned int unused:(CpuNumOfBits - CpuUnused);
 317 #endif
 318     } bitfield;
 319   unsigned int array[CpuNumOfUints];
 320 } i386_cpu_flags;
 321
 322 /* Position of opcode_modifier bits.  */
 323
 324 enum
 325 {
 326   /* has direction bit. */
 327   D = 0,
 328   /* set if operands can be words or dwords encoded the canonical way */
 329   W,
 330   /* Skip the current insn and use the next insn in i386-opc.tbl to swap
 331      operand in encoding.  */
 332   S,
 333   /* insn has a modrm byte. */
 334   Modrm,
 335   /* register is in low 3 bits of opcode */
 336   ShortForm,
 337   /* special case for jump insns.  */
 338   Jump,
 339   /* call and jump */
 340   JumpDword,
 341   /* loop and jecxz */
 342   JumpByte,
 343   /* special case for intersegment leaps/calls */
 344   JumpInterSegment,
 345   /* FP insn memory format bit, sized by 0x4 */
 346   FloatMF,
 347   /* src/dest swap for floats. */
 348   FloatR,
 349   /* has float insn direction bit. */
 350   FloatD,
 351   /* needs size prefix if in 32-bit mode */
 352   Size16,
 353   /* needs size prefix if in 16-bit mode */
 354   Size32,
 355   /* needs size prefix if in 64-bit mode */
 356   Size64,
 357   /* check register size.  */
 358   CheckRegSize,
 359   /* instruction ignores operand size prefix and in Intel mode ignores
 360      mnemonic size suffix check.  */
 361   IgnoreSize,
 362   /* default insn size depends on mode */
 363   DefaultSize,
 364   /* b suffix on instruction illegal */
 365   No_bSuf,
 366   /* w suffix on instruction illegal */
 367   No_wSuf,
 368   /* l suffix on instruction illegal */
 369   No_lSuf,
 370   /* s suffix on instruction illegal */
 371   No_sSuf,
 372   /* q suffix on instruction illegal */
 373   No_qSuf,
 374   /* long double suffix on instruction illegal */
 375   No_ldSuf,
 376   /* instruction needs FWAIT */
 377   FWait,
 378   /* quick test for string instructions */
 379   IsString,
 380   /* quick test if branch instruction is MPX supported */
 381   BNDPrefixOk,
 382   /* quick test for lockable instructions */
 383   IsLockable,
 384   /* fake an extra reg operand for clr, imul and special register
 385      processing for some instructions.  */
 386   RegKludge,
 387   /* The first operand must be xmm0 */
 388   FirstXmm0,
 389   /* An implicit xmm0 as the first operand */
 390   Implicit1stXmm0,
 391   /* The HLE prefix is OK:
 392      1. With a LOCK prefix.
 393      2. With or without a LOCK prefix.
 394      3. With a RELEASE (0xf3) prefix.
 395    */
 396 #define HLEPrefixNone           0
 397 #define HLEPrefixLock           1
 398 #define HLEPrefixAny            2
 399 #define HLEPrefixRelease        3
 400   HLEPrefixOk,
 401   /* An instruction on which a "rep" prefix is acceptable.  */
 402   RepPrefixOk,
 403   /* Convert to DWORD */
 404   ToDword,
 405   /* Convert to QWORD */
 406   ToQword,
 407   /* Address prefix changes operand 0 */
 408   AddrPrefixOp0,
 409   /* opcode is a prefix */
 410   IsPrefix,
 411   /* instruction has extension in 8 bit imm */
 412   ImmExt,
 413   /* instruction don't need Rex64 prefix.  */
 414   NoRex64,
 415   /* instruction require Rex64 prefix.  */
 416   Rex64,
 417   /* deprecated fp insn, gets a warning */
 418   Ugh,
 419   /* insn has VEX prefix:
 420         1: 128bit VEX prefix.
 421         2: 256bit VEX prefix.
 422         3: Scalar VEX prefix.
 423    */
 424 #define VEX128          1
 425 #define VEX256          2
 426 #define VEXScalar       3
 427   Vex,
 428   /* How to encode VEX.vvvv:
 429      0: VEX.vvvv must be 1111b.
 430      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 431         the content of source registers will be preserved.
 432         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 433         where the content of first source register will be overwritten
 434         by the result.
 435         VEX.NDD2.  The second destination register operand is encoded in
 436         VEX.vvvv for instructions with 2 destination register operands.
 437         For assembler, there are no difference between VEX.NDS, VEX.DDS
 438         and VEX.NDD2.
 439      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 440      instructions with 1 destination register operand.
 441      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 442         of the operands can access a memory location.
 443    */
 444 #define VEXXDS  1
 445 #define VEXNDD  2
 446 #define VEXLWP  3
 447   VexVVVV,
 448   /* How the VEX.W bit is used:
 449      0: Set by the REX.W bit.
 450      1: VEX.W0.  Should always be 0.
 451      2: VEX.W1.  Should always be 1.
 452    */
 453 #define VEXW0   1
 454 #define VEXW1   2
 455   VexW,
 456   /* VEX opcode prefix:
 457      0: VEX 0x0F opcode prefix.
 458      1: VEX 0x0F38 opcode prefix.
 459      2: VEX 0x0F3A opcode prefix
 460      3: XOP 0x08 opcode prefix.
 461      4: XOP 0x09 opcode prefix
 462      5: XOP 0x0A opcode prefix.
 463    */
 464 #define VEX0F           0
 465 #define VEX0F38         1
 466 #define VEX0F3A         2
 467 #define XOP08           3
 468 #define XOP09           4
 469 #define XOP0A           5
 470   VexOpcode,
 471   /* number of VEX source operands:
 472      0: <= 2 source operands.
 473      1: 2 XOP source operands.
 474      2: 3 source operands.
 475    */
 476 #define XOP2SOURCES     1
 477 #define VEX3SOURCES     2
 478   VexSources,
 479   /* instruction has VEX 8 bit imm */
 480   VexImmExt,
 481   /* Instruction with vector SIB byte:
 482         1: 128bit vector register.
 483         2: 256bit vector register.
 484         3: 512bit vector register.
 485    */
 486 #define VecSIB128       1
 487 #define VecSIB256       2
 488 #define VecSIB512       3
 489   VecSIB,
 490   /* SSE to AVX support required */
 491   SSE2AVX,
 492   /* No AVX equivalent */
 493   NoAVX,
 494
 495   /* insn has EVEX prefix:
 496         1: 512bit EVEX prefix.
 497         2: 128bit EVEX prefix.
 498         3: 256bit EVEX prefix.
 499         4: Length-ignored (LIG) EVEX prefix.
 500    */
 501 #define EVEX512                1
 502 #define EVEX128                2
 503 #define EVEX256                3
 504 #define EVEXLIG                4
 505   EVex,
 506
 507   /* AVX512 masking support:
 508         1: Zeroing-masking.
 509         2: Merging-masking.
 510         3: Both zeroing and merging masking.
 511    */
 512 #define ZEROING_MASKING 1
 513 #define MERGING_MASKING 2
 514 #define BOTH_MASKING    3
 515   Masking,
 516
 517   /* Input element size of vector insn:
 518         0: 32bit.
 519         1: 64bit.
 520    */
 521   VecESize,
 522
 523   /* Broadcast factor.
 524         0: No broadcast.
 525         1: 1to16 broadcast.
 526         2: 1to8 broadcast.
 527    */
 528 #define NO_BROADCAST    0
 529 #define BROADCAST_1TO16 1
 530 #define BROADCAST_1TO8  2
 531 #define BROADCAST_1TO4  3
 532 #define BROADCAST_1TO2  4
 533   Broadcast,
 534
 535   /* Static rounding control is supported.  */
 536   StaticRounding,
 537
 538   /* Supress All Exceptions is supported.  */
 539   SAE,
 540
 541   /* Copressed Disp8*N attribute.  */
 542   Disp8MemShift,
 543
 544   /* Default mask isn't allowed.  */
 545   NoDefMask,
 546
 547   /* Compatible with old (<= 2.8.1) versions of gcc  */
 548   OldGcc,
 549   /* AT&T mnemonic.  */
 550   ATTMnemonic,
 551   /* AT&T syntax.  */
 552   ATTSyntax,
 553   /* Intel syntax.  */
 554   IntelSyntax,
 555   /* AMD64.  */
 556   AMD64,
 557   /* Intel64.  */
 558   Intel64,
 559   /* The last bitfield in i386_opcode_modifier.  */
 560   Opcode_Modifier_Max
 561 };
 562
 563 typedef struct i386_opcode_modifier
 564 {
 565   unsigned int d:1;
 566   unsigned int w:1;
 567   unsigned int s:1;
 568   unsigned int modrm:1;
 569   unsigned int shortform:1;
 570   unsigned int jump:1;
 571   unsigned int jumpdword:1;
 572   unsigned int jumpbyte:1;
 573   unsigned int jumpintersegment:1;
 574   unsigned int floatmf:1;
 575   unsigned int floatr:1;
 576   unsigned int floatd:1;
 577   unsigned int size16:1;
 578   unsigned int size32:1;
 579   unsigned int size64:1;
 580   unsigned int checkregsize:1;
 581   unsigned int ignoresize:1;
 582   unsigned int defaultsize:1;
 583   unsigned int no_bsuf:1;
 584   unsigned int no_wsuf:1;
 585   unsigned int no_lsuf:1;
 586   unsigned int no_ssuf:1;
 587   unsigned int no_qsuf:1;
 588   unsigned int no_ldsuf:1;
 589   unsigned int fwait:1;
 590   unsigned int isstring:1;
 591   unsigned int bndprefixok:1;
 592   unsigned int islockable:1;
 593   unsigned int regkludge:1;
 594   unsigned int firstxmm0:1;
 595   unsigned int implicit1stxmm0:1;
 596   unsigned int hleprefixok:2;
 597   unsigned int repprefixok:1;
 598   unsigned int todword:1;
 599   unsigned int toqword:1;
 600   unsigned int addrprefixop0:1;
 601   unsigned int isprefix:1;
 602   unsigned int immext:1;
 603   unsigned int norex64:1;
 604   unsigned int rex64:1;
 605   unsigned int ugh:1;
 606   unsigned int vex:2;
 607   unsigned int vexvvvv:2;
 608   unsigned int vexw:2;
 609   unsigned int vexopcode:3;
 610   unsigned int vexsources:2;
 611   unsigned int veximmext:1;
 612   unsigned int vecsib:2;
 613   unsigned int sse2avx:1;
 614   unsigned int noavx:1;
 615   unsigned int evex:3;
 616   unsigned int masking:2;
 617   unsigned int vecesize:1;
 618   unsigned int broadcast:3;
 619   unsigned int staticrounding:1;
 620   unsigned int sae:1;
 621   unsigned int disp8memshift:3;
 622   unsigned int nodefmask:1;
 623   unsigned int oldgcc:1;
 624   unsigned int attmnemonic:1;
 625   unsigned int attsyntax:1;
 626   unsigned int intelsyntax:1;
 627   unsigned int amd64:1;
 628   unsigned int intel64:1;
 629 } i386_opcode_modifier;
 630
 631 /* Position of operand_type bits.  */
 632
 633 enum
 634 {
 635   /* 8bit register */
 636   Reg8 = 0,
 637   /* 16bit register */
 638   Reg16,
 639   /* 32bit register */
 640   Reg32,
 641   /* 64bit register */
 642   Reg64,
 643   /* Floating pointer stack register */
 644   FloatReg,
 645   /* MMX register */
 646   RegMMX,
 647   /* SSE register */
 648   RegXMM,
 649   /* AVX registers */
 650   RegYMM,
 651   /* AVX512 registers */
 652   RegZMM,
 653   /* Vector Mask registers */
 654   RegMask,
 655   /* Control register */
 656   Control,
 657   /* Debug register */
 658   Debug,
 659   /* Test register */
 660   Test,
 661   /* 2 bit segment register */
 662   SReg2,
 663   /* 3 bit segment register */
 664   SReg3,
 665   /* 1 bit immediate */
 666   Imm1,
 667   /* 8 bit immediate */
 668   Imm8,
 669   /* 8 bit immediate sign extended */
 670   Imm8S,
 671   /* 16 bit immediate */
 672   Imm16,
 673   /* 32 bit immediate */
 674   Imm32,
 675   /* 32 bit immediate sign extended */
 676   Imm32S,
 677   /* 64 bit immediate */
 678   Imm64,
 679   /* 8bit/16bit/32bit displacements are used in different ways,
 680      depending on the instruction.  For jumps, they specify the
 681      size of the PC relative displacement, for instructions with
 682      memory operand, they specify the size of the offset relative
 683      to the base register, and for instructions with memory offset
 684      such as `mov 1234,%al' they specify the size of the offset
 685      relative to the segment base.  */
 686   /* 8 bit displacement */
 687   Disp8,
 688   /* 16 bit displacement */
 689   Disp16,
 690   /* 32 bit displacement */
 691   Disp32,
 692   /* 32 bit signed displacement */
 693   Disp32S,
 694   /* 64 bit displacement */
 695   Disp64,
 696   /* Accumulator %al/%ax/%eax/%rax */
 697   Acc,
 698   /* Floating pointer top stack register %st(0) */
 699   FloatAcc,
 700   /* Register which can be used for base or index in memory operand.  */
 701   BaseIndex,
 702   /* Register to hold in/out port addr = dx */
 703   InOutPortReg,
 704   /* Register to hold shift count = cl */
 705   ShiftCount,
 706   /* Absolute address for jump.  */
 707   JumpAbsolute,
 708   /* String insn operand with fixed es segment */
 709   EsSeg,
 710   /* RegMem is for instructions with a modrm byte where the register
 711      destination operand should be encoded in the mod and regmem fields.
 712      Normally, it will be encoded in the reg field. We add a RegMem
 713      flag to the destination register operand to indicate that it should
 714      be encoded in the regmem field.  */
 715   RegMem,
 716   /* Memory.  */
 717   Mem,
 718   /* BYTE memory. */
 719   Byte,
 720   /* WORD memory. 2 byte */
 721   Word,
 722   /* DWORD memory. 4 byte */
 723   Dword,
 724   /* FWORD memory. 6 byte */
 725   Fword,
 726   /* QWORD memory. 8 byte */
 727   Qword,
 728   /* TBYTE memory. 10 byte */
 729   Tbyte,
 730   /* XMMWORD memory. */
 731   Xmmword,
 732   /* YMMWORD memory. */
 733   Ymmword,
 734   /* ZMMWORD memory.  */
 735   Zmmword,
 736   /* Unspecified memory size.  */
 737   Unspecified,
 738   /* Any memory size.  */
 739   Anysize,
 740
 741   /* Vector 4 bit immediate.  */
 742   Vec_Imm4,
 743
 744   /* Bound register.  */
 745   RegBND,
 746
 747   /* Vector 8bit displacement */
 748   Vec_Disp8,
 749
 750   /* The last bitfield in i386_operand_type.  */
 751   OTMax
 752 };
 753
 754 #define OTNumOfUints \
 755   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 756 #define OTNumOfBits \
 757   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 758
 759 /* If you get a compiler error for zero width of the unused field,
 760    comment it out.  */
 761 #define OTUnused                (OTMax + 1)
 762
 763 typedef union i386_operand_type
 764 {
 765   struct
 766     {
 767       unsigned int reg8:1;
 768       unsigned int reg16:1;
 769       unsigned int reg32:1;
 770       unsigned int reg64:1;
 771       unsigned int floatreg:1;
 772       unsigned int regmmx:1;
 773       unsigned int regxmm:1;
 774       unsigned int regymm:1;
 775       unsigned int regzmm:1;
 776       unsigned int regmask:1;
 777       unsigned int control:1;
 778       unsigned int debug:1;
 779       unsigned int test:1;
 780       unsigned int sreg2:1;
 781       unsigned int sreg3:1;
 782       unsigned int imm1:1;
 783       unsigned int imm8:1;
 784       unsigned int imm8s:1;
 785       unsigned int imm16:1;
 786       unsigned int imm32:1;
 787       unsigned int imm32s:1;
 788       unsigned int imm64:1;
 789       unsigned int disp8:1;
 790       unsigned int disp16:1;
 791       unsigned int disp32:1;
 792       unsigned int disp32s:1;
 793       unsigned int disp64:1;
 794       unsigned int acc:1;
 795       unsigned int floatacc:1;
 796       unsigned int baseindex:1;
 797       unsigned int inoutportreg:1;
 798       unsigned int shiftcount:1;
 799       unsigned int jumpabsolute:1;
 800       unsigned int esseg:1;
 801       unsigned int regmem:1;
 802       unsigned int mem:1;
 803       unsigned int byte:1;
 804       unsigned int word:1;
 805       unsigned int dword:1;
 806       unsigned int fword:1;
 807       unsigned int qword:1;
 808       unsigned int tbyte:1;
 809       unsigned int xmmword:1;
 810       unsigned int ymmword:1;
 811       unsigned int zmmword:1;
 812       unsigned int unspecified:1;
 813       unsigned int anysize:1;
 814       unsigned int vec_imm4:1;
 815       unsigned int regbnd:1;
 816       unsigned int vec_disp8:1;
 817 #ifdef OTUnused
 818       unsigned int unused:(OTNumOfBits - OTUnused);
 819 #endif
 820     } bitfield;
 821   unsigned int array[OTNumOfUints];
 822 } i386_operand_type;
 823
 824 typedef struct insn_template
 825 {
 826   /* instruction name sans width suffix ("mov" for movl insns) */
 827   char *name;
 828
 829   /* how many operands */
 830   unsigned int operands;
 831
 832   /* base_opcode is the fundamental opcode byte without optional
 833      prefix(es).  */
 834   unsigned int base_opcode;
 835 #define Opcode_D        0x2 /* Direction bit:
 836                                set if Reg --> Regmem;
 837                                unset if Regmem --> Reg. */
 838 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 839 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 840
 841   /* extension_opcode is the 3 bit extension for group <n> insns.
 842      This field is also used to store the 8-bit opcode suffix for the
 843      AMD 3DNow! instructions.
 844      If this template has no extension opcode (the usual case) use None
 845      Instructions */
 846   unsigned int extension_opcode;
 847 #define None 0xffff             /* If no extension_opcode is possible.  */
 848
 849   /* Opcode length.  */
 850   unsigned char opcode_length;
 851
 852   /* cpu feature flags */
 853   i386_cpu_flags cpu_flags;
 854
 855   /* the bits in opcode_modifier are used to generate the final opcode from
 856      the base_opcode.  These bits also are used to detect alternate forms of
 857      the same instruction */
 858   i386_opcode_modifier opcode_modifier;
 859
 860   /* operand_types[i] describes the type of operand i.  This is made
 861      by OR'ing together all of the possible type masks.  (e.g.
 862      'operand_types[i] = Reg|Imm' specifies that operand i can be
 863      either a register or an immediate operand.  */
 864   i386_operand_type operand_types[MAX_OPERANDS];
 865 }
 866 insn_template;
 867
 868 extern const insn_template i386_optab[];
 869
 870 /* these are for register name --> number & type hash lookup */
 871 typedef struct
 872 {
 873   char *reg_name;
 874   i386_operand_type reg_type;
 875   unsigned char reg_flags;
 876 #define RegRex      0x1  /* Extended register.  */
 877 #define RegRex64    0x2  /* Extended 8 bit register.  */
 878 #define RegVRex     0x4  /* Extended vector register.  */
 879   unsigned char reg_num;
 880 #define RegRip  ((unsigned char ) ~0)
 881 #define RegEip  (RegRip - 1)
 882 /* EIZ and RIZ are fake index registers.  */
 883 #define RegEiz  (RegEip - 1)
 884 #define RegRiz  (RegEiz - 1)
 885 /* FLAT is a fake segment register (Intel mode).  */
 886 #define RegFlat     ((unsigned char) ~0)
 887   signed char dw2_regnum[2];
 888 #define Dw2Inval (-1)
 889 }
 890 reg_entry;
 891
 892 /* Entries in i386_regtab.  */
 893 #define REGNAM_AL 1
 894 #define REGNAM_AX 25
 895 #define REGNAM_EAX 41
 896
 897 extern const reg_entry i386_regtab[];
 898 extern const unsigned int i386_regtab_size;
 899
 900 typedef struct
 901 {
 902   char *seg_name;
 903   unsigned int seg_prefix;
 904 }
 905 seg_entry;
 906
 907 extern const seg_entry cs;
 908 extern const seg_entry ds;
 909 extern const seg_entry ss;
 910 extern const seg_entry es;
 911 extern const seg_entry fs;
 912 extern const seg_entry gs;