opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2017 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #ifdef HAVE_LIMITS_H
  23 #include <limits.h>
  24 #endif
  25
  26 #ifndef CHAR_BIT
  27 #define CHAR_BIT 8
  28 #endif
  29
  30 /* Position of cpu flags bitfiled.  */
  31
  32 enum
  33 {
  34   /* i186 or better required */
  35   Cpu186 = 0,
  36   /* i286 or better required */
  37   Cpu286,
  38   /* i386 or better required */
  39   Cpu386,
  40   /* i486 or better required */
  41   Cpu486,
  42   /* i585 or better required */
  43   Cpu586,
  44   /* i686 or better required */
  45   Cpu686,
  46   /* CLFLUSH Instruction support required */
  47   CpuClflush,
  48   /* NOP Instruction support required */
  49   CpuNop,
  50   /* SYSCALL Instructions support required */
  51   CpuSYSCALL,
  52   /* Floating point support required */
  53   Cpu8087,
  54   /* i287 support required */
  55   Cpu287,
  56   /* i387 support required */
  57   Cpu387,
  58   /* i686 and floating point support required */
  59   Cpu687,
  60   /* SSE3 and floating point support required */
  61   CpuFISTTP,
  62   /* MMX support required */
  63   CpuMMX,
  64   /* SSE support required */
  65   CpuSSE,
  66   /* SSE2 support required */
  67   CpuSSE2,
  68   /* 3dnow! support required */
  69   Cpu3dnow,
  70   /* 3dnow! Extensions support required */
  71   Cpu3dnowA,
  72   /* SSE3 support required */
  73   CpuSSE3,
  74   /* VIA PadLock required */
  75   CpuPadLock,
  76   /* AMD Secure Virtual Machine Ext-s required */
  77   CpuSVME,
  78   /* VMX Instructions required */
  79   CpuVMX,
  80   /* SMX Instructions required */
  81   CpuSMX,
  82   /* SSSE3 support required */
  83   CpuSSSE3,
  84   /* SSE4a support required */
  85   CpuSSE4a,
  86   /* ABM New Instructions required */
  87   CpuABM,
  88   /* SSE4.1 support required */
  89   CpuSSE4_1,
  90   /* SSE4.2 support required */
  91   CpuSSE4_2,
  92   /* AVX support required */
  93   CpuAVX,
  94   /* AVX2 support required */
  95   CpuAVX2,
  96   /* Intel AVX-512 Foundation Instructions support required */
  97   CpuAVX512F,
  98   /* Intel AVX-512 Conflict Detection Instructions support required */
  99   CpuAVX512CD,
 100   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 101      required */
 102   CpuAVX512ER,
 103   /* Intel AVX-512 Prefetch Instructions support required */
 104   CpuAVX512PF,
 105   /* Intel AVX-512 VL Instructions support required.  */
 106   CpuAVX512VL,
 107   /* Intel AVX-512 DQ Instructions support required.  */
 108   CpuAVX512DQ,
 109   /* Intel AVX-512 BW Instructions support required.  */
 110   CpuAVX512BW,
 111   /* Intel L1OM support required */
 112   CpuL1OM,
 113   /* Intel K1OM support required */
 114   CpuK1OM,
 115   /* Intel IAMCU support required */
 116   CpuIAMCU,
 117   /* Xsave/xrstor New Instructions support required */
 118   CpuXsave,
 119   /* Xsaveopt New Instructions support required */
 120   CpuXsaveopt,
 121   /* AES support required */
 122   CpuAES,
 123   /* PCLMUL support required */
 124   CpuPCLMUL,
 125   /* FMA support required */
 126   CpuFMA,
 127   /* FMA4 support required */
 128   CpuFMA4,
 129   /* XOP support required */
 130   CpuXOP,
 131   /* LWP support required */
 132   CpuLWP,
 133   /* BMI support required */
 134   CpuBMI,
 135   /* TBM support required */
 136   CpuTBM,
 137   /* MOVBE Instruction support required */
 138   CpuMovbe,
 139   /* CMPXCHG16B instruction support required.  */
 140   CpuCX16,
 141   /* EPT Instructions required */
 142   CpuEPT,
 143   /* RDTSCP Instruction support required */
 144   CpuRdtscp,
 145   /* FSGSBASE Instructions required */
 146   CpuFSGSBase,
 147   /* RDRND Instructions required */
 148   CpuRdRnd,
 149   /* F16C Instructions required */
 150   CpuF16C,
 151   /* Intel BMI2 support required */
 152   CpuBMI2,
 153   /* LZCNT support required */
 154   CpuLZCNT,
 155   /* HLE support required */
 156   CpuHLE,
 157   /* RTM support required */
 158   CpuRTM,
 159   /* INVPCID Instructions required */
 160   CpuINVPCID,
 161   /* VMFUNC Instruction required */
 162   CpuVMFUNC,
 163   /* Intel MPX Instructions required  */
 164   CpuMPX,
 165   /* 64bit support available, used by -march= in assembler.  */
 166   CpuLM,
 167   /* RDRSEED instruction required.  */
 168   CpuRDSEED,
 169   /* Multi-presisionn add-carry instructions are required.  */
 170   CpuADX,
 171   /* Supports prefetchw and prefetch instructions.  */
 172   CpuPRFCHW,
 173   /* SMAP instructions required.  */
 174   CpuSMAP,
 175   /* SHA instructions required.  */
 176   CpuSHA,
 177   /* VREX support required  */
 178   CpuVREX,
 179   /* CLFLUSHOPT instruction required */
 180   CpuClflushOpt,
 181   /* XSAVES/XRSTORS instruction required */
 182   CpuXSAVES,
 183   /* XSAVEC instruction required */
 184   CpuXSAVEC,
 185   /* PREFETCHWT1 instruction required */
 186   CpuPREFETCHWT1,
 187   /* SE1 instruction required */
 188   CpuSE1,
 189   /* CLWB instruction required */
 190   CpuCLWB,
 191   /* Intel AVX-512 IFMA Instructions support required.  */
 192   CpuAVX512IFMA,
 193   /* Intel AVX-512 VBMI Instructions support required.  */
 194   CpuAVX512VBMI,
 195   /* Intel AVX-512 4FMAPS Instructions support required.  */
 196   CpuAVX512_4FMAPS,
 197   /* Intel AVX-512 4VNNIW Instructions support required.  */
 198   CpuAVX512_4VNNIW,
 199   /* Intel AVX-512 VPOPCNTDQ Instructions support required.  */
 200   CpuAVX512_VPOPCNTDQ,
 201   /* Intel AVX-512 VBMI2 Instructions support required.  */
 202   CpuAVX512_VBMI2,
 203   /* mwaitx instruction required */
 204   CpuMWAITX,
 205   /* Clzero instruction required */
 206   CpuCLZERO,
 207   /* OSPKE instruction required */
 208   CpuOSPKE,
 209   /* RDPID instruction required */
 210   CpuRDPID,
 211   /* PTWRITE instruction required */
 212   CpuPTWRITE,
 213   /* CET instruction support required */
 214   CpuCET,
 215   /* GFNI instructions required */
 216   CpuGFNI,
 217   /* VAES instructions required */
 218   CpuVAES,
 219   /* VPCLMULQDQ instructions required */
 220   CpuVPCLMULQDQ,
 221   /* MMX register support required */
 222   CpuRegMMX,
 223   /* XMM register support required */
 224   CpuRegXMM,
 225   /* YMM register support required */
 226   CpuRegYMM,
 227   /* ZMM register support required */
 228   CpuRegZMM,
 229   /* Mask register support required */
 230   CpuRegMask,
 231   /* 64bit support required  */
 232   Cpu64,
 233   /* Not supported in the 64bit mode  */
 234   CpuNo64,
 235   /* The last bitfield in i386_cpu_flags.  */
 236   CpuMax = CpuNo64
 237 };
 238
 239 #define CpuNumOfUints \
 240   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 241 #define CpuNumOfBits \
 242   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 243
 244 /* If you get a compiler error for zero width of the unused field,
 245    comment it out.  */
 246  #define CpuUnused      (CpuMax + 1)
 247
 248 /* We can check if an instruction is available with array instead
 249    of bitfield. */
 250 typedef union i386_cpu_flags
 251 {
 252   struct
 253     {
 254       unsigned int cpui186:1;
 255       unsigned int cpui286:1;
 256       unsigned int cpui386:1;
 257       unsigned int cpui486:1;
 258       unsigned int cpui586:1;
 259       unsigned int cpui686:1;
 260       unsigned int cpuclflush:1;
 261       unsigned int cpunop:1;
 262       unsigned int cpusyscall:1;
 263       unsigned int cpu8087:1;
 264       unsigned int cpu287:1;
 265       unsigned int cpu387:1;
 266       unsigned int cpu687:1;
 267       unsigned int cpufisttp:1;
 268       unsigned int cpummx:1;
 269       unsigned int cpusse:1;
 270       unsigned int cpusse2:1;
 271       unsigned int cpua3dnow:1;
 272       unsigned int cpua3dnowa:1;
 273       unsigned int cpusse3:1;
 274       unsigned int cpupadlock:1;
 275       unsigned int cpusvme:1;
 276       unsigned int cpuvmx:1;
 277       unsigned int cpusmx:1;
 278       unsigned int cpussse3:1;
 279       unsigned int cpusse4a:1;
 280       unsigned int cpuabm:1;
 281       unsigned int cpusse4_1:1;
 282       unsigned int cpusse4_2:1;
 283       unsigned int cpuavx:1;
 284       unsigned int cpuavx2:1;
 285       unsigned int cpuavx512f:1;
 286       unsigned int cpuavx512cd:1;
 287       unsigned int cpuavx512er:1;
 288       unsigned int cpuavx512pf:1;
 289       unsigned int cpuavx512vl:1;
 290       unsigned int cpuavx512dq:1;
 291       unsigned int cpuavx512bw:1;
 292       unsigned int cpul1om:1;
 293       unsigned int cpuk1om:1;
 294       unsigned int cpuiamcu:1;
 295       unsigned int cpuxsave:1;
 296       unsigned int cpuxsaveopt:1;
 297       unsigned int cpuaes:1;
 298       unsigned int cpupclmul:1;
 299       unsigned int cpufma:1;
 300       unsigned int cpufma4:1;
 301       unsigned int cpuxop:1;
 302       unsigned int cpulwp:1;
 303       unsigned int cpubmi:1;
 304       unsigned int cputbm:1;
 305       unsigned int cpumovbe:1;
 306       unsigned int cpucx16:1;
 307       unsigned int cpuept:1;
 308       unsigned int cpurdtscp:1;
 309       unsigned int cpufsgsbase:1;
 310       unsigned int cpurdrnd:1;
 311       unsigned int cpuf16c:1;
 312       unsigned int cpubmi2:1;
 313       unsigned int cpulzcnt:1;
 314       unsigned int cpuhle:1;
 315       unsigned int cpurtm:1;
 316       unsigned int cpuinvpcid:1;
 317       unsigned int cpuvmfunc:1;
 318       unsigned int cpumpx:1;
 319       unsigned int cpulm:1;
 320       unsigned int cpurdseed:1;
 321       unsigned int cpuadx:1;
 322       unsigned int cpuprfchw:1;
 323       unsigned int cpusmap:1;
 324       unsigned int cpusha:1;
 325       unsigned int cpuvrex:1;
 326       unsigned int cpuclflushopt:1;
 327       unsigned int cpuxsaves:1;
 328       unsigned int cpuxsavec:1;
 329       unsigned int cpuprefetchwt1:1;
 330       unsigned int cpuse1:1;
 331       unsigned int cpuclwb:1;
 332       unsigned int cpuavx512ifma:1;
 333       unsigned int cpuavx512vbmi:1;
 334       unsigned int cpuavx512_4fmaps:1;
 335       unsigned int cpuavx512_4vnniw:1;
 336       unsigned int cpuavx512_vpopcntdq:1;
 337       unsigned int cpuavx512_vbmi2:1;
 338       unsigned int cpumwaitx:1;
 339       unsigned int cpuclzero:1;
 340       unsigned int cpuospke:1;
 341       unsigned int cpurdpid:1;
 342       unsigned int cpuptwrite:1;
 343       unsigned int cpucet:1;
 344       unsigned int cpugfni:1;
 345       unsigned int cpuvaes:1;
 346       unsigned int cpuvpclmulqdq:1;
 347       unsigned int cpuregmmx:1;
 348       unsigned int cpuregxmm:1;
 349       unsigned int cpuregymm:1;
 350       unsigned int cpuregzmm:1;
 351       unsigned int cpuregmask:1;
 352       unsigned int cpu64:1;
 353       unsigned int cpuno64:1;
 354 #ifdef CpuUnused
 355       unsigned int unused:(CpuNumOfBits - CpuUnused);
 356 #endif
 357     } bitfield;
 358   unsigned int array[CpuNumOfUints];
 359 } i386_cpu_flags;
 360
 361 /* Position of opcode_modifier bits.  */
 362
 363 enum
 364 {
 365   /* has direction bit. */
 366   D = 0,
 367   /* set if operands can be words or dwords encoded the canonical way */
 368   W,
 369   /* load form instruction. Must be placed before store form.  */
 370   Load,
 371   /* insn has a modrm byte. */
 372   Modrm,
 373   /* register is in low 3 bits of opcode */
 374   ShortForm,
 375   /* special case for jump insns.  */
 376   Jump,
 377   /* call and jump */
 378   JumpDword,
 379   /* loop and jecxz */
 380   JumpByte,
 381   /* special case for intersegment leaps/calls */
 382   JumpInterSegment,
 383   /* FP insn memory format bit, sized by 0x4 */
 384   FloatMF,
 385   /* src/dest swap for floats. */
 386   FloatR,
 387   /* has float insn direction bit. */
 388   FloatD,
 389   /* needs size prefix if in 32-bit mode */
 390   Size16,
 391   /* needs size prefix if in 16-bit mode */
 392   Size32,
 393   /* needs size prefix if in 64-bit mode */
 394   Size64,
 395   /* check register size.  */
 396   CheckRegSize,
 397   /* instruction ignores operand size prefix and in Intel mode ignores
 398      mnemonic size suffix check.  */
 399   IgnoreSize,
 400   /* default insn size depends on mode */
 401   DefaultSize,
 402   /* b suffix on instruction illegal */
 403   No_bSuf,
 404   /* w suffix on instruction illegal */
 405   No_wSuf,
 406   /* l suffix on instruction illegal */
 407   No_lSuf,
 408   /* s suffix on instruction illegal */
 409   No_sSuf,
 410   /* q suffix on instruction illegal */
 411   No_qSuf,
 412   /* long double suffix on instruction illegal */
 413   No_ldSuf,
 414   /* instruction needs FWAIT */
 415   FWait,
 416   /* quick test for string instructions */
 417   IsString,
 418   /* quick test if branch instruction is MPX supported */
 419   BNDPrefixOk,
 420   /* quick test if NOTRACK prefix is supported */
 421   NoTrackPrefixOk,
 422   /* quick test for lockable instructions */
 423   IsLockable,
 424   /* fake an extra reg operand for clr, imul and special register
 425      processing for some instructions.  */
 426   RegKludge,
 427   /* The first operand must be xmm0 */
 428   FirstXmm0,
 429   /* An implicit xmm0 as the first operand */
 430   Implicit1stXmm0,
 431   /* The HLE prefix is OK:
 432      1. With a LOCK prefix.
 433      2. With or without a LOCK prefix.
 434      3. With a RELEASE (0xf3) prefix.
 435    */
 436 #define HLEPrefixNone           0
 437 #define HLEPrefixLock           1
 438 #define HLEPrefixAny            2
 439 #define HLEPrefixRelease        3
 440   HLEPrefixOk,
 441   /* An instruction on which a "rep" prefix is acceptable.  */
 442   RepPrefixOk,
 443   /* Convert to DWORD */
 444   ToDword,
 445   /* Convert to QWORD */
 446   ToQword,
 447   /* Address prefix changes operand 0 */
 448   AddrPrefixOp0,
 449   /* opcode is a prefix */
 450   IsPrefix,
 451   /* instruction has extension in 8 bit imm */
 452   ImmExt,
 453   /* instruction don't need Rex64 prefix.  */
 454   NoRex64,
 455   /* instruction require Rex64 prefix.  */
 456   Rex64,
 457   /* deprecated fp insn, gets a warning */
 458   Ugh,
 459   /* insn has VEX prefix:
 460         1: 128bit VEX prefix.
 461         2: 256bit VEX prefix.
 462         3: Scalar VEX prefix.
 463    */
 464 #define VEX128          1
 465 #define VEX256          2
 466 #define VEXScalar       3
 467   Vex,
 468   /* How to encode VEX.vvvv:
 469      0: VEX.vvvv must be 1111b.
 470      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 471         the content of source registers will be preserved.
 472         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 473         where the content of first source register will be overwritten
 474         by the result.
 475         VEX.NDD2.  The second destination register operand is encoded in
 476         VEX.vvvv for instructions with 2 destination register operands.
 477         For assembler, there are no difference between VEX.NDS, VEX.DDS
 478         and VEX.NDD2.
 479      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 480      instructions with 1 destination register operand.
 481      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 482         of the operands can access a memory location.
 483    */
 484 #define VEXXDS  1
 485 #define VEXNDD  2
 486 #define VEXLWP  3
 487   VexVVVV,
 488   /* How the VEX.W bit is used:
 489      0: Set by the REX.W bit.
 490      1: VEX.W0.  Should always be 0.
 491      2: VEX.W1.  Should always be 1.
 492    */
 493 #define VEXW0   1
 494 #define VEXW1   2
 495   VexW,
 496   /* VEX opcode prefix:
 497      0: VEX 0x0F opcode prefix.
 498      1: VEX 0x0F38 opcode prefix.
 499      2: VEX 0x0F3A opcode prefix
 500      3: XOP 0x08 opcode prefix.
 501      4: XOP 0x09 opcode prefix
 502      5: XOP 0x0A opcode prefix.
 503    */
 504 #define VEX0F           0
 505 #define VEX0F38         1
 506 #define VEX0F3A         2
 507 #define XOP08           3
 508 #define XOP09           4
 509 #define XOP0A           5
 510   VexOpcode,
 511   /* number of VEX source operands:
 512      0: <= 2 source operands.
 513      1: 2 XOP source operands.
 514      2: 3 source operands.
 515    */
 516 #define XOP2SOURCES     1
 517 #define VEX3SOURCES     2
 518   VexSources,
 519   /* instruction has VEX 8 bit imm */
 520   VexImmExt,
 521   /* Instruction with vector SIB byte:
 522         1: 128bit vector register.
 523         2: 256bit vector register.
 524         3: 512bit vector register.
 525    */
 526 #define VecSIB128       1
 527 #define VecSIB256       2
 528 #define VecSIB512       3
 529   VecSIB,
 530   /* SSE to AVX support required */
 531   SSE2AVX,
 532   /* No AVX equivalent */
 533   NoAVX,
 534
 535   /* insn has EVEX prefix:
 536         1: 512bit EVEX prefix.
 537         2: 128bit EVEX prefix.
 538         3: 256bit EVEX prefix.
 539         4: Length-ignored (LIG) EVEX prefix.
 540    */
 541 #define EVEX512                1
 542 #define EVEX128                2
 543 #define EVEX256                3
 544 #define EVEXLIG                4
 545   EVex,
 546
 547   /* AVX512 masking support:
 548         1: Zeroing-masking.
 549         2: Merging-masking.
 550         3: Both zeroing and merging masking.
 551    */
 552 #define ZEROING_MASKING 1
 553 #define MERGING_MASKING 2
 554 #define BOTH_MASKING    3
 555   Masking,
 556
 557   /* Input element size of vector insn:
 558         0: 32bit.
 559         1: 64bit.
 560    */
 561   VecESize,
 562
 563   /* Broadcast factor.
 564         0: No broadcast.
 565         1: 1to16 broadcast.
 566         2: 1to8 broadcast.
 567    */
 568 #define NO_BROADCAST    0
 569 #define BROADCAST_1TO16 1
 570 #define BROADCAST_1TO8  2
 571 #define BROADCAST_1TO4  3
 572 #define BROADCAST_1TO2  4
 573   Broadcast,
 574
 575   /* Static rounding control is supported.  */
 576   StaticRounding,
 577
 578   /* Supress All Exceptions is supported.  */
 579   SAE,
 580
 581   /* Copressed Disp8*N attribute.  */
 582   Disp8MemShift,
 583
 584   /* Default mask isn't allowed.  */
 585   NoDefMask,
 586
 587   /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
 588      It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
 589    */
 590   ImplicitQuadGroup,
 591
 592   /* Compatible with old (<= 2.8.1) versions of gcc  */
 593   OldGcc,
 594   /* AT&T mnemonic.  */
 595   ATTMnemonic,
 596   /* AT&T syntax.  */
 597   ATTSyntax,
 598   /* Intel syntax.  */
 599   IntelSyntax,
 600   /* AMD64.  */
 601   AMD64,
 602   /* Intel64.  */
 603   Intel64,
 604   /* The last bitfield in i386_opcode_modifier.  */
 605   Opcode_Modifier_Max
 606 };
 607
 608 typedef struct i386_opcode_modifier
 609 {
 610   unsigned int d:1;
 611   unsigned int w:1;
 612   unsigned int load:1;
 613   unsigned int modrm:1;
 614   unsigned int shortform:1;
 615   unsigned int jump:1;
 616   unsigned int jumpdword:1;
 617   unsigned int jumpbyte:1;
 618   unsigned int jumpintersegment:1;
 619   unsigned int floatmf:1;
 620   unsigned int floatr:1;
 621   unsigned int floatd:1;
 622   unsigned int size16:1;
 623   unsigned int size32:1;
 624   unsigned int size64:1;
 625   unsigned int checkregsize:1;
 626   unsigned int ignoresize:1;
 627   unsigned int defaultsize:1;
 628   unsigned int no_bsuf:1;
 629   unsigned int no_wsuf:1;
 630   unsigned int no_lsuf:1;
 631   unsigned int no_ssuf:1;
 632   unsigned int no_qsuf:1;
 633   unsigned int no_ldsuf:1;
 634   unsigned int fwait:1;
 635   unsigned int isstring:1;
 636   unsigned int bndprefixok:1;
 637   unsigned int notrackprefixok:1;
 638   unsigned int islockable:1;
 639   unsigned int regkludge:1;
 640   unsigned int firstxmm0:1;
 641   unsigned int implicit1stxmm0:1;
 642   unsigned int hleprefixok:2;
 643   unsigned int repprefixok:1;
 644   unsigned int todword:1;
 645   unsigned int toqword:1;
 646   unsigned int addrprefixop0:1;
 647   unsigned int isprefix:1;
 648   unsigned int immext:1;
 649   unsigned int norex64:1;
 650   unsigned int rex64:1;
 651   unsigned int ugh:1;
 652   unsigned int vex:2;
 653   unsigned int vexvvvv:2;
 654   unsigned int vexw:2;
 655   unsigned int vexopcode:3;
 656   unsigned int vexsources:2;
 657   unsigned int veximmext:1;
 658   unsigned int vecsib:2;
 659   unsigned int sse2avx:1;
 660   unsigned int noavx:1;
 661   unsigned int evex:3;
 662   unsigned int masking:2;
 663   unsigned int vecesize:1;
 664   unsigned int broadcast:3;
 665   unsigned int staticrounding:1;
 666   unsigned int sae:1;
 667   unsigned int disp8memshift:3;
 668   unsigned int nodefmask:1;
 669   unsigned int implicitquadgroup:1;
 670   unsigned int oldgcc:1;
 671   unsigned int attmnemonic:1;
 672   unsigned int attsyntax:1;
 673   unsigned int intelsyntax:1;
 674   unsigned int amd64:1;
 675   unsigned int intel64:1;
 676 } i386_opcode_modifier;
 677
 678 /* Position of operand_type bits.  */
 679
 680 enum
 681 {
 682   /* 8bit register */
 683   Reg8 = 0,
 684   /* 16bit register */
 685   Reg16,
 686   /* 32bit register */
 687   Reg32,
 688   /* 64bit register */
 689   Reg64,
 690   /* Floating pointer stack register */
 691   FloatReg,
 692   /* MMX register */
 693   RegMMX,
 694   /* SSE register */
 695   RegXMM,
 696   /* AVX registers */
 697   RegYMM,
 698   /* AVX512 registers */
 699   RegZMM,
 700   /* Vector Mask registers */
 701   RegMask,
 702   /* Control register */
 703   Control,
 704   /* Debug register */
 705   Debug,
 706   /* Test register */
 707   Test,
 708   /* 2 bit segment register */
 709   SReg2,
 710   /* 3 bit segment register */
 711   SReg3,
 712   /* 1 bit immediate */
 713   Imm1,
 714   /* 8 bit immediate */
 715   Imm8,
 716   /* 8 bit immediate sign extended */
 717   Imm8S,
 718   /* 16 bit immediate */
 719   Imm16,
 720   /* 32 bit immediate */
 721   Imm32,
 722   /* 32 bit immediate sign extended */
 723   Imm32S,
 724   /* 64 bit immediate */
 725   Imm64,
 726   /* 8bit/16bit/32bit displacements are used in different ways,
 727      depending on the instruction.  For jumps, they specify the
 728      size of the PC relative displacement, for instructions with
 729      memory operand, they specify the size of the offset relative
 730      to the base register, and for instructions with memory offset
 731      such as `mov 1234,%al' they specify the size of the offset
 732      relative to the segment base.  */
 733   /* 8 bit displacement */
 734   Disp8,
 735   /* 16 bit displacement */
 736   Disp16,
 737   /* 32 bit displacement */
 738   Disp32,
 739   /* 32 bit signed displacement */
 740   Disp32S,
 741   /* 64 bit displacement */
 742   Disp64,
 743   /* Accumulator %al/%ax/%eax/%rax */
 744   Acc,
 745   /* Floating pointer top stack register %st(0) */
 746   FloatAcc,
 747   /* Register which can be used for base or index in memory operand.  */
 748   BaseIndex,
 749   /* Register to hold in/out port addr = dx */
 750   InOutPortReg,
 751   /* Register to hold shift count = cl */
 752   ShiftCount,
 753   /* Absolute address for jump.  */
 754   JumpAbsolute,
 755   /* String insn operand with fixed es segment */
 756   EsSeg,
 757   /* RegMem is for instructions with a modrm byte where the register
 758      destination operand should be encoded in the mod and regmem fields.
 759      Normally, it will be encoded in the reg field. We add a RegMem
 760      flag to the destination register operand to indicate that it should
 761      be encoded in the regmem field.  */
 762   RegMem,
 763   /* Memory.  */
 764   Mem,
 765   /* BYTE memory. */
 766   Byte,
 767   /* WORD memory. 2 byte */
 768   Word,
 769   /* DWORD memory. 4 byte */
 770   Dword,
 771   /* FWORD memory. 6 byte */
 772   Fword,
 773   /* QWORD memory. 8 byte */
 774   Qword,
 775   /* TBYTE memory. 10 byte */
 776   Tbyte,
 777   /* XMMWORD memory. */
 778   Xmmword,
 779   /* YMMWORD memory. */
 780   Ymmword,
 781   /* ZMMWORD memory.  */
 782   Zmmword,
 783   /* Unspecified memory size.  */
 784   Unspecified,
 785   /* Any memory size.  */
 786   Anysize,
 787
 788   /* Vector 4 bit immediate.  */
 789   Vec_Imm4,
 790
 791   /* Bound register.  */
 792   RegBND,
 793
 794   /* Vector 8bit displacement */
 795   Vec_Disp8,
 796
 797   /* The last bitfield in i386_operand_type.  */
 798   OTMax
 799 };
 800
 801 #define OTNumOfUints \
 802   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 803 #define OTNumOfBits \
 804   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 805
 806 /* If you get a compiler error for zero width of the unused field,
 807    comment it out.  */
 808 #define OTUnused                (OTMax + 1)
 809
 810 typedef union i386_operand_type
 811 {
 812   struct
 813     {
 814       unsigned int reg8:1;
 815       unsigned int reg16:1;
 816       unsigned int reg32:1;
 817       unsigned int reg64:1;
 818       unsigned int floatreg:1;
 819       unsigned int regmmx:1;
 820       unsigned int regxmm:1;
 821       unsigned int regymm:1;
 822       unsigned int regzmm:1;
 823       unsigned int regmask:1;
 824       unsigned int control:1;
 825       unsigned int debug:1;
 826       unsigned int test:1;
 827       unsigned int sreg2:1;
 828       unsigned int sreg3:1;
 829       unsigned int imm1:1;
 830       unsigned int imm8:1;
 831       unsigned int imm8s:1;
 832       unsigned int imm16:1;
 833       unsigned int imm32:1;
 834       unsigned int imm32s:1;
 835       unsigned int imm64:1;
 836       unsigned int disp8:1;
 837       unsigned int disp16:1;
 838       unsigned int disp32:1;
 839       unsigned int disp32s:1;
 840       unsigned int disp64:1;
 841       unsigned int acc:1;
 842       unsigned int floatacc:1;
 843       unsigned int baseindex:1;
 844       unsigned int inoutportreg:1;
 845       unsigned int shiftcount:1;
 846       unsigned int jumpabsolute:1;
 847       unsigned int esseg:1;
 848       unsigned int regmem:1;
 849       unsigned int mem:1;
 850       unsigned int byte:1;
 851       unsigned int word:1;
 852       unsigned int dword:1;
 853       unsigned int fword:1;
 854       unsigned int qword:1;
 855       unsigned int tbyte:1;
 856       unsigned int xmmword:1;
 857       unsigned int ymmword:1;
 858       unsigned int zmmword:1;
 859       unsigned int unspecified:1;
 860       unsigned int anysize:1;
 861       unsigned int vec_imm4:1;
 862       unsigned int regbnd:1;
 863       unsigned int vec_disp8:1;
 864 #ifdef OTUnused
 865       unsigned int unused:(OTNumOfBits - OTUnused);
 866 #endif
 867     } bitfield;
 868   unsigned int array[OTNumOfUints];
 869 } i386_operand_type;
 870
 871 typedef struct insn_template
 872 {
 873   /* instruction name sans width suffix ("mov" for movl insns) */
 874   char *name;
 875
 876   /* how many operands */
 877   unsigned int operands;
 878
 879   /* base_opcode is the fundamental opcode byte without optional
 880      prefix(es).  */
 881   unsigned int base_opcode;
 882 #define Opcode_D        0x2 /* Direction bit:
 883                                set if Reg --> Regmem;
 884                                unset if Regmem --> Reg. */
 885 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 886 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 887
 888   /* extension_opcode is the 3 bit extension for group <n> insns.
 889      This field is also used to store the 8-bit opcode suffix for the
 890      AMD 3DNow! instructions.
 891      If this template has no extension opcode (the usual case) use None
 892      Instructions */
 893   unsigned int extension_opcode;
 894 #define None 0xffff             /* If no extension_opcode is possible.  */
 895
 896   /* Opcode length.  */
 897   unsigned char opcode_length;
 898
 899   /* cpu feature flags */
 900   i386_cpu_flags cpu_flags;
 901
 902   /* the bits in opcode_modifier are used to generate the final opcode from
 903      the base_opcode.  These bits also are used to detect alternate forms of
 904      the same instruction */
 905   i386_opcode_modifier opcode_modifier;
 906
 907   /* operand_types[i] describes the type of operand i.  This is made
 908      by OR'ing together all of the possible type masks.  (e.g.
 909      'operand_types[i] = Reg|Imm' specifies that operand i can be
 910      either a register or an immediate operand.  */
 911   i386_operand_type operand_types[MAX_OPERANDS];
 912 }
 913 insn_template;
 914
 915 extern const insn_template i386_optab[];
 916
 917 /* these are for register name --> number & type hash lookup */
 918 typedef struct
 919 {
 920   char *reg_name;
 921   i386_operand_type reg_type;
 922   unsigned char reg_flags;
 923 #define RegRex      0x1  /* Extended register.  */
 924 #define RegRex64    0x2  /* Extended 8 bit register.  */
 925 #define RegVRex     0x4  /* Extended vector register.  */
 926   unsigned char reg_num;
 927 #define RegRip  ((unsigned char ) ~0)
 928 #define RegEip  (RegRip - 1)
 929 /* EIZ and RIZ are fake index registers.  */
 930 #define RegEiz  (RegEip - 1)
 931 #define RegRiz  (RegEiz - 1)
 932 /* FLAT is a fake segment register (Intel mode).  */
 933 #define RegFlat     ((unsigned char) ~0)
 934   signed char dw2_regnum[2];
 935 #define Dw2Inval (-1)
 936 }
 937 reg_entry;
 938
 939 /* Entries in i386_regtab.  */
 940 #define REGNAM_AL 1
 941 #define REGNAM_AX 25
 942 #define REGNAM_EAX 41
 943
 944 extern const reg_entry i386_regtab[];
 945 extern const unsigned int i386_regtab_size;
 946
 947 typedef struct
 948 {
 949   char *seg_name;
 950   unsigned int seg_prefix;
 951 }
 952 seg_entry;
 953
 954 extern const seg_entry cs;
 955 extern const seg_entry ds;
 956 extern const seg_entry ss;
 957 extern const seg_entry es;
 958 extern const seg_entry fs;
 959 extern const seg_entry gs;