opcodes/i386-opc.tbl

   1 // i386 opcode table.
   2 // Copyright (C) 2007-2021 Free Software Foundation, Inc.
   3 //
   4 // This file is part of the GNU opcodes library.
   5 //
   6 // This library is free software; you can redistribute it and/or modify
   7 // it under the terms of the GNU General Public License as published by
   8 // the Free Software Foundation; either version 3, or (at your option)
   9 // any later version.
  10 //
  11 // It is distributed in the hope that it will be useful, but WITHOUT
  12 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13 // or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14 // License for more details.
  15 //
  16 // You should have received a copy of the GNU General Public License
  17 // along with GAS; see the file COPYING.  If not, write to the Free
  18 // Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19 // 02110-1301, USA.
  20
  21 #define OPCODE_I386_H
  22 #include "i386-opc.h"
  23 #undef None
  24
  25 #define Amd64           ISA64=AMD64
  26 #define Intel64         ISA64=INTEL64
  27 #define Intel64Only     ISA64=INTEL64ONLY
  28
  29 #define Reg8  Class=Reg|Byte
  30 #define Reg16 Class=Reg|Word
  31 #define Reg32 Class=Reg|Dword
  32 #define Reg64 Class=Reg|Qword
  33
  34 #define Acc  Instance=Accum
  35 #define RegC Instance=RegC
  36 #define RegD Instance=RegD
  37 #define RegB Instance=RegB
  38
  39 #define ShiftCount   RegC|Byte
  40 #define InOutPortReg RegD|Word
  41
  42 #define FloatAcc Acc|Tbyte
  43 #define FloatReg Class=Reg|Tbyte
  44
  45 #define SReg  Class=SReg
  46
  47 #define Control Class=RegCR
  48 #define Debug   Class=RegDR
  49 #define Test    Class=RegTR
  50
  51 #define RegMMX Class=RegMMX
  52 #define RegXMM Class=RegSIMD|Xmmword
  53 #define RegYMM Class=RegSIMD|Ymmword
  54 #define RegZMM Class=RegSIMD|Zmmword
  55 #define RegTMM Class=RegSIMD|Tmmword
  56
  57 #define RegMask Class=RegMask
  58
  59 #define RegBND Class=RegBND
  60
  61 #define Mmword Qword
  62 #define Oword  Xmmword
  63
  64 #define JumpByte         Jump=JUMP_BYTE
  65 #define JumpDword        Jump=JUMP_DWORD
  66 #define JumpAbsolute     Jump=JUMP_ABSOLUTE
  67 #define JumpInterSegment Jump=JUMP_INTERSEGMENT
  68
  69 #define Size16 Size=SIZE16
  70 #define Size32 Size=SIZE32
  71 #define Size64 Size=SIZE64
  72
  73 #define IgnoreSize      MnemonicSize=IGNORESIZE
  74 #define DefaultSize     MnemonicSize=DEFAULTSIZE
  75
  76 // RegMem implies a ModR/M byte
  77 #define RegMem Modrm|RegMem
  78
  79 #define IsStringEsOp0 IsString=IS_STRING_ES_OP0
  80 #define IsStringEsOp1 IsString=IS_STRING_ES_OP1
  81
  82 #define RepPrefixOk      PrefixOk=PrefixRep
  83 #define LockPrefixOk     PrefixOk=PrefixLock
  84 #define HLEPrefixAny     PrefixOk=PrefixHLEAny
  85 #define HLEPrefixLock    PrefixOk=PrefixHLELock
  86 #define HLEPrefixRelease PrefixOk=PrefixHLERelease
  87 #define NoTrackPrefixOk  PrefixOk=PrefixNoTrack
  88
  89 #define AddrPrefixOpReg AddrPrefixOpReg|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf
  90
  91 #define Prefix_0X66 OpcodePrefix=PREFIX_0X66
  92 #define Prefix_0XF2 OpcodePrefix=PREFIX_0XF2
  93 #define Prefix_0XF3 OpcodePrefix=PREFIX_0XF3
  94
  95 #define VexW0 VexW=VEXW0
  96 #define VexW1 VexW=VEXW1
  97 #define VexWIG VexW=VEXWIG
  98
  99 #define Vex128 Vex=VEX128
 100 #define Vex256 Vex=VEX256
 101 #define VexLIG Vex=VEXScalar
 102
 103 #define VecSIB128 SIB=VECSIB128
 104 #define VecSIB256 SIB=VECSIB256
 105 #define VecSIB512 SIB=VECSIB512
 106 #define Sibmem SIB=SIBMEM|Modrm
 107
 108 #define EVex128 EVex=EVEX128
 109 #define EVex256 EVex=EVEX256
 110 #define EVex512 EVex=EVEX512
 111 #define EVexLIG EVex=EVEXLIG
 112 #define EVexDYN EVex=EVEXDYN
 113
 114 // The EVEX purpose of StaticRounding appears only together with SAE. Re-use
 115 // the bit to mark commutative VEX encodings where swapping the source
 116 // operands may allow to switch from 3-byte to 2-byte VEX encoding.
 117 #define C StaticRounding
 118
 119 #define CpuFP Cpu387|Cpu287|Cpu8087
 120
 121 ### MARKER ###
 122
 123 // Move instructions.
 124 mov, 0xa0, None, 1, 0, D|W|No_sSuf|No_qSuf|No_ldSuf, { Disp16|Disp32|Disp64|Unspecified|Byte|Word|Dword|Qword, Acc|Byte|Word|Dword|Qword }
 125 mov, 0x88, None, 1, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|HLEPrefixRelease, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 126 // In the 64bit mode the short form mov immediate is redefined to have
 127 // 64bit value.
 128 mov, 0xb0, None, 1, 0, W|No_sSuf|No_qSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32 }
 129 mov, 0xc6, 0x0, 1, 0, W|Modrm|No_sSuf|No_ldSuf|HLEPrefixRelease|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 130 mov, 0xb8, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|Optimize, { Imm64, Reg64 }
 131 // The segment register moves accept WordReg so that a segment register
 132 // can be copied to a 32 bit register, and vice versa, without using a
 133 // size prefix.  When moving to a 32 bit register, the upper 16 bits
 134 // are set to an implementation defined value (on the Pentium Pro, the
 135 // implementation defined value is zero).
 136 mov, 0x8c, None, 1, 0, RegMem|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { SReg, Reg16|Reg32|Reg64 }
 137 mov, 0x8c, None, 1, 0, D|Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg, Word|Unspecified|BaseIndex }
 138 mov, 0x8e, None, 1, 0, Modrm|IgnoreSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg16|Reg32|Reg64, SReg }
 139 // Move to/from control debug registers.  In the 16 or 32bit modes
 140 // they are 32bit.  In the 64bit mode they are 64bit.
 141 mov, 0xf20, None, 2, Cpu386|CpuNo64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Control, Reg32 }
 142 mov, 0xf20, None, 2, Cpu64, D|RegMem|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Control, Reg64 }
 143 mov, 0xf21, None, 2, Cpu386|CpuNo64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Debug, Reg32 }
 144 mov, 0xf21, None, 2, Cpu64, D|RegMem|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Debug, Reg64 }
 145 mov, 0xf24, None, 2, Cpu386|CpuNo64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Test, Reg32 }
 146 movabs, 0xa0, None, 1, Cpu64, D|W|No_sSuf|No_ldSuf, { Disp64|Unspecified|Byte|Word|Dword|Qword, Acc|Byte|Word|Dword|Qword }
 147 movabs, 0xb8, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Imm64, Reg64 }
 148
 149 // Move after swapping the bytes
 150 movbe, 0x0f38f0, None, 3, CpuMovbe, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 151 movbe, 0x0f38f1, None, 3, CpuMovbe, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64, Word|Dword|Qword|Unspecified|BaseIndex }
 152
 153 // Move with sign extend.
 154 // "movsbl" & "movsbw" must not be unified into "movsb" to avoid
 155 // conflict with the "movs" string move instruction.
 156 movsbl, 0xfbe, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex, Reg32 }
 157 movsbw, 0xfbe, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex, Reg16 }
 158 movswl, 0xfbf, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex, Reg32 }
 159 movsbq, 0xfbe, None, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg8|Byte|Unspecified|BaseIndex, Reg64 }
 160 movswq, 0xfbf, None, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg16|Word|Unspecified|BaseIndex, Reg64 }
 161 movslq, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg32|Dword|Unspecified|BaseIndex, Reg64 }
 162 movsx, 0xfbe, None, 2, Cpu386, W|Modrm|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 163 movsx, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 }
 164 movsxd, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 }
 165 movsxd, 0x63, None, 1, Cpu64, Amd64|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, Reg16 }
 166 movsxd, 0x63, None, 1, Cpu64, Intel64|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Unspecified|BaseIndex, Reg16 }
 167
 168 // Move with zero extend.
 169 movzb, 0xfb6, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 170 movzw, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex, Reg32|Reg64 }
 171 // The 64-bit variant is not particularly useful since the zero extend
 172 // 32->64 is implicit, but we can encode them.
 173 movzx, 0xfb6, None, 2, Cpu386, W|Modrm|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 174
 175 // Push instructions.
 176 push, 0x50, None, 1, CpuNo64, No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32 }
 177 push, 0xff, 0x6, 1, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex }
 178 push, 0x6a, None, 1, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8S }
 179 push, 0x68, None, 1, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16|Imm32 }
 180 push, 0x6, None, 1, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg }
 181 // In 64bit mode, the operand size is implicitly 64bit.
 182 push, 0x50, None, 1, Cpu64, No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64 }
 183 push, 0xff, 0x6, 1, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex }
 184 push, 0x6a, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8S }
 185 push, 0x68, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Imm16|Imm32S }
 186 push, 0xfa0, None, 2, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { SReg }
 187
 188 pusha, 0x60, None, 1, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 189
 190 // Pop instructions.
 191 pop, 0x58, None, 1, CpuNo64, No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32 }
 192 pop, 0x8f, 0x0, 1, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex }
 193 pop, 0x7, None, 1, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg }
 194 // In 64bit mode, the operand size is implicitly 64bit.
 195 pop, 0x58, None, 1, Cpu64, No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64 }
 196 pop, 0x8f, 0x0, 1, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex }
 197 pop, 0xfa1, None, 2, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { SReg }
 198
 199 popa, 0x61, None, 1, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 200
 201 // Exchange instructions.
 202 // xchg commutes:  we allow both operand orders.
 203
 204 // In the 64bit code, xchg rax, rax is reused for new nop instruction.
 205 xchg, 0x90, None, 1, 0, CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64, Acc|Word|Dword|Qword }
 206 xchg, 0x90, None, 1, 0, CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Acc|Word|Dword|Qword, Reg16|Reg32|Reg64 }
 207 xchg, 0x86, None, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|HLEPrefixAny, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 208 xchg, 0x86, None, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|HLEPrefixAny, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
 209
 210 // In/out from ports.
 211 in, 0xe4, None, 1, 0, W|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Acc|Byte|Word|Dword }
 212 in, 0xec, None, 1, 0, W|No_sSuf|No_qSuf|No_ldSuf, { InOutPortReg, Acc|Byte|Word|Dword }
 213 in, 0xe4, None, 1, 0, W|No_sSuf|No_qSuf|No_ldSuf, { Imm8 }
 214 in, 0xec, None, 1, 0, W|No_sSuf|No_qSuf|No_ldSuf, { InOutPortReg }
 215 out, 0xe6, None, 1, 0, W|No_sSuf|No_qSuf|No_ldSuf, { Acc|Byte|Word|Dword, Imm8 }
 216 out, 0xee, None, 1, 0, W|No_sSuf|No_qSuf|No_ldSuf, { Acc|Byte|Word|Dword, InOutPortReg }
 217 out, 0xe6, None, 1, 0, W|No_sSuf|No_qSuf|No_ldSuf, { Imm8 }
 218 out, 0xee, None, 1, 0, W|No_sSuf|No_qSuf|No_ldSuf, { InOutPortReg }
 219
 220 // Load effective address.
 221 lea, 0x8d, None, 1, 0, Modrm|Anysize|No_bSuf|No_sSuf|No_ldSuf, { BaseIndex, Reg16|Reg32|Reg64 }
 222
 223 // Load segment registers from memory.
 224 lds, 0xc5, None, 1, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { DWord|Fword|Unspecified|BaseIndex, Reg16|Reg32 }
 225 les, 0xc4, None, 1, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { DWord|Fword|Unspecified|BaseIndex, Reg16|Reg32 }
 226 lfs, 0xfb4, None, 2, Cpu386, Amd64|Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Fword|Unspecified|BaseIndex, Reg16|Reg32 }
 227 lfs, 0xfb4, None, 2, Cpu64, Intel64|Modrm|No_bSuf|No_sSuf|No_ldSuf, { Dword|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 228 lgs, 0xfb5, None, 2, Cpu386, Amd64|Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Fword|Unspecified|BaseIndex, Reg16|Reg32 }
 229 lgs, 0xfb5, None, 2, Cpu64, Intel64|Modrm|No_bSuf|No_sSuf|No_ldSuf, { Dword|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 230 lss, 0xfb2, None, 2, Cpu386, Amd64|Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Fword|Unspecified|BaseIndex, Reg16|Reg32 }
 231 lss, 0xfb2, None, 2, Cpu64, Intel64|Modrm|No_bSuf|No_sSuf|No_ldSuf, { Dword|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 232
 233 // Flags register instructions.
 234 clc, 0xf8, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 235 cld, 0xfc, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 236 cli, 0xfa, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 237 clts, 0xf06, None, 2, Cpu286, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 238 cmc, 0xf5, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 239 lahf, 0x9f, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 240 sahf, 0x9e, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 241 pushf, 0x9c, None, 1, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 242 pushf, 0x9c, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, {}
 243 popf, 0x9d, None, 1, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 244 popf, 0x9d, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, {}
 245 stc, 0xf9, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 246 std, 0xfd, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 247 sti, 0xfb, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 248
 249 // Arithmetic.
 250 add, 0x0, None, 1, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 251 add, 0x83, 0x0, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
 252 add, 0x4, None, 1, 0, W|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
 253 add, 0x80, 0x0, 1, 0, W|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 254
 255 inc, 0x40, None, 1, CpuNo64, No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32 }
 256 inc, 0xfe, 0x0, 1, 0, W|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 257
 258 sub, 0x28, None, 1, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 259 sub, 0x83, 0x5, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
 260 sub, 0x2c, None, 1, 0, W|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
 261 sub, 0x80, 0x5, 1, 0, W|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 262
 263 dec, 0x48, None, 1, CpuNo64, No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32 }
 264 dec, 0xfe, 0x1, 1, 0, W|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 265
 266 sbb, 0x18, None, 1, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 267 sbb, 0x83, 0x3, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
 268 sbb, 0x1c, None, 1, 0, W|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
 269 sbb, 0x80, 0x3, 1, 0, W|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 270
 271 cmp, 0x38, None, 1, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 272 cmp, 0x83, 0x7, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
 273 cmp, 0x3c, None, 1, 0, W|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
 274 cmp, 0x80, 0x7, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 275
 276 test, 0x84, None, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|Byte|Word|Dword|Qword|BaseIndex }
 277 test, 0x84, None, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
 278 test, 0xa8, None, 1, 0, W|No_sSuf|No_ldSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
 279 test, 0xf6, 0x0, 1, 0, W|Modrm|No_sSuf|No_ldSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 280
 281 and, 0x20, None, 1, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 282 and, 0x83, 0x4, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf|HLEPrefixLock|Optimize, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
 283 and, 0x24, None, 1, 0, W|No_sSuf|No_ldSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
 284 and, 0x80, 0x4, 1, 0, W|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 285
 286 or, 0x8, None, 1, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 287 or, 0x83, 0x1, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
 288 or, 0xc, None, 1, 0, W|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
 289 or, 0x80, 0x1, 1, 0, W|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 290
 291 xor, 0x30, None, 1, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 292 xor, 0x83, 0x6, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
 293 xor, 0x34, None, 1, 0, W|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
 294 xor, 0x80, 0x6, 1, 0, W|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 295
 296 // clr with 1 operand is really xor with 2 operands.
 297 clr, 0x30, None, 1, 0, W|Modrm|No_sSuf|No_ldSuf|RegKludge|Optimize, { Reg8|Reg16|Reg32|Reg64 }
 298
 299 adc, 0x10, None, 1, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 300 adc, 0x83, 0x2, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
 301 adc, 0x14, None, 1, 0, W|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
 302 adc, 0x80, 0x2, 1, 0, W|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 303
 304 neg, 0xf6, 0x3, 1, 0, W|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 305 not, 0xf6, 0x2, 1, 0, W|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 306
 307 aaa, 0x37, None, 1, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 308 aas, 0x3f, None, 1, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 309 daa, 0x27, None, 1, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 310 das, 0x2f, None, 1, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 311 aad, 0xd50a, None, 2, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 312 aad, 0xd5, None, 1, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8 }
 313 aam, 0xd40a, None, 2, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 314 aam, 0xd4, None, 1, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8 }
 315
 316 // Conversion insns.
 317 // Intel naming
 318 cbw, 0x98, None, 1, 0, Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 319 cdqe, 0x98, None, 1, Cpu64, Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 320 cwde, 0x98, None, 1, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 321 cwd, 0x99, None, 1, 0, Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 322 cdq, 0x99, None, 1, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 323 cqo, 0x99, None, 1, Cpu64, Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 324 // AT&T naming
 325 cbtw, 0x98, None, 1, 0, Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 326 cltq, 0x98, None, 1, Cpu64, Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 327 cwtl, 0x98, None, 1, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 328 cwtd, 0x99, None, 1, 0, Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 329 cltd, 0x99, None, 1, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 330 cqto, 0x99, None, 1, Cpu64, Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 331
 332 // Warning! the mul/imul (opcode 0xf6) must only have 1 operand!  They are
 333 // expanding 64-bit multiplies, and *cannot* be selected to accomplish
 334 // 'imul %ebx, %eax' (opcode 0x0faf must be used in this case)
 335 // These multiplies can only be selected with single operand forms.
 336 mul, 0xf6, 0x4, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 337 imul, 0xf6, 0x5, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 338 imul, 0xfaf, None, 2, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Unspecified|Word|Dword|Qword|BaseIndex, Reg16|Reg32|Reg64 }
 339 imul, 0x6b, None, 1, Cpu186, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 340 imul, 0x69, None, 1, Cpu186, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 341 // imul with 2 operands mimics imul with 3 by putting the register in
 342 // both i.rm.reg & i.rm.regmem fields.  RegKludge enables this
 343 // transformation.
 344 imul, 0x6b, None, 1, Cpu186, Modrm|No_bSuf|No_sSuf|No_ldSuf|RegKludge, { Imm8S, Reg16|Reg32|Reg64 }
 345 imul, 0x69, None, 1, Cpu186, Modrm|No_bSuf|No_sSuf|No_ldSuf|RegKludge, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64 }
 346
 347 div, 0xf6, 0x6, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 348 div, 0xf6, 0x6, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
 349 idiv, 0xf6, 0x7, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 350 idiv, 0xf6, 0x7, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
 351
 352 rol, 0xd0, 0x0, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 353 rol, 0xc0, 0x0, 1, Cpu186, W|Modrm|No_sSuf|No_ldSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 354 rol, 0xd2, 0x0, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 355 rol, 0xd0, 0x0, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 356
 357 ror, 0xd0, 0x1, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 358 ror, 0xc0, 0x1, 1, Cpu186, W|Modrm|No_sSuf|No_ldSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 359 ror, 0xd2, 0x1, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 360 ror, 0xd0, 0x1, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 361
 362 rcl, 0xd0, 0x2, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 363 rcl, 0xc0, 0x2, 1, Cpu186, W|Modrm|No_sSuf|No_ldSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 364 rcl, 0xd2, 0x2, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 365 rcl, 0xd0, 0x2, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 366
 367 rcr, 0xd0, 0x3, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 368 rcr, 0xc0, 0x3, 1, Cpu186, W|Modrm|No_sSuf|No_ldSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 369 rcr, 0xd2, 0x3, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 370 rcr, 0xd0, 0x3, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 371
 372 sal, 0xd0, 0x4, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 373 sal, 0xc0, 0x4, 1, Cpu186, W|Modrm|No_sSuf|No_ldSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 374 sal, 0xd2, 0x4, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 375 sal, 0xd0, 0x4, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 376
 377 shl, 0xd0, 0x4, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 378 shl, 0xc0, 0x4, 1, Cpu186, W|Modrm|No_sSuf|No_ldSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 379 shl, 0xd2, 0x4, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 380 shl, 0xd0, 0x4, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 381
 382 shr, 0xd0, 0x5, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 383 shr, 0xc0, 0x5, 1, Cpu186, W|Modrm|No_sSuf|No_ldSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 384 shr, 0xd2, 0x5, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 385 shr, 0xd0, 0x5, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 386
 387 sar, 0xd0, 0x7, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 388 sar, 0xc0, 0x7, 1, Cpu186, W|Modrm|No_sSuf|No_ldSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 389 sar, 0xd2, 0x7, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 390 sar, 0xd0, 0x7, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 391
 392 shld, 0xfa4, None, 2, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
 393 shld, 0xfa5, None, 2, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
 394 shld, 0xfa5, None, 2, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
 395
 396 shrd, 0xfac, None, 2, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
 397 shrd, 0xfad, None, 2, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
 398 shrd, 0xfad, None, 2, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
 399
 400 // Control transfer instructions.
 401 call, 0xe8, None, 1, CpuNo64, JumpDword|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp16|Disp32 }
 402 call, 0xe8, None, 1, Cpu64, Amd64|JumpDword|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk, { Disp16|Disp32S }
 403 call, 0xe8, None, 1, Cpu64, Intel64|JumpDword|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk, { Disp32S }
 404 call, 0xff, 0x2, 1, CpuNo64, Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg32|Unspecified|BaseIndex }
 405 call, 0xff, 0x2, 1, Cpu64, Amd64|Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg64|Unspecified|BaseIndex }
 406 call, 0xff, 0x2, 1, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg64|Unspecified|BaseIndex }
 407 // Intel Syntax remaining call instances.
 408 call, 0x9a, None, 1, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 }
 409 call, 0xff, 0x3, 1, 0, Amd64|Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Dword|Fword|BaseIndex }
 410 call, 0xff, 0x3, 1, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Fword|Tbyte|BaseIndex }
 411 lcall, 0x9a, None, 1, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 }
 412 lcall, 0xff, 0x3, 1, 0, Amd64|Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex }
 413 lcall, 0xff, 0x3, 1, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex }
 414
 415 jmp, 0xeb, None, 1, 0, Amd64|Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32|Disp32S }
 416 jmp, 0xeb, None, 1, Cpu64, Intel64|Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp32S }
 417 jmp, 0xff, 0x4, 1, CpuNo64, Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg32|Unspecified|BaseIndex }
 418 jmp, 0xff, 0x4, 1, Cpu64, Amd64|Modrm|JumpAbsolute|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg64|Unspecified|BaseIndex }
 419 jmp, 0xff, 0x4, 1, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg64|Unspecified|BaseIndex }
 420 // Intel Syntax remaining jmp instances.
 421 jmp, 0xea, None, 1, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 }
 422 jmp, 0xff, 0x5, 1, 0, Amd64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Dword|Fword|BaseIndex }
 423 jmp, 0xff, 0x5, 1, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Fword|Tbyte|BaseIndex }
 424 ljmp, 0xea, None, 1, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 }
 425 ljmp, 0xff, 0x5, 1, 0, Amd64|Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex }
 426 ljmp, 0xff, 0x5, 1, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex }
 427
 428 ret, 0xc3, None, 1, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|RepPrefixOk|BNDPrefixOk, {}
 429 ret, 0xc2, None, 1, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|RepPrefixOk|BNDPrefixOk, { Imm16 }
 430 ret, 0xc3, None, 1, Cpu64, Amd64|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|RepPrefixOk|BNDPrefixOk, {}
 431 ret, 0xc2, None, 1, Cpu64, Amd64|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { Imm16 }
 432 ret, 0xc3, None, 1, Cpu64, Intel64|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|RepPrefixOk|BNDPrefixOk, {}
 433 ret, 0xc2, None, 1, Cpu64, Intel64|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { Imm16 }
 434 lret, 0xcb, None, 1, 0, DefaultSize|No_bSuf|No_sSuf|No_ldSuf, {}
 435 lret, 0xca, None, 1, 0, DefaultSize|No_bSuf|No_sSuf|No_ldSuf, { Imm16 }
 436 // Intel Syntax.
 437 retf, 0xcb, None, 1, 0, DefaultSize|No_bSuf|No_sSuf|No_ldSuf, {}
 438 retf, 0xca, None, 1, 0, DefaultSize|No_bSuf|No_sSuf|No_ldSuf, { Imm16 }
 439
 440 enter, 0xc8, None, 1, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm8 }
 441 enter, 0xc8, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Imm16, Imm8 }
 442 leave, 0xc9, None, 1, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 443 leave, 0xc9, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, {}
 444
 445 <cc:opc, o:0, no:1, b:2, c:2, nae:2, nb:3, nc:3, ae:3, e:4, z:4, ne:5, nz:5, be:6, na:6, nbe:7, a:7, \
 446          s:8, ns:9, p:a, pe:a, np:b, po:b, l:c, nge:c, nl:d, ge:d, le:e, ng:e, nle:f, g:f>
 447
 448 // Conditional jumps.
 449 j<cc>, 0x7<cc:opc>, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32|Disp32S }
 450
 451 // jcxz vs. jecxz is chosen on the basis of the address size prefix.
 452 jcxz, 0xe3, None, 1, CpuNo64, JumpByte|Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8 }
 453 jecxz, 0xe3, None, 1, 0, JumpByte|Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8 }
 454 jrcxz, 0xe3, None, 1, Cpu64, JumpByte|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Disp8 }
 455
 456 // The loop instructions also use the address size prefix to select
 457 // %cx rather than %ecx for the loop count, so the `w' form of these
 458 // instructions emit an address size prefix rather than a data size
 459 //  prefix.
 460 loop, 0xe2, None, 1, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8 }
 461 loop, 0xe2, None, 1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8 }
 462 loopz, 0xe1, None, 1, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8 }
 463 loopz, 0xe1, None, 1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8 }
 464 loope, 0xe1, None, 1, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8 }
 465 loope, 0xe1, None, 1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8 }
 466 loopnz, 0xe0, None, 1, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8 }
 467 loopnz, 0xe0, None, 1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8 }
 468 loopne, 0xe0, None, 1, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8 }
 469 loopne, 0xe0, None, 1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8 }
 470
 471 // Set byte on flag instructions.
 472 set<cc>, 0xf9<cc:opc>, 0x0, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex }
 473
 474 // String manipulation.
 475 cmps, 0xa6, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, {}
 476 cmps, 0xa6, None, 1, 0, W|No_sSuf|No_ldSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 477 scmp, 0xa6, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, {}
 478 scmp, 0xa6, None, 1, 0, W|No_sSuf|No_ldSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 479 ins, 0x6c, None, 1, Cpu186, W|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, {}
 480 ins, 0x6c, None, 1, Cpu186, W|No_sSuf|No_qSuf|No_ldSuf|IsStringEsOp1|RepPrefixOk, { InOutPortReg, Byte|Word|Dword|Unspecified|BaseIndex }
 481 outs, 0x6e, None, 1, Cpu186, W|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, {}
 482 outs, 0x6e, None, 1, Cpu186, W|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Unspecified|BaseIndex, InOutPortReg }
 483 lods, 0xac, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, {}
 484 lods, 0xac, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 485 lods, 0xac, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
 486 slod, 0xac, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, {}
 487 slod, 0xac, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 488 slod, 0xac, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
 489 movs, 0xa4, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, {}
 490 movs, 0xa4, None, 1, 0, W|No_sSuf|No_ldSuf|IsStringEsOp1|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 491 smov, 0xa4, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, {}
 492 smov, 0xa4, None, 1, 0, W|No_sSuf|No_ldSuf|IsStringEsOp1|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 493 scas, 0xae, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, {}
 494 scas, 0xae, None, 1, 0, W|No_sSuf|No_ldSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 495 scas, 0xae, None, 1, 0, W|No_sSuf|No_ldSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
 496 ssca, 0xae, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, {}
 497 ssca, 0xae, None, 1, 0, W|No_sSuf|No_ldSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 498 ssca, 0xae, None, 1, 0, W|No_sSuf|No_ldSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
 499 stos, 0xaa, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, {}
 500 stos, 0xaa, None, 1, 0, W|No_sSuf|No_ldSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 501 stos, 0xaa, None, 1, 0, W|No_sSuf|No_ldSuf|IsStringEsOp1|RepPrefixOk, { Acc|Byte|Word|Dword|Qword, Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 502 ssto, 0xaa, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, {}
 503 ssto, 0xaa, None, 1, 0, W|No_sSuf|No_ldSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 504 ssto, 0xaa, None, 1, 0, W|No_sSuf|No_ldSuf|IsStringEsOp1|RepPrefixOk, { Acc|Byte|Word|Dword|Qword, Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 505 xlat, 0xd7, None, 1, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString, {}
 506 xlat, 0xd7, None, 1, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString, { Byte|Unspecified|BaseIndex }
 507
 508 // Bit manipulation.
 509 bsf, 0xfbc, None, 2, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf|RepPrefixOk, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 510 bsr, 0xfbd, None, 2, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf|RepPrefixOk, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 511 bt, 0xfa3, None, 2, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
 512 bt, 0xfba, 0x4, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
 513 btc, 0xfbb, None, 2, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
 514 btc, 0xfba, 0x7, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
 515 btr, 0xfb3, None, 2, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
 516 btr, 0xfba, 0x6, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
 517 bts, 0xfab, None, 2, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
 518 bts, 0xfba, 0x5, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
 519
 520 // Interrupts & op. sys insns.
 521 // See gas/config/tc-i386.c for conversion of 'int $3' into the special
 522 // int 3 insn.
 523 int, 0xcd, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8 }
 524 int3, 0xcc, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 525 into, 0xce, None, 1, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 526 iret, 0xcf, None, 1, 0, DefaultSize|No_bSuf|No_sSuf|No_ldSuf, {}
 527 // i386sl, i486sl, later 486, and Pentium.
 528 rsm, 0xfaa, None, 2, Cpu386, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 529
 530 bound, 0x62, None, 1, Cpu186|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32, Dword|Qword|Unspecified|BaseIndex }
 531
 532 hlt, 0xf4, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 533
 534 nop, 0xf1f, 0x0, 2, CpuNop, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
 535
 536 // nop is actually "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
 537 // 32bit mode and "xchg %rax,%rax" in 64bit mode.
 538 nop, 0x90, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|RepPrefixOk, {}
 539
 540 // Protection control.
 541 arpl, 0x63, None, 1, Cpu286|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16, Reg16|Word|Unspecified|BaseIndex }
 542 lar, 0xf02, None, 2, Cpu286, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 543 lgdt, 0xf01, 0x2, 2, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Fword|Unspecified|BaseIndex }
 544 lgdt, 0xf01, 0x2, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
 545 lidt, 0xf01, 0x3, 2, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Fword|Unspecified|BaseIndex }
 546 lidt, 0xf01, 0x3, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
 547 lldt, 0xf00, 0x2, 2, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex }
 548 lmsw, 0xf01, 0x6, 2, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex }
 549 lsl, 0xf03, None, 2, Cpu286, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 550 ltr, 0xf00, 0x3, 2, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex }
 551
 552 sgdt, 0xf01, 0x0, 2, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Fword|Unspecified|BaseIndex }
 553 sgdt, 0xf01, 0x0, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
 554 sidt, 0xf01, 0x1, 2, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Fword|Unspecified|BaseIndex }
 555 sidt, 0xf01, 0x1, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
 556 sldt, 0xf00, 0x0, 2, Cpu286, Modrm|No_bSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg32|Reg64 }
 557 sldt, 0xf00, 0x0, 2, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex }
 558 smsw, 0xf01, 0x4, 2, Cpu286, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64 }
 559 smsw, 0xf01, 0x4, 2, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex }
 560 str, 0xf00, 0x1, 2, Cpu286, Modrm|No_bSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg32|Reg64 }
 561 str, 0xf00, 0x1, 2, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex }
 562
 563 verr, 0xf00, 0x4, 2, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex }
 564 verw, 0xf00, 0x5, 2, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex }
 565
 566 // Floating point instructions.
 567
 568 // load
 569 fld, 0xd9c0, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
 570 fld, 0xd9, 0x0, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex }
 571 fld, 0xd9c0, None, 2, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh, { FloatReg }
 572 // Intel Syntax
 573 fld, 0xdb, 0x5, 1, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Tbyte|Unspecified|BaseIndex }
 574 fild, 0xdf, 0x0, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex }
 575 fild, 0xdf, 0x5, 1, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex }
 576 fildll, 0xdf, 0x5, 1, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex }
 577 fldt, 0xdb, 0x5, 1, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Tbyte|Unspecified|BaseIndex }
 578 fbld, 0xdf, 0x4, 1, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Tbyte|Unspecified|BaseIndex }
 579
 580 // store (no pop)
 581 fst, 0xddd0, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
 582 fst, 0xd9, 0x2, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex }
 583 fst, 0xddd0, None, 2, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh, { FloatReg }
 584 fist, 0xdf, 0x2, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex }
 585
 586 // store (with pop)
 587 fstp, 0xddd8, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
 588 fstp, 0xd9, 0x3, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex }
 589 fstp, 0xddd8, None, 2, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh, { FloatReg }
 590 // Intel Syntax
 591 fstp, 0xdb, 0x7, 1, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Tbyte|Unspecified|BaseIndex }
 592 fistp, 0xdf, 0x3, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex }
 593 fistp, 0xdf, 0x7, 1, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex }
 594 fistpll, 0xdf, 0x7, 1, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex }
 595 fstpt, 0xdb, 0x7, 1, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Tbyte|Unspecified|BaseIndex }
 596 fbstp, 0xdf, 0x6, 1, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Tbyte|Unspecified|BaseIndex }
 597
 598 // exchange %st<n> with %st0
 599 fxch, 0xd9c8, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
 600 // alias for fxch %st(1)
 601 fxch, 0xd9c9, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 602
 603 // comparison (without pop)
 604 fcom, 0xd8d0, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
 605 // alias for fcom %st(1)
 606 fcom, 0xd8d1, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 607 fcom, 0xd8, 0x2, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex }
 608 fcom, 0xd8d0, None, 2, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh, { FloatReg }
 609 ficom, 0xde, 0x2, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex }
 610
 611 // comparison (with pop)
 612 fcomp, 0xd8d8, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
 613 // alias for fcomp %st(1)
 614 fcomp, 0xd8d9, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 615 fcomp, 0xd8, 0x3, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex }
 616 fcomp, 0xd8d8, None, 2, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh, { FloatReg }
 617 ficomp, 0xde, 0x3, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex }
 618 fcompp, 0xded9, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 619
 620 // unordered comparison (with pop)
 621 fucom, 0xdde0, None, 2, Cpu387, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
 622 // alias for fucom %st(1)
 623 fucom, 0xdde1, None, 2, Cpu387, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 624 fucomp, 0xdde8, None, 2, Cpu387, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
 625 // alias for fucomp %st(1)
 626 fucomp, 0xdde9, None, 2, Cpu387, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 627 fucompp, 0xdae9, None, 2, Cpu387, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 628
 629 ftst, 0xd9e4, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 630 fxam, 0xd9e5, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 631
 632 // load constants into %st0
 633 fld1, 0xd9e8, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 634 fldl2t, 0xd9e9, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 635 fldl2e, 0xd9ea, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 636 fldpi, 0xd9eb, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 637 fldlg2, 0xd9ec, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 638 fldln2, 0xd9ed, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 639 fldz, 0xd9ee, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 640
 641 // Arithmetic.
 642
 643 // add
 644 fadd, 0xd8c0, None, 2, CpuFP, D|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc }
 645 // alias for fadd %st(i), %st
 646 fadd, 0xd8c0, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
 647 // alias for faddp
 648 fadd, 0xdec1, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic, {}
 649 fadd, 0xd8, 0x0, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex }
 650 fiadd, 0xde, 0x0, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex }
 651
 652 faddp, 0xdec0, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatAcc, FloatReg }
 653 faddp, 0xdec0, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
 654 // alias for faddp %st, %st(1)
 655 faddp, 0xdec1, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 656 faddp, 0xdec0, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh, { FloatReg, FloatAcc }
 657
 658 // subtract
 659 fsub, 0xd8e0, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
 660 fsub, 0xd8e0, None, 2, CpuFP, D|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatReg, FloatAcc }
 661 // alias for fsubp
 662 fsub, 0xdee1, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|ATTSyntax, {}
 663 fsub, 0xdee9, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic, {}
 664 fsub, 0xd8e0, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|D|FloatR, { FloatReg, FloatAcc }
 665 fsub, 0xd8, 0x4, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex }
 666 fisub, 0xde, 0x4, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex }
 667
 668 fsubp, 0xdee0, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg }
 669 fsubp, 0xdee0, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatReg }
 670 fsubp, 0xdee1, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, {}
 671 fsubp, 0xdee8, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { FloatAcc, FloatReg }
 672 fsubp, 0xdee8, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { FloatReg }
 673 fsubp, 0xdee9, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 674
 675 // subtract reverse
 676 fsubr, 0xd8e8, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
 677 fsubr, 0xd8e8, None, 2, CpuFP, D|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatReg, FloatAcc }
 678 // alias for fsubrp
 679 fsubr, 0xdee9, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|ATTSyntax, {}
 680 fsubr, 0xdee1, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic, {}
 681 fsubr, 0xd8e8, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|D|FloatR, { FloatReg, FloatAcc }
 682 fsubr, 0xd8, 0x5, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex }
 683 fisubr, 0xde, 0x5, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex }
 684
 685 fsubrp, 0xdee8, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg }
 686 fsubrp, 0xdee8, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatReg }
 687 fsubrp, 0xdee9, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, {}
 688 fsubrp, 0xdee0, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { FloatAcc, FloatReg }
 689 fsubrp, 0xdee0, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { FloatReg }
 690 fsubrp, 0xdee1, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, {}
 691
 692 // multiply
 693 fmul, 0xd8c8, None, 2, CpuFP, D|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc }
 694 fmul, 0xd8c8, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
 695 // alias for fmulp
 696 fmul, 0xdec9, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic, {}
 697 fmul, 0xd8, 0x1, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex }
 698 fimul, 0xde, 0x1, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex }
 699
 700 fmulp, 0xdec8, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatAcc, FloatReg }
 701 fmulp, 0xdec8, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
 702 fmulp, 0xdec9, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 703 fmulp, 0xdec8, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh, { FloatReg, FloatAcc }
 704
 705 // divide
 706 fdiv, 0xd8f0, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
 707 fdiv, 0xd8f0, None, 2, CpuFP, D|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatReg, FloatAcc }
 708 // alias for fdivp
 709 fdiv, 0xdef1, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|ATTSyntax, {}
 710 fdiv, 0xdef9, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic, {}
 711 fdiv, 0xd8f0, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|D|FloatR, { FloatReg, FloatAcc }
 712 fdiv, 0xd8, 0x6, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex }
 713 fidiv, 0xde, 0x6, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex }
 714
 715 fdivp, 0xdef0, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg }
 716 fdivp, 0xdef0, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatReg }
 717 fdivp, 0xdef1, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, {}
 718 fdivp, 0xdef8, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { FloatAcc, FloatReg }
 719 fdivp, 0xdef8, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { FloatReg }
 720 fdivp, 0xdef9, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, {}
 721
 722 // divide reverse
 723 fdivr, 0xd8f8, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
 724 fdivr, 0xd8f8, None, 2, CpuFP, D|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatReg, FloatAcc }
 725 // alias for fdivrp
 726 fdivr, 0xdef9, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic|ATTSyntax, {}
 727 fdivr, 0xdef1, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic, {}
 728 fdivr, 0xd8f8, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|D|FloatR, { FloatReg, FloatAcc }
 729 fdivr, 0xd8, 0x7, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex }
 730 fidivr, 0xde, 0x7, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex }
 731
 732 fdivrp, 0xdef8, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg }
 733 fdivrp, 0xdef8, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatReg }
 734 fdivrp, 0xdef9, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, {}
 735 fdivrp, 0xdef0, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { FloatAcc, FloatReg }
 736 fdivrp, 0xdef0, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { FloatReg }
 737 fdivrp, 0xdef1, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, {}
 738
 739 f2xm1, 0xd9f0, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 740 fyl2x, 0xd9f1, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 741 fptan, 0xd9f2, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 742 fpatan, 0xd9f3, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 743 fxtract, 0xd9f4, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 744 fprem1, 0xd9f5, None, 2, Cpu387, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 745 fdecstp, 0xd9f6, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 746 fincstp, 0xd9f7, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 747 fprem, 0xd9f8, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 748 fyl2xp1, 0xd9f9, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 749 fsqrt, 0xd9fa, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 750 fsincos, 0xd9fb, None, 2, Cpu387, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 751 frndint, 0xd9fc, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 752 fscale, 0xd9fd, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 753 fsin, 0xd9fe, None, 2, Cpu387, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 754 fcos, 0xd9ff, None, 2, Cpu387, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 755 fchs, 0xd9e0, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 756 fabs, 0xd9e1, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 757
 758 // processor control
 759 fninit, 0xdbe3, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 760 finit, 0xdbe3, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FWait, {}
 761 fldcw, 0xd9, 0x5, 1, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex }
 762 fnstcw, 0xd9, 0x7, 1, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex }
 763 fstcw, 0xd9, 0x7, 1, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FWait, { Word|Unspecified|BaseIndex }
 764 fnstsw, 0xdfe0, None, 2, Cpu287|Cpu387, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Acc|Word }
 765 fnstsw, 0xdd, 0x7, 1, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex }
 766 fnstsw, 0xdfe0, None, 2, Cpu287|Cpu387, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 767 fstsw, 0xdfe0, None, 2, Cpu287|Cpu387, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FWait, { Acc|Word }
 768 fstsw, 0xdd, 0x7, 1, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FWait, { Word|Unspecified|BaseIndex }
 769 fstsw, 0xdfe0, None, 2, Cpu287|Cpu387, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FWait, {}
 770 fnclex, 0xdbe2, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 771 fclex, 0xdbe2, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FWait, {}
 772 // Short forms of fldenv, fstenv, fsave, and frstor use data size prefix.
 773 fnstenv, 0xd9, 0x6, 1, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex }
 774 fstenv, 0xd9, 0x6, 1, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf|No_ldSuf|FWait, { Unspecified|BaseIndex }
 775 fldenv, 0xd9, 0x4, 1, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex }
 776 fnsave, 0xdd, 0x6, 1, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex }
 777 fsave, 0xdd, 0x6, 1, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf|No_ldSuf|FWait, { Unspecified|BaseIndex }
 778 frstor, 0xdd, 0x4, 1, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex }
 779 // 8087 only
 780 fneni, 0xdbe0, None, 2, Cpu8087, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 781 feni, 0xdbe0, None, 2, Cpu8087, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FWait, {}
 782 fndisi, 0xdbe1, None, 2, Cpu8087, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 783 fdisi, 0xdbe1, None, 2, Cpu8087, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FWait, {}
 784 // 287 only
 785 fnsetpm, 0xdbe4, None, 2, Cpu287, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 786 fsetpm, 0xdbe4, None, 2, Cpu287, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|FWait, {}
 787 frstpm, 0xdbe5, None, 2, Cpu287, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 788
 789 ffree, 0xddc0, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
 790 // P6:free st(i), pop st
 791 ffreep, 0xdfc0, None, 2, Cpu687, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
 792 fnop, 0xd9d0, None, 2, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 793 fwait, 0x9b, None, 1, CpuFP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 794
 795 // Opcode prefixes; we allow them as separate insns too.
 796
 797 addr16, 0x67, None, 1, Cpu386|CpuNo64, Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 798 addr32, 0x67, None, 1, Cpu386, Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 799 aword, 0x67, None, 1, Cpu386|CpuNo64, Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 800 adword, 0x67, None, 1, Cpu386, Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 801 data16, 0x66, None, 1, Cpu386, Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 802 data32, 0x66, None, 1, Cpu386|CpuNo64, Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 803 word, 0x66, None, 1, Cpu386, Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 804 dword, 0x66, None, 1, Cpu386|CpuNo64, Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 805 lock, 0xf0, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 806 wait, 0x9b, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 807 cs, 0x2e, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 808 ds, 0x3e, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 809 es, 0x26, None, 1, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 810 fs, 0x64, None, 1, Cpu386, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 811 gs, 0x65, None, 1, Cpu386, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 812 ss, 0x36, None, 1, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 813 rep, 0xf3, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 814 repe, 0xf3, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 815 repz, 0xf3, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 816 repne, 0xf2, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 817 repnz, 0xf2, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 818 ht, 0x3e, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 819 hnt, 0x2e, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 820 rex, 0x40, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 821 rexz, 0x41, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 822 rexy, 0x42, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 823 rexyz, 0x43, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 824 rexx, 0x44, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 825 rexxz, 0x45, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 826 rexxy, 0x46, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 827 rexxyz, 0x47, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 828 rex64, 0x48, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 829 rex64z, 0x49, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 830 rex64y, 0x4a, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 831 rex64yz, 0x4b, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 832 rex64x, 0x4c, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 833 rex64xz, 0x4d, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 834 rex64xy, 0x4e, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 835 rex64xyz, 0x4f, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 836 rex.b, 0x41, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 837 rex.x, 0x42, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 838 rex.xb, 0x43, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 839 rex.r, 0x44, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 840 rex.rb, 0x45, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 841 rex.rx, 0x46, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 842 rex.rxb, 0x47, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 843 rex.w, 0x48, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 844 rex.wb, 0x49, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 845 rex.wx, 0x4a, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 846 rex.wxb, 0x4b, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 847 rex.wr, 0x4c, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 848 rex.wrb, 0x4d, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 849 rex.wrx, 0x4e, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 850 rex.wrxb, 0x4f, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 851
 852 // Pseudo prefixes (opcode_length == 0)
 853
 854 {disp8}, Prefix_Disp8, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 855 {disp16}, Prefix_Disp16, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 856 {disp32}, Prefix_Disp32, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 857 {load}, Prefix_Load, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 858 {store}, Prefix_Store, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 859 {vex}, Prefix_VEX, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 860 {vex2}, Prefix_VEX, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 861 {vex3}, Prefix_VEX3, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 862 {evex}, Prefix_EVEX, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 863 {rex}, Prefix_REX, None, 0, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 864 {nooptimize}, Prefix_NoOptimize, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
 865
 866 // 486 extensions.
 867
 868 bswap, 0xfc8, None, 2, Cpu486, No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64 }
 869 xadd, 0xfc0, None, 2, Cpu486, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 870 cmpxchg, 0xfb0, None, 2, Cpu486, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 871 invd, 0xf08, None, 2, Cpu486, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 872 wbinvd, 0xf09, None, 2, Cpu486, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 873 invlpg, 0xf01, 0x7, 2, Cpu486, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex }
 874
 875 // 586 and late 486 extensions.
 876 cpuid, 0xfa2, None, 2, Cpu486, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 877
 878 // Pentium extensions.
 879 wrmsr, 0xf30, None, 2, Cpu586, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 880 rdtsc, 0xf31, None, 2, Cpu586, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 881 rdmsr, 0xf32, None, 2, Cpu586, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 882 cmpxchg8b, 0xfc7, 0x1, 2, Cpu586, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64|HLEPrefixLock, { Qword|Unspecified|BaseIndex }
 883
 884 // Pentium II/Pentium Pro extensions.
 885 sysenter, 0xf34, None, 2, Cpu64, Intel64Only|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 886 sysenter, 0xf34, None, 2, Cpu686|CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 887 sysexit, 0xf35, None, 2, Cpu64, Intel64Only|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, {}
 888 sysexit, 0xf35, None, 2, Cpu686|CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 889 fxsave, 0xfae, 0x0, 2, CpuFXSR, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex }
 890 fxsave64, 0xfae, 0x0, 2, CpuFXSR|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Unspecified|BaseIndex }
 891 fxrstor, 0xfae, 0x1, 2, CpuFXSR, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex }
 892 fxrstor64, 0xfae, 0x1, 2, CpuFXSR|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Unspecified|BaseIndex }
 893 rdpmc, 0xf33, None, 2, Cpu686, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 894 // official undefined instr.
 895 ud2, 0xf0b, None, 2, Cpu186, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 896 // alias for ud2
 897 ud2a, 0xf0b, None, 2, Cpu186, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 898 // 2nd. official undefined instr.
 899 ud1, 0xfb9, None, 2, Cpu186, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 900 // alias for ud1
 901 ud2b, 0xfb9, None, 2, Cpu186, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 902 // 3rd official undefined instr (older CPUs don't take a ModR/M byte)
 903 ud0, 0xfff, None, 2, Cpu186, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 904
 905 cmov<cc>, 0xf4<cc:opc>, None, 2, CpuCMOV, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 906
 907 fcmovb, 0xdac0, None, 2, Cpu687, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc }
 908 fcmovnae, 0xdac0, None, 2, Cpu687, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc }
 909 fcmove, 0xdac8, None, 2, Cpu687, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc }
 910 fcmovbe, 0xdad0, None, 2, Cpu687, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc }
 911 fcmovna, 0xdad0, None, 2, Cpu687, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc }
 912 fcmovu, 0xdad8, None, 2, Cpu687, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc }
 913 fcmovae, 0xdbc0, None, 2, Cpu687, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc }
 914 fcmovnb, 0xdbc0, None, 2, Cpu687, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc }
 915 fcmovne, 0xdbc8, None, 2, Cpu687, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc }
 916 fcmova, 0xdbd0, None, 2, Cpu687, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc }
 917 fcmovnbe, 0xdbd0, None, 2, Cpu687, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc }
 918 fcmovnu, 0xdbd8, None, 2, Cpu687, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc }
 919
 920 fcomi, 0xdbf0, None, 2, Cpu687, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc }
 921 fcomi, 0xdbf1, None, 2, Cpu687, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 922 fcomi, 0xdbf0, None, 2, Cpu687, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
 923 fucomi, 0xdbe8, None, 2, Cpu687, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc }
 924 fucomi, 0xdbe9, None, 2, Cpu687, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 925 fucomi, 0xdbe8, None, 2, Cpu687, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
 926 fcomip, 0xdff0, None, 2, Cpu687, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc }
 927 fcomip, 0xdff1, None, 2, Cpu687, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 928 fcomip, 0xdff0, None, 2, Cpu687, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
 929 fcompi, 0xdff0, None, 2, Cpu687, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc }
 930 fcompi, 0xdff1, None, 2, Cpu687, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 931 fcompi, 0xdff0, None, 2, Cpu687, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
 932 fucomip, 0xdfe8, None, 2, Cpu687, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc }
 933 fucomip, 0xdfe9, None, 2, Cpu687, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 934 fucomip, 0xdfe8, None, 2, Cpu687, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
 935 fucompi, 0xdfe8, None, 2, Cpu687, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg, FloatAcc }
 936 fucompi, 0xdfe9, None, 2, Cpu687, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 937 fucompi, 0xdfe8, None, 2, Cpu687, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { FloatReg }
 938
 939 // Pentium4 extensions.
 940
 941 movnti, 0xfc3, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoAVX, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
 942 clflush, 0xfae, 0x7, 2, CpuClflush, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex }
 943 lfence, 0xfaee8, None, 3, CpuSSE2, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, {}
 944 mfence, 0xfaef0, None, 3, CpuSSE2, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, {}
 945 // Processors that do not support PAUSE treat this opcode as a NOP instruction.
 946 pause, 0xf390, None, 2, Cpu186, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 947
 948 // MMX/SSE2 instructions.
 949
 950 emms, 0xf77, None, 2, CpuMMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
 951 // These really shouldn't allow for Reg64 (movq is the right mnemonic for
 952 // copying between Reg64/Mem64 and RegXMM/RegMMX, as is mandated by Intel's
 953 // spec). AMD's spec, having been in existence for much longer, failed to
 954 // recognize that and specified movd for 32- and 64-bit operations.
 955 movd, 0x666e, None, 1, CpuAVX, D|Modrm|Vex=1|OpcodePrefix=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Reg32|Unspecified|BaseIndex, RegXMM }
 956 movd, 0x666e, None, 1, CpuAVX|Cpu64, D|Modrm|Vex=1|OpcodePrefix=0|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64|SSE2AVX, { Reg64|BaseIndex, RegXMM }
 957 movd, 0x0f6e, None, 2, CpuSSE2, Prefix_0X66|D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, RegXMM }
 958 movd, 0x0f6e, None, 2, CpuSSE2|Cpu64, Prefix_0X66|D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|BaseIndex, RegXMM }
 959 movd, 0xf6e, None, 2, CpuMMX, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, RegMMX }
 960 movd, 0xf6e, None, 2, CpuMMX|Cpu64, D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|BaseIndex, RegMMX }
 961 // In the 64bit mode the short form mov immediate is redefined to have
 962 // 64bit displacement value.  We put the 64bit displacement first and
 963 // we only mark constants larger than 32bit as Disp64.
 964 movq, 0xa1, None, 1, Cpu64, D|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp64|Unspecified|Qword, Acc|Qword }
 965 movq, 0x89, None, 1, Cpu64, D|Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|HLEPrefixRelease, { Reg64, Reg64|Unspecified|Qword|BaseIndex }
 966 movq, 0xc7, 0x0, 1, Cpu64, Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|HLEPrefixRelease|Optimize, { Imm32S, Reg64|Qword|Unspecified|BaseIndex }
 967 movq, 0xb8, None, 1, Cpu64, Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Imm64, Reg64 }
 968 movq, 0xf37e, None, 1, CpuAVX, Load|Modrm|Vex=1|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
 969 movq, 0x66d6, None, 1, CpuAVX, Modrm|Vex=1|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM }
 970 movq, 0x666e, None, 1, CpuAVX|Cpu64, D|Modrm|Vex=1|OpcodePrefix=0|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64|SSE2AVX, { Reg64|Unspecified|BaseIndex, RegXMM }
 971 movq, 0x0f7e, None, 2, CpuSSE2, Prefix_0XF3|Load|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Unspecified|Qword|BaseIndex|RegXMM, RegXMM }
 972 movq, 0x0fd6, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegXMM, Unspecified|Qword|BaseIndex|RegXMM }
 973 movq, 0x0f6e, None, 2, Cpu64, Prefix_0X66|D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Unspecified|BaseIndex, RegXMM }
 974 movq, 0xf6f, None, 2, CpuMMX, D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Unspecified|Qword|BaseIndex|RegMMX, RegMMX }
 975 movq, 0xf6e, None, 2, Cpu64, D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Unspecified|BaseIndex, RegMMX }
 976 // The segment register moves accept Reg64 so that a segment register
 977 // can be copied to a 64 bit register, and vice versa.
 978 movq, 0x8c, None, 1, Cpu64, D|RegMem|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg, Reg64 }
 979 // Move to/from control debug registers.  In the 16 or 32bit modes they
 980 // are 32bit.  In the 64bit mode they are 64bit.
 981 movq, 0xf20, None, 2, Cpu64, D|RegMem|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Control, Reg64 }
 982 movq, 0xf21, None, 2, Cpu64, D|RegMem|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Debug, Reg64 }
 983 // Real MMX/SSE instructions.
 984 packssdw, 0x666b, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
 985 packssdw, 0x0f6b, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
 986 packssdw, 0xf6b, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
 987 packsswb, 0x6663, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
 988 packsswb, 0x0f63, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
 989 packsswb, 0xf63, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
 990 packuswb, 0x6667, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
 991 packuswb, 0x0f67, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
 992 packuswb, 0xf67, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
 993 paddb, 0x66fc, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
 994 paddb, 0x0ffc, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
 995 paddb, 0xffc, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
 996 paddw, 0x66fd, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
 997 paddw, 0x0ffd, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
 998 paddw, 0xffd, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
 999 paddd, 0x66fe, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1000 paddd, 0x0ffe, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1001 paddd, 0xffe, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1002 paddq, 0x66d4, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1003 paddq, 0x0fd4, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1004 paddq, 0xfd4, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1005 paddsb, 0x66ec, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1006 paddsb, 0x0fec, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1007 paddsb, 0xfec, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1008 paddsw, 0x66ed, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1009 paddsw, 0x0fed, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1010 paddsw, 0xfed, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1011 paddusb, 0x66dc, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1012 paddusb, 0x0fdc, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1013 paddusb, 0xfdc, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1014 paddusw, 0x66dd, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1015 paddusw, 0x0fdd, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1016 paddusw, 0xfdd, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1017 pand, 0x66db, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1018 pand, 0x0fdb, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1019 pand, 0xfdb, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1020 pandn, 0x66df, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1021 pandn, 0x0fdf, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1022 pandn, 0xfdf, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1023 pcmpeqb, 0x6674, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1024 pcmpeqb, 0x0f74, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1025 pcmpeqb, 0xf74, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1026 pcmpeqw, 0x6675, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1027 pcmpeqw, 0x0f75, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1028 pcmpeqw, 0xf75, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1029 pcmpeqd, 0x6676, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1030 pcmpeqd, 0x0f76, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1031 pcmpeqd, 0xf76, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1032 pcmpgtb, 0x6664, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1033 pcmpgtb, 0x0f64, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1034 pcmpgtb, 0xf64, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1035 pcmpgtw, 0x6665, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1036 pcmpgtw, 0x0f65, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1037 pcmpgtw, 0xf65, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1038 pcmpgtd, 0x6666, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1039 pcmpgtd, 0x0f66, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1040 pcmpgtd, 0xf66, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1041 pmaddwd, 0x66f5, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1042 pmaddwd, 0x0ff5, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1043 pmaddwd, 0xff5, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1044 pmulhw, 0x66e5, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1045 pmulhw, 0x0fe5, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1046 pmulhw, 0xfe5, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1047 pmullw, 0x66d5, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1048 pmullw, 0x0fd5, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1049 pmullw, 0xfd5, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1050 por, 0x66eb, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1051 por, 0x0feb, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1052 por, 0xfeb, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1053 psllw, 0x6671, 0x6, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=2|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM }
1054 psllw, 0x66f1, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1055 psllw, 0x0f71, 0x6, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM }
1056 psllw, 0x0ff1, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1057 psllw, 0xf71, 0x6, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMMX }
1058 psllw, 0xff1, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1059 pslld, 0x6672, 0x6, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=2|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM }
1060 pslld, 0x66f2, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1061 pslld, 0x0f72, 0x6, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM }
1062 pslld, 0x0ff2, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1063 pslld, 0xf72, 0x6, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMMX }
1064 pslld, 0xff2, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1065 psllq, 0x6673, 0x6, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=2|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM }
1066 psllq, 0x66f3, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1067 psllq, 0x0f73, 0x6, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM }
1068 psllq, 0x0ff3, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1069 psllq, 0xf73, 0x6, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMMX }
1070 psllq, 0xff3, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1071 psraw, 0x6671, 0x4, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=2|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM }
1072 psraw, 0x66e1, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1073 psraw, 0x0f71, 0x4, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM }
1074 psraw, 0x0fe1, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1075 psraw, 0xf71, 0x4, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMMX }
1076 psraw, 0xfe1, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1077 psrad, 0x6672, 0x4, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=2|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM }
1078 psrad, 0x66e2, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1079 psrad, 0x0f72, 0x4, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM }
1080 psrad, 0x0fe2, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1081 psrad, 0xf72, 0x4, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMMX }
1082 psrad, 0xfe2, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1083 psrlw, 0x6671, 0x2, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=2|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM }
1084 psrlw, 0x66d1, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1085 psrlw, 0x0f71, 0x2, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM }
1086 psrlw, 0x0fd1, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1087 psrlw, 0xf71, 0x2, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMMX }
1088 psrlw, 0xfd1, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1089 psrld, 0x6672, 0x2, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=2|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM }
1090 psrld, 0x66d2, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1091 psrld, 0x0f72, 0x2, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM }
1092 psrld, 0x0fd2, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1093 psrld, 0xf72, 0x2, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMMX }
1094 psrld, 0xfd2, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1095 psrlq, 0x6673, 0x2, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=2|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM }
1096 psrlq, 0x66d3, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1097 psrlq, 0x0f73, 0x2, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM }
1098 psrlq, 0x0fd3, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1099 psrlq, 0xf73, 0x2, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMMX }
1100 psrlq, 0xfd3, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1101 psubb, 0x66f8, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1102 psubb, 0x0ff8, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1103 psubb, 0xff8, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1104 psubw, 0x66f9, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1105 psubw, 0x0ff9, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1106 psubw, 0xff9, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1107 psubd, 0x66fa, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1108 psubd, 0x0ffa, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1109 psubd, 0xffa, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1110 psubq, 0x66fb, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1111 psubq, 0x0ffb, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1112 psubq, 0xffb, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1113 psubsb, 0x66e8, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1114 psubsb, 0x0fe8, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1115 psubsb, 0xfe8, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1116 psubsw, 0x66e9, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1117 psubsw, 0x0fe9, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1118 psubsw, 0xfe9, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1119 psubusb, 0x66d8, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1120 psubusb, 0x0fd8, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1121 psubusb, 0xfd8, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1122 psubusw, 0x66d9, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1123 psubusw, 0x0fd9, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1124 psubusw, 0xfd9, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1125 punpckhbw, 0x6668, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1126 punpckhbw, 0x0f68, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1127 punpckhbw, 0xf68, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1128 punpckhwd, 0x6669, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1129 punpckhwd, 0x0f69, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1130 punpckhwd, 0xf69, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1131 punpckhdq, 0x666a, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1132 punpckhdq, 0x0f6a, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1133 punpckhdq, 0xf6a, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1134 punpcklbw, 0x6660, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1135 punpcklbw, 0x0f60, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1136 punpcklbw, 0xf60, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegMMX, RegMMX }
1137 punpcklwd, 0x6661, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1138 punpcklwd, 0x0f61, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1139 punpcklwd, 0xf61, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegMMX, RegMMX }
1140 punpckldq, 0x6662, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1141 punpckldq, 0x0f62, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1142 punpckldq, 0xf62, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegMMX, RegMMX }
1143 pxor, 0x66ef, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1144 pxor, 0x0fef, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1145 pxor, 0xfef, None, 2, CpuMMX, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1146
1147 // SSE instructions.
1148
1149 <sse_frel:imm:comm, eq:0:C, lt:1:, le:2:, unord:3:C, neq:4:C, nlt:5:, nle:6:, ord:7:C>
1150
1151 addps, 0x58, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1152 addps, 0xf58, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1153 addss, 0xf358, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1154 addss, 0x0f58, None, 2, CpuSSE, Prefix_0XF3|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1155 andnps, 0x55, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1156 andnps, 0xf55, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1157 andps, 0x54, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1158 andps, 0xf54, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1159 cmp<sse_frel>ps, 0xc2, <sse_frel:imm>, 1, CpuAVX, Modrm|<sse_frel:comm>|Vex128|OpcodePrefix=0|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1160 cmp<sse_frel>ps, 0xfc2, <sse_frel:imm>, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
1161 cmp<sse_frel>ss, 0xf3c2, <sse_frel:imm>, 1, CpuAVX, Modrm|<sse_frel:comm>|VexLIG|OpcodePrefix=0|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM }
1162 cmp<sse_frel>ss, 0x0fc2, <sse_frel:imm>, 2, CpuSSE, Prefix_0XF3|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM }
1163 cmpps, 0xc2, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1164 cmpps, 0xfc2, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1165 cmpss, 0xf3c2, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1166 cmpss, 0x0fc2, None, 2, CpuSSE, Prefix_0XF3|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1167 comiss, 0x2f, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1168 comiss, 0xf2f, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1169 cvtpi2ps, 0xf2a, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegXMM }
1170 cvtps2pi, 0xf2d, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|NoAVX, { Qword|Unspecified|BaseIndex|RegXMM, RegMMX }
1171 cvtsi2ss, 0xf32a, None, 1, CpuAVX|CpuNo64, Modrm|Vex=3|OpcodePrefix=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Reg32|Dword|Unspecified|BaseIndex, RegXMM }
1172 cvtsi2ss, 0xf32a, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|OpcodePrefix=0|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX|ATTSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM }
1173 cvtsi2ss, 0xf32a, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|OpcodePrefix=0|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX|IntelSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM }
1174 cvtsi2ss, 0x0f2a, None, 2, CpuSSE|CpuNo64, Prefix_0XF3|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex, RegXMM }
1175 cvtsi2ss, 0x0f2a, None, 2, CpuSSE|Cpu64, Prefix_0XF3|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ATTSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM }
1176 cvtsi2ss, 0x0f2a, None, 2, CpuSSE|Cpu64, Prefix_0XF3|Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|IntelSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM }
1177 cvtss2si, 0xf32d, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToQword|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 }
1178 cvtss2si, 0x0f2d, None, 2, CpuSSE, Prefix_0XF3|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToQword, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 }
1179 cvttps2pi, 0xf2c, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|NoAVX, { Qword|Unspecified|BaseIndex|RegXMM, RegMMX }
1180 cvttss2si, 0xf32c, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToQword|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 }
1181 cvttss2si, 0x0f2c, None, 2, CpuSSE, Prefix_0XF3|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToQword, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 }
1182 divps, 0x5e, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1183 divps, 0xf5e, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1184 divss, 0xf35e, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1185 divss, 0x0f5e, None, 2, CpuSSE, Prefix_0XF3|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1186 ldmxcsr, 0xae, 0x2, 1, CpuAVX, Modrm|Vex128|OpcodePrefix=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex }
1187 ldmxcsr, 0xfae, 0x2, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Dword|Unspecified|BaseIndex }
1188 maskmovq, 0xff7, None, 2, CpuSSE|Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { RegMMX, RegMMX }
1189 maxps, 0x5f, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1190 maxps, 0xf5f, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1191 maxss, 0xf35f, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1192 maxss, 0x0f5f, None, 2, CpuSSE, Prefix_0XF3|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1193 minps, 0x5d, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1194 minps, 0xf5d, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1195 minss, 0xf35d, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1196 minss, 0x0f5d, None, 2, CpuSSE, Prefix_0XF3|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1197 movaps, 0x28, None, 1, CpuAVX, D|Modrm|Vex|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1198 movaps, 0xf28, None, 2, CpuSSE, D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1199 movhlps, 0x12, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM }
1200 movhlps, 0xf12, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM }
1201 movhps, 0x16, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM }
1202 movhps, 0x17, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex }
1203 movhps, 0xf16, None, 2, CpuSSE, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
1204 movlhps, 0x16, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM }
1205 movlhps, 0xf16, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM }
1206 movlps, 0x12, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM }
1207 movlps, 0x13, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex }
1208 movlps, 0xf12, None, 2, CpuSSE, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
1209 movmskps, 0x50, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexW0|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX, { RegXMM, Reg32|Reg64 }
1210 movmskps, 0xf50, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM, Reg32|Reg64 }
1211 movntps, 0x2b, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex }
1212 movntps, 0xf2b, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex }
1213 movntq, 0xfe7, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { RegMMX, Qword|Unspecified|BaseIndex }
1214 movntdq, 0x66e7, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex }
1215 movntdq, 0x0fe7, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex }
1216 movss, 0xf310, None, 1, CpuAVX, D|Modrm|Vex=3|OpcodePrefix=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex, RegXMM }
1217 movss, 0xf310, None, 1, CpuAVX, D|Modrm|Vex=3|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM }
1218 movss, 0x0f10, None, 2, CpuSSE, Prefix_0XF3|D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1219 movups, 0x10, None, 1, CpuAVX, D|Modrm|Vex|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1220 movups, 0xf10, None, 2, CpuSSE, D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1221 mulps, 0x59, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1222 mulps, 0xf59, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1223 mulss, 0xf359, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1224 mulss, 0x0f59, None, 2, CpuSSE, Prefix_0XF3|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1225 orps, 0x56, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1226 orps, 0xf56, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1227 pavgb, 0xfe0, None, 2, CpuSSE|Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1228 pavgb, 0x66e0, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1229 pavgb, 0x0fe0, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1230 pavgw, 0xfe3, None, 2, CpuSSE|Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1231 pavgw, 0x66e3, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1232 pavgw, 0x0fe3, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1233 pextrw, 0x66c5, None, 1, CpuAVX, Load|Modrm|Vex|OpcodePrefix=0|VexW0|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Reg32|Reg64 }
1234 pextrw, 0x6615, None, 1, CpuAVX, RegMem|Vex|OpcodePrefix=2|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Reg32|Reg64 }
1235 pextrw, 0x6615, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Word|Unspecified|BaseIndex }
1236 pextrw, 0x0fc5, None, 2, CpuSSE2, Prefix_0X66|Load|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64 }
1237 pextrw, 0x0f3a15, None, 3, CpuSSE4_1, Prefix_0X66|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64 }
1238 pextrw, 0x0f3a15, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Word|Unspecified|BaseIndex }
1239 pextrw, 0xfc5, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|NoAVX, { Imm8, RegMMX, Reg32|Reg64 }
1240 pinsrw, 0x66c4, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW0|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX, { Imm8, Reg32|Reg64, RegXMM }
1241 pinsrw, 0x66c4, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Word|Unspecified|BaseIndex, RegXMM }
1242 pinsrw, 0x0fc4, None, 2, CpuSSE2, Prefix_0X66|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, Reg32|Reg64, RegXMM }
1243 pinsrw, 0x0fc4, None, 2, CpuSSE2, Prefix_0X66|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Word|Unspecified|BaseIndex, RegXMM }
1244 pinsrw, 0xfc4, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|NoAVX, { Imm8, Reg32|Reg64, RegMMX }
1245 pinsrw, 0xfc4, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Imm8, Word|Unspecified|BaseIndex, RegMMX }
1246 pmaxsw, 0x66ee, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1247 pmaxsw, 0x0fee, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1248 pmaxsw, 0xfee, None, 2, CpuSSE|Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1249 pmaxub, 0x66de, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1250 pmaxub, 0x0fde, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1251 pmaxub, 0xfde, None, 2, CpuSSE|Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1252 pminsw, 0x66ea, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1253 pminsw, 0x0fea, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1254 pminsw, 0xfea, None, 2, CpuSSE|Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1255 pminub, 0x66da, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1256 pminub, 0x0fda, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1257 pminub, 0xfda, None, 2, CpuSSE|Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1258 pmovmskb, 0x66d7, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexW0|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX, { RegXMM, Reg32|Reg64 }
1259 pmovmskb, 0x0fd7, None, 2, CpuSSE2, Prefix_0X66|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM, Reg32|Reg64 }
1260 pmovmskb, 0xfd7, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|NoAVX, { RegMMX, Reg32|Reg64 }
1261 pmulhuw, 0x66e4, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1262 pmulhuw, 0x0fe4, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1263 pmulhuw, 0xfe4, None, 2, CpuSSE|Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1264 prefetchnta, 0xf18, 0x0, 2, CpuSSE|Cpu3dnowA, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { BaseIndex }
1265 prefetcht0, 0xf18, 0x1, 2, CpuSSE|Cpu3dnowA, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { BaseIndex }
1266 prefetcht1, 0xf18, 0x2, 2, CpuSSE|Cpu3dnowA, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { BaseIndex }
1267 prefetcht2, 0xf18, 0x3, 2, CpuSSE|Cpu3dnowA, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { BaseIndex }
1268 psadbw, 0xff6, None, 2, CpuSSE|Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1269 psadbw, 0x66f6, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1270 psadbw, 0x0ff6, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1271 pshufw, 0xf70, None, 2, CpuSSE|Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|NoAVX, { Imm8, Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1272 rcpps, 0x53, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1273 rcpps, 0xf53, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1274 rcpss, 0xf353, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1275 rcpss, 0x0f53, None, 2, CpuSSE, Prefix_0XF3|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1276 rsqrtps, 0x52, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1277 rsqrtps, 0xf52, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1278 rsqrtss, 0xf352, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1279 rsqrtss, 0x0f52, None, 2, CpuSSE, Prefix_0XF3|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1280 sfence, 0xfaef8, None, 3, CpuSSE|Cpu3dnowA, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, {}
1281 shufps, 0xc6, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1282 shufps, 0xfc6, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1283 sqrtps, 0x51, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1284 sqrtps, 0xf51, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1285 sqrtss, 0xf351, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1286 sqrtss, 0x0f51, None, 2, CpuSSE, Prefix_0XF3|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1287 stmxcsr, 0xae, 0x3, 1, CpuAVX, Modrm|Vex128|OpcodePrefix=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex }
1288 stmxcsr, 0xfae, 0x3, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Dword|Unspecified|BaseIndex }
1289 subps, 0x5c, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1290 subps, 0xf5c, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1291 subss, 0xf35c, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1292 subss, 0x0f5c, None, 2, CpuSSE, Prefix_0XF3|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1293 ucomiss, 0x2e, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1294 ucomiss, 0xf2e, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1295 unpckhps, 0x15, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1296 unpckhps, 0xf15, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1297 unpcklps, 0x14, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1298 unpcklps, 0xf14, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1299 xorps, 0x57, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1300 xorps, 0xf57, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1301
1302 // SSE2 instructions.
1303
1304 addpd, 0x6658, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1305 addpd, 0x0f58, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1306 addsd, 0xf258, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1307 addsd, 0x0f58, None, 2, CpuSSE2, Prefix_0XF2|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1308 andnpd, 0x6655, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1309 andnpd, 0x0f55, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1310 andpd, 0x6654, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1311 andpd, 0x0f54, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1312 cmp<sse_frel>pd, 0x66c2, <sse_frel:imm>, 1, CpuAVX, Modrm|<sse_frel:comm>|Vex|OpcodePrefix=0|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1313 cmp<sse_frel>pd, 0x0fc2, <sse_frel:imm>, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
1314 cmp<sse_frel>sd, 0xf2c2, <sse_frel:imm>, 1, CpuAVX, Modrm|<sse_frel:comm>|VexLIG|OpcodePrefix=0|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
1315 cmp<sse_frel>sd, 0x0fc2, <sse_frel:imm>, 2, CpuSSE2, Prefix_0XF2|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|NoRex64, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
1316 cmppd, 0x66c2, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1317 cmppd, 0x0fc2, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1318 // Intel mode string compare.
1319 cmpsd, 0xa7, None, 1, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, {}
1320 cmpsd, 0xa7, None, 1, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsStringEsOp0|RepPrefixOk, { Dword|Unspecified|BaseIndex, Dword|Unspecified|BaseIndex }
1321 cmpsd, 0xf2c2, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1322 cmpsd, 0x0fc2, None, 2, CpuSSE2, Prefix_0XF2|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1323 comisd, 0x662f, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1324 comisd, 0x0f2f, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1325 cvtpi2pd, 0x0f2a, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|NoAVX, { RegMMX, RegXMM }
1326 cvtpi2pd, 0xf3e6, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM }
1327 cvtpi2pd, 0x0f2a, None, 2, CpuSSE2, Prefix_0X66|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex, RegXMM }
1328 cvtsi2sd, 0xf22a, None, 1, CpuAVX|CpuNo64, Modrm|Vex=3|OpcodePrefix=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Reg32|Dword|Unspecified|BaseIndex, RegXMM }
1329 cvtsi2sd, 0xf22a, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|OpcodePrefix=0|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX|ATTSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM }
1330 cvtsi2sd, 0xf22a, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|OpcodePrefix=0|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX|IntelSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM }
1331 cvtsi2sd, 0x0f2a, None, 2, CpuSSE2|CpuNo64, Prefix_0XF2|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex, RegXMM }
1332 cvtsi2sd, 0x0f2a, None, 2, CpuSSE2|Cpu64, Prefix_0XF2|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ATTSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM }
1333 cvtsi2sd, 0x0f2a, None, 2, CpuSSE2|Cpu64, Prefix_0XF2|Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|IntelSyntax, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, RegXMM }
1334 divpd, 0x665e, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1335 divpd, 0x0f5e, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1336 divsd, 0xf25e, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1337 divsd, 0x0f5e, None, 2, CpuSSE2, Prefix_0XF2|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1338 maxpd, 0x665f, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1339 maxpd, 0x0f5f, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1340 maxsd, 0xf25f, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1341 maxsd, 0x0f5f, None, 2, CpuSSE2, Prefix_0XF2|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1342 minpd, 0x665d, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1343 minpd, 0x0f5d, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1344 minsd, 0xf25d, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1345 minsd, 0x0f5d, None, 2, CpuSSE2, Prefix_0XF2|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1346 movapd, 0x6628, None, 1, CpuAVX, D|Modrm|Vex|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1347 movapd, 0x0f28, None, 2, CpuSSE2, Prefix_0X66|D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1348 movhpd, 0x6616, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM }
1349 movhpd, 0x6617, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex }
1350 movhpd, 0x0f16, None, 2, CpuSSE2, Prefix_0X66|D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
1351 movlpd, 0x6612, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM }
1352 movlpd, 0x6613, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex }
1353 movlpd, 0x0f12, None, 2, CpuSSE2, Prefix_0X66|D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
1354 movmskpd, 0x6650, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX, { RegXMM, Reg32|Reg64 }
1355 movmskpd, 0x0f50, None, 2, CpuSSE2, Prefix_0X66|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM, Reg32|Reg64 }
1356 movntpd, 0x662b, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex }
1357 movntpd, 0x0f2b, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex }
1358 // Intel mode string move.
1359 movsd, 0xa5, None, 1, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, {}
1360 movsd, 0xa5, None, 1, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsStringEsOp1|RepPrefixOk, { Dword|Unspecified|BaseIndex, Dword|Unspecified|BaseIndex }
1361 movsd, 0xf210, None, 1, CpuAVX, D|Modrm|Vex=3|OpcodePrefix=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM }
1362 movsd, 0xf210, None, 1, CpuAVX, D|Modrm|Vex=3|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM }
1363 movsd, 0x0f10, None, 2, CpuSSE2, Prefix_0XF2|D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1364 movupd, 0x6610, None, 1, CpuAVX, D|Modrm|Vex|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1365 movupd, 0x0f10, None, 2, CpuSSE2, Prefix_0X66|D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1366 mulpd, 0x6659, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1367 mulpd, 0x0f59, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1368 mulsd, 0xf259, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1369 mulsd, 0x0f59, None, 2, CpuSSE2, Prefix_0XF2|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1370 orpd, 0x6656, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1371 orpd, 0x0f56, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1372 shufpd, 0x66c6, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1373 shufpd, 0x0fc6, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1374 sqrtpd, 0x6651, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1375 sqrtpd, 0x0f51, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1376 sqrtsd, 0xf251, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1377 sqrtsd, 0x0f51, None, 2, CpuSSE2, Prefix_0XF2|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1378 subpd, 0x665c, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1379 subpd, 0x0f5c, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1380 subsd, 0xf25c, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1381 subsd, 0x0f5c, None, 2, CpuSSE2, Prefix_0XF2|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1382 ucomisd, 0x662e, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1383 ucomisd, 0x0f2e, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1384 unpckhpd, 0x6615, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1385 unpckhpd, 0x0f15, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1386 unpcklpd, 0x6614, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1387 unpcklpd, 0x0f14, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1388 xorpd, 0x6657, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1389 xorpd, 0xf57, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1390 cvtdq2pd, 0xf3e6, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1391 cvtdq2pd, 0xfe6, None, 2, CpuSSE2, Prefix_0XF3|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1392 cvtpd2dq, 0xf2e6, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1393 cvtpd2dq, 0xfe6, None, 2, CpuSSE2, Prefix_0XF2|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1394 cvtdq2ps, 0x5b, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1395 cvtdq2ps, 0xf5b, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1396 cvtpd2pi, 0x0f2d, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { RegXMM|Unspecified|BaseIndex, RegMMX }
1397 cvtpd2ps, 0x665a, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1398 cvtpd2ps, 0x0f5a, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1399 cvtps2pd, 0x5a, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1400 cvtps2pd, 0xf5a, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1401 cvtps2dq, 0x665b, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1402 cvtps2dq, 0x0f5b, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1403 cvtsd2si, 0xf22d, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToDword|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 }
1404 cvtsd2si, 0x0f2d, None, 2, CpuSSE2, Prefix_0XF2|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToDword, { Qword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 }
1405 cvtsd2ss, 0xf25a, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1406 cvtsd2ss, 0x0f5a, None, 2, CpuSSE2, Prefix_0XF2|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1407 cvtss2sd, 0xf35a, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1408 cvtss2sd, 0x0f5a, None, 2, CpuSSE2, Prefix_0XF3|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1409 cvttpd2pi, 0x0f2c, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { RegXMM|Unspecified|BaseIndex, RegMMX }
1410 cvttsd2si, 0xf22c, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToDword|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 }
1411 cvttsd2si, 0x0f2c, None, 2, CpuSSE2, Prefix_0XF2|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToDword, { Qword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 }
1412 cvttpd2dq, 0x66e6, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1413 cvttpd2dq, 0x0fe6, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1414 cvttps2dq, 0xf35b, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1415 cvttps2dq, 0x0f5b, None, 2, CpuSSE2, Prefix_0XF3|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1416 maskmovdqu, 0x66f7, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM }
1417 maskmovdqu, 0x0ff7, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM }
1418 movdqa, 0x666f, None, 1, CpuAVX, D|Modrm|Vex|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1419 movdqa, 0x0f6f, None, 2, CpuSSE2, Prefix_0X66|D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1420 movdqu, 0xf36f, None, 1, CpuAVX, D|Modrm|Vex|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1421 movdqu, 0x0f6f, None, 2, CpuSSE2, Prefix_0XF3|D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1422 movdq2q, 0x0fd6, None, 2, CpuSSE2, Prefix_0XF2|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { RegXMM, RegMMX }
1423 movq2dq, 0x0fd6, None, 2, CpuSSE2, Prefix_0XF3|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { RegMMX, RegXMM }
1424 pmuludq, 0x66f4, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1425 pmuludq, 0x0ff4, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1426 pmuludq, 0xff4, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1427 pshufd, 0x6670, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1428 pshufd, 0x0f70, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1429 pshufhw, 0xf370, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1430 pshufhw, 0x0f70, None, 2, CpuSSE2, Prefix_0XF3|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1431 pshuflw, 0xf270, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1432 pshuflw, 0x0f70, None, 2, CpuSSE2, Prefix_0XF2|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1433 pslldq, 0x6673, 0x7, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=2|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM }
1434 pslldq, 0x0f73, 0x7, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM }
1435 psrldq, 0x6673, 0x3, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=2|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM }
1436 psrldq, 0x0f73, 0x3, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM }
1437 punpckhqdq, 0x666d, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1438 punpckhqdq, 0x0f6d, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1439 punpcklqdq, 0x666c, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1440 punpcklqdq, 0x0f6c, None, 2, CpuSSE2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1441
1442 // SSE3 instructions.
1443
1444 addsubpd, 0x66d0, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1445 addsubpd, 0x0fd0, None, 2, CpuSSE3, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1446 addsubps, 0xf2d0, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1447 addsubps, 0x0fd0, None, 2, CpuSSE3, Prefix_0XF2|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1448 cmpxchg16b, 0xfc7, 0x1, 2, CpuCX16|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64|LockPrefixOk, { Oword|Unspecified|BaseIndex }
1449 fisttp, 0xdf, 0x1, 1, CpuFISTTP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex }
1450 fisttp, 0xdd, 0x1, 1, CpuFISTTP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex }
1451 fisttpll, 0xdd, 0x1, 1, CpuFISTTP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex }
1452 haddpd, 0x667c, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1453 haddpd, 0x0f7c, None, 2, CpuSSE3, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1454 haddps, 0xf27c, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1455 haddps, 0x0f7c, None, 2, CpuSSE3, Prefix_0XF2|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1456 hsubpd, 0x667d, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1457 hsubpd, 0x0f7d, None, 2, CpuSSE3, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1458 hsubps, 0xf27d, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1459 hsubps, 0x0f7d, None, 2, CpuSSE3, Prefix_0XF2|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1460 lddqu, 0xf2f0, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex, RegXMM }
1461 lddqu, 0x0ff0, None, 2, CpuSSE3, Prefix_0XF2|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex, RegXMM }
1462 monitor, 0xf01c8, None, 3, CpuSSE3, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, {}
1463 // monitor is very special. CX and DX are always 32 bits. The
1464 // address size override prefix can be used to overrride the AX size in
1465 // all modes.
1466 monitor, 0xf01c8, None, 3, CpuSSE3, AddrPrefixOpReg|NoAVX, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword }
1467 // The 64-bit form exists only for compatibility with older gas.
1468 monitor, 0xf01c8, None, 3, CpuSSE3|Cpu64, AddrPrefixOpReg|NoAVX, { Acc|Dword|Qword, RegC|Qword, RegD|Qword }
1469 movddup, 0xf212, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1470 movddup, 0x0f12, None, 2, CpuSSE3, Prefix_0XF2|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1471 movshdup, 0xf316, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1472 movshdup, 0x0f16, None, 2, CpuSSE3, Prefix_0XF3|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1473 movsldup, 0xf312, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1474 movsldup, 0x0f12, None, 2, CpuSSE3, Prefix_0XF3|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1475 mwait, 0xf01c9, None, 3, CpuSSE3, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, {}
1476 // mwait is very special. AX and CX are always 32 bits.
1477 // The 64-bit form exists only for compatibility with older gas.
1478 mwait, 0xf01c9, None, 3, CpuSSE3, CheckRegSize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|NoAVX, { Acc|Dword|Qword, RegC|Dword|Qword }
1479
1480 // VMX instructions.
1481
1482 vmcall, 0xf01c1, None, 3, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
1483 vmclear, 0x0fc7, 0x6, 2, CpuVMX, Prefix_0X66|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex }
1484 vmlaunch, 0xf01c2, None, 3, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
1485 vmresume, 0xf01c3, None, 3, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
1486 vmptrld, 0xfc7, 0x6, 2, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex }
1487 vmptrst, 0xfc7, 0x7, 2, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex }
1488 vmread, 0xf78, None, 2, CpuVMX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, Reg32|Unspecified|BaseIndex }
1489 vmread, 0xf78, None, 2, CpuVMX|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg64, Reg64|Qword|Unspecified|BaseIndex }
1490 vmwrite, 0xf79, None, 2, CpuVMX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, Reg32 }
1491 vmwrite, 0xf79, None, 2, CpuVMX|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg64|Qword|Unspecified|BaseIndex, Reg64 }
1492 vmxoff, 0xf01c4, None, 3, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
1493 vmxon, 0x0fc7, 0x6, 2, CpuVMX, Prefix_0XF3|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex }
1494
1495 // VMFUNC instruction
1496
1497 vmfunc, 0xf01d4, None, 3, CpuVMFUNC, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
1498
1499 // SMX instructions.
1500
1501 getsec, 0xf37, None, 2, CpuSMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
1502
1503 // EPT instructions.
1504
1505 invept, 0x0f3880, None, 3, CpuEPT|CpuNo64, Prefix_0X66|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf, { Oword|Unspecified|BaseIndex, Reg32 }
1506 invept, 0x0f3880, None, 3, CpuEPT|Cpu64, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 }
1507 invvpid, 0x0f3881, None, 3, CpuEPT|CpuNo64, Prefix_0X66|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf, { Oword|Unspecified|BaseIndex, Reg32 }
1508 invvpid, 0x0f3881, None, 3, CpuEPT|Cpu64, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 }
1509
1510 // INVPCID instruction
1511
1512 invpcid, 0x0f3882, None, 3, CpuINVPCID|CpuNo64, Prefix_0X66|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf, { Oword|Unspecified|BaseIndex, Reg32 }
1513 invpcid, 0x0f3882, None, 3, CpuINVPCID|Cpu64, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 }
1514
1515 // SSSE3 instructions.
1516
1517 phaddw, 0x6601, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1518 phaddw, 0x0f3801, None, 3, CpuSSSE3, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1519 phaddw, 0xf3801, None, 3, CpuSSSE3, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1520 phaddd, 0x6602, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1521 phaddd, 0x0f3802, None, 3, CpuSSSE3, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1522 phaddd, 0xf3802, None, 3, CpuSSSE3, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1523 phaddsw, 0x6603, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1524 phaddsw, 0x0f3803, None, 3, CpuSSSE3, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1525 phaddsw, 0xf3803, None, 3, CpuSSSE3, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1526 phsubw, 0x6605, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1527 phsubw, 0x0f3805, None, 3, CpuSSSE3, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1528 phsubw, 0xf3805, None, 3, CpuSSSE3, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1529 phsubd, 0x6606, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1530 phsubd, 0x0f3806, None, 3, CpuSSSE3, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1531 phsubd, 0xf3806, None, 3, CpuSSSE3, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1532 phsubsw, 0x6607, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1533 phsubsw, 0x0f3807, None, 3, CpuSSSE3, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1534 phsubsw, 0xf3807, None, 3, CpuSSSE3, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1535 pmaddubsw, 0x6604, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1536 pmaddubsw, 0x0f3804, None, 3, CpuSSSE3, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1537 pmaddubsw, 0xf3804, None, 3, CpuSSSE3, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1538 pmulhrsw, 0x660b, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1539 pmulhrsw, 0x0f380b, None, 3, CpuSSSE3, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1540 pmulhrsw, 0xf380b, None, 3, CpuSSSE3, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1541 pshufb, 0x6600, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1542 pshufb, 0x0f3800, None, 3, CpuSSSE3, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1543 pshufb, 0xf3800, None, 3, CpuSSSE3, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1544 psignb, 0x6608, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1545 psignb, 0x0f3808, None, 3, CpuSSSE3, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1546 psignb, 0xf3808, None, 3, CpuSSSE3, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1547 psignw, 0x6609, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1548 psignw, 0x0f3809, None, 3, CpuSSSE3, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1549 psignw, 0xf3809, None, 3, CpuSSSE3, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1550 psignd, 0x660a, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1551 psignd, 0x0f380a, None, 3, CpuSSSE3, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1552 psignd, 0xf380a, None, 3, CpuSSSE3, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1553 palignr, 0x660f, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1554 palignr, 0x0f3a0f, None, 3, CpuSSSE3, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1555 palignr, 0xf3a0f, None, 3, CpuSSSE3, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|NoAVX, { Imm8, Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1556 pabsb, 0x661c, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1557 pabsb, 0x0f381c, None, 3, CpuSSSE3, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1558 pabsb, 0xf381c, None, 3, CpuSSSE3, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1559 pabsw, 0x661d, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1560 pabsw, 0x0f381d, None, 3, CpuSSSE3, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1561 pabsw, 0xf381d, None, 3, CpuSSSE3, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1562 pabsd, 0x661e, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1563 pabsd, 0x0f381e, None, 3, CpuSSSE3, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1564 pabsd, 0xf381e, None, 3, CpuSSSE3, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
1565
1566 // SSE4.1 instructions.
1567
1568 blendpd, 0x660d, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1569 blendpd, 0x0f3a0d, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1570 blendps, 0x660c, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1571 blendps, 0x0f3a0c, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1572 blendvpd, 0x664b, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM }
1573 blendvpd, 0x664b, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Implicit1stXmm0|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1574 blendvpd, 0x0f3815, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM }
1575 blendvpd, 0x0f3815, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1576 blendvps, 0x664a, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM }
1577 blendvps, 0x664a, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Implicit1stXmm0|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1578 blendvps, 0x0f3814, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM }
1579 blendvps, 0x0f3814, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1580 dppd, 0x6641, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1581 dppd, 0x0f3a41, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1582 dpps, 0x6640, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1583 dpps, 0x0f3a40, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1584 extractps, 0x6617, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex }
1585 extractps, 0x6617, None, 1, CpuAVX|Cpu64, RegMem|Vex|OpcodePrefix=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Reg64 }
1586 extractps, 0x0f3a17, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex }
1587 extractps, 0x0f3a17, None, 3, CpuSSE4_1|Cpu64, Prefix_0X66|RegMem|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg64 }
1588 insertps, 0x6621, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1589 insertps, 0x0f3a21, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1590 movntdqa, 0x662a, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex, RegXMM }
1591 movntdqa, 0x0f382a, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex, RegXMM }
1592 mpsadbw, 0x6642, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1593 mpsadbw, 0x0f3a42, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1594 packusdw, 0x662b, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1595 packusdw, 0x0f382b, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1596 pblendvb, 0x664c, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM }
1597 pblendvb, 0x664c, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Implicit1stXmm0|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1598 pblendvb, 0x0f3810, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM }
1599 pblendvb, 0x0f3810, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1600 pblendw, 0x660e, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1601 pblendw, 0x0f3a0e, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1602 pcmpeqq, 0x6629, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1603 pcmpeqq, 0x0f3829, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1604 pextrb, 0x6614, None, 1, CpuAVX, RegMem|Vex|OpcodePrefix=2|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Reg32|Reg64 }
1605 pextrb, 0x6614, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Byte|Unspecified|BaseIndex }
1606 pextrb, 0x0f3a14, None, 3, CpuSSE4_1, Prefix_0X66|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64 }
1607 pextrb, 0x0f3a14, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Byte|Unspecified|BaseIndex }
1608 pextrd, 0x6616, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex }
1609 pextrd, 0x0f3a16, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex }
1610 pextrq, 0x6616, None, 1, CpuAVX|Cpu64, Modrm|Vex|OpcodePrefix=2|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Reg64|Unspecified|BaseIndex }
1611 pextrq, 0x0f3a16, None, 3, CpuSSE4_1|Cpu64, Prefix_0X66|Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg64|Unspecified|BaseIndex }
1612 phminposuw, 0x6641, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1613 phminposuw, 0x0f3841, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1614 pinsrb, 0x6620, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Reg32|Reg64, RegXMM }
1615 pinsrb, 0x6620, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Byte|Unspecified|BaseIndex, RegXMM }
1616 pinsrb, 0x0f3a20, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, Reg32|Reg64, RegXMM }
1617 pinsrb, 0x0f3a20, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Byte|Unspecified|BaseIndex, RegXMM }
1618 pinsrd, 0x6622, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Reg32|Dword|Unspecified|BaseIndex, RegXMM }
1619 pinsrd, 0x0f3a22, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Dword|Unspecified|BaseIndex, RegXMM }
1620 pinsrq, 0x6622, None, 1, CpuAVX|Cpu64, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Reg64|Unspecified|BaseIndex, RegXMM }
1621 pinsrq, 0x0f3a22, None, 3, CpuSSE4_1|Cpu64, Prefix_0X66|Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg64|Unspecified|BaseIndex, RegXMM }
1622 pmaxsb, 0x663c, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1623 pmaxsb, 0x0f383c, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1624 pmaxsd, 0x663d, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1625 pmaxsd, 0x0f383d, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1626 pmaxud, 0x663f, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1627 pmaxud, 0x0f383f, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1628 pmaxuw, 0x663e, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1629 pmaxuw, 0x0f383e, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1630 pminsb, 0x6638, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1631 pminsb, 0x0f3838, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1632 pminsd, 0x6639, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1633 pminsd, 0x0f3839, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1634 pminud, 0x663b, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1635 pminud, 0x0f383b, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1636 pminuw, 0x663a, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1637 pminuw, 0x0f383a, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1638 pmovsxbw, 0x6620, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1639 pmovsxbw, 0x0f3820, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { QWord|Unspecified|BaseIndex|RegXMM, RegXMM }
1640 pmovsxbd, 0x6621, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1641 pmovsxbd, 0x0f3821, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1642 pmovsxbq, 0x6622, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Word|Unspecified|BaseIndex|RegXMM, RegXMM }
1643 pmovsxbq, 0x0f3822, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex|RegXMM, RegXMM }
1644 pmovsxwd, 0x6623, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1645 pmovsxwd, 0x0f3823, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1646 pmovsxwq, 0x6624, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1647 pmovsxwq, 0x0f3824, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1648 pmovsxdq, 0x6625, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1649 pmovsxdq, 0x0f3825, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { QWord|Unspecified|BaseIndex|RegXMM, RegXMM }
1650 pmovzxbw, 0x6630, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1651 pmovzxbw, 0x0f3830, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1652 pmovzxbd, 0x6631, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1653 pmovzxbd, 0x0f3831, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1654 pmovzxbq, 0x6632, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Word|Unspecified|BaseIndex|RegXMM, RegXMM }
1655 pmovzxbq, 0x0f3832, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex|RegXMM, RegXMM }
1656 pmovzxwd, 0x6633, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1657 pmovzxwd, 0x0f3833, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1658 pmovzxwq, 0x6634, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1659 pmovzxwq, 0x0f3834, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1660 pmovzxdq, 0x6635, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1661 pmovzxdq, 0x0f3835, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { QWord|Unspecified|BaseIndex|RegXMM, RegXMM }
1662 pmuldq, 0x6628, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1663 pmuldq, 0x0f3828, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1664 pmulld, 0x6640, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1665 pmulld, 0x0f3840, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1666 ptest, 0x6617, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1667 ptest, 0x0f3817, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1668 roundpd, 0x6609, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1669 roundpd, 0x0f3a09, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1670 roundps, 0x6608, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1671 roundps, 0x0f3a08, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1672 roundsd, 0x660b, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=2|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1673 roundsd, 0x0f3a0b, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1674 roundss, 0x660a, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1675 roundss, 0x0f3a0a, None, 3, CpuSSE4_1, Prefix_0X66|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1676
1677 // SSE4.2 instructions.
1678
1679 pcmpgtq, 0x6637, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1680 pcmpgtq, 0x0f3837, None, 3, CpuSSE4_2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1681 pcmpestri, 0x6661, None, 1, CpuAVX|CpuNo64, Modrm|Vex|OpcodePrefix=2|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1682 pcmpestri, 0x6661, None, 1, CpuAVX|Cpu64, Modrm|Vex|OpcodePrefix=2|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
1683 pcmpestri, 0x0f3a61, None, 3, CpuSSE4_2|CpuNo64, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1684 pcmpestri, 0x0f3a61, None, 3, CpuSSE4_2|Cpu64, Prefix_0X66|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
1685 pcmpestrm, 0x6660, None, 1, CpuAVX|CpuNo64, Modrm|Vex|OpcodePrefix=2|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1686 pcmpestrm, 0x6660, None, 1, CpuAVX|Cpu64, Modrm|Vex|OpcodePrefix=2|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
1687 pcmpestrm, 0x0f3a60, None, 3, CpuSSE4_2|CpuNo64, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1688 pcmpestrm, 0x0f3a60, None, 3, CpuSSE4_2|Cpu64, Prefix_0X66|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
1689 pcmpistri, 0x6663, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1690 pcmpistri, 0x0f3a63, None, 3, CpuSSE4_2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1691 pcmpistrm, 0x6662, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1692 pcmpistrm, 0x0f3a62, None, 3, CpuSSE4_2, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1693 crc32, 0x0f38f0, None, 3, CpuSSE4_2, Prefix_0XF2|W|Modrm|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Reg8|Reg16|Reg32|Unspecified|BaseIndex, Reg32 }
1694 crc32, 0x0f38f0, None, 3, CpuSSE4_2|Cpu64, Prefix_0XF2|W|Modrm|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoAVX, { Reg8|Reg64|Unspecified|BaseIndex, Reg64 }
1695
1696 // xsave/xrstor New Instructions.
1697
1698 xsave, 0xfae, 0x4, 2, CpuXsave, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex }
1699 xsave64, 0xfae, 0x4, 2, CpuXsave|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Unspecified|BaseIndex }
1700 xrstor, 0xfae, 0x5, 2, CpuXsave, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex }
1701 xrstor64, 0xfae, 0x5, 2, CpuXsave|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Unspecified|BaseIndex }
1702 xgetbv, 0xf01d0, None, 3, CpuXsave, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
1703 xsetbv, 0xf01d1, None, 3, CpuXsave, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
1704
1705 // xsaveopt
1706 xsaveopt, 0xfae, 0x6, 2, CpuXsaveopt, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex }
1707 xsaveopt64, 0xfae, 0x6, 2, CpuXsaveopt|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Unspecified|BaseIndex }
1708
1709 // AES instructions.
1710
1711 aesdec, 0x66de, None, 1, CpuAVX|CpuAES, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1712 aesdec, 0x0f38de, None, 3, CpuAES, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1713 aesdeclast, 0x66df, None, 1, CpuAVX|CpuAES, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1714 aesdeclast, 0x0f38df, None, 3, CpuAES, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1715 aesenc, 0x66dc, None, 1, CpuAVX|CpuAES, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1716 aesenc, 0x0f38dc, None, 3, CpuAES, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1717 aesenclast, 0x66dd, None, 1, CpuAVX|CpuAES, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1718 aesenclast, 0x0f38dd, None, 3, CpuAES, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1719 aesimc, 0x66db, None, 1, CpuAVX|CpuAES, Modrm|Vex|OpcodePrefix=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1720 aesimc, 0x0f38db, None, 3, CpuAES, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1721 aeskeygenassist, 0x66df, None, 1, CpuAVX|CpuAES, Modrm|Vex|OpcodePrefix=2|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1722 aeskeygenassist, 0x0f3adf, None, 3, CpuAES, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1723
1724 // VAES
1725
1726 vaesdec, 0x66de, None, 1, CpuVAES, Modrm|Vex=2|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Unspecified|BaseIndex, RegYMM, RegYMM }
1727 vaesdeclast, 0x66df, None, 1, CpuVAES, Modrm|Vex=2|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Unspecified|BaseIndex, RegYMM, RegYMM }
1728 vaesenc, 0x66dc, None, 1, CpuVAES, Modrm|Vex=2|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Unspecified|BaseIndex, RegYMM, RegYMM }
1729 vaesenclast, 0x66dd, None, 1, CpuVAES, Modrm|Vex=2|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Unspecified|BaseIndex, RegYMM, RegYMM }
1730
1731 // PCLMUL
1732
1733 pclmulqdq, 0x6644, None, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1734 pclmulqdq, 0x0f3a44, None, 3, CpuPCLMUL, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1735 pclmullqlqdq, 0x6644, 0x0, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1736 pclmullqlqdq, 0x0f3a44, 0x0, 3, CpuPCLMUL, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
1737 pclmulhqlqdq, 0x6644, 0x1, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1738 pclmulhqlqdq, 0x0f3a44, 0x1, 3, CpuPCLMUL, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
1739 pclmullqhqdq, 0x6644, 0x10, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1740 pclmullqhqdq, 0x0f3a44, 0x10, 3, CpuPCLMUL, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
1741 pclmulhqhqdq, 0x6644, 0x11, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1742 pclmulhqhqdq, 0x0f3a44, 0x11, 3, CpuPCLMUL, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
1743
1744 // GFNI
1745
1746 gf2p8affineqb, 0x66ce, None, 1, CpuAVX|CpuGFNI, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1747 gf2p8affineqb, 0x0f3ace, None, 3, CpuGFNI, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1748 gf2p8affineinvqb, 0x66cf, None, 1, CpuAVX|CpuGFNI, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1749 gf2p8affineinvqb, 0x0f3acf, None, 3, CpuGFNI, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
1750 gf2p8mulb, 0x66cf, None, 1, CpuAVX|CpuGFNI, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM }
1751 gf2p8mulb, 0x0f38cf, None, 3, CpuGFNI, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
1752
1753 // AVX instructions.
1754
1755 <avx_frel:imm:comm, eq:00:C, eq_oq:00:C, lt:01:, lt_os:01:, le:02:, le_os:02:, \
1756     unord:03:C, unord_q:03:C, neq:04:C, neq_uq:04:C, nlt:05:, nlt_us:05:, \
1757     nle:06:, nle_us:06:, ord:07:C, ord_q:07:C, eq_uq:08:C, \
1758     nge:09:, nge_us:09:, ngt:0a:, ngt_us:0a:, false:0b:C, false_oq:0b:C, \
1759     neq_oq:0c:C, ge:0d:, ge_os:0d:, gt:0e:, gt_os:0e:, true:0f:C, \
1760     true_uq:0f:C, eq_os:10:C, lt_oq:11:, le_oq:12:, \
1761     unord_s:13:C, neq_us:14:C, nlt_uq:15:, nle_uq:16:, ord_s:17:C, eq_us:18:C, \
1762     nge_uq:19:, ngt_uq:1a:, false_os:1b:C, neq_os:1c:C, ge_oq:1d:, gt_oq:1e:, \
1763     true_us:1f:C>
1764
1765 vaddpd, 0x6658, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
1766 vaddps, 0x58, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
1767 vaddsd, 0xf258, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1768 vaddss, 0xf358, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1769 vaddsubpd, 0x66d0, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
1770 vaddsubps, 0xf2d0, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
1771 vandnpd, 0x6655, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
1772 vandnps, 0x55, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
1773 vandpd, 0x6654, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
1774 vandps, 0x54, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
1775 vblendpd, 0x660d, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
1776 vblendps, 0x660c, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
1777 vblendvpd, 0x664b, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=1|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
1778 vblendvps, 0x664a, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=1|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
1779 vbroadcastf128, 0x661a, None, 1, CpuAVX, Modrm|Vex=2|OpcodePrefix=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex, RegYMM }
1780 vbroadcastsd, 0x6619, None, 1, CpuAVX, Modrm|Vex=2|OpcodePrefix=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegYMM }
1781 vbroadcastss, 0x6618, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM|RegYMM }
1782 vcmp<avx_frel>pd, 0x66c2, 0x<avx_frel:imm>, 1, CpuAVX, Modrm|<avx_frel:comm>|Vex|OpcodePrefix=0|VexVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
1783 vcmp<avx_frel>ps, 0xc2, 0x<avx_frel:imm>, 1, CpuAVX, Modrm|<avx_frel:comm>|Vex|OpcodePrefix=0|VexVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
1784 vcmp<avx_frel>sd, 0xf2c2, 0x<avx_frel:imm>, 1, CpuAVX, Modrm|<avx_frel:comm>|VexLIG|OpcodePrefix=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
1785 vcmp<avx_frel>ss, 0xf3c2, 0x<avx_frel:imm>, 1, CpuAVX, Modrm|<avx_frel:comm>|VexLIG|OpcodePrefix=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
1786 vcmppd, 0x66c2, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
1787 vcmpps, 0xc2, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
1788 vcmpsd, 0xf2c2, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1789 vcmpss, 0xf3c2, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1790 vcomisd, 0x662f, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1791 vcomiss, 0x2f, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1792 vcvtdq2pd, 0xf3e6, None, 1, CpuAVX, Modrm|Vex128|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
1793 vcvtdq2pd, 0xf3e6, None, 1, CpuAVX, Modrm|Vex256|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegYMM }
1794 vcvtdq2ps, 0x5b, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
1795 vcvtpd2dq, 0xf2e6, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM }
1796 vcvtpd2dq, 0xf2e6, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|RegYMM, RegXMM }
1797 vcvtpd2dqx, 0xf2e6, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex|RegXMM, RegXMM }
1798 vcvtpd2dqy, 0xf2e6, None, 1, CpuAVX, Modrm|Vex=2|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex|RegYMM, RegXMM }
1799 vcvtpd2ps, 0x665a, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM }
1800 vcvtpd2ps, 0x665a, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|RegYMM, RegXMM }
1801 vcvtpd2psx, 0x665a, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex|RegXMM, RegXMM }
1802 vcvtpd2psy, 0x665a, None, 1, CpuAVX, Modrm|Vex=2|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Unspecified|BaseIndex|RegYMM, RegXMM }
1803 vcvtps2dq, 0x665b, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
1804 vcvtps2pd, 0x5a, None, 1, CpuAVX, Modrm|Vex128|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
1805 vcvtps2pd, 0x5a, None, 1, CpuAVX, Modrm|Vex256|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegYMM }
1806 vcvtsd2si, 0xf22d, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToDword, { Qword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 }
1807 vcvtsd2ss, 0xf25a, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1808 vcvtsi2sd, 0xf22a, None, 1, CpuAVX, Modrm|VexLIG|OpcodePrefix=0|VexVVVV|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
1809 vcvtsi2sd, 0xf22a, None, 1, CpuAVX, Modrm|VexLIG|OpcodePrefix=0|VexVVVV|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
1810 vcvtsi2ss, 0xf32a, None, 1, CpuAVX, Modrm|VexLIG|OpcodePrefix=0|VexVVVV|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
1811 vcvtsi2ss, 0xf32a, None, 1, CpuAVX, Modrm|VexLIG|OpcodePrefix=0|VexVVVV|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
1812 vcvtss2sd, 0xf35a, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1813 vcvtss2si, 0xf32d, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToQword, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 }
1814 vcvttpd2dq, 0x66e6, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM }
1815 vcvttpd2dq, 0x66e6, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|RegYMM, RegXMM }
1816 vcvttpd2dqx, 0x66e6, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTsyntax, { Unspecified|BaseIndex|RegXMM, RegXMM }
1817 vcvttpd2dqy, 0x66e6, None, 1, CpuAVX, Modrm|Vex=2|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTsyntax, { Unspecified|BaseIndex|RegYMM, RegXMM }
1818 vcvttps2dq, 0xf35b, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
1819 vcvttsd2si, 0xf22c, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToDword, { Qword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 }
1820 vcvttss2si, 0xf32c, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToQword, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 }
1821 vdivpd, 0x665e, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
1822 vdivps, 0x5e, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
1823 vdivsd, 0xf25e, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1824 vdivss, 0xf35e, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1825 vdppd, 0x6641, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1826 vdpps, 0x6640, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
1827 vextractf128, 0x6619, None, 1, CpuAVX, Modrm|Vex=2|OpcodePrefix=2|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM }
1828 vextractps, 0x6617, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex }
1829 vextractps, 0x6617, None, 1, CpuAVX|Cpu64, RegMem|Vex|OpcodePrefix=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg64 }
1830 vhaddpd, 0x667c, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
1831 vhaddps, 0xf27c, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
1832 vhsubpd, 0x667d, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
1833 vhsubps, 0xf27d, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
1834 vinsertf128, 0x6618, None, 1, CpuAVX, Modrm|Vex=2|OpcodePrefix=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegYMM, RegYMM }
1835 vinsertps, 0x6621, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1836 vlddqu, 0xf2f0, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM }
1837 vldmxcsr, 0xae, 0x2, 1, CpuAVX, Modrm|Vex128|OpcodePrefix=0|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex }
1838 vmaskmovdqu, 0x66f7, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM }
1839 vmaskmovpd, 0x662f, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex }
1840 vmaskmovpd, 0x662d, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
1841 vmaskmovps, 0x662e, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex }
1842 vmaskmovps, 0x662c, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
1843 vmaxpd, 0x665f, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
1844 vmaxps, 0x5f, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
1845 vmaxsd, 0xf25f, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1846 vmaxss, 0xf35f, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1847 vminpd, 0x665d, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
1848 vminps, 0x5d, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
1849 vminsd, 0xf25d, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1850 vminss, 0xf35d, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1851 vmovapd, 0x6628, None, 1, CpuAVX, D|Modrm|Vex|OpcodePrefix=0|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
1852 vmovaps, 0x28, None, 1, CpuAVX, D|Modrm|Vex|OpcodePrefix=0|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
1853 // vmovd really shouldn't allow for 64bit operand (vmovq is the right
1854 // mnemonic for copying between Reg64/Mem64 and RegXMM, as is mandated
1855 // by Intel AVX spec).  To avoid extra template in gcc x86 backend and
1856 // support assembler for AMD64, we accept 64bit operand on vmovd so
1857 // that we can use one template for both SSE and AVX instructions.
1858 vmovd, 0x666e, None, 1, CpuAVX, D|Modrm|Vex=1|OpcodePrefix=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, RegXMM }
1859 vmovd, 0x667e, None, 1, CpuAVX|Cpu64, D|RegMem|Vex=1|OpcodePrefix=0|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { RegXMM, Reg64 }
1860 vmovddup, 0xf212, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1861 vmovddup, 0xf212, None, 1, CpuAVX, Modrm|Vex=2|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM }
1862 vmovdqa, 0x666f, None, 1, CpuAVX, D|Modrm|Vex|OpcodePrefix=0|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
1863 vmovdqu, 0xf36f, None, 1, CpuAVX, D|Modrm|Vex|OpcodePrefix=0|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
1864 vmovhlps, 0x12, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
1865 vmovhpd, 0x6616, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
1866 vmovhpd, 0x6617, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex }
1867 vmovhps, 0x16, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
1868 vmovhps, 0x17, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex }
1869 vmovlhps, 0x16, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
1870 vmovlpd, 0x6612, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
1871 vmovlpd, 0x6613, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex }
1872 vmovlps, 0x12, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
1873 vmovlps, 0x13, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex }
1874 vmovmskpd, 0x6650, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { RegXMM|RegYMM, Reg32|Reg64 }
1875 vmovmskps, 0x50, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { RegXMM|RegYMM, Reg32|Reg64 }
1876 vmovntdq, 0x66e7, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex }
1877 vmovntdqa, 0x662a, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex, RegXMM }
1878 vmovntpd, 0x662b, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex }
1879 vmovntps, 0x2b, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex }
1880 vmovq, 0xf37e, None, 1, CpuAVX, Load|Modrm|Vex=1|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1881 vmovq, 0x66d6, None, 1, CpuAVX, Modrm|Vex=1|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM }
1882 vmovq, 0x666e, None, 1, CpuAVX|Cpu64, D|Modrm|Vex=1|OpcodePrefix=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Unspecified|BaseIndex, RegXMM }
1883 vmovsd, 0xf210, None, 1, CpuAVX, D|Modrm|Vex=3|OpcodePrefix=0|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
1884 vmovsd, 0xf210, None, 1, CpuAVX, D|Modrm|Vex=3|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
1885 vmovshdup, 0xf316, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
1886 vmovsldup, 0xf312, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
1887 vmovss, 0xf310, None, 1, CpuAVX, D|Modrm|Vex=3|OpcodePrefix=0|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM }
1888 vmovss, 0xf310, None, 1, CpuAVX, D|Modrm|Vex=3|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
1889 vmovupd, 0x6610, None, 1, CpuAVX, D|Modrm|Vex|OpcodePrefix=0|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
1890 vmovups, 0x10, None, 1, CpuAVX, D|Modrm|Vex|OpcodePrefix=0|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
1891 vmpsadbw, 0x6642, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1892 vmulpd, 0x6659, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
1893 vmulps, 0x59, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
1894 vmulsd, 0xf259, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1895 vmulss, 0xf359, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1896 vorpd, 0x6656, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
1897 vorps, 0x56, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
1898 vpabsb, 0x661c, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM }
1899 vpabsd, 0x661e, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM }
1900 vpabsw, 0x661d, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM }
1901 vpackssdw, 0x666b, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1902 vpacksswb, 0x6663, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1903 vpackusdw, 0x662b, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1904 vpackuswb, 0x6667, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1905 vpaddsb, 0x66ec, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1906 vpaddsw, 0x66ed, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1907 vpaddb, 0x66fc, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1908 vpaddd, 0x66fe, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1909 vpaddq, 0x66d4, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1910 vpaddw, 0x66fd, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1911 vpaddusb, 0x66dc, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1912 vpaddusw, 0x66dd, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1913 vpalignr, 0x660f, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1914 vpand, 0x66db, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1915 vpandn, 0x66df, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1916 vpavgb, 0x66e0, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1917 vpavgw, 0x66e3, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1918 vpblendvb, 0x664c, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1919 vpblendw, 0x660e, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1920 vpcmpeqb, 0x6674, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1921 vpcmpeqd, 0x6676, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1922 vpcmpeqq, 0x6629, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1923 vpcmpeqw, 0x6675, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1924 vpcmpestri, 0x6661, None, 1, CpuAVX|CpuNo64, Modrm|Vex|OpcodePrefix=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM }
1925 vpcmpestri, 0x6661, None, 1, CpuAVX|Cpu64, Modrm|Vex|OpcodePrefix=2|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
1926 vpcmpestrm, 0x6660, None, 1, CpuAVX|CpuNo64, Modrm|Vex|OpcodePrefix=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM }
1927 vpcmpestrm, 0x6660, None, 1, CpuAVX|Cpu64, Modrm|Vex|OpcodePrefix=2|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
1928 vpcmpgtb, 0x6664, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1929 vpcmpgtd, 0x6666, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1930 vpcmpgtq, 0x6637, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1931 vpcmpgtw, 0x6665, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1932 vpcmpistri, 0x6663, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM }
1933 vpcmpistrm, 0x6662, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM }
1934 vperm2f128, 0x6606, None, 1, CpuAVX, Modrm|Vex=2|OpcodePrefix=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
1935 vpermilpd, 0x660d, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
1936 vpermilpd, 0x6605, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
1937 vpermilps, 0x660c, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
1938 vpermilps, 0x6604, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
1939 vpextrb, 0x6614, None, 1, CpuAVX, RegMem|Vex|OpcodePrefix=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64 }
1940 vpextrb, 0x6614, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Byte|Unspecified|BaseIndex }
1941 vpextrd, 0x6616, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex }
1942 vpextrq, 0x6616, None, 1, CpuAVX|Cpu64, Modrm|Vex|OpcodePrefix=2|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg64|Unspecified|BaseIndex }
1943 vpextrw, 0x66c5, None, 1, CpuAVX, Load|Modrm|Vex|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64 }
1944 vpextrw, 0x6615, None, 1, CpuAVX, RegMem|Vex|OpcodePrefix=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64 }
1945 vpextrw, 0x6615, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Word|Unspecified|BaseIndex }
1946 vphaddd, 0x6602, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1947 vphaddsw, 0x6603, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1948 vphaddw, 0x6601, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1949 vphminposuw, 0x6641, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM }
1950 vphsubd, 0x6606, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1951 vphsubsw, 0x6607, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1952 vphsubw, 0x6605, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1953 vpinsrb, 0x6620, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM }
1954 vpinsrb, 0x6620, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Byte|Unspecified|BaseIndex, RegXMM, RegXMM }
1955 vpinsrd, 0x6622, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
1956 vpinsrq, 0x6622, None, 1, CpuAVX|Cpu64, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
1957 vpinsrw, 0x66c4, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM }
1958 vpinsrw, 0x66c4, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Word|Unspecified|BaseIndex, RegXMM, RegXMM }
1959 vpmaddubsw, 0x6604, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1960 vpmaddwd, 0x66f5, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1961 vpmaxsb, 0x663c, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1962 vpmaxsd, 0x663d, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1963 vpmaxsw, 0x66ee, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1964 vpmaxub, 0x66de, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1965 vpmaxud, 0x663f, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1966 vpmaxuw, 0x663e, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1967 vpminsb, 0x6638, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1968 vpminsd, 0x6639, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1969 vpminsw, 0x66ea, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1970 vpminub, 0x66da, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1971 vpminud, 0x663b, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1972 vpminuw, 0x663a, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1973 vpmovmskb, 0x66d7, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { RegXMM, Reg32|Reg64 }
1974 vpmovsxbd, 0x6621, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1975 vpmovsxbq, 0x6622, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex|RegXMM, RegXMM }
1976 vpmovsxbw, 0x6620, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1977 vpmovsxdq, 0x6625, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1978 vpmovsxwd, 0x6623, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1979 vpmovsxwq, 0x6624, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1980 vpmovzxbd, 0x6631, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1981 vpmovzxbq, 0x6632, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex|RegXMM, RegXMM }
1982 vpmovzxbw, 0x6630, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1983 vpmovzxdq, 0x6635, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1984 vpmovzxwd, 0x6633, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
1985 vpmovzxwq, 0x6634, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
1986 vpmuldq, 0x6628, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1987 vpmulhrsw, 0x660b, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1988 vpmulhuw, 0x66e4, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1989 vpmulhw, 0x66e5, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1990 vpmulld, 0x6640, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1991 vpmullw, 0x66d5, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1992 vpmuludq, 0x66f4, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1993 vpor, 0x66eb, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1994 vpsadbw, 0x66f6, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1995 vpshufb, 0x6600, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
1996 vpshufd, 0x6670, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM }
1997 vpshufhw, 0xf370, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM }
1998 vpshuflw, 0xf270, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM }
1999 vpsignb, 0x6608, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2000 vpsignd, 0x660a, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2001 vpsignw, 0x6609, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2002 vpslld, 0x6672, 0x6, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM }
2003 vpslld, 0x66f2, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2004 vpslldq, 0x6673, 0x7, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM }
2005 vpsllq, 0x6673, 0x6, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM }
2006 vpsllq, 0x66f3, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2007 vpsllw, 0x6671, 0x6, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM }
2008 vpsllw, 0x66f1, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2009 vpsrad, 0x6672, 0x4, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM }
2010 vpsrad, 0x66e2, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2011 vpsraw, 0x6671, 0x4, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM }
2012 vpsraw, 0x66e1, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2013 vpsrld, 0x6672, 0x2, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM }
2014 vpsrld, 0x66d2, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2015 vpsrldq, 0x6673, 0x3, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM }
2016 vpsrlq, 0x6673, 0x2, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM }
2017 vpsrlq, 0x66d3, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2018 vpsrlw, 0x6671, 0x2, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM }
2019 vpsrlw, 0x66d1, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2020 vpsubb, 0x66f8, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2021 vpsubd, 0x66fa, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2022 vpsubq, 0x66fb, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2023 vpsubsb, 0x66e8, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2024 vpsubsw, 0x66e9, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2025 vpsubusb, 0x66d8, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2026 vpsubusw, 0x66d9, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2027 vpsubw, 0x66f9, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2028 vptest, 0x6617, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
2029 vpunpckhbw, 0x6668, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2030 vpunpckhdq, 0x666a, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2031 vpunpckhqdq, 0x666d, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2032 vpunpckhwd, 0x6669, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2033 vpunpcklbw, 0x6660, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2034 vpunpckldq, 0x6662, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2035 vpunpcklqdq, 0x666c, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2036 vpunpcklwd, 0x6661, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2037 vpxor, 0x66ef, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2038 vrcpps, 0x53, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
2039 vrcpss, 0xf353, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2040 vroundpd, 0x6609, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
2041 vroundps, 0x6608, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=2|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
2042 vroundsd, 0x660b, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=2|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2043 vroundss, 0x660a, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=2|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2044 vrsqrtps, 0x52, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
2045 vrsqrtss, 0xf352, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2046 vshufpd, 0x66c6, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2047 vshufps, 0xc6, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2048 vsqrtpd, 0x6651, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
2049 vsqrtps, 0x51, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
2050 vsqrtsd, 0xf251, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2051 vsqrtss, 0xf351, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2052 vstmxcsr, 0xae, 0x3, 1, CpuAVX, Modrm|Vex128|OpcodePrefix=0|VexWIG|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex }
2053 vsubpd, 0x665c, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2054 vsubps, 0x5c, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2055 vsubsd, 0xf25c, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2056 vsubss, 0xf35c, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2057 vtestpd, 0x660f, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
2058 vtestps, 0x660e, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
2059 vucomisd, 0x662e, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
2060 vucomiss, 0x2e, None, 1, CpuAVX, Modrm|Vex=3|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
2061 vunpckhpd, 0x6615, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2062 vunpckhps, 0x15, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2063 vunpcklpd, 0x6614, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2064 vunpcklps, 0x14, None, 1, CpuAVX, Modrm|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2065 vxorpd, 0x6657, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2066 vxorps, 0x57, None, 1, CpuAVX, Modrm|C|Vex|OpcodePrefix=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2067 vzeroall, 0x77, None, 1, CpuAVX, Vex=2|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
2068 vzeroupper, 0x77, None, 1, CpuAVX, Vex|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
2069
2070 // 256bit integer AVX2 instructions.
2071
2072 vmovntdqa, 0x662a, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex, RegYMM }
2073 vmpsadbw, 0x6642, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=2|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2074 vpabsb, 0x661c, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM }
2075 vpabsd, 0x661e, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM }
2076 vpabsw, 0x661d, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM }
2077 vpackssdw, 0x666b, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2078 vpacksswb, 0x6663, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2079 vpackusdw, 0x662b, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2080 vpackuswb, 0x6667, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2081 vpaddsb, 0x66ec, None, 1, CpuAVX2, Modrm|C|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2082 vpaddsw, 0x66ed, None, 1, CpuAVX2, Modrm|C|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2083 vpaddb, 0x66fc, None, 1, CpuAVX2, Modrm|C|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2084 vpaddd, 0x66fe, None, 1, CpuAVX2, Modrm|C|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2085 vpaddq, 0x66d4, None, 1, CpuAVX2, Modrm|C|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2086 vpaddw, 0x66fd, None, 1, CpuAVX2, Modrm|C|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2087 vpaddusb, 0x66dc, None, 1, CpuAVX2, Modrm|C|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2088 vpaddusw, 0x66dd, None, 1, CpuAVX2, Modrm|C|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2089 vpalignr, 0x660f, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=2|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2090 vpand, 0x66db, None, 1, CpuAVX2, Modrm|C|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2091 vpandn, 0x66df, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2092 vpavgb, 0x66e0, None, 1, CpuAVX2, Modrm|C|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2093 vpavgw, 0x66e3, None, 1, CpuAVX2, Modrm|C|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2094 vpblendvb, 0x664c, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=2|VexVVVV=1|VexSources=2|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2095 vpblendw, 0x660e, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=2|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2096 vpcmpeqb, 0x6674, None, 1, CpuAVX2, Modrm|C|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2097 vpcmpeqd, 0x6676, None, 1, CpuAVX2, Modrm|C|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2098 vpcmpeqq, 0x6629, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2099 vpcmpeqw, 0x6675, None, 1, CpuAVX2, Modrm|C|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2100 vpcmpgtb, 0x6664, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2101 vpcmpgtd, 0x6666, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2102 vpcmpgtq, 0x6637, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2103 vpcmpgtw, 0x6665, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2104 vphaddd, 0x6602, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2105 vphaddsw, 0x6603, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2106 vphaddw, 0x6601, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2107 vphsubd, 0x6606, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2108 vphsubsw, 0x6607, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2109 vphsubw, 0x6605, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2110 vpmaddubsw, 0x6604, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2111 vpmaddwd, 0x66f5, None, 1, CpuAVX2, Modrm|C|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2112 vpmaxsb, 0x663c, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2113 vpmaxsd, 0x663d, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2114 vpmaxsw, 0x66ee, None, 1, CpuAVX2, Modrm|C|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2115 vpmaxub, 0x66de, None, 1, CpuAVX2, Modrm|C|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2116 vpmaxud, 0x663f, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2117 vpmaxuw, 0x663e, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2118 vpminsb, 0x6638, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2119 vpminsd, 0x6639, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2120 vpminsw, 0x66ea, None, 1, CpuAVX2, Modrm|C|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2121 vpminub, 0x66da, None, 1, CpuAVX2, Modrm|C|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2122 vpminud, 0x663b, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2123 vpminuw, 0x663a, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2124 vpmovmskb, 0x66d7, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { RegYMM, Reg32|Reg64 }
2125 vpmovsxbd, 0x6621, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegYMM }
2126 vpmovsxbq, 0x6622, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegYMM }
2127 vpmovsxbw, 0x6620, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegYMM }
2128 vpmovsxdq, 0x6625, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegYMM }
2129 vpmovsxwd, 0x6623, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegYMM }
2130 vpmovsxwq, 0x6624, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegYMM }
2131 vpmovzxbd, 0x6631, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegYMM }
2132 vpmovzxbq, 0x6632, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegYMM }
2133 vpmovzxbw, 0x6630, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegYMM }
2134 vpmovzxdq, 0x6635, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegYMM }
2135 vpmovzxwd, 0x6633, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegYMM }
2136 vpmovzxwq, 0x6634, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegYMM }
2137 vpmuldq, 0x6628, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2138 vpmulhrsw, 0x660b, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2139 vpmulhuw, 0x66e4, None, 1, CpuAVX2, Modrm|C|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2140 vpmulhw, 0x66e5, None, 1, CpuAVX2, Modrm|C|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2141 vpmulld, 0x6640, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2142 vpmullw, 0x66d5, None, 1, CpuAVX2, Modrm|C|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2143 vpmuludq, 0x66f4, None, 1, CpuAVX2, Modrm|C|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2144 vpor, 0x66eb, None, 1, CpuAVX2, Modrm|C|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2145 vpsadbw, 0x66f6, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2146 vpshufb, 0x6600, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2147 vpshufd, 0x6670, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM }
2148 vpshufhw, 0xf370, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM }
2149 vpshuflw, 0xf270, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM }
2150 vpsignb, 0x6608, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2151 vpsignd, 0x660a, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2152 vpsignw, 0x6609, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2153 vpslld, 0x6672, 0x6, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, RegYMM }
2154 vpslld, 0x66f2, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegYMM, RegYMM }
2155 vpslldq, 0x6673, 0x7, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, RegYMM }
2156 vpsllq, 0x6673, 0x6, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, RegYMM }
2157 vpsllq, 0x66f3, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegYMM, RegYMM }
2158 vpsllw, 0x6671, 0x6, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, RegYMM }
2159 vpsllw, 0x66f1, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegYMM, RegYMM }
2160 vpsrad, 0x6672, 0x4, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, RegYMM }
2161 vpsrad, 0x66e2, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegYMM, RegYMM }
2162 vpsraw, 0x6671, 0x4, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, RegYMM }
2163 vpsraw, 0x66e1, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegYMM, RegYMM }
2164 vpsrld, 0x6672, 0x2, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, RegYMM }
2165 vpsrld, 0x66d2, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegYMM, RegYMM }
2166 vpsrldq, 0x6673, 0x3, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, RegYMM }
2167 vpsrlq, 0x6673, 0x2, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, RegYMM }
2168 vpsrlq, 0x66d3, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegYMM, RegYMM }
2169 vpsrlw, 0x6671, 0x2, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, RegYMM }
2170 vpsrlw, 0x66d1, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegYMM, RegYMM }
2171 vpsubb, 0x66f8, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2172 vpsubd, 0x66fa, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2173 vpsubq, 0x66fb, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2174 vpsubsb, 0x66e8, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2175 vpsubsw, 0x66e9, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2176 vpsubusb, 0x66d8, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2177 vpsubusw, 0x66d9, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2178 vpsubw, 0x66f9, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2179 vpunpckhbw, 0x6668, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2180 vpunpckhdq, 0x666a, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2181 vpunpckhqdq, 0x666d, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2182 vpunpckhwd, 0x6669, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2183 vpunpcklbw, 0x6660, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2184 vpunpckldq, 0x6662, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2185 vpunpcklqdq, 0x666c, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2186 vpunpcklwd, 0x6661, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2187 vpxor, 0x66ef, None, 1, CpuAVX2, Modrm|C|Vex=2|OpcodePrefix=0|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2188
2189 // New AVX2 instructions.
2190
2191 vbroadcasti128, 0x665A, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex, RegYMM }
2192 vbroadcastsd, 0x6619, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegYMM }
2193 vbroadcastss, 0x6618, None, 1, CpuAVX2, Modrm|Vex|OpcodePrefix=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|RegYMM }
2194 vpblendd, 0x6602, None, 1, CpuAVX2, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2195 vpbroadcastb, 0x6678, None, 1, CpuAVX2, Modrm|Vex=1|OpcodePrefix=1|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Byte|Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM }
2196 vpbroadcastd, 0x6658, None, 1, CpuAVX2, Modrm|Vex=1|OpcodePrefix=1|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM }
2197 vpbroadcastq, 0x6659, None, 1, CpuAVX2, Modrm|Vex=1|OpcodePrefix=1|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM }
2198 vpbroadcastw, 0x6679, None, 1, CpuAVX2, Modrm|Vex=1|OpcodePrefix=1|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM }
2199 vperm2i128, 0x6646, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2200 vpermd, 0x6636, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2201 vpermpd, 0x6601, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=2|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM }
2202 vpermps, 0x6616, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2203 vpermq, 0x6600, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=2|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM }
2204 vextracti128, 0x6639, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=2|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM }
2205 vinserti128, 0x6638, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegYMM, RegYMM }
2206 vpmaskmovd, 0x668e, None, 1, CpuAVX2, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex }
2207 vpmaskmovd, 0x668c, None, 1, CpuAVX2, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
2208 vpmaskmovq, 0x668e, None, 1, CpuAVX2, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex }
2209 vpmaskmovq, 0x668c, None, 1, CpuAVX2, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
2210 vpsllvd, 0x6647, None, 1, CpuAVX2, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2211 vpsllvq, 0x6647, None, 1, CpuAVX2, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2212 vpsravd, 0x6646, None, 1, CpuAVX2, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2213 vpsrlvd, 0x6645, None, 1, CpuAVX2, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2214 vpsrlvq, 0x6645, None, 1, CpuAVX2, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2215
2216 // AVX gather instructions
2217 vgatherdpd, 0x6692, None, 1, CpuAVX2, Modrm|Vex|OpcodePrefix=1|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM, Qword|Unspecified|BaseIndex, RegXMM }
2218 vgatherdpd, 0x6692, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegYMM, Qword|Unspecified|BaseIndex, RegYMM }
2219 vgatherdps, 0x6692, None, 1, CpuAVX2, Modrm|Vex|OpcodePrefix=1|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM }
2220 vgatherdps, 0x6692, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB256, { RegYMM, Dword|Unspecified|BaseIndex, RegYMM }
2221 vgatherqpd, 0x6693, None, 1, CpuAVX2, Modrm|Vex|OpcodePrefix=1|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM, Qword|Unspecified|BaseIndex, RegXMM }
2222 vgatherqpd, 0x6693, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB256, { RegYMM, Qword|Unspecified|BaseIndex, RegYMM }
2223 vgatherqps, 0x6693, None, 1, CpuAVX2, Modrm|Vex|OpcodePrefix=1|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM }
2224 vgatherqps, 0x6693, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB256, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM }
2225 vpgatherdd, 0x6690, None, 1, CpuAVX2, Modrm|Vex|OpcodePrefix=1|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM }
2226 vpgatherdd, 0x6690, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB256, { RegYMM, Dword|Unspecified|BaseIndex, RegYMM }
2227 vpgatherdq, 0x6690, None, 1, CpuAVX2, Modrm|Vex|OpcodePrefix=1|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM, Qword|Unspecified|BaseIndex, RegXMM }
2228 vpgatherdq, 0x6690, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegYMM, Qword|Unspecified|BaseIndex, RegYMM }
2229 vpgatherqd, 0x6691, None, 1, CpuAVX2, Modrm|Vex|OpcodePrefix=1|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM }
2230 vpgatherqd, 0x6691, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB256, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM }
2231 vpgatherqq, 0x6691, None, 1, CpuAVX2, Modrm|Vex|OpcodePrefix=1|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM, Qword|Unspecified|BaseIndex, RegXMM }
2232 vpgatherqq, 0x6691, None, 1, CpuAVX2, Modrm|Vex=2|OpcodePrefix=1|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB256, { RegYMM, Qword|Unspecified|BaseIndex, RegYMM }
2233
2234 // AES + AVX
2235
2236 vaesdec, 0x66de, None, 1, CpuAVX|CpuAES, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2237 vaesdeclast, 0x66df, None, 1, CpuAVX|CpuAES, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2238 vaesenc, 0x66dc, None, 1, CpuAVX|CpuAES, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2239 vaesenclast, 0x66dd, None, 1, CpuAVX|CpuAES, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2240 vaesimc, 0x66db, None, 1, CpuAVX|CpuAES, Modrm|Vex|OpcodePrefix=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM }
2241 vaeskeygenassist, 0x66df, None, 1, CpuAVX|CpuAES, Modrm|Vex|OpcodePrefix=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM }
2242
2243 // PCLMUL + AVX
2244
2245 vpclmulqdq, 0x6644, None, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2246 vpclmullqlqdq, 0x6644, 0x0, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2247 vpclmulhqlqdq, 0x6644, 0x1, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2248 vpclmullqhqdq, 0x6644, 0x10, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2249 vpclmulhqhqdq, 0x6644, 0x11, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2250
2251 // GFNI + AVX
2252
2253 vgf2p8affineinvqb, 0x66cf, None, 1, CpuAVX|CpuGFNI, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2254 vgf2p8affineqb, 0x66ce, None, 1, CpuAVX|CpuGFNI, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2255 vgf2p8mulb, 0x66cf, None, 1, CpuAVX|CpuGFNI, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2256
2257 // FSGSBASE, RDRND and F16C
2258
2259 rdfsbase, 0x0fae, 0x0, 2, CpuFSGSBase, Prefix_0XF3|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 }
2260 rdgsbase, 0x0fae, 0x1, 2, CpuFSGSBase, Prefix_0XF3|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 }
2261 rdrand, 0xfc7, 0x6, 2, CpuRdRnd, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64 }
2262 wrfsbase, 0x0fae, 0x2, 2, CpuFSGSBase, Prefix_0XF3|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 }
2263 wrgsbase, 0x0fae, 0x3, 2, CpuFSGSBase, Prefix_0XF3|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 }
2264 vcvtph2ps, 0x6613, None, 1, CpuF16C, Modrm|Vex|OpcodePrefix=1|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
2265 vcvtph2ps, 0x6613, None, 1, CpuF16C, Modrm|Vex=2|OpcodePrefix=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegYMM }
2266 vcvtps2ph, 0x661d, None, 1, CpuF16C, Modrm|Vex|OpcodePrefix=2|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Qword|Unspecified|BaseIndex|RegXMM }
2267 vcvtps2ph, 0x661d, None, 1, CpuF16C, Modrm|Vex=2|OpcodePrefix=2|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM }
2268
2269 // FMA instructions
2270
2271 vfmadd132pd, 0x6698, None, 1, CpuFMA, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2272 vfmadd132ps, 0x6698, None, 1, CpuFMA, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2273 vfmadd213pd, 0x66a8, None, 1, CpuFMA, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2274 vfmadd213ps, 0x66a8, None, 1, CpuFMA, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2275 vfmadd231pd, 0x66b8, None, 1, CpuFMA, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2276 vfmadd231ps, 0x66b8, None, 1, CpuFMA, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2277 vfmadd132sd, 0x6699, None, 1, CpuFMA, Modrm|Vex=3|OpcodePrefix=1|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2278 vfmadd132ss, 0x6699, None, 1, CpuFMA, Modrm|Vex=3|OpcodePrefix=1|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2279 vfmadd213sd, 0x66a9, None, 1, CpuFMA, Modrm|Vex=3|OpcodePrefix=1|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2280 vfmadd213ss, 0x66a9, None, 1, CpuFMA, Modrm|Vex=3|OpcodePrefix=1|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2281 vfmadd231sd, 0x66b9, None, 1, CpuFMA, Modrm|Vex=3|OpcodePrefix=1|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2282 vfmadd231ss, 0x66b9, None, 1, CpuFMA, Modrm|Vex=3|OpcodePrefix=1|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2283 vfmaddsub132pd, 0x6696, None, 1, CpuFMA, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2284 vfmaddsub132ps, 0x6696, None, 1, CpuFMA, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2285 vfmaddsub213pd, 0x66a6, None, 1, CpuFMA, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2286 vfmaddsub213ps, 0x66a6, None, 1, CpuFMA, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2287 vfmaddsub231pd, 0x66b6, None, 1, CpuFMA, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2288 vfmaddsub231ps, 0x66b6, None, 1, CpuFMA, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2289 vfmsubadd132pd, 0x6697, None, 1, CpuFMA, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2290 vfmsubadd132ps, 0x6697, None, 1, CpuFMA, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2291 vfmsubadd213pd, 0x66a7, None, 1, CpuFMA, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2292 vfmsubadd213ps, 0x66a7, None, 1, CpuFMA, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2293 vfmsubadd231pd, 0x66b7, None, 1, CpuFMA, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2294 vfmsubadd231ps, 0x66b7, None, 1, CpuFMA, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2295 vfmsub132pd, 0x669a, None, 1, CpuFMA, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2296 vfmsub132ps, 0x669a, None, 1, CpuFMA, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2297 vfmsub213pd, 0x66aa, None, 1, CpuFMA, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2298 vfmsub213ps, 0x66aa, None, 1, CpuFMA, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2299 vfmsub231pd, 0x66ba, None, 1, CpuFMA, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2300 vfmsub231ps, 0x66ba, None, 1, CpuFMA, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2301 vfmsub132sd, 0x669b, None, 1, CpuFMA, Modrm|Vex=3|OpcodePrefix=1|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2302 vfmsub132ss, 0x669b, None, 1, CpuFMA, Modrm|Vex=3|OpcodePrefix=1|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2303 vfmsub213sd, 0x66ab, None, 1, CpuFMA, Modrm|Vex=3|OpcodePrefix=1|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2304 vfmsub213ss, 0x66ab, None, 1, CpuFMA, Modrm|Vex=3|OpcodePrefix=1|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2305 vfmsub231sd, 0x66bb, None, 1, CpuFMA, Modrm|Vex=3|OpcodePrefix=1|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2306 vfmsub231ss, 0x66bb, None, 1, CpuFMA, Modrm|Vex=3|OpcodePrefix=1|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2307 vfnmadd132pd, 0x669c, None, 1, CpuFMA, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2308 vfnmadd132ps, 0x669c, None, 1, CpuFMA, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2309 vfnmadd213pd, 0x66ac, None, 1, CpuFMA, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2310 vfnmadd213ps, 0x66ac, None, 1, CpuFMA, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2311 vfnmadd231pd, 0x66bc, None, 1, CpuFMA, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2312 vfnmadd231ps, 0x66bc, None, 1, CpuFMA, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2313 vfnmadd132sd, 0x669d, None, 1, CpuFMA, Modrm|Vex=3|OpcodePrefix=1|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2314 vfnmadd132ss, 0x669d, None, 1, CpuFMA, Modrm|Vex=3|OpcodePrefix=1|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2315 vfnmadd213sd, 0x66ad, None, 1, CpuFMA, Modrm|Vex=3|OpcodePrefix=1|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2316 vfnmadd213ss, 0x66ad, None, 1, CpuFMA, Modrm|Vex=3|OpcodePrefix=1|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2317 vfnmadd231sd, 0x66bd, None, 1, CpuFMA, Modrm|Vex=3|OpcodePrefix=1|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2318 vfnmadd231ss, 0x66bd, None, 1, CpuFMA, Modrm|Vex=3|OpcodePrefix=1|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2319 vfnmsub132pd, 0x669e, None, 1, CpuFMA, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2320 vfnmsub132ps, 0x669e, None, 1, CpuFMA, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2321 vfnmsub213pd, 0x66ae, None, 1, CpuFMA, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2322 vfnmsub213ps, 0x66ae, None, 1, CpuFMA, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2323 vfnmsub231pd, 0x66be, None, 1, CpuFMA, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2324 vfnmsub231ps, 0x66be, None, 1, CpuFMA, Modrm|Vex|OpcodePrefix=1|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2325 vfnmsub132sd, 0x669f, None, 1, CpuFMA, Modrm|Vex=3|OpcodePrefix=1|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2326 vfnmsub132ss, 0x669f, None, 1, CpuFMA, Modrm|Vex=3|OpcodePrefix=1|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2327 vfnmsub213sd, 0x66af, None, 1, CpuFMA, Modrm|Vex=3|OpcodePrefix=1|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2328 vfnmsub213ss, 0x66af, None, 1, CpuFMA, Modrm|Vex=3|OpcodePrefix=1|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2329 vfnmsub231sd, 0x66bf, None, 1, CpuFMA, Modrm|Vex=3|OpcodePrefix=1|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2330 vfnmsub231ss, 0x66bf, None, 1, CpuFMA, Modrm|Vex=3|OpcodePrefix=1|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2331
2332 // HLE prefixes
2333
2334 xacquire, 0xf2, None, 1, CpuHLE, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
2335 xrelease, 0xf3, None, 1, CpuHLE, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
2336
2337 // RTM instructions
2338 xabort, 0xc6f8, None, 2, CpuRTM, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8 }
2339 xbegin, 0xc7f8, None, 2, CpuRTM,  JumpDword|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Disp16|Disp32|Disp32S }
2340 xend, 0xf01d5, None, 3, CpuRTM, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
2341 xtest, 0xf01d6, None, 3, CpuHLE|CpuRTM, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
2342
2343 // BMI2 instructions.
2344 bzhi, 0xf5, None, 1, CpuBMI2, Modrm|CheckRegSize|Vex128|OpcodePrefix=1|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
2345 mulx, 0xf2f6, None, 1, CpuBMI2, Modrm|CheckRegSize|Vex128|OpcodePrefix=1|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 }
2346 pdep, 0xf2f5, None, 1, CpuBMI2, Modrm|CheckRegSize|Vex128|OpcodePrefix=1|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 }
2347 pext, 0xf3f5, None, 1, CpuBMI2, Modrm|CheckRegSize|Vex128|OpcodePrefix=1|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 }
2348 rorx, 0xf2f0, None, 1, CpuBMI2, Modrm|CheckRegSize|Vex128|OpcodePrefix=2|VexVVVV=0|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Imm8, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
2349 sarx, 0xf3f7, None, 1, CpuBMI2, Modrm|CheckRegSize|Vex128|OpcodePrefix=1|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
2350 shlx, 0x66f7, None, 1, CpuBMI2, Modrm|CheckRegSize|Vex128|OpcodePrefix=1|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
2351 shrx, 0xf2f7, None, 1, CpuBMI2, Modrm|CheckRegSize|Vex128|OpcodePrefix=1|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
2352
2353 // FMA4 instructions
2354
2355 vfmaddpd, 0x6669, None, 1, CpuFMA4, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=2|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2356 vfmaddpd, 0x6669, None, 1, CpuFMA4, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=1|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2357 vfmaddps, 0x6668, None, 1, CpuFMA4, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=2|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2358 vfmaddps, 0x6668, None, 1, CpuFMA4, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=1|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2359 vfmaddsd, 0x666b, None, 1, CpuFMA4, Modrm|VexLIG|OpcodePrefix=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
2360 vfmaddsd, 0x666b, None, 1, CpuFMA4, Modrm|VexLIG|OpcodePrefix=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2361 vfmaddss, 0x666a, None, 1, CpuFMA4, Modrm|VexLIG|OpcodePrefix=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
2362 vfmaddss, 0x666a, None, 1, CpuFMA4, Modrm|VexLIG|OpcodePrefix=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2363 vfmaddsubpd, 0x665d, None, 1, CpuFMA4, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=2|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2364 vfmaddsubpd, 0x665d, None, 1, CpuFMA4, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=1|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2365 vfmaddsubps, 0x665c, None, 1, CpuFMA4, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=2|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2366 vfmaddsubps, 0x665c, None, 1, CpuFMA4, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=1|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2367 vfmsubaddpd, 0x665f, None, 1, CpuFMA4, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=2|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2368 vfmsubaddpd, 0x665f, None, 1, CpuFMA4, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=1|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2369 vfmsubaddps, 0x665e, None, 1, CpuFMA4, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=2|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2370 vfmsubaddps, 0x665e, None, 1, CpuFMA4, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=1|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2371 vfmsubpd, 0x666d, None, 1, CpuFMA4, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=2|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2372 vfmsubpd, 0x666d, None, 1, CpuFMA4, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=1|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2373 vfmsubps, 0x666c, None, 1, CpuFMA4, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=2|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2374 vfmsubps, 0x666c, None, 1, CpuFMA4, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=1|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2375 vfmsubsd, 0x666f, None, 1, CpuFMA4, Modrm|VexLIG|OpcodePrefix=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
2376 vfmsubsd, 0x666f, None, 1, CpuFMA4, Modrm|VexLIG|OpcodePrefix=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2377 vfmsubss, 0x666e, None, 1, CpuFMA4, Modrm|VexLIG|OpcodePrefix=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
2378 vfmsubss, 0x666e, None, 1, CpuFMA4, Modrm|VexLIG|OpcodePrefix=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2379 vfnmaddpd, 0x6679, None, 1, CpuFMA4, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=2|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2380 vfnmaddpd, 0x6679, None, 1, CpuFMA4, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=1|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2381 vfnmaddps, 0x6678, None, 1, CpuFMA4, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=2|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2382 vfnmaddps, 0x6678, None, 1, CpuFMA4, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=1|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2383 vfnmaddsd, 0x667b, None, 1, CpuFMA4, Modrm|VexLIG|OpcodePrefix=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
2384 vfnmaddsd, 0x667b, None, 1, CpuFMA4, Modrm|VexLIG|OpcodePrefix=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2385 vfnmaddss, 0x667a, None, 1, CpuFMA4, Modrm|VexLIG|OpcodePrefix=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
2386 vfnmaddss, 0x667a, None, 1, CpuFMA4, Modrm|VexLIG|OpcodePrefix=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2387 vfnmsubpd, 0x667d, None, 1, CpuFMA4, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=2|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2388 vfnmsubpd, 0x667d, None, 1, CpuFMA4, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=1|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2389 vfnmsubps, 0x667c, None, 1, CpuFMA4, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=2|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2390 vfnmsubps, 0x667c, None, 1, CpuFMA4, Modrm|Vex|OpcodePrefix=2|VexVVVV=1|VexW=1|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2391 vfnmsubsd, 0x667f, None, 1, CpuFMA4, Modrm|VexLIG|OpcodePrefix=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
2392 vfnmsubsd, 0x667f, None, 1, CpuFMA4, Modrm|VexLIG|OpcodePrefix=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2393 vfnmsubss, 0x667e, None, 1, CpuFMA4, Modrm|VexLIG|OpcodePrefix=2|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM }
2394 vfnmsubss, 0x667e, None, 1, CpuFMA4, Modrm|VexLIG|OpcodePrefix=2|VexVVVV|VexW0|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
2395
2396 // XOP instructions
2397
2398 <xop_elem:opc, b:0, w:1, d:2, q:3>
2399 <xop_irel:imm, lt:0, le:1, gt:2, ge:3, eq:4, neq:5, false:6, true:7>
2400 <xop_sign:opc, :00, u:20>
2401
2402 vfrczpd, 0x81, None, 1, CpuXOP, Modrm|OpcodePrefix=4|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
2403 vfrczps, 0x80, None, 1, CpuXOP, Modrm|OpcodePrefix=4|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
2404 vfrczsd, 0x83, None, 1, CpuXOP, Modrm|OpcodePrefix=4|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Qword|RegXMM|Unspecified|BaseIndex, RegXMM }
2405 vfrczss, 0x82, None, 1, CpuXOP, Modrm|OpcodePrefix=4|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Dword|RegXMM|Unspecified|BaseIndex, RegXMM }
2406 vpcmov, 0xa2, None, 1, CpuXOP, Modrm|OpcodePrefix=3|VexSources=2|VexVVVV=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2407 vpcmov, 0xa2, None, 1, CpuXOP, Modrm|OpcodePrefix=3|VexSources=2|VexVVVV=1|VexW=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2408 vpcom<xop_sign><xop_elem>, 0xcc | 0x<xop_sign:opc> | <xop_elem:opc>, None, 1, CpuXOP, Modrm|Vex128|OpcodePrefix=3|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
2409 vpcom<xop_irel><xop_sign><xop_elem>, 0xcc | 0x<xop_sign:opc> | <xop_elem:opc>, <xop_irel:imm>, 1, CpuXOP, Modrm|Vex128|OpcodePrefix=3|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
2410 vpermil2pd, 0x6649, None, 1, CpuXOP, Modrm|OpcodePrefix=2|VexVVVV=1|VexW=1|Vex|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2411 vpermil2pd, 0x6649, None, 1, CpuXOP, Modrm|OpcodePrefix=2|VexVVVV=1|VexW=2|Vex|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2412 vpermil2ps, 0x6648, None, 1, CpuXOP, Modrm|OpcodePrefix=2|VexVVVV=1|VexW=1|Vex|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2413 vpermil2ps, 0x6648, None, 1, CpuXOP, Modrm|OpcodePrefix=2|VexVVVV=1|VexW=2|Vex|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
2414 vphaddbd, 0xc2, None, 1, CpuXOP, Modrm|OpcodePrefix=4|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM }
2415 vphaddbq, 0xc3, None, 1, CpuXOP, Modrm|OpcodePrefix=4|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM }
2416 vphaddbw, 0xc1, None, 1, CpuXOP, Modrm|OpcodePrefix=4|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM }
2417 vphadddq, 0xcb, None, 1, CpuXOP, Modrm|OpcodePrefix=4|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM }
2418 vphaddubd, 0xd2, None, 1, CpuXOP, Modrm|OpcodePrefix=4|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM }
2419 vphaddubq, 0xd3, None, 1, CpuXOP, Modrm|OpcodePrefix=4|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM }
2420 vphaddubw, 0xd1, None, 1, CpuXOP, Modrm|OpcodePrefix=4|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM }
2421 vphaddudq, 0xdb, None, 1, CpuXOP, Modrm|OpcodePrefix=4|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM }
2422 vphadduwd, 0xd6, None, 1, CpuXOP, Modrm|OpcodePrefix=4|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM }
2423 vphadduwq, 0xd7, None, 1, CpuXOP, Modrm|OpcodePrefix=4|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM }
2424 vphaddwd, 0xc6, None, 1, CpuXOP, Modrm|OpcodePrefix=4|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM }
2425 vphaddwq, 0xc7, None, 1, CpuXOP, Modrm|OpcodePrefix=4|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM }
2426 vphsubbw, 0xe1, None, 1, CpuXOP, Modrm|OpcodePrefix=4|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM }
2427 vphsubdq, 0xe3, None, 1, CpuXOP, Modrm|OpcodePrefix=4|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM }
2428 vphsubwd, 0xe2, None, 1, CpuXOP, Modrm|OpcodePrefix=4|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM }
2429 vpmacsdd, 0x9e, None, 1, CpuXOP, Modrm|OpcodePrefix=3|VexSources=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
2430 vpmacsdqh, 0x9f, None, 1, CpuXOP, Modrm|OpcodePrefix=3|VexSources=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
2431 vpmacsdql, 0x97, None, 1, CpuXOP, Modrm|OpcodePrefix=3|VexSources=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
2432 vpmacssdd, 0x8e, None, 1, CpuXOP, Modrm|OpcodePrefix=3|VexSources=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
2433 vpmacssdqh, 0x8f, None, 1, CpuXOP, Modrm|OpcodePrefix=3|VexSources=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
2434 vpmacssdql, 0x87, None, 1, CpuXOP, Modrm|OpcodePrefix=3|VexSources=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
2435 vpmacsswd, 0x86, None, 1, CpuXOP, Modrm|OpcodePrefix=3|VexSources=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
2436 vpmacssww, 0x85, None, 1, CpuXOP, Modrm|OpcodePrefix=3|VexSources=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
2437 vpmacswd, 0x96, None, 1, CpuXOP, Modrm|OpcodePrefix=3|VexSources=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
2438 vpmacsww, 0x95, None, 1, CpuXOP, Modrm|OpcodePrefix=3|VexSources=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
2439 vpmadcsswd, 0xa6, None, 1, CpuXOP, Modrm|OpcodePrefix=3|VexSources=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
2440 vpmadcswd, 0xb6, None, 1, CpuXOP, Modrm|OpcodePrefix=3|VexSources=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
2441 vpperm, 0xa3, None, 1, CpuXOP, Modrm|OpcodePrefix=3|VexSources=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
2442 vpperm, 0xa3, None, 1, CpuXOP, Modrm|OpcodePrefix=3|VexSources=2|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM, RegXMM }
2443 vprot<xop_elem>, 0x90 | <xop_elem:opc>, None, 1, CpuXOP, Modrm|Vex128|OpcodePrefix=4|VexW0|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM }
2444 vprot<xop_elem>, 0x90 | <xop_elem:opc>, None, 1, CpuXOP, Modrm|Vex128|OpcodePrefix=4|VexW1|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
2445 vprot<xop_elem>, 0xc0 | <xop_elem:opc>, None, 1, CpuXOP, Modrm|Vex128|OpcodePrefix=3|VexW0|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
2446 vpsha<xop_elem>, 0x98 | <xop_elem:opc>, None, 1, CpuXOP, Modrm|Vex128|OpcodePrefix=4|VexW0|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM }
2447 vpsha<xop_elem>, 0x98 | <xop_elem:opc>, None, 1, CpuXOP, Modrm|Vex128|OpcodePrefix=4|VexW1|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
2448 vpshl<xop_elem>, 0x94 | <xop_elem:opc>, None, 1, CpuXOP, Modrm|Vex128|OpcodePrefix=4|VexW0|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM }
2449 vpshl<xop_elem>, 0x94 | <xop_elem:opc>, None, 1, CpuXOP, Modrm|Vex128|OpcodePrefix=4|VexW1|VexSources=1|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
2450
2451 // LWP instructions
2452
2453 llwpcb, 0x12, 0x0, 1, CpuLWP, Modrm|OpcodePrefix=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Reg32|Reg64 }
2454 slwpcb, 0x12, 0x1, 1, CpuLWP, Modrm|OpcodePrefix=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Reg32|Reg64 }
2455 lwpval, 0x12, 0x1, 1, CpuLWP, Modrm|OpcodePrefix=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexVVVV=3|Vex, { Imm32|Imm32S, Reg32|Unspecified|BaseIndex, Reg32|Reg64 }
2456 lwpins, 0x12, 0x0, 1, CpuLWP, Modrm|OpcodePrefix=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexVVVV=3|Vex, { Imm32|Imm32S, Reg32|Unspecified|BaseIndex, Reg32|Reg64 }
2457
2458 // BMI instructions
2459
2460 andn, 0xf2, None, 1, CpuBMI, Modrm|CheckRegSize|Vex128|OpcodePrefix=1|VexVVVV=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 }
2461 bextr, 0xf7, None, 1, CpuBMI, Modrm|CheckRegSize|Vex128|OpcodePrefix=1|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
2462 blsi, 0xf3, 0x3, 1, CpuBMI, Modrm|CheckRegSize|Vex128|OpcodePrefix=1|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
2463 blsmsk, 0xf3, 0x2, 1, CpuBMI, Modrm|CheckRegSize|Vex128|OpcodePrefix=1|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
2464 blsr, 0xf3, 0x1, 1, CpuBMI, Modrm|CheckRegSize|Vex128|OpcodePrefix=1|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
2465 tzcnt, 0x0fbc, None, 2, CpuBMI, Prefix_0XF3|Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
2466
2467 // TBM instructions
2468 bextr, 0x10, None, 1, CpuTBM, Modrm|CheckRegSize|Vex128|OpcodePrefix=5|VexVVVV=0|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Imm32|Imm32S, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
2469 blcfill, 0x01, 0x1, 1, CpuTBM, Modrm|CheckRegSize|Vex128|OpcodePrefix=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
2470 blci, 0x02, 0x6, 1, CpuTBM, Modrm|CheckRegSize|Vex128|OpcodePrefix=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
2471 blcic, 0x01, 0x5, 1, CpuTBM, Modrm|CheckRegSize|Vex128|OpcodePrefix=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
2472 blcmsk, 0x02, 0x1, 1, CpuTBM, Modrm|CheckRegSize|Vex128|OpcodePrefix=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
2473 blcs, 0x01, 0x3, 1, CpuTBM, Modrm|CheckRegSize|Vex128|OpcodePrefix=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
2474 blsfill, 0x01, 0x2, 1, CpuTBM, Modrm|CheckRegSize|Vex128|OpcodePrefix=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
2475 blsic, 0x01, 0x6, 1, CpuTBM, Modrm|CheckRegSize|Vex128|OpcodePrefix=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
2476 t1mskc, 0x01, 0x7, 1, CpuTBM, Modrm|CheckRegSize|Vex128|OpcodePrefix=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
2477 tzmsk, 0x01, 0x4, 1, CpuTBM, Modrm|CheckRegSize|Vex128|OpcodePrefix=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
2478
2479 // AMD 3DNow! instructions.
2480
2481 prefetch, 0xf0d, 0x0, 2, Cpu3dnow|CpuPRFCHW, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex }
2482 prefetchw, 0xf0d, 0x1, 2, Cpu3dnow|CpuPRFCHW, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex }
2483 femms, 0xf0e, None, 2, Cpu3dnow, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
2484 pavgusb, 0xf0f, 0xbf, 2, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
2485 pf2id, 0xf0f, 0x1d, 2, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
2486 pf2iw, 0xf0f, 0x1c, 2, Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
2487 pfacc, 0xf0f, 0xae, 2, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
2488 pfadd, 0xf0f, 0x9e, 2, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
2489 pfcmpeq, 0xf0f, 0xb0, 2, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
2490 pfcmpge, 0xf0f, 0x90, 2, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
2491 pfcmpgt, 0xf0f, 0xa0, 2, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
2492 pfmax, 0xf0f, 0xa4, 2, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
2493 pfmin, 0xf0f, 0x94, 2, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
2494 pfmul, 0xf0f, 0xb4, 2, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
2495 pfnacc, 0xf0f, 0x8a, 2, Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
2496 pfpnacc, 0xf0f, 0x8e, 2, Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
2497 pfrcp, 0xf0f, 0x96, 2, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
2498 pfrcpit1, 0xf0f, 0xa6, 2, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
2499 pfrcpit2, 0xf0f, 0xb6, 2, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
2500 pfrsqit1, 0xf0f, 0xa7, 2, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
2501 pfrsqrt, 0xf0f, 0x97, 2, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
2502 pfsub, 0xf0f, 0x9a, 2, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
2503 pfsubr, 0xf0f, 0xaa, 2, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
2504 pi2fd, 0xf0f, 0xd, 2, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
2505 pi2fw, 0xf0f, 0xc, 2, Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
2506 pmulhrw, 0xf0f, 0xb7, 2, Cpu3dnow, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
2507 pswapd, 0xf0f, 0xbb, 2, Cpu3dnowA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|ImmExt, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
2508
2509 // AMD extensions.
2510 syscall, 0xf05, None, 2, CpuSYSCALL, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
2511 sysret, 0xf07, None, 2, CpuSYSCALL, No_bSuf|No_wSuf|No_sSuf|No_ldSuf, {}
2512 swapgs, 0xf01f8, None, 3, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
2513 rdtscp, 0xf01f9, None, 3, CpuRdtscp, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
2514
2515 // AMD Pacifica additions.
2516 clgi, 0xf01dd, None, 3, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
2517 invlpga, 0xf01df, None, 3, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
2518 invlpga, 0xf01df, None, 3, CpuSVME, AddrPrefixOpReg, { Acc|Word|Dword|Qword, RegC|Dword }
2519 skinit, 0xf01de, None, 3, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
2520 skinit, 0xf01de, None, 3, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Acc|Dword }
2521 stgi, 0xf01dc, None, 3, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
2522 vmgexit, 0x0f01d9, None, 3, CpuSEV_ES, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
2523 vmload, 0xf01da, None, 3, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
2524 vmload, 0xf01da, None, 3, CpuSVME, AddrPrefixOpReg, { Acc|Word|Dword|Qword }
2525 vmmcall, 0xf01d9, None, 3, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
2526 vmrun, 0xf01d8, None, 3, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
2527 vmrun, 0xf01d8, None, 3, CpuSVME, AddrPrefixOpReg, { Acc|Word|Dword|Qword }
2528 vmsave, 0xf01db, None, 3, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
2529 vmsave, 0xf01db, None, 3, CpuSVME, AddrPrefixOpReg, { Acc|Word|Dword|Qword }
2530
2531
2532 // SSE4a instructions
2533 movntsd, 0x0f2b, None, 2, CpuSSE4a, Prefix_0XF2|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex }
2534 movntss, 0x0f2b, None, 2, CpuSSE4a, Prefix_0XF3|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex }
2535 extrq, 0x0f78, 0x0, 2, CpuSSE4a, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Imm8, RegXMM }
2536 extrq, 0x0f79, None, 2, CpuSSE4a, Prefix_0X66|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM }
2537 insertq, 0x0f79, None, 2, CpuSSE4a, Prefix_0XF2|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM }
2538 insertq, 0x0f78, None, 2, CpuSSE4a, Prefix_0XF2|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Imm8, RegXMM, RegXMM }
2539
2540 // LZCNT instruction
2541 lzcnt, 0x0fbd, None, 2, CpuLZCNT, Prefix_0XF3|Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
2542
2543 // POPCNT instruction
2544 popcnt, 0x0fb8, None, 2, CpuPOPCNT, Prefix_0XF3|Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf|NoAVX, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
2545
2546 // VIA PadLock extensions.
2547 xstore-rng, 0xfa7c0, None, 3, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, {}
2548 xcrypt-ecb, 0x0fa7c8, None, 3, CpuPadLock, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, {}
2549 xcrypt-cbc, 0x0fa7d0, None, 3, CpuPadLock, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, {}
2550 xcrypt-ctr, 0x0fa7d8, None, 3, CpuPadLock, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, {}
2551 xcrypt-cfb, 0x0fa7e0, None, 3, CpuPadLock, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, {}
2552 xcrypt-ofb, 0x0fa7e8, None, 3, CpuPadLock, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, {}
2553 montmul, 0x0fa6c0, None, 3, CpuPadLock, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, {}
2554 xsha1, 0x0fa6c8, None, 3, CpuPadLock, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, {}
2555 xsha256, 0x0fa6d0, None, 3, CpuPadLock, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, {}
2556 // Aliases without hyphens.
2557 xstorerng, 0xfa7c0, None, 3, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, {}
2558 xcryptecb, 0x0fa7c8, None, 3, CpuPadLock, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, {}
2559 xcryptcbc, 0x0fa7d0, None, 3, CpuPadLock, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, {}
2560 xcryptctr, 0x0fa7d8, None, 3, CpuPadLock, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, {}
2561 xcryptcfb, 0x0fa7e0, None, 3, CpuPadLock, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, {}
2562 xcryptofb, 0x0fa7e8, None, 3, CpuPadLock, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, {}
2563 // Alias for xstore-rng.
2564 xstore, 0xfa7c0, None, 3, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, {}
2565
2566 // Multy-precision Add Carry, rdseed instructions.
2567 adcx, 0x0f38f6, None, 3, CpuADX, Prefix_0X66|Modrm|CheckRegSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
2568 adox, 0x0f38f6, None, 3, CpuADX, Prefix_0XF3|Modrm|CheckRegSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
2569 rdseed, 0xfc7, 0x7, 2, CpuRdSeed, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64 }
2570
2571 // SMAP instructions.
2572 clac, 0xf01ca, None, 3, CpuSMAP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
2573 stac, 0xf01cb, None, 3, CpuSMAP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
2574
2575 // BND prefix
2576 bnd, 0xf2, None, 1, CpuMPX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
2577
2578 // MPX instructions.
2579 bndmk, 0x0f1b, None, 2, CpuMPX, Prefix_0XF3|Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex, RegBND }
2580 bndmov, 0x0f1a, None, 2, CpuMPX, Prefix_0X66|D|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegBND, RegBND }
2581 bndcl, 0x0f1a, None, 2, CpuMPX|CpuNo64, Prefix_0XF3|Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|BaseIndex, RegBND }
2582 bndcl, 0x0f1a, None, 2, CpuMPX|Cpu64, Prefix_0XF3|Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64|BaseIndex, RegBND }
2583 bndcu, 0x0f1a, None, 2, CpuMPX|CpuNo64, Prefix_0XF2|Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|BaseIndex, RegBND }
2584 bndcu, 0x0f1a, None, 2, CpuMPX|Cpu64, Prefix_0XF2|Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64|BaseIndex, RegBND }
2585 bndcn, 0x0f1b, None, 2, CpuMPX|CpuNo64, Prefix_0XF2|Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|BaseIndex, RegBND }
2586 bndcn, 0x0f1b, None, 2, CpuMPX|Cpu64, Prefix_0XF2|Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64|BaseIndex, RegBND }
2587 bndstx, 0x0f1b, None, 2, CpuMPX, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegBND, BaseIndex }
2588 bndldx, 0x0f1a, None, 2, CpuMPX, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex, RegBND }
2589
2590 // SHA instructions.
2591 sha1rnds4, 0xf3acc, None, 3, CpuSHA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
2592 sha1nexte, 0xf38c8, None, 3, CpuSHA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
2593 sha1msg1, 0xf38c9, None, 3, CpuSHA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
2594 sha1msg2, 0xf38ca, None, 3, CpuSHA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
2595 sha256rnds2, 0xf38cb, None, 3, CpuSHA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM }
2596 sha256rnds2, 0xf38cb, None, 3, CpuSHA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
2597 sha256msg1, 0xf38cc, None, 3, CpuSHA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
2598 sha256msg2, 0xf38cd, None, 3, CpuSHA, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
2599
2600 // VPCLMULQDQ instructions
2601
2602 vpclmulqdq, 0x6644, None, 1, CpuVPCLMULQDQ, Modrm|Vex=2|OpcodePrefix=2|VexWIG|VexVVVV=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2603 vpclmullqlqdq, 0x6644, 0x00, 1, CpuVPCLMULQDQ, Modrm|Vex=2|OpcodePrefix=2|VexWIG|VexVVVV=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2604 vpclmulhqlqdq, 0x6644, 0x01, 1, CpuVPCLMULQDQ, Modrm|Vex=2|OpcodePrefix=2|VexWIG|VexVVVV=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2605 vpclmullqhqdq, 0x6644, 0x10, 1, CpuVPCLMULQDQ, Modrm|Vex=2|OpcodePrefix=2|VexWIG|VexVVVV=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2606 vpclmulhqhqdq, 0x6644, 0x11, 1, CpuVPCLMULQDQ, Modrm|Vex=2|OpcodePrefix=2|VexWIG|VexVVVV=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
2607
2608 // VPCLMULQDQ instructions end
2609
2610 // AVX512F instructions.
2611
2612 #define Disp8ShiftVL Disp8MemShift=DISP8_SHIFT_VL
2613 #define MaskingMorZ  Masking=DYNAMIC_MASKING
2614
2615 kandnw, 0x42, None, 1, CpuAVX512F, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
2616 kandw, 0x41, None, 1, CpuAVX512F, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
2617 korw, 0x45, None, 1, CpuAVX512F, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
2618 kxnorw, 0x46, None, 1, CpuAVX512F, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
2619 kxorw, 0x47, None, 1, CpuAVX512F, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
2620
2621 kmovw, 0x90, None, 1, CpuAVX512F, Modrm|Vex=1|OpcodePrefix=0|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask|Word|Unspecified|BaseIndex, RegMask }
2622 kmovw, 0x91, None, 1, CpuAVX512F, Modrm|Vex=1|OpcodePrefix=0|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, Word|Unspecified|BaseIndex }
2623 kmovw, 0x92, None, 1, CpuAVX512F, D|Modrm|Vex=1|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegMask }
2624
2625 knotw, 0x44, None, 1, CpuAVX512F, Modrm|Vex=1|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
2626 kortestw, 0x98, None, 1, CpuAVX512F, Modrm|Vex=1|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
2627
2628 kshiftlw, 0x6632, None, 1, CpuAVX512F, Modrm|Vex=1|OpcodePrefix=2|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask }
2629 kshiftrw, 0x6630, None, 1, CpuAVX512F, Modrm|Vex=1|OpcodePrefix=2|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask }
2630
2631 kunpckbw, 0x664B, None, 1, CpuAVX512F, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
2632
2633 vaddpd, 0x6658, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2634 vaddpd, 0x6658, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2635 vdivpd, 0x665E, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2636 vdivpd, 0x665E, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2637 vmulpd, 0x6659, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2638 vmulpd, 0x6659, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2639 vsubpd, 0x665C, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2640 vsubpd, 0x665C, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2641
2642 vaddps, 0x58, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2643 vaddps, 0x58, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2644 vdivps, 0x5E, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2645 vdivps, 0x5E, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2646 vmulps, 0x59, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2647 vmulps, 0x59, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2648 vsubps, 0x5C, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2649 vsubps, 0x5C, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2650
2651 vaddsd, 0xF258, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=0|VexVVVV|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
2652 vaddsd, 0xF258, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
2653 vdivsd, 0xF25E, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=0|VexVVVV|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
2654 vdivsd, 0xF25E, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
2655 vmulsd, 0xF259, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=0|VexVVVV|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
2656 vmulsd, 0xF259, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
2657 vsqrtsd, 0xF251, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=0|VexVVVV|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
2658 vsqrtsd, 0xF251, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
2659 vsubsd, 0xF25C, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=0|VexVVVV|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
2660 vsubsd, 0xF25C, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
2661
2662 vaddss, 0xF358, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=0|VexVVVV|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
2663 vaddss, 0xF358, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
2664 vdivss, 0xF35E, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=0|VexVVVV|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
2665 vdivss, 0xF35E, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
2666 vmulss, 0xF359, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=0|VexVVVV|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
2667 vmulss, 0xF359, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
2668 vsqrtss, 0xF351, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=0|VexVVVV|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
2669 vsqrtss, 0xF351, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
2670 vsubss, 0xF35C, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=0|VexVVVV|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
2671 vsubss, 0xF35C, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
2672
2673 valignd, 0x6603, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2674 vpternlogd, 0x6625, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2675
2676 valignq, 0x6603, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2677 vpternlogq, 0x6625, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2678
2679 vblendmpd, 0x6665, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2680 vpblendmq, 0x6664, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2681 vpermi2pd, 0x6677, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2682 vpermi2q, 0x6676, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2683 vpermt2pd, 0x667F, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2684 vpermt2q, 0x667E, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2685 vpmaxsq, 0x663D, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2686 vpmaxuq, 0x663F, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2687 vpminsq, 0x6639, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2688 vpminuq, 0x663B, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2689 vpmuldq, 0x6628, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2690 vprolvq, 0x6615, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2691 vprorvq, 0x6614, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2692 vpsllvq, 0x6647, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2693 vpsravq, 0x6646, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2694 vpsrlvq, 0x6645, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2695
2696 vblendmps, 0x6665, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2697 vpblendmd, 0x6664, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2698 vpermi2d, 0x6676, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2699 vpermi2ps, 0x6677, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2700 vpermt2d, 0x667E, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2701 vpermt2ps, 0x667F, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2702 vpmaxsd, 0x663D, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2703 vpmaxud, 0x663F, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2704 vpminsd, 0x6639, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2705 vpminud, 0x663B, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2706 vpmulld, 0x6640, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2707 vprolvd, 0x6615, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2708 vprorvd, 0x6614, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2709 vpsllvd, 0x6647, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2710 vpsravd, 0x6646, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2711 vpsrlvd, 0x6645, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2712
2713 vbroadcastf32x4, 0x661A, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM }
2714 vbroadcasti32x4, 0x665A, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM }
2715
2716 vbroadcastf64x4, 0x661B, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexW=2|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { YMMword|Unspecified|BaseIndex, RegZMM }
2717 vbroadcasti64x4, 0x665B, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexW=2|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { YMMword|Unspecified|BaseIndex, RegZMM }
2718
2719 vbroadcastss, 0x6618, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
2720 vbroadcastsd, 0x6619, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM }
2721
2722 vpbroadcastd, 0x6658, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
2723 vpbroadcastd, 0x667C, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegXMM|RegYMM|RegZMM }
2724
2725 vcmp<avx_frel>pd, 0x66C2, 0x<avx_frel:imm>, 1, CpuAVX512F, Modrm|Masking=2|OpcodePrefix=0|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
2726 vcmp<avx_frel>pd, 0x66C2, 0x<avx_frel:imm>, 1, CpuAVX512F, Modrm|EVex512|Masking=2|OpcodePrefix=0|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { Imm8, RegZMM, RegZMM, RegMask }
2727 vcmppd, 0x66C2, None, 1, CpuAVX512F, Modrm|Masking=2|OpcodePrefix=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
2728 vcmppd, 0x66C2, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|OpcodePrefix=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, Imm8, RegZMM, RegZMM, RegMask }
2729
2730 vcmp<avx_frel>ps, 0xC2, 0x<avx_frel:imm>, 1, CpuAVX512F, Modrm|Masking=2|OpcodePrefix=0|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
2731 vcmp<avx_frel>ps, 0xC2, 0x<avx_frel:imm>, 1, CpuAVX512F, Modrm|EVex512|Masking=2|OpcodePrefix=0|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { Imm8, RegZMM, RegZMM, RegMask }
2732 vcmpps, 0xC2, None, 1, CpuAVX512F, Modrm|Masking=2|OpcodePrefix=0|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
2733 vcmpps, 0xC2, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, Imm8, RegZMM, RegZMM, RegMask }
2734
2735 vcmp<avx_frel>sd, 0xF2C2, 0x<avx_frel:imm>, 1, CpuAVX512F, Modrm|EVexLIG|Masking=2|OpcodePrefix=0|VexVVVV|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegMask }
2736 vcmp<avx_frel>sd, 0xF2C2, 0x<avx_frel:imm>, 1, CpuAVX512F, Modrm|EVexLIG|Masking=2|OpcodePrefix=0|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { Imm8, RegXMM, RegXMM, RegMask }
2737 vcmpsd, 0xF2C2, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=2|OpcodePrefix=0|VexVVVV|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegMask }
2738 vcmpsd, 0xF2C2, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=2|OpcodePrefix=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, Imm8, RegXMM, RegXMM, RegMask }
2739
2740 vcmp<avx_frel>ss, 0xF3C2, 0x<avx_frel:imm>, 1, CpuAVX512F, Modrm|EVexLIG|Masking=2|OpcodePrefix=0|VexVVVV|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegMask }
2741 vcmp<avx_frel>ss, 0xF3C2, 0x<avx_frel:imm>, 1, CpuAVX512F, Modrm|EVexLIG|Masking=2|OpcodePrefix=0|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { Imm8, RegXMM, RegXMM, RegMask }
2742 vcmpss, 0xF3C2, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=2|OpcodePrefix=0|VexVVVV|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegMask }
2743 vcmpss, 0xF3C2, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=2|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, Imm8, RegXMM, RegXMM, RegMask }
2744
2745 vcomisd, 0x662F, None, 1, CpuAVX512F, Modrm|EVex=4|OpcodePrefix=0|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
2746 vcomisd, 0x662F, None, 1, CpuAVX512F, Modrm|EVex=4|OpcodePrefix=0|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM, RegXMM }
2747 vucomisd, 0x662E, None, 1, CpuAVX512F, Modrm|EVex=4|OpcodePrefix=0|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
2748 vucomisd, 0x662E, None, 1, CpuAVX512F, Modrm|EVex=4|OpcodePrefix=0|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM, RegXMM }
2749
2750 vcomiss, 0x2F, None, 1, CpuAVX512F, Modrm|EVex=4|OpcodePrefix=0|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM }
2751 vcomiss, 0x2F, None, 1, CpuAVX512F, Modrm|EVex=4|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM, RegXMM }
2752 vucomiss, 0x2E, None, 1, CpuAVX512F, Modrm|EVex=4|OpcodePrefix=0|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM }
2753 vucomiss, 0x2E, None, 1, CpuAVX512F, Modrm|EVex=4|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM, RegXMM }
2754
2755 vcompresspd, 0x668A, None, 1, CpuAVX512F, Modrm|MaskingMorZ|OpcodePrefix=1|VexW=2|Disp8MemShift=3|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex }
2756 vcompressps, 0x668A, None, 1, CpuAVX512F, Modrm|MaskingMorZ|OpcodePrefix=1|VexW=1|Disp8MemShift=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex }
2757 vpcompressq, 0x668B, None, 1, CpuAVX512F, Modrm|MaskingMorZ|OpcodePrefix=1|VexW=2|Disp8MemShift=3|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex }
2758 vpcompressd, 0x668B, None, 1, CpuAVX512F, Modrm|MaskingMorZ|OpcodePrefix=1|VexW=1|Disp8MemShift=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex }
2759
2760 vpscatterdq, 0x66A0, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|OpcodePrefix=1|VexW1|Disp8MemShift=3|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, Dword|Unspecified|BaseIndex }
2761 vpscatterqq, 0x66A1, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|OpcodePrefix=1|VexW1|Disp8MemShift=3|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, Dword|Unspecified|BaseIndex }
2762 vscatterdpd, 0x66A2, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|OpcodePrefix=1|VexW1|Disp8MemShift=3|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, Dword|Unspecified|BaseIndex }
2763 vscatterqpd, 0x66A3, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|OpcodePrefix=1|VexW1|Disp8MemShift=3|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, Dword|Unspecified|BaseIndex }
2764
2765 vpscatterdd, 0x66A0, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|OpcodePrefix=1|VexW0|Disp8MemShift=2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, Dword|Unspecified|BaseIndex }
2766 vscatterdps, 0x66A2, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|OpcodePrefix=1|VexW0|Disp8MemShift=2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, Dword|Unspecified|BaseIndex }
2767
2768 vcvtdq2pd, 0xF3E6, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=1|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM }
2769 vcvtudq2pd, 0xF37A, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=1|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM }
2770
2771 vcvtdq2ps, 0x5B, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
2772 vcvtdq2ps, 0x5B, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM }
2773 vcvtps2udq, 0x79, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
2774 vcvtps2udq, 0x79, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM }
2775 vsqrtps, 0x51, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
2776 vsqrtps, 0x51, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM }
2777
2778 vcvtpd2dq, 0xF2E6, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8MemShift=6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Qword|Unspecified|BaseIndex, RegYMM }
2779 vcvtpd2dq, 0xF2E6, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegYMM }
2780
2781 vcvtpd2ps, 0x665A, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8MemShift=6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Qword|Unspecified|BaseIndex, RegYMM }
2782 vcvtpd2ps, 0x665A, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegYMM }
2783
2784 vcvtpd2udq, 0x79, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8MemShift=6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Qword|Unspecified|BaseIndex, RegYMM }
2785 vcvtpd2udq, 0x79, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegYMM }
2786
2787 vcvtph2ps, 0x6613, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexW=1|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Unspecified|BaseIndex, RegZMM }
2788 vcvtph2ps, 0x6613, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegYMM, RegZMM }
2789
2790 vcvtps2dq, 0x665B, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
2791 vcvtps2dq, 0x665B, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM }
2792
2793 vcvtps2pd, 0x5A, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=1|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM }
2794 vcvtps2pd, 0x5A, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegYMM, RegZMM }
2795
2796 vcvtps2ph, 0x661D, None, 1, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|OpcodePrefix=2|VexW=1|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex }
2797 vcvtps2ph, 0x661D, None, 1, CpuAVX512F, RegMem|EVex=1|Masking=3|OpcodePrefix=2|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, Imm8, RegZMM, RegYMM }
2798
2799 vcvtsd2si, 0xF22D, None, 1, CpuAVX512F, Modrm|EVex=4|OpcodePrefix=0|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToDword, { RegXMM|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
2800 vcvtsd2si, 0xF22D, None, 1, CpuAVX512F, Modrm|EVex=4|OpcodePrefix=0|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, Reg32|Reg64 }
2801 vcvtsd2usi, 0xF279, None, 1, CpuAVX512F, Modrm|EVex=4|OpcodePrefix=0|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ToDword, { RegXMM|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
2802 vcvtsd2usi, 0xF279, None, 1, CpuAVX512F, Modrm|EVex=4|OpcodePrefix=0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, Reg32|Reg64 }
2803
2804 vcvtsd2ss, 0xF25A, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=0|VexVVVV|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
2805 vcvtsd2ss, 0xF25A, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
2806
2807 vcvtsi2sd, 0xF22A, None, 1, CpuAVX512F, Modrm|EVexLIG|OpcodePrefix=0|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
2808 vcvtsi2sd, 0xF22A, None, 1, CpuAVX512F, Modrm|EVexLIG|OpcodePrefix=0|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
2809 vcvtsi2sd, 0xF22A, None, 1, CpuAVX512F, Modrm|EVexLIG|OpcodePrefix=0|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|StaticRounding|SAE, { Reg64, Imm8, RegXMM, RegXMM }
2810 vcvtsi2sd, 0xF22A, None, 1, CpuAVX512F, Modrm|EVexLIG|OpcodePrefix=0|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Imm8, Reg64, RegXMM, RegXMM }
2811 vcvtusi2sd, 0xF27B, None, 1, CpuAVX512F, Modrm|EVexLIG|OpcodePrefix=0|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
2812 vcvtusi2sd, 0xF27B, None, 1, CpuAVX512F, Modrm|EVexLIG|OpcodePrefix=0|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
2813 vcvtusi2sd, 0xF27B, None, 1, CpuAVX512F, Modrm|EVexLIG|OpcodePrefix=0|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|StaticRounding|SAE, { Reg64, Imm8, RegXMM, RegXMM }
2814 vcvtusi2sd, 0xF27B, None, 1, CpuAVX512F, Modrm|EVexLIG|OpcodePrefix=0|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Imm8, Reg64, RegXMM, RegXMM }
2815
2816 vcvtsi2ss, 0xF32A, None, 1, CpuAVX512F, Modrm|EVexLIG|OpcodePrefix=0|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
2817 vcvtsi2ss, 0xF32A, None, 1, CpuAVX512F, Modrm|EVexLIG|OpcodePrefix=0|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
2818 vcvtsi2ss, 0xF32A, None, 1, CpuAVX512F, Modrm|EVexLIG|OpcodePrefix=0|VexVVVV|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE, { Reg32|Reg64, Imm8, RegXMM, RegXMM }
2819 vcvtsi2ss, 0xF32A, None, 1, CpuAVX512F, Modrm|EVexLIG|OpcodePrefix=0|VexVVVV|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Imm8, Reg32|Reg64, RegXMM, RegXMM }
2820 vcvtusi2ss, 0xF37B, None, 1, CpuAVX512F, Modrm|EVexLIG|OpcodePrefix=0|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
2821 vcvtusi2ss, 0xF37B, None, 1, CpuAVX512F, Modrm|EVexLIG|OpcodePrefix=0|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
2822 vcvtusi2ss, 0xF37B, None, 1, CpuAVX512F, Modrm|EVexLIG|OpcodePrefix=0|VexVVVV|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE, { Reg32|Reg64, Imm8, RegXMM, RegXMM }
2823 vcvtusi2ss, 0xF37B, None, 1, CpuAVX512F, Modrm|EVexLIG|OpcodePrefix=0|VexVVVV|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Imm8, Reg32|Reg64, RegXMM, RegXMM }
2824
2825 vcvtss2sd, 0xF35A, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=0|VexVVVV|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
2826 vcvtss2sd, 0xF35A, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
2827
2828 vcvtss2si, 0xF32D, None, 1, CpuAVX512F, Modrm|EVex=4|OpcodePrefix=0|Disp8MemShift=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToQword, { RegXMM|Dword|Unspecified|BaseIndex, Reg32|Reg64 }
2829 vcvtss2si, 0xF32D, None, 1, CpuAVX512F, Modrm|EVex=4|OpcodePrefix=0|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, Reg32|Reg64 }
2830 vcvtss2usi, 0xF379, None, 1, CpuAVX512F, Modrm|EVex=4|OpcodePrefix=0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ToQword, { RegXMM|Dword|Unspecified|BaseIndex, Reg32|Reg64 }
2831 vcvtss2usi, 0xF379, None, 1, CpuAVX512F, Modrm|EVex=4|OpcodePrefix=0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, Reg32|Reg64 }
2832
2833 vcvttpd2dq, 0x66E6, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8MemShift=6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegYMM }
2834 vcvttpd2dq, 0x66E6, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegZMM, RegYMM }
2835 vcvttpd2udq, 0x78, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8MemShift=6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegYMM }
2836 vcvttpd2udq, 0x78, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegZMM, RegYMM }
2837
2838 vcvttps2dq, 0xF35B, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
2839 vcvttps2dq, 0xF35B, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegZMM, RegZMM }
2840 vcvttps2udq, 0x78, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
2841 vcvttps2udq, 0x78, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegZMM, RegZMM }
2842
2843 vcvttsd2si, 0xF22C, None, 1, CpuAVX512F, Modrm|EVex=4|OpcodePrefix=0|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToDword, { RegXMM|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
2844 vcvttsd2si, 0xF22C, None, 1, CpuAVX512F, Modrm|EVex=4|OpcodePrefix=0|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SAE, { Imm8, RegXMM, Reg32|Reg64 }
2845 vcvttsd2usi, 0xF278, None, 1, CpuAVX512F, Modrm|EVex=4|OpcodePrefix=0|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ToDword, { RegXMM|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
2846 vcvttsd2usi, 0xF278, None, 1, CpuAVX512F, Modrm|EVex=4|OpcodePrefix=0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM, Reg32|Reg64 }
2847
2848 vcvttss2si, 0xF32C, None, 1, CpuAVX512F, Modrm|EVex=4|OpcodePrefix=0|Disp8MemShift=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToQword, { RegXMM|Dword|Unspecified|BaseIndex, Reg32|Reg64 }
2849 vcvttss2si, 0xF32C, None, 1, CpuAVX512F, Modrm|EVex=4|OpcodePrefix=0|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SAE, { Imm8, RegXMM, Reg32|Reg64 }
2850 vcvttss2usi, 0xF378, None, 1, CpuAVX512F, Modrm|EVex=4|OpcodePrefix=0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ToQword, { RegXMM|Dword|Unspecified|BaseIndex, Reg32|Reg64 }
2851 vcvttss2usi, 0xF378, None, 1, CpuAVX512F, Modrm|EVex=4|OpcodePrefix=0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM, Reg32|Reg64 }
2852
2853 vcvtudq2ps, 0xF27A, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
2854 vcvtudq2ps, 0xF27A, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM }
2855
2856 vexpandpd, 0x6688, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexW=2|Disp8MemShift=3|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
2857 vpexpandq, 0x6689, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexW=2|Disp8MemShift=3|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
2858
2859 vexpandps, 0x6688, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexW=1|Disp8MemShift=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
2860 vpexpandd, 0x6689, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexW=1|Disp8MemShift=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
2861
2862 vextractf32x4, 0x6619, None, 1, CpuAVX512F, Modrm|MaskingMorZ|OpcodePrefix=2|VexW=1|Disp8MemShift=4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex }
2863 vextracti32x4, 0x6639, None, 1, CpuAVX512F, Modrm|MaskingMorZ|OpcodePrefix=2|VexW=1|Disp8MemShift=4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex }
2864
2865 vextractf64x4, 0x661B, None, 1, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|OpcodePrefix=2|VexW=2|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex }
2866 vextracti64x4, 0x663B, None, 1, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|OpcodePrefix=2|VexW=2|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex }
2867
2868 vextractps, 0x6617, None, 1, CpuAVX512F, Modrm|EVex128|OpcodePrefix=2|VexWIG|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex }
2869 vextractps, 0x6617, None, 1, CpuAVX512F|Cpu64, RegMem|EVex128|OpcodePrefix=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg64 }
2870
2871 vfixupimmpd, 0x6654, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2872 vfixupimmpd, 0x6654, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, Imm8, RegZMM, RegZMM, RegZMM }
2873
2874 vfixupimmps, 0x6654, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2875 vfixupimmps, 0x6654, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, Imm8, RegZMM, RegZMM, RegZMM }
2876
2877 vfixupimmsd, 0x6655, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=2|VexVVVV|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
2878 vfixupimmsd, 0x6655, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, Imm8, RegXMM, RegXMM, RegXMM }
2879 vgetmantsd, 0x6627, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=2|VexVVVV|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
2880 vgetmantsd, 0x6627, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, Imm8, RegXMM, RegXMM, RegXMM }
2881 vrndscalesd, 0x660B, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=2|VexVVVV|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
2882 vrndscalesd, 0x660B, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, Imm8, RegXMM, RegXMM, RegXMM }
2883
2884 vfixupimmss, 0x6655, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=2|VexVVVV|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
2885 vfixupimmss, 0x6655, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, Imm8, RegXMM, RegXMM, RegXMM }
2886 vgetmantss, 0x6627, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=2|VexVVVV|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
2887 vgetmantss, 0x6627, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, Imm8, RegXMM, RegXMM, RegXMM }
2888 vrndscaless, 0x660A, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=2|VexVVVV|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
2889 vrndscaless, 0x660A, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, Imm8, RegXMM, RegXMM, RegXMM }
2890
2891 vfmadd132pd, 0x6698, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2892 vfmadd132pd, 0x6698, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2893 vfmadd213pd, 0x66A8, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2894 vfmadd213pd, 0x66A8, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2895 vfmadd231pd, 0x66B8, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2896 vfmadd231pd, 0x66B8, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2897 vfmaddsub132pd, 0x6696, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2898 vfmaddsub132pd, 0x6696, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2899 vfmaddsub213pd, 0x66A6, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2900 vfmaddsub213pd, 0x66A6, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2901 vfmaddsub231pd, 0x66B6, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2902 vfmaddsub231pd, 0x66B6, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2903 vfmsub132pd, 0x669A, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2904 vfmsub132pd, 0x669A, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2905 vfmsub213pd, 0x66AA, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2906 vfmsub213pd, 0x66AA, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2907 vfmsub231pd, 0x66BA, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2908 vfmsub231pd, 0x66BA, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2909 vfmsubadd132pd, 0x6697, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2910 vfmsubadd132pd, 0x6697, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2911 vfmsubadd213pd, 0x66A7, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2912 vfmsubadd213pd, 0x66A7, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2913 vfmsubadd231pd, 0x66B7, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2914 vfmsubadd231pd, 0x66B7, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2915 vfnmadd132pd, 0x669C, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2916 vfnmadd132pd, 0x669C, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2917 vfnmadd213pd, 0x66AC, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2918 vfnmadd213pd, 0x66AC, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2919 vfnmadd231pd, 0x66BC, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2920 vfnmadd231pd, 0x66BC, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2921 vfnmsub132pd, 0x669E, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2922 vfnmsub132pd, 0x669E, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2923 vfnmsub213pd, 0x66AE, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2924 vfnmsub213pd, 0x66AE, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2925 vfnmsub231pd, 0x66BE, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2926 vfnmsub231pd, 0x66BE, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2927 vscalefpd, 0x662C, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2928 vscalefpd, 0x662C, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2929
2930 vfmadd132ps, 0x6698, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2931 vfmadd132ps, 0x6698, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2932 vfmadd213ps, 0x66A8, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2933 vfmadd213ps, 0x66A8, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2934 vfmadd231ps, 0x66B8, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2935 vfmadd231ps, 0x66B8, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2936 vfmaddsub132ps, 0x6696, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2937 vfmaddsub132ps, 0x6696, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2938 vfmaddsub213ps, 0x66A6, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2939 vfmaddsub213ps, 0x66A6, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2940 vfmaddsub231ps, 0x66B6, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2941 vfmaddsub231ps, 0x66B6, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2942 vfmsub132ps, 0x669A, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2943 vfmsub132ps, 0x669A, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2944 vfmsub213ps, 0x66AA, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2945 vfmsub213ps, 0x66AA, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2946 vfmsub231ps, 0x66BA, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2947 vfmsub231ps, 0x66BA, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2948 vfmsubadd132ps, 0x6697, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2949 vfmsubadd132ps, 0x6697, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2950 vfmsubadd213ps, 0x66A7, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2951 vfmsubadd213ps, 0x66A7, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2952 vfmsubadd231ps, 0x66B7, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2953 vfmsubadd231ps, 0x66B7, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2954 vfnmadd132ps, 0x669C, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2955 vfnmadd132ps, 0x669C, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2956 vfnmadd213ps, 0x66AC, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2957 vfnmadd213ps, 0x66AC, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2958 vfnmadd231ps, 0x66BC, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2959 vfnmadd231ps, 0x66BC, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2960 vfnmsub132ps, 0x669E, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2961 vfnmsub132ps, 0x669E, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2962 vfnmsub213ps, 0x66AE, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2963 vfnmsub213ps, 0x66AE, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2964 vfnmsub231ps, 0x66BE, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2965 vfnmsub231ps, 0x66BE, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2966 vscalefps, 0x662C, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
2967 vscalefps, 0x662C, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
2968
2969 vfmadd132sd, 0x6699, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
2970 vfmadd132sd, 0x6699, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
2971 vfmadd213sd, 0x66A9, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
2972 vfmadd213sd, 0x66A9, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
2973 vfmadd231sd, 0x66B9, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
2974 vfmadd231sd, 0x66B9, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
2975 vfmsub132sd, 0x669B, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
2976 vfmsub132sd, 0x669B, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
2977 vfmsub213sd, 0x66AB, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
2978 vfmsub213sd, 0x66AB, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
2979 vfmsub231sd, 0x66BB, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
2980 vfmsub231sd, 0x66BB, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
2981 vfnmadd132sd, 0x669D, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
2982 vfnmadd132sd, 0x669D, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
2983 vfnmadd213sd, 0x66AD, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
2984 vfnmadd213sd, 0x66AD, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
2985 vfnmadd231sd, 0x66BD, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
2986 vfnmadd231sd, 0x66BD, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
2987 vfnmsub132sd, 0x669F, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
2988 vfnmsub132sd, 0x669F, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
2989 vfnmsub213sd, 0x66AF, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
2990 vfnmsub213sd, 0x66AF, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
2991 vfnmsub231sd, 0x66BF, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
2992 vfnmsub231sd, 0x66BF, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
2993 vscalefsd, 0x662D, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
2994 vscalefsd, 0x662D, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
2995
2996 vfmadd132ss, 0x6699, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
2997 vfmadd132ss, 0x6699, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
2998 vfmadd213ss, 0x66A9, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
2999 vfmadd213ss, 0x66A9, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
3000 vfmadd231ss, 0x66B9, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
3001 vfmadd231ss, 0x66B9, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
3002 vfmsub132ss, 0x669B, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
3003 vfmsub132ss, 0x669B, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
3004 vfmsub213ss, 0x66AB, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
3005 vfmsub213ss, 0x66AB, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
3006 vfmsub231ss, 0x66BB, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
3007 vfmsub231ss, 0x66BB, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
3008 vfnmadd132ss, 0x669D, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
3009 vfnmadd132ss, 0x669D, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
3010 vfnmadd213ss, 0x66AD, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
3011 vfnmadd213ss, 0x66AD, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
3012 vfnmadd231ss, 0x66BD, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
3013 vfnmadd231ss, 0x66BD, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
3014 vfnmsub132ss, 0x669F, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
3015 vfnmsub132ss, 0x669F, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
3016 vfnmsub213ss, 0x66AF, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
3017 vfnmsub213ss, 0x66AF, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
3018 vfnmsub231ss, 0x66BF, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
3019 vfnmsub231ss, 0x66BF, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
3020 vscalefss, 0x662D, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
3021 vscalefss, 0x662D, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
3022
3023 vgatherdpd, 0x6692, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|OpcodePrefix=1|VexW1|Disp8MemShift=3|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegZMM }
3024 vgatherqpd, 0x6693, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|OpcodePrefix=1|VexW1|Disp8MemShift=3|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegZMM }
3025 vpgatherdq, 0x6690, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|OpcodePrefix=1|VexW1|Disp8MemShift=3|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegZMM }
3026 vpgatherqq, 0x6691, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|OpcodePrefix=1|VexW1|Disp8MemShift=3|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegZMM }
3027
3028 vgatherdps, 0x6692, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|OpcodePrefix=1|VexW0|Disp8MemShift=2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegZMM }
3029 vmovntdqa, 0x662A, None, 1, CpuAVX512F, Modrm|OpcodePrefix=1|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { XMMword|YMMword|ZMMword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3030 vpgatherdd, 0x6690, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|OpcodePrefix=1|VexW0|Disp8MemShift=2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegZMM }
3031
3032 vgatherqps, 0x6693, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|OpcodePrefix=1|VexW0|Disp8MemShift=2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegYMM }
3033 vpgatherqd, 0x6691, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|OpcodePrefix=1|VexW0|Disp8MemShift=2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegYMM }
3034
3035 vgetexppd, 0x6642, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3036 vgetexppd, 0x6642, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegZMM, RegZMM }
3037
3038 vgetexpps, 0x6642, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3039 vgetexpps, 0x6642, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegZMM, RegZMM }
3040
3041 vgetexpsd, 0x6643, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
3042 vgetexpsd, 0x6643, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
3043
3044 vgetexpss, 0x6643, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
3045 vgetexpss, 0x6643, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
3046
3047 vgetmantpd, 0x6626, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=2|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3048 vgetmantpd, 0x6626, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=2|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, Imm8, RegZMM, RegZMM }
3049 vrndscalepd, 0x6609, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=2|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3050 vrndscalepd, 0x6609, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=2|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, Imm8, RegZMM, RegZMM }
3051
3052 vgetmantps, 0x6626, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=2|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3053 vgetmantps, 0x6626, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=2|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, Imm8, RegZMM, RegZMM }
3054 vrndscaleps, 0x6608, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=2|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3055 vrndscaleps, 0x6608, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=2|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, Imm8, RegZMM, RegZMM }
3056
3057 vinsertf32x4, 0x6618, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=1|Disp8MemShift=4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
3058 vinserti32x4, 0x6638, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=1|Disp8MemShift=4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
3059
3060 vinsertf64x4, 0x661A, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=2|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM }
3061 vinserti64x4, 0x663A, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=2|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM }
3062
3063 vinsertps, 0x6621, None, 1, CpuAVX512F, Modrm|EVex128|OpcodePrefix=2|VexVVVV|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
3064
3065 vmaxpd, 0x665F, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3066 vmaxpd, 0x665F, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
3067 vminpd, 0x665D, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3068 vminpd, 0x665D, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
3069
3070 vmaxps, 0x5F, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3071 vmaxps, 0x5F, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
3072 vminps, 0x5D, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3073 vminps, 0x5D, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegZMM, RegZMM, RegZMM }
3074
3075 vmaxsd, 0xF25F, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=0|VexVVVV|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
3076 vmaxsd, 0xF25F, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
3077 vminsd, 0xF25D, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=0|VexVVVV|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
3078 vminsd, 0xF25D, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
3079
3080 vmaxss, 0xF35F, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=0|VexVVVV|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
3081 vmaxss, 0xF35F, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
3082 vminss, 0xF35D, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=0|VexVVVV|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
3083 vminss, 0xF35D, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
3084
3085 vmovapd, 0x6628, None, 1, CpuAVX512F, D|Modrm|MaskingMorZ|OpcodePrefix=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3086 vmovntpd, 0x662B, None, 1, CpuAVX512F, Modrm|OpcodePrefix=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, XMMword|YMMword|ZMMword|Unspecified|BaseIndex }
3087 vmovupd, 0x6610, None, 1, CpuAVX512F, D|Modrm|Load|MaskingMorZ|OpcodePrefix=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3088
3089 vmovaps, 0x28, None, 1, CpuAVX512F, D|Modrm|MaskingMorZ|OpcodePrefix=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3090 vmovntps, 0x2B, None, 1, CpuAVX512F, Modrm|OpcodePrefix=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, XMMword|YMMword|ZMMword|Unspecified|BaseIndex }
3091 vmovups, 0x10, None, 1, CpuAVX512F, D|Modrm|MaskingMorZ|OpcodePrefix=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3092
3093 vmovd, 0x666E, None, 1, CpuAVX512F, D|Modrm|EVex=2|OpcodePrefix=0|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, RegXMM }
3094
3095 vmovddup, 0xF212, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|RegZMM|Unspecified|BaseIndex, RegYMM|RegZMM }
3096
3097 vmovdqa64, 0x666F, None, 1, CpuAVX512F, D|Modrm|MaskingMorZ|OpcodePrefix=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3098 vmovdqa32, 0x666F, None, 1, CpuAVX512F, D|Modrm|MaskingMorZ|OpcodePrefix=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3099 vmovntdq, 0x66E7, None, 1, CpuAVX512F, Modrm|OpcodePrefix=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, XMMword|YMMword|ZMMword|Unspecified|BaseIndex }
3100 vmovdqu32, 0xF36F, None, 1, CpuAVX512F, D|Modrm|MaskingMorZ|OpcodePrefix=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3101 vmovdqu64, 0xF36F, None, 1, CpuAVX512F, D|Modrm|MaskingMorZ|OpcodePrefix=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3102
3103 vmovhlps, 0x12, None, 1, CpuAVX512F, Modrm|EVex=4|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
3104 vmovlhps, 0x16, None, 1, CpuAVX512F, Modrm|EVex=4|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
3105
3106 vmovhpd, 0x6616, None, 1, CpuAVX512F, Modrm|EVex=4|OpcodePrefix=0|VexVVVV=1|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
3107 vmovhpd, 0x6617, None, 1, CpuAVX512F, Modrm|EVex=4|OpcodePrefix=0|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex }
3108 vmovlpd, 0x6612, None, 1, CpuAVX512F, Modrm|EVex=4|OpcodePrefix=0|VexVVVV=1|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
3109 vmovlpd, 0x6613, None, 1, CpuAVX512F, Modrm|EVex=4|OpcodePrefix=0|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex }
3110
3111 vmovhps, 0x16, None, 1, CpuAVX512F, Modrm|EVex=4|OpcodePrefix=0|VexVVVV=1|VexW=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
3112 vmovhps, 0x17, None, 1, CpuAVX512F, Modrm|EVex=4|OpcodePrefix=0|VexW=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex }
3113 vmovlps, 0x12, None, 1, CpuAVX512F, Modrm|EVex=4|OpcodePrefix=0|VexVVVV=1|VexW=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
3114 vmovlps, 0x13, None, 1, CpuAVX512F, Modrm|EVex=4|OpcodePrefix=0|VexW=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex }
3115
3116 vmovq, 0x666E, None, 1, CpuAVX512F|Cpu64, D|Modrm|EVex=2|OpcodePrefix=0|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg64|Unspecified|BaseIndex, RegXMM }
3117 vmovq, 0xF37E, None, 1, CpuAVX512F, Load|Modrm|EVex=2|OpcodePrefix=0|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
3118 vmovq, 0x66D6, None, 1, CpuAVX512F, Modrm|EVex=2|OpcodePrefix=0|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM }
3119
3120 vmovsd, 0xF210, None, 1, CpuAVX512F, D|Modrm|EVex=4|MaskingMorZ|OpcodePrefix=0|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
3121 vmovsd, 0xF210, None, 1, CpuAVX512F, D|Modrm|EVex=4|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
3122
3123 vmovshdup, 0xF316, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3124 vmovsldup, 0xF312, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3125
3126 vmovss, 0xF310, None, 1, CpuAVX512F, D|Modrm|EVex=4|MaskingMorZ|OpcodePrefix=0|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM }
3127 vmovss, 0xF310, None, 1, CpuAVX512F, D|Modrm|EVex=4|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
3128
3129 vpabsd, 0x661E, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3130 vrcp14ps, 0x664C, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3131 vrsqrt14ps, 0x664E, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3132
3133 vpabsq, 0x661F, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3134 vrcp14pd, 0x664C, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3135 vrsqrt14pd, 0x664E, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3136
3137 vpaddd, 0x66FE, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3138 vpandd, 0x66DB, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3139 vpandnd, 0x66DF, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3140 vpord, 0x66EB, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3141 vpsubd, 0x66FA, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3142 vpunpckhdq, 0x666A, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3143 vpunpckldq, 0x6662, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3144 vpxord, 0x66EF, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3145
3146 vpaddq, 0x66D4, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3147 vpandnq, 0x66DF, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3148 vpandq, 0x66DB, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3149 vpmuludq, 0x66F4, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3150 vporq, 0x66EB, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3151 vpsubq, 0x66FB, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3152 vpunpckhqdq, 0x666D, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3153 vpunpcklqdq, 0x666C, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3154 vpxorq, 0x66EF, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3155 vunpckhpd, 0x6615, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3156 vunpcklpd, 0x6614, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3157
3158 vpbroadcastq, 0x6659, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3159 vpbroadcastq, 0x667C, None, 1, CpuAVX512F|Cpu64, Modrm|Masking=3|OpcodePrefix=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg64, RegXMM|RegYMM|RegZMM }
3160
3161 <avx_irel:imm, eq:0, lt:1, le:2, neq:4, nlt:5, nle:6>
3162
3163 vpcmpeqd, 0x6676, None, 1, CpuAVX512F, Modrm|Masking=2|OpcodePrefix=0|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
3164 vpcmpgtd, 0x6666, None, 1, CpuAVX512F, Modrm|Masking=2|OpcodePrefix=0|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
3165 vpcmpd, 0x661F, None, 1, CpuAVX512F, Modrm|Masking=2|OpcodePrefix=2|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
3166 vpcmp<avx_irel>d, 0x661F, <avx_irel:imm>, 1, CpuAVX512F, Modrm|Masking=2|OpcodePrefix=2|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
3167 vpcmpud, 0x661E, None, 1, CpuAVX512F, Modrm|Masking=2|OpcodePrefix=2|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
3168 vpcmp<avx_irel>ud, 0x661E, <avx_irel:imm>, 1, CpuAVX512F, Modrm|Masking=2|OpcodePrefix=2|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
3169
3170 vpcmpeqq, 0x6629, None, 1, CpuAVX512F, Modrm|Masking=2|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
3171 vpcmpgtq, 0x6637, None, 1, CpuAVX512F, Modrm|Masking=2|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
3172 vpcmpq, 0x661F, None, 1, CpuAVX512F, Modrm|Masking=2|OpcodePrefix=2|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
3173 vpcmp<avx_irel>q, 0x661F, <avx_irel:imm>, 1, CpuAVX512F, Modrm|Masking=2|OpcodePrefix=2|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
3174 vpcmpuq, 0x661E, None, 1, CpuAVX512F, Modrm|Masking=2|OpcodePrefix=2|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
3175 vpcmp<avx_irel>uq, 0x661E, <avx_irel:imm>, 1, CpuAVX512F, Modrm|Masking=2|OpcodePrefix=2|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
3176
3177 vptestmd, 0x6627, None, 1, CpuAVX512F, Modrm|Masking=2|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
3178 vptestnmd, 0xF327, None, 1, CpuAVX512F, Modrm|Masking=2|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
3179
3180 vptestmq, 0x6627, None, 1, CpuAVX512F, Modrm|Masking=2|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
3181 vptestnmq, 0xF327, None, 1, CpuAVX512F, Modrm|Masking=2|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
3182
3183 vpermd, 0x6636, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
3184 vpermps, 0x6616, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
3185
3186 vpermilpd, 0x6605, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=2|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3187 vpermilpd, 0x660D, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3188
3189 vpermilps, 0x6604, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=2|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3190 vpermilps, 0x660C, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3191
3192 vpermpd, 0x6601, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=2|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM }
3193 vpermpd, 0x6616, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
3194 vpermq, 0x6600, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=2|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM }
3195 vpermq, 0x6636, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
3196
3197 vpmovdb, 0xF331, None, 1, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|OpcodePrefix=1|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegXMM|Unspecified|BaseIndex }
3198 vpmovsdb, 0xF321, None, 1, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|OpcodePrefix=1|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegXMM|Unspecified|BaseIndex }
3199 vpmovusdb, 0xF311, None, 1, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|OpcodePrefix=1|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegXMM|Unspecified|BaseIndex }
3200
3201 vpmovdw, 0xF333, None, 1, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|OpcodePrefix=1|VexW=1|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegYMM|Unspecified|BaseIndex }
3202 vpmovsdw, 0xF323, None, 1, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|OpcodePrefix=1|VexW=1|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegYMM|Unspecified|BaseIndex }
3203 vpmovusdw, 0xF313, None, 1, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|OpcodePrefix=1|VexW=1|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegYMM|Unspecified|BaseIndex }
3204
3205 vpmovqb, 0xF332, None, 1, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|OpcodePrefix=1|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegXMM|Qword|Unspecified|BaseIndex }
3206 vpmovsqb, 0xF322, None, 1, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|OpcodePrefix=1|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegXMM|Qword|Unspecified|BaseIndex }
3207 vpmovusqb, 0xF312, None, 1, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|OpcodePrefix=1|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegXMM|Qword|Unspecified|BaseIndex }
3208
3209 vpmovqd, 0xF335, None, 1, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|OpcodePrefix=1|VexW=1|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegYMM|Unspecified|BaseIndex }
3210 vpmovsqd, 0xF325, None, 1, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|OpcodePrefix=1|VexW=1|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegYMM|Unspecified|BaseIndex }
3211 vpmovusqd, 0xF315, None, 1, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|OpcodePrefix=1|VexW=1|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegYMM|Unspecified|BaseIndex }
3212
3213 vpmovqw, 0xF334, None, 1, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|OpcodePrefix=1|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegXMM|Unspecified|BaseIndex }
3214 vpmovsqw, 0xF324, None, 1, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|OpcodePrefix=1|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegXMM|Unspecified|BaseIndex }
3215 vpmovusqw, 0xF314, None, 1, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|OpcodePrefix=1|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegXMM|Unspecified|BaseIndex }
3216
3217 vpmovsxbd, 0x6621, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexWIG|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegZMM }
3218 vpmovzxbd, 0x6631, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexWIG|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegZMM }
3219
3220 vpmovsxbq, 0x6622, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexWIG|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegZMM }
3221 vpmovzxbq, 0x6632, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexWIG|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegZMM }
3222
3223 vpmovsxdq, 0x6625, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexW=1|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Unspecified|BaseIndex, RegZMM }
3224 vpmovzxdq, 0x6635, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexW=1|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Unspecified|BaseIndex, RegZMM }
3225
3226 vpmovsxwd, 0x6623, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexWIG|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Unspecified|BaseIndex, RegZMM }
3227 vpmovzxwd, 0x6633, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexWIG|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Unspecified|BaseIndex, RegZMM }
3228
3229 vpmovsxwq, 0x6624, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexWIG|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegZMM }
3230 vpmovzxwq, 0x6634, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexWIG|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegZMM }
3231
3232 vprold, 0x6672, 1, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=2|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3233 vprord, 0x6672, 0, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=2|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3234
3235 vprolq, 0x6672, 1, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=2|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3236 vprorq, 0x6672, 0, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=2|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3237
3238 vpscatterqd, 0x66A1, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|OpcodePrefix=1|VexW0|Disp8MemShift=2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Dword|Unspecified|BaseIndex }
3239 vscatterqps, 0x66A3, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|OpcodePrefix=1|VexW0|Disp8MemShift=2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Dword|Unspecified|BaseIndex }
3240
3241 vpshufd, 0x6670, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3242
3243 vpslld, 0x66F2, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|Disp8MemShift=4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
3244 vpslld, 0x6672, 6, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=2|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3245 vpsrad, 0x66E2, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|Disp8MemShift=4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
3246 vpsrad, 0x6672, 4, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=2|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3247 vpsrld, 0x66D2, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|Disp8MemShift=4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
3248 vpsrld, 0x6672, 2, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=2|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3249
3250 vpsllq, 0x66F3, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|Disp8MemShift=4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
3251 vpsllq, 0x6673, 6, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=2|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3252 vpsraq, 0x66E2, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|Disp8MemShift=4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
3253 vpsraq, 0x6672, 4, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=2|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3254 vpsrlq, 0x66D3, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|Disp8MemShift=4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
3255 vpsrlq, 0x6673, 2, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=2|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3256
3257 vrcp14sd, 0x664D, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
3258 vrsqrt14sd, 0x664F, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
3259
3260 vrcp14ss, 0x664D, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
3261 vrsqrt14ss, 0x664F, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
3262
3263 vshuff32x4, 0x6623, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
3264 vshufi32x4, 0x6643, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
3265
3266 vshuff64x2, 0x6623, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
3267 vshufi64x2, 0x6643, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
3268
3269 vshufpd, 0x66C6, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3270
3271 vshufps, 0xC6, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3272
3273 vsqrtpd, 0x6651, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3274 vsqrtpd, 0x6651, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM }
3275
3276 vunpckhps, 0x15, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3277 vunpcklps, 0x14, None, 1, CpuAVX512F, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3278
3279 // AVX512F instructions end.
3280
3281 // AVX512CD instructions.
3282
3283 vpbroadcastmb2q, 0xF32A, None, 1, CpuAVX512CD, Modrm|OpcodePrefix=1|EVex=5|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegXMM|RegYMM|RegZMM }
3284 vpbroadcastmw2d, 0xF33A, None, 1, CpuAVX512CD, Modrm|OpcodePrefix=1|EVex=5|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegXMM|RegYMM|RegZMM }
3285
3286 vpconflictd, 0x66C4, None, 1, CpuAVX512CD, Modrm|Masking=3|OpcodePrefix=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3287 vpconflictq, 0x66C4, None, 1, CpuAVX512CD, Modrm|Masking=3|OpcodePrefix=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3288
3289 vplzcntd, 0x6644, None, 1, CpuAVX512CD, Modrm|Masking=3|OpcodePrefix=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3290 vplzcntq, 0x6644, None, 1, CpuAVX512CD, Modrm|Masking=3|OpcodePrefix=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3291
3292 // AVX512CD instructions end.
3293
3294 // AVX512ER instructions.
3295
3296 vexp2pd, 0x66C8, None, 1, CpuAVX512ER, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexW=2|Broadcast|Disp8MemShift=6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Qword|Unspecified|BaseIndex, RegZMM }
3297 vexp2pd, 0x66C8, None, 1, CpuAVX512ER, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegZMM, RegZMM }
3298
3299 vexp2ps, 0x66C8, None, 1, CpuAVX512ER, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexW=1|Broadcast|Disp8MemShift=6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Dword|Unspecified|BaseIndex, RegZMM }
3300 vexp2ps, 0x66C8, None, 1, CpuAVX512ER, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegZMM, RegZMM }
3301
3302 vrcp28pd, 0x66CA, None, 1, CpuAVX512ER, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexW=2|Broadcast|Disp8MemShift=6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Qword|Unspecified|BaseIndex, RegZMM }
3303 vrcp28pd, 0x66CA, None, 1, CpuAVX512ER, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegZMM, RegZMM }
3304 vrsqrt28pd, 0x66CC, None, 1, CpuAVX512ER, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexW=2|Broadcast|Disp8MemShift=6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Qword|Unspecified|BaseIndex, RegZMM }
3305 vrsqrt28pd, 0x66CC, None, 1, CpuAVX512ER, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegZMM, RegZMM }
3306
3307 vrcp28ps, 0x66CA, None, 1, CpuAVX512ER, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexW=1|Broadcast|Disp8MemShift=6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Dword|Unspecified|BaseIndex, RegZMM }
3308 vrcp28ps, 0x66CA, None, 1, CpuAVX512ER, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegZMM, RegZMM }
3309 vrsqrt28ps, 0x66CC, None, 1, CpuAVX512ER, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexW=1|Broadcast|Disp8MemShift=6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Dword|Unspecified|BaseIndex, RegZMM }
3310 vrsqrt28ps, 0x66CC, None, 1, CpuAVX512ER, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegZMM, RegZMM }
3311
3312 vrcp28sd, 0x66CB, None, 1, CpuAVX512ER, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
3313 vrcp28sd, 0x66CB, None, 1, CpuAVX512ER, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
3314 vrsqrt28sd, 0x66CD, None, 1, CpuAVX512ER, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
3315 vrsqrt28sd, 0x66CD, None, 1, CpuAVX512ER, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
3316
3317 vrcp28ss, 0x66CB, None, 1, CpuAVX512ER, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
3318 vrcp28ss, 0x66CB, None, 1, CpuAVX512ER, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
3319 vrsqrt28ss, 0x66CD, None, 1, CpuAVX512ER, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
3320 vrsqrt28ss, 0x66CD, None, 1, CpuAVX512ER, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
3321
3322 // AVX512ER instructions end.
3323
3324 // AVX512PF instructions.
3325
3326 vgatherpf0dpd, 0x66C6, 1, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|OpcodePrefix=1|VexW1|Disp8MemShift=3|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex }
3327 vgatherpf0qpd, 0x66C7, 1, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|OpcodePrefix=1|VexW1|Disp8MemShift=3|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex }
3328 vgatherpf1dpd, 0x66C6, 2, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|OpcodePrefix=1|VexW1|Disp8MemShift=3|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex }
3329 vgatherpf1qpd, 0x66C7, 2, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|OpcodePrefix=1|VexW1|Disp8MemShift=3|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex }
3330 vscatterpf0dpd, 0x66C6, 5, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|OpcodePrefix=1|VexW1|Disp8MemShift=3|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex }
3331 vscatterpf0qpd, 0x66C7, 5, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|OpcodePrefix=1|VexW1|Disp8MemShift=3|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex }
3332 vscatterpf1dpd, 0x66C6, 6, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|OpcodePrefix=1|VexW1|Disp8MemShift=3|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex }
3333 vscatterpf1qpd, 0x66C7, 6, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|OpcodePrefix=1|VexW1|Disp8MemShift=3|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex }
3334
3335 vgatherpf0dps, 0x66C6, 1, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|OpcodePrefix=1|VexW0|Disp8MemShift=2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex }
3336 vgatherpf0qps, 0x66C7, 1, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|OpcodePrefix=1|VexW0|Disp8MemShift=2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex }
3337 vgatherpf1dps, 0x66C6, 2, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|OpcodePrefix=1|VexW0|Disp8MemShift=2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex }
3338 vgatherpf1qps, 0x66C7, 2, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|OpcodePrefix=1|VexW0|Disp8MemShift=2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex }
3339 vscatterpf0dps, 0x66C6, 5, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|OpcodePrefix=1|VexW0|Disp8MemShift=2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex }
3340 vscatterpf0qps, 0x66C7, 5, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|OpcodePrefix=1|VexW0|Disp8MemShift=2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex }
3341 vscatterpf1dps, 0x66C6, 6, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|OpcodePrefix=1|VexW0|Disp8MemShift=2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex }
3342 vscatterpf1qps, 0x66C7, 6, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|OpcodePrefix=1|VexW0|Disp8MemShift=2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex }
3343
3344 // AVX512PF instructions end.
3345
3346 // CpuPREFETCHWT1 instructions.
3347
3348 prefetchwt1, 0x0F0D, 2, 2, CpuPREFETCHWT1, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex }
3349
3350 // CpuPREFETCHWT1 instructions end.
3351
3352 // CLFLUSHOPT instructions.
3353
3354 clflushopt, 0x0fae, 0x7, 2, CpuClflushOpt, Prefix_0X66|Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex }
3355
3356 // CLFLUSHOPT instructions end.
3357
3358 // XSAVES/XRSTORS instructions.
3359
3360 xrstors, 0xfc7, 0x3, 2, CpuXSAVES, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex }
3361 xrstors64, 0xfc7, 0x3, 2, CpuXSAVES|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Unspecified|BaseIndex }
3362 xsaves, 0xfc7, 0x5, 2, CpuXSAVES, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex }
3363 xsaves64, 0xfc7, 0x5, 2, CpuXSAVES|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Unspecified|BaseIndex }
3364
3365 // XSAVES instructions end.
3366
3367 // XSAVEC instructions.
3368
3369 xsavec, 0xfc7, 0x4, 2, CpuXSAVEC, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex }
3370 xsavec64, 0xfc7, 0x4, 2, CpuXSAVEC|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Unspecified|BaseIndex }
3371
3372 // XSAVEC instructions end.
3373
3374 // SGX instructions.
3375
3376 encls, 0xf01cf, None, 3, CpuSE1, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
3377 enclu, 0xf01d7, None, 3, CpuSE1, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
3378 enclv, 0xf01c0, None, 3, CpuSE1, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
3379
3380 // SGX instructions end.
3381
3382 // AVX512VL instructions.
3383
3384 vgatherdpd, 0x6692, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|Masking=2|NoDefMask|OpcodePrefix=1|VexW1|Disp8MemShift=3|VecSIB128|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM|RegYMM }
3385 vgatherqpd, 0x6693, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|OpcodePrefix=1|VexW1|Disp8MemShift=3|VecSIB128|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
3386 vgatherqpd, 0x6693, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|OpcodePrefix=1|VexW1|Disp8MemShift=3|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegYMM }
3387 vpgatherdq, 0x6690, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|Masking=2|NoDefMask|OpcodePrefix=1|VexW1|Disp8MemShift=3|VecSIB128|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM|RegYMM }
3388 vpgatherqq, 0x6691, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|OpcodePrefix=1|VexW1|Disp8MemShift=3|VecSIB128|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
3389 vpgatherqq, 0x6691, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|OpcodePrefix=1|VexW1|Disp8MemShift=3|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegYMM }
3390 vpscatterdq, 0x66A0, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|Masking=2|NoDefMask|OpcodePrefix=1|VexW1|Disp8MemShift=3|VecSIB128|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex }
3391 vpscatterqq, 0x66A1, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|OpcodePrefix=1|VexW1|Disp8MemShift=3|VecSIB128|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex }
3392 vpscatterqq, 0x66A1, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|OpcodePrefix=1|VexW1|Disp8MemShift=3|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Qword|Unspecified|BaseIndex }
3393 vscatterdpd, 0x66A2, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|Masking=2|NoDefMask|OpcodePrefix=1|VexW1|Disp8MemShift=3|VecSIB128|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex }
3394 vscatterqpd, 0x66A3, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|OpcodePrefix=1|VexW1|Disp8MemShift=3|VecSIB128|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex }
3395 vscatterqpd, 0x66A3, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|OpcodePrefix=1|VexW1|Disp8MemShift=3|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Qword|Unspecified|BaseIndex }
3396
3397 vgatherdps, 0x6692, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|OpcodePrefix=1|VexW0|Disp8MemShift=2|VecSIB128|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM }
3398 vgatherdps, 0x6692, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|OpcodePrefix=1|VexW0|Disp8MemShift=2|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegYMM }
3399 vgatherqps, 0x6693, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|OpcodePrefix=1|VexW0|Disp8MemShift=2|VecSIB128|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM }
3400 vgatherqps, 0x6693, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|OpcodePrefix=1|VexW0|Disp8MemShift=2|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM }
3401 vpgatherdd, 0x6690, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|OpcodePrefix=1|VexW0|Disp8MemShift=2|VecSIB128|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM }
3402 vpgatherdd, 0x6690, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|OpcodePrefix=1|VexW0|Disp8MemShift=2|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegYMM }
3403 vpgatherqd, 0x6691, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|OpcodePrefix=1|VexW0|Disp8MemShift=2|VecSIB128|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM }
3404 vpgatherqd, 0x6691, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|OpcodePrefix=1|VexW0|Disp8MemShift=2|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM }
3405 vpscatterdd, 0x66A0, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|OpcodePrefix=1|VexW0|Disp8MemShift=2|VecSIB128|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex }
3406 vpscatterdd, 0x66A0, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|OpcodePrefix=1|VexW0|Disp8MemShift=2|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Dword|Unspecified|BaseIndex }
3407 vpscatterqd, 0x66A1, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|OpcodePrefix=1|VexW0|Disp8MemShift=2|VecSIB128|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex }
3408 vpscatterqd, 0x66A1, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|OpcodePrefix=1|VexW0|Disp8MemShift=2|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex }
3409 vscatterdps, 0x66A2, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|OpcodePrefix=1|VexW0|Disp8MemShift=2|VecSIB128|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex }
3410 vscatterdps, 0x66A2, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|OpcodePrefix=1|VexW0|Disp8MemShift=2|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Dword|Unspecified|BaseIndex }
3411 vscatterqps, 0x66A3, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|OpcodePrefix=1|VexW0|Disp8MemShift=2|VecSIB128|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex }
3412 vscatterqps, 0x66A3, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|OpcodePrefix=1|VexW0|Disp8MemShift=2|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex }
3413
3414 vcvtdq2pd, 0xF3E6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=3|OpcodePrefix=0|VexW0|Broadcast|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM }
3415 vcvtdq2pd, 0xF3E6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=3|OpcodePrefix=0|VexW0|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM }
3416 vcvtudq2pd, 0xF37A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=3|OpcodePrefix=0|VexW0|Broadcast|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM }
3417 vcvtudq2pd, 0xF37A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=3|OpcodePrefix=0|VexW0|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM }
3418
3419 vcvtpd2dq, 0xF2E6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { RegXMM|RegYMM|Qword|Unspecified|BaseIndex, RegXMM }
3420 vcvtpd2dq, 0xF2E6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|RegYMM|Qword|BaseIndex, RegXMM }
3421 vcvtpd2dqx, 0xF2E6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
3422 vcvtpd2dqy, 0xF2E6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegYMM|Qword|Unspecified|BaseIndex, RegXMM }
3423
3424 vcvtpd2ps, 0x665A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { RegXMM|RegYMM|Qword|Unspecified|BaseIndex, RegXMM }
3425 vcvtpd2ps, 0x665A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|RegYMM|Qword|BaseIndex, RegXMM }
3426 vcvtpd2psx, 0x665A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
3427 vcvtpd2psy, 0x665A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegYMM|Qword|Unspecified|BaseIndex, RegXMM }
3428
3429 vcvtpd2udq, 0x79, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { RegXMM|RegYMM|Qword|Unspecified|BaseIndex, RegXMM }
3430 vcvtpd2udq, 0x79, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|RegYMM|Qword|BaseIndex, RegXMM }
3431 vcvtpd2udqx, 0x79, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
3432 vcvtpd2udqy, 0x79, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegYMM|Qword|Unspecified|BaseIndex, RegXMM }
3433
3434 vcvtph2ps, 0x6613, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|OpcodePrefix=1|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
3435 vcvtph2ps, 0x6613, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|OpcodePrefix=1|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegYMM }
3436
3437 vcvtps2pd, 0x5A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=3|OpcodePrefix=0|VexW0|Broadcast|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM }
3438 vcvtps2pd, 0x5A, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=3|OpcodePrefix=0|VexW0|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM }
3439
3440 vcvtps2ph, 0x661D, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|MaskingMorZ|OpcodePrefix=2|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM|Qword|Unspecified|BaseIndex }
3441 vcvtps2ph, 0x661D, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|MaskingMorZ|OpcodePrefix=2|VexW0|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, RegXMM|Unspecified|BaseIndex }
3442
3443 vcvttpd2dq, 0x66E6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { RegXMM|RegYMM|Unspecified|Qword|BaseIndex, RegXMM }
3444 vcvttpd2dq, 0x66E6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|RegYMM|Qword|BaseIndex, RegXMM }
3445 vcvttpd2dqx, 0x66E6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
3446 vcvttpd2dqy, 0x66E6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegYMM|Qword|Unspecified|BaseIndex, RegXMM }
3447
3448 vcvttpd2udq, 0x78, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { RegXMM|RegYMM|Qword|Unspecified|BaseIndex, RegXMM }
3449 vcvttpd2udq, 0x78, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|RegYMM|Qword|BaseIndex, RegXMM }
3450 vcvttpd2udqx, 0x78, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
3451 vcvttpd2udqy, 0x78, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegYMM|Qword|Unspecified|BaseIndex, RegXMM }
3452
3453 vmovddup, 0xF212, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|OpcodePrefix=0|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
3454
3455 vpslld, 0x66F2, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
3456 vpsrad, 0x66E2, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
3457 vpsrld, 0x66D2, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
3458
3459 vpsllq, 0x66F3, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
3460 vpsraq, 0x66E2, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
3461 vpsrlq, 0x66D3, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
3462
3463 vpmovdb, 0xF331, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|OpcodePrefix=1|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex }
3464 vpmovdb, 0xF331, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|OpcodePrefix=1|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex }
3465 vpmovsdb, 0xF321, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|OpcodePrefix=1|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex }
3466 vpmovsdb, 0xF321, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|OpcodePrefix=1|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex }
3467 vpmovusdb, 0xF311, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|OpcodePrefix=1|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex }
3468 vpmovusdb, 0xF311, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|OpcodePrefix=1|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex }
3469
3470 vpmovdw, 0xF333, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|OpcodePrefix=1|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex }
3471 vpmovdw, 0xF333, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|OpcodePrefix=1|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|Unspecified|BaseIndex }
3472 vpmovsdw, 0xF323, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|OpcodePrefix=1|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex }
3473 vpmovsdw, 0xF323, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|OpcodePrefix=1|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|Unspecified|BaseIndex }
3474 vpmovusdw, 0xF313, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|OpcodePrefix=1|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex }
3475 vpmovusdw, 0xF313, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|OpcodePrefix=1|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|Unspecified|BaseIndex }
3476
3477 vpmovqb, 0xF332, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|OpcodePrefix=1|VexW0|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|Word|Unspecified|BaseIndex }
3478 vpmovqb, 0xF332, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|OpcodePrefix=1|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|Dword|Unspecified|BaseIndex }
3479 vpmovsqb, 0xF322, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|OpcodePrefix=1|VexW0|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|Word|Unspecified|BaseIndex }
3480 vpmovsqb, 0xF322, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|OpcodePrefix=1|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|Dword|Unspecified|BaseIndex }
3481 vpmovusqb, 0xF312, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|OpcodePrefix=1|VexW0|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|Word|Unspecified|BaseIndex }
3482 vpmovusqb, 0xF312, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|OpcodePrefix=1|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|Dword|Unspecified|BaseIndex }
3483
3484 vpmovqd, 0xF335, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|OpcodePrefix=1|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex }
3485 vpmovqd, 0xF335, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|OpcodePrefix=1|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|Unspecified|BaseIndex }
3486 vpmovsqd, 0xF325, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|OpcodePrefix=1|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex }
3487 vpmovsqd, 0xF325, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|OpcodePrefix=1|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|Unspecified|BaseIndex }
3488 vpmovusqd, 0xF315, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|OpcodePrefix=1|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex }
3489 vpmovusqd, 0xF315, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|OpcodePrefix=1|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|Unspecified|BaseIndex }
3490
3491 vpmovqw, 0xF334, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|OpcodePrefix=1|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex }
3492 vpmovqw, 0xF334, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|OpcodePrefix=1|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex }
3493 vpmovsqw, 0xF324, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|OpcodePrefix=1|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex }
3494 vpmovsqw, 0xF324, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|OpcodePrefix=1|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex }
3495 vpmovusqw, 0xF314, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|OpcodePrefix=1|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex }
3496 vpmovusqw, 0xF314, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|OpcodePrefix=1|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex }
3497
3498 vpmovsxbd, 0x6621, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|OpcodePrefix=1|VexWIG|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM }
3499 vpmovsxbd, 0x6621, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|OpcodePrefix=1|VexWIG|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM }
3500 vpmovzxbd, 0x6631, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|OpcodePrefix=1|VexWIG|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM }
3501 vpmovzxbd, 0x6631, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|OpcodePrefix=1|VexWIG|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM }
3502
3503 vpmovsxbq, 0x6622, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|OpcodePrefix=1|VexWIG|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM }
3504 vpmovsxbq, 0x6622, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|OpcodePrefix=1|VexWIG|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM }
3505 vpmovzxbq, 0x6632, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|OpcodePrefix=1|VexWIG|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM }
3506 vpmovzxbq, 0x6632, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|OpcodePrefix=1|VexWIG|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM }
3507
3508 vpmovsxdq, 0x6625, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|OpcodePrefix=1|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
3509 vpmovsxdq, 0x6625, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|OpcodePrefix=1|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegYMM }
3510 vpmovzxdq, 0x6635, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|OpcodePrefix=1|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
3511 vpmovzxdq, 0x6635, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|OpcodePrefix=1|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegYMM }
3512
3513 vpmovsxwd, 0x6623, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|OpcodePrefix=1|VexWIG|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
3514 vpmovsxwd, 0x6623, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|OpcodePrefix=1|VexWIG|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegYMM }
3515 vpmovzxwd, 0x6633, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|OpcodePrefix=1|VexWIG|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
3516 vpmovzxwd, 0x6633, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|OpcodePrefix=1|VexWIG|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegYMM }
3517
3518 vpmovsxwq, 0x6624, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|OpcodePrefix=1|VexWIG|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM }
3519 vpmovsxwq, 0x6624, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|OpcodePrefix=1|VexWIG|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM }
3520 vpmovzxwq, 0x6634, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|OpcodePrefix=1|VexWIG|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM }
3521 vpmovzxwq, 0x6634, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|OpcodePrefix=1|VexWIG|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM }
3522
3523 // AVX512VL instructions end.
3524
3525 // AVX512BW instructions.
3526
3527 kaddd, 0x664A, None, 1, CpuAVX512BW, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
3528 kandd, 0x6641, None, 1, CpuAVX512BW, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
3529 kandnd, 0x6642, None, 1, CpuAVX512BW, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegMask, RegMask, RegMask }
3530 kmovd, 0x6690, None, 1, CpuAVX512BW, Modrm|Vex=1|OpcodePrefix=0|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask|Dword|Unspecified|BaseIndex, RegMask }
3531 kmovd, 0x6691, None, 1, CpuAVX512BW, Modrm|Vex=1|OpcodePrefix=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, Dword|Unspecified|BaseIndex }
3532 kmovd, 0xF292, None, 1, CpuAVX512BW, D|Modrm|Vex=1|OpcodePrefix=0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegMask }
3533 knotd, 0x6644, None, 1, CpuAVX512BW, Modrm|Vex=1|OpcodePrefix=0|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
3534 kord, 0x6645, None, 1, CpuAVX512BW, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
3535 kortestd, 0x6698, None, 1, CpuAVX512BW, Modrm|Vex=1|OpcodePrefix=0|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
3536 ktestd, 0x6699, None, 1, CpuAVX512BW, Modrm|Vex=1|OpcodePrefix=0|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
3537 kxnord, 0x6646, None, 1, CpuAVX512BW, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
3538 kxord, 0x6647, None, 1, CpuAVX512BW, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegMask, RegMask, RegMask }
3539
3540 kaddq, 0x4A, None, 1, CpuAVX512BW, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
3541 kandnq, 0x42, None, 1, CpuAVX512BW, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegMask, RegMask, RegMask }
3542 kandq, 0x41, None, 1, CpuAVX512BW, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
3543 kmovq, 0x90, None, 1, CpuAVX512BW, Modrm|Vex=1|OpcodePrefix=0|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask|Qword|Unspecified|BaseIndex, RegMask }
3544 kmovq, 0x91, None, 1, CpuAVX512BW, Modrm|Vex=1|OpcodePrefix=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, Qword|Unspecified|BaseIndex }
3545 kmovq, 0xF292, None, 1, CpuAVX512BW, D|Modrm|Vex=1|OpcodePrefix=0|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg64, RegMask }
3546 knotq, 0x44, None, 1, CpuAVX512BW, Modrm|Vex=1|OpcodePrefix=0|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
3547 korq, 0x45, None, 1, CpuAVX512BW, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
3548 kortestq, 0x98, None, 1, CpuAVX512BW, Modrm|Vex=1|OpcodePrefix=0|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
3549 ktestq, 0x99, None, 1, CpuAVX512BW, Modrm|Vex=1|OpcodePrefix=0|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
3550 kunpckdq, 0x4B, None, 1, CpuAVX512BW, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
3551 kunpckwd, 0x4B, None, 1, CpuAVX512BW, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
3552 kxnorq, 0x46, None, 1, CpuAVX512BW, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
3553 kxorq, 0x47, None, 1, CpuAVX512BW, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegMask, RegMask, RegMask }
3554
3555 kshiftld, 0x6633, None, 1, CpuAVX512BW, Modrm|Vex=1|OpcodePrefix=2|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask }
3556 kshiftlq, 0x6633, None, 1, CpuAVX512BW, Modrm|Vex=1|OpcodePrefix=2|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask }
3557 kshiftrd, 0x6631, None, 1, CpuAVX512BW, Modrm|Vex=1|OpcodePrefix=2|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask }
3558 kshiftrq, 0x6631, None, 1, CpuAVX512BW, Modrm|Vex=1|OpcodePrefix=2|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask }
3559
3560 vdbpsadbw, 0x6642, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3561
3562 vmovdqu8, 0xF26F, None, 1, CpuAVX512BW, D|Modrm|MaskingMorZ|OpcodePrefix=0|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3563 vmovdqu16, 0xF26F, None, 1, CpuAVX512BW, D|Modrm|MaskingMorZ|OpcodePrefix=0|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3564
3565 vpabsb, 0x661C, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=1|VexWIG|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3566 vpmaxsb, 0x663C, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=1|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3567 vpminsb, 0x6638, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=1|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3568 vpshufb, 0x6600, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=1|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3569
3570 vpabsw, 0x661D, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=1|VexWIG|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3571 vpmaddubsw, 0x6604, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=1|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3572 vpmaxuw, 0x663E, None, 1, CpuAVX512BW, Modrm|Masking=3|VexWIG|OpcodePrefix=1|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3573 vpminuw, 0x663A, None, 1, CpuAVX512BW, Modrm|Masking=3|VexWIG|OpcodePrefix=1|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3574 vpmulhrsw, 0x660B, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=1|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3575
3576 vpackssdw, 0x666B, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3577 vpacksswb, 0x6663, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=0|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3578 vpackuswb, 0x6667, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=0|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3579 vpackusdw, 0x662B, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3580
3581 vpaddb, 0x66FC, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=0|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3582 vpaddsb, 0x66EC, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=0|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3583 vpaddusb, 0x66DC, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=0|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3584 vpavgb, 0x66E0, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=0|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3585 vpmaxub, 0x66DE, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=0|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3586 vpminub, 0x66DA, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=0|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3587 vpsubb, 0x66F8, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=0|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3588 vpsubsb, 0x66E8, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=0|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3589 vpsubusb, 0x66D8, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=0|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3590 vpunpckhbw, 0x6668, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=0|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3591 vpunpcklbw, 0x6660, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=0|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3592
3593 vpaddsw, 0x66ED, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=0|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3594 vpaddusw, 0x66DD, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=0|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3595 vpaddw, 0x66FD, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=0|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3596 vpavgw, 0x66E3, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=0|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3597 vpmaxsw, 0x66EE, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=0|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3598 vpminsw, 0x66EA, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=0|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3599 vpmulhuw, 0x66E4, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=0|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3600 vpmulhw, 0x66E5, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=0|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3601 vpmullw, 0x66D5, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=0|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3602 vpsllw, 0x6671, 6, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=0|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3603 vpsllw, 0x66F1, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|OpcodePrefix=0|VexVVVV=1|VexWIG|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
3604 vpsllw, 0x66F1, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexWIG|Disp8MemShift=4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
3605 vpsraw, 0x6671, 4, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=0|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3606 vpsraw, 0x66E1, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|OpcodePrefix=0|VexWIG|VexVVVV=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
3607 vpsraw, 0x66E1, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=0|VexWIG|VexVVVV=1|Disp8MemShift=4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
3608 vpsrlw, 0x6671, 2, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=0|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3609 vpsrlw, 0x66D1, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|OpcodePrefix=0|VexWIG|VexVVVV=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
3610 vpsrlw, 0x66D1, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=0|VexWIG|VexVVVV=1|Disp8MemShift=4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
3611 vpsubsw, 0x66E9, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=0|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3612 vpsubusw, 0x66D9, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=0|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3613 vpsubw, 0x66F9, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexWIG|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3614 vpunpckhwd, 0x6669, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=0|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3615 vpunpcklwd, 0x6661, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=0|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3616
3617 vpalignr, 0x660F, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=2|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3618
3619 vpblendmb, 0x6666, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3620 vpbroadcastb, 0x6678, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=1|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Byte|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3621 vpbroadcastb, 0x667A, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegXMM|RegYMM|RegZMM }
3622
3623 vpblendmw, 0x6666, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3624 vpermi2w, 0x6675, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3625 vpermt2w, 0x667D, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3626 vpermw, 0x668D, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3627 vpsllvw, 0x6612, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3628 vpsravw, 0x6611, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3629 vpsrlvw, 0x6610, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3630
3631 vpbroadcastw, 0x6679, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=1|VexW0|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3632 vpbroadcastw, 0x667B, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegXMM|RegYMM|RegZMM }
3633
3634 vpcmpeqb, 0x6674, None, 1, CpuAVX512BW, Modrm|Masking=2|OpcodePrefix=0|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
3635 vpcmpgtb, 0x6664, None, 1, CpuAVX512BW, Modrm|Masking=2|OpcodePrefix=0|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
3636 vpcmpb, 0x663F, None, 1, CpuAVX512BW, Modrm|Masking=2|OpcodePrefix=2|VexVVVV=1|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
3637 vpcmp<avx_irel>b, 0x663F, <avx_irel:imm>, 1, CpuAVX512BW, Modrm|Masking=2|OpcodePrefix=2|VexVVVV|VexW0|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
3638 vpcmpub, 0x663E, None, 1, CpuAVX512BW, Modrm|Masking=2|OpcodePrefix=2|VexVVVV=1|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
3639 vpcmp<avx_irel>ub, 0x663E, <avx_irel:imm>, 1, CpuAVX512BW, Modrm|Masking=2|OpcodePrefix=2|VexVVVV|VexW0|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
3640
3641 vpcmpeqw, 0x6675, None, 1, CpuAVX512BW, Modrm|Masking=2|OpcodePrefix=0|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
3642 vpcmpgtw, 0x6665, None, 1, CpuAVX512BW, Modrm|Masking=2|OpcodePrefix=0|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
3643 vpcmpw, 0x663F, None, 1, CpuAVX512BW, Modrm|Masking=2|OpcodePrefix=2|VexVVVV=1|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
3644 vpcmp<avx_irel>w, 0x663F, <avx_irel:imm>, 1, CpuAVX512BW, Modrm|Masking=2|OpcodePrefix=2|VexVVVV|VexW1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
3645 vpcmpuw, 0x663E, None, 1, CpuAVX512BW, Modrm|Masking=2|OpcodePrefix=2|VexVVVV=1|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
3646 vpcmp<avx_irel>uw, 0x663E, <avx_irel:imm>, 1, CpuAVX512BW, Modrm|Masking=2|OpcodePrefix=2|VexVVVV|VexW1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
3647
3648 vpslldq, 0x6673, 7, 1, CpuAVX512BW, Modrm|OpcodePrefix=0|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3649 vpsrldq, 0x6673, 3, 1, CpuAVX512BW, Modrm|OpcodePrefix=0|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3650
3651 vpextrw, 0x66C5, None, 1, CpuAVX512BW, Load|Modrm|EVex128|OpcodePrefix=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64 }
3652 vpextrw, 0x6615, None, 1, CpuAVX512BW, RegMem|EVex128|OpcodePrefix=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64 }
3653 vpextrw, 0x6615, None, 1, CpuAVX512BW, Modrm|EVex128|OpcodePrefix=2|VexWIG|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Word|Unspecified|BaseIndex }
3654 vpinsrw, 0x66C4, None, 1, CpuAVX512BW, Modrm|EVex128|OpcodePrefix=0|VexWIG|VexVVVV=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM }
3655 vpinsrw, 0x66C4, None, 1, CpuAVX512BW, Modrm|EVex128|OpcodePrefix=0|VexWIG|VexVVVV|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Word|Unspecified|BaseIndex, RegXMM, RegXMM }
3656
3657 vpextrb, 0x6614, None, 1, CpuAVX512BW, RegMem|EVex128|OpcodePrefix=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64 }
3658 vpextrb, 0x6614, None, 1, CpuAVX512BW, Modrm|EVex128|OpcodePrefix=2|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Byte|Unspecified|BaseIndex }
3659 vpinsrb, 0x6620, None, 1, CpuAVX512BW, Modrm|EVex128|OpcodePrefix=2|VexWIG|VexVVVV=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM }
3660 vpinsrb, 0x6620, None, 1, CpuAVX512BW, Modrm|EVex128|OpcodePrefix=2|VexWIG|VexVVVV|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Byte|Unspecified|BaseIndex, RegXMM, RegXMM }
3661
3662 vpmaddwd, 0x66F5, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexWIG|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3663
3664 vpmovb2m, 0xF329, None, 1, CpuAVX512BW, Modrm|EVex=5|OpcodePrefix=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegMask }
3665 vpmovw2m, 0xF329, None, 1, CpuAVX512BW, Modrm|EVex=5|OpcodePrefix=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegMask }
3666
3667 vpmovm2b, 0xF328, None, 1, CpuAVX512BW, Modrm|EVex=5|OpcodePrefix=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegXMM|RegYMM|RegZMM }
3668 vpmovm2w, 0xF328, None, 1, CpuAVX512BW, Modrm|EVex=5|OpcodePrefix=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegXMM|RegYMM|RegZMM }
3669
3670 vpmovswb, 0xF320, None, 1, CpuAVX512BW, Modrm|EVex=1|MaskingMorZ|OpcodePrefix=1|VexW=1|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegYMM|Unspecified|BaseIndex }
3671 vpmovswb, 0xF320, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|OpcodePrefix=1|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex }
3672 vpmovswb, 0xF320, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|OpcodePrefix=1|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|Unspecified|BaseIndex }
3673
3674 vpmovuswb, 0xF310, None, 1, CpuAVX512BW, Modrm|EVex=1|MaskingMorZ|OpcodePrefix=1|VexW=1|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegYMM|Unspecified|BaseIndex }
3675 vpmovuswb, 0xF310, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|OpcodePrefix=1|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex }
3676 vpmovuswb, 0xF310, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|OpcodePrefix=1|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|Unspecified|BaseIndex }
3677
3678 vpmovwb, 0xF330, None, 1, CpuAVX512BW, Modrm|EVex=1|MaskingMorZ|OpcodePrefix=1|VexW=1|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegYMM|Unspecified|BaseIndex }
3679 vpmovwb, 0xF330, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|OpcodePrefix=1|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex }
3680 vpmovwb, 0xF330, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|OpcodePrefix=1|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|Unspecified|BaseIndex }
3681
3682 vpmovsxbw, 0x6620, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexWIG|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Unspecified|BaseIndex, RegZMM }
3683 vpmovsxbw, 0x6620, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexWIG|OpcodePrefix=1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
3684 vpmovsxbw, 0x6620, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexWIG|OpcodePrefix=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegYMM }
3685 vpmovzxbw, 0x6630, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexWIG|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Unspecified|BaseIndex, RegZMM }
3686 vpmovzxbw, 0x6630, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexWIG|OpcodePrefix=1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
3687 vpmovzxbw, 0x6630, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexWIG|OpcodePrefix=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegYMM }
3688
3689 vpsadbw, 0x66F6, None, 1, CpuAVX512BW, Modrm|OpcodePrefix=0|VexVVVV=1|VexWIG|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3690
3691 vpshufhw, 0xF370, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=0|VexWIG|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3692 vpshuflw, 0xF270, None, 1, CpuAVX512BW, Modrm|Masking=3|OpcodePrefix=0|VexWIG|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3693
3694 vptestmb, 0x6626, None, 1, CpuAVX512BW, Modrm|Masking=2|OpcodePrefix=1|VexVVVV=1|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
3695 vptestmw, 0x6626, None, 1, CpuAVX512BW, Modrm|Masking=2|OpcodePrefix=1|VexVVVV=1|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
3696
3697 vptestnmb, 0xF326, None, 1, CpuAVX512BW, Modrm|Masking=2|OpcodePrefix=1|VexVVVV=1|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
3698 vptestnmw, 0xF326, None, 1, CpuAVX512BW, Modrm|Masking=2|OpcodePrefix=1|VexVVVV=1|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
3699
3700 // AVX512BW instructions end.
3701
3702 // AVX512DQ instructions.
3703
3704 kaddb, 0x664A, None, 1, CpuAVX512DQ, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
3705 kandb, 0x6641, None, 1, CpuAVX512DQ, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
3706 kandnb, 0x6642, None, 1, CpuAVX512DQ, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
3707 kmovb, 0x6690, None, 1, CpuAVX512DQ, Modrm|Vex=1|OpcodePrefix=0|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask|Byte|Unspecified|BaseIndex, RegMask }
3708 kmovb, 0x6691, None, 1, CpuAVX512DQ, Modrm|Vex=1|OpcodePrefix=0|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, Byte|Unspecified|BaseIndex }
3709 kmovb, 0x6692, None, 1, CpuAVX512DQ, D|Modrm|Vex=1|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegMask }
3710 knotb, 0x6644, None, 1, CpuAVX512DQ, Modrm|Vex=1|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
3711 korb, 0x6645, None, 1, CpuAVX512DQ, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
3712 kortestb, 0x6698, None, 1, CpuAVX512DQ, Modrm|Vex=1|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
3713 ktestb, 0x6699, None, 1, CpuAVX512DQ, Modrm|Vex=1|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
3714 kxnorb, 0x6646, None, 1, CpuAVX512DQ, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
3715 kxorb, 0x6647, None, 1, CpuAVX512DQ, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
3716
3717 kaddw, 0x4A, None, 1, CpuAVX512DQ, Modrm|Vex=2|OpcodePrefix=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
3718 ktestw, 0x99, None, 1, CpuAVX512DQ, Modrm|Vex=1|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
3719
3720 kshiftlb, 0x6632, None, 1, CpuAVX512DQ, Modrm|Vex=1|OpcodePrefix=2|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask }
3721 kshiftrb, 0x6630, None, 1, CpuAVX512DQ, Modrm|Vex=1|OpcodePrefix=2|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask }
3722
3723 vandnpd, 0x6655, None, 1, CpuAVX512DQ, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3724 vandpd, 0x6654, None, 1, CpuAVX512DQ, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3725 vorpd, 0x6656, None, 1, CpuAVX512DQ, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3726 vxorpd, 0x6657, None, 1, CpuAVX512DQ, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3727
3728 vandnps, 0x55, None, 1, CpuAVX512DQ, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3729 vandps, 0x54, None, 1, CpuAVX512DQ, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3730 vorps, 0x56, None, 1, CpuAVX512DQ, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3731 vxorps, 0x57, None, 1, CpuAVX512DQ, Modrm|Masking=3|OpcodePrefix=0|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3732
3733 vbroadcastf32x2, 0x6619, None, 1, CpuAVX512DQ, Modrm|Masking=3|OpcodePrefix=1|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM }
3734 vbroadcastf32x8, 0x661B, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexW=1|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { YMMword|Unspecified|BaseIndex, RegZMM }
3735 vbroadcasti32x2, 0x6659, None, 1, CpuAVX512DQ, Modrm|Masking=3|OpcodePrefix=1|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3736 vbroadcasti32x8, 0x665B, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexW=1|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { YMMword|Unspecified|BaseIndex, RegZMM }
3737
3738 vbroadcastf64x2, 0x661A, None, 1, CpuAVX512DQ, Modrm|Masking=3|OpcodePrefix=1|VexW=2|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM }
3739 vbroadcasti64x2, 0x665A, None, 1, CpuAVX512DQ, Modrm|Masking=3|OpcodePrefix=1|VexW=2|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM }
3740
3741 vcvtpd2qq, 0x667B, None, 1, CpuAVX512DQ, Modrm|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3742 vcvtpd2qq, 0x667B, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM }
3743 vcvtpd2uqq, 0x6679, None, 1, CpuAVX512DQ, Modrm|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3744 vcvtpd2uqq, 0x6679, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM }
3745
3746 vcvtps2qq, 0x667B, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=1|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM }
3747 vcvtps2qq, 0x667B, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegYMM, RegZMM }
3748 vcvtps2qq, 0x667B, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex128|Masking=3|OpcodePrefix=0|VexW0|Broadcast|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM }
3749 vcvtps2qq, 0x667B, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Masking=3|OpcodePrefix=0|VexW0|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM }
3750 vcvtps2uqq, 0x6679, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=1|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM }
3751 vcvtps2uqq, 0x6679, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegYMM, RegZMM }
3752 vcvtps2uqq, 0x6679, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex128|Masking=3|OpcodePrefix=0|VexW0|Broadcast|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM }
3753 vcvtps2uqq, 0x6679, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Masking=3|OpcodePrefix=0|VexW0|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegXMM|Dword|Unspecified|BaseIndex, RegYMM }
3754
3755 vcvtqq2pd, 0xF3E6, None, 1, CpuAVX512DQ, Modrm|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3756 vcvtqq2pd, 0xF3E6, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM }
3757 vcvtuqq2pd, 0xF37A, None, 1, CpuAVX512DQ, Modrm|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3758 vcvtuqq2pd, 0xF37A, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegZMM }
3759
3760 vcvtqq2ps, 0x5B, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8MemShift=6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Qword|Unspecified|BaseIndex, RegYMM }
3761 vcvtqq2ps, 0x5B, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegYMM }
3762 vcvtqq2ps, 0x5B, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { RegXMM|RegYMM|Qword|Unspecified|BaseIndex, RegXMM }
3763 vcvtqq2ps, 0x5B, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|RegYMM|Qword|BaseIndex, RegXMM }
3764 vcvtqq2psx, 0x5B, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=2|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
3765 vcvtqq2psy, 0x5B, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=3|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegYMM|Qword|Unspecified|BaseIndex, RegXMM }
3766
3767 vcvttpd2qq, 0x667A, None, 1, CpuAVX512DQ, Modrm|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3768 vcvttpd2qq, 0x667A, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegZMM, RegZMM }
3769 vcvttpd2uqq, 0x6678, None, 1, CpuAVX512DQ, Modrm|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3770 vcvttpd2uqq, 0x6678, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegZMM, RegZMM }
3771
3772 vcvttps2qq, 0x667A, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=1|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM }
3773 vcvttps2qq, 0x667A, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegYMM, RegZMM }
3774 vcvttps2qq, 0x667A, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex128|Masking=3|OpcodePrefix=0|VexW0|Broadcast|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM }
3775 vcvttps2qq, 0x667A, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Masking=3|OpcodePrefix=0|VexW0|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM }
3776 vcvttps2uqq, 0x6678, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=1|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM }
3777 vcvttps2uqq, 0x6678, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegYMM, RegZMM }
3778 vcvttps2uqq, 0x6678, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex128|Masking=3|OpcodePrefix=0|VexW0|Broadcast|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM }
3779 vcvttps2uqq, 0x6678, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Masking=3|OpcodePrefix=0|VexW0|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM }
3780
3781 vcvtuqq2ps, 0xF27A, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8MemShift=6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Qword|Unspecified|BaseIndex, RegYMM }
3782 vcvtuqq2ps, 0xF27A, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=3|OpcodePrefix=0|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegZMM, RegYMM }
3783 vcvtuqq2ps, 0xF27A, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { RegXMM|RegYMM|Qword|Unspecified|BaseIndex, RegXMM }
3784 vcvtuqq2ps, 0xF27A, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|RegYMM|Qword|BaseIndex, RegXMM }
3785 vcvtuqq2psx, 0xF27A, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=2|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
3786 vcvtuqq2psy, 0xF27A, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=3|Masking=3|OpcodePrefix=0|VexW=2|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegYMM|Qword|Unspecified|BaseIndex, RegXMM }
3787
3788 vextractf32x8, 0x661B, None, 1, CpuAVX512DQ, Modrm|EVex=1|MaskingMorZ|OpcodePrefix=2|VexW=1|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex }
3789 vextracti32x8, 0x663B, None, 1, CpuAVX512DQ, Modrm|EVex=1|MaskingMorZ|OpcodePrefix=2|VexW=1|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex }
3790 vinsertf32x8, 0x661A, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=1|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM }
3791 vinserti32x8, 0x663A, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=1|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM }
3792
3793 vfpclassss, 0x6667, None, 1, CpuAVX512DQ, Modrm|EVex=4|Masking=2|OpcodePrefix=2|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Dword|Unspecified|BaseIndex, RegMask }
3794 vpextrd, 0x6616, None, 1, CpuAVX512DQ, Modrm|EVex128|OpcodePrefix=2|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex }
3795 vpinsrd, 0x6622, None, 1, CpuAVX512DQ, Modrm|EVex128|OpcodePrefix=2|VexVVVV=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
3796
3797 vfpclasssd, 0x6667, None, 1, CpuAVX512DQ, Modrm|EVex=4|Masking=2|OpcodePrefix=2|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Qword|Unspecified|BaseIndex, RegMask }
3798 vpextrq, 0x6616, None, 1, CpuAVX512DQ|Cpu64, Modrm|EVex128|OpcodePrefix=2|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg64|Unspecified|BaseIndex }
3799 vpinsrq, 0x6622, None, 1, CpuAVX512DQ|Cpu64, Modrm|EVex128|OpcodePrefix=2|VexVVVV=1|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
3800
3801 vextractf64x2, 0x6619, None, 1, CpuAVX512DQ, Modrm|MaskingMorZ|OpcodePrefix=2|VexW=2|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex }
3802 vextracti64x2, 0x6639, None, 1, CpuAVX512DQ, Modrm|MaskingMorZ|OpcodePrefix=2|VexW=2|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex }
3803 vinsertf64x2, 0x6618, None, 1, CpuAVX512DQ, Modrm|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=2|Disp8MemShift=4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
3804 vinserti64x2, 0x6638, None, 1, CpuAVX512DQ, Modrm|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=2|Disp8MemShift=4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
3805
3806 vfpclasspd, 0x6666, None, 1, CpuAVX512DQ, Modrm|Masking=2|OpcodePrefix=2|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Imm8, RegXMM|RegYMM|RegZMM|Qword|BaseIndex, RegMask }
3807 vfpclasspd, 0x6666, None, 1, CpuAVX512DQ, Modrm|Masking=2|OpcodePrefix=2|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegMask }
3808 vfpclasspdz, 0x6666, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=2|OpcodePrefix=2|VexW=2|Broadcast|Disp8MemShift=6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM|Qword|Unspecified|BaseIndex, RegMask }
3809 vfpclasspdx, 0x6666, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=2|Masking=2|OpcodePrefix=2|VexW=2|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Qword|Unspecified|BaseIndex, RegMask }
3810 vfpclasspdy, 0x6666, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=3|Masking=2|OpcodePrefix=2|VexW=2|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Qword|Unspecified|BaseIndex, RegMask }
3811
3812 vfpclassps, 0x6666, None, 1, CpuAVX512DQ, Modrm|Masking=2|OpcodePrefix=2|VexW=1|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Imm8, RegXMM|RegYMM|RegZMM|Dword|BaseIndex, RegMask }
3813 vfpclassps, 0x6666, None, 1, CpuAVX512DQ, Modrm|Masking=2|OpcodePrefix=2|VexW=1|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegMask }
3814 vfpclasspsz, 0x6666, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=2|OpcodePrefix=2|VexW=1|Broadcast|Disp8MemShift=6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM|Dword|Unspecified|BaseIndex, RegMask }
3815 vfpclasspsx, 0x6666, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=2|Masking=2|OpcodePrefix=2|VexW=1|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Dword|Unspecified|BaseIndex, RegMask }
3816 vfpclasspsy, 0x6666, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=3|Masking=2|OpcodePrefix=2|VexW=1|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Dword|Unspecified|BaseIndex, RegMask }
3817
3818 vpmovd2m, 0xF339, None, 1, CpuAVX512DQ, Modrm|EVex=5|OpcodePrefix=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegMask }
3819 vpmovq2m, 0xF339, None, 1, CpuAVX512DQ, Modrm|EVex=5|OpcodePrefix=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegMask }
3820
3821 vpmovm2d, 0xF338, None, 1, CpuAVX512DQ, Modrm|EVex=5|OpcodePrefix=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegXMM|RegYMM|RegZMM }
3822 vpmovm2q, 0xF338, None, 1, CpuAVX512DQ, Modrm|EVex=5|OpcodePrefix=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegXMM|RegYMM|RegZMM }
3823
3824 vpmullq, 0x6640, None, 1, CpuAVX512DQ, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3825
3826 vrangepd, 0x6650, None, 1, CpuAVX512DQ, Modrm|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3827 vrangepd, 0x6650, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, Imm8, RegZMM, RegZMM, RegZMM }
3828 vreducepd, 0x6656, None, 1, CpuAVX512DQ, Modrm|Masking=3|OpcodePrefix=2|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3829 vreducepd, 0x6656, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=3|OpcodePrefix=2|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, Imm8, RegZMM, RegZMM }
3830
3831 vrangeps, 0x6650, None, 1, CpuAVX512DQ, Modrm|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3832 vrangeps, 0x6650, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, Imm8, RegZMM, RegZMM, RegZMM }
3833 vreduceps, 0x6656, None, 1, CpuAVX512DQ, Modrm|Masking=3|OpcodePrefix=2|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3834 vreduceps, 0x6656, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=3|OpcodePrefix=2|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, Imm8, RegZMM, RegZMM }
3835
3836 vrangesd, 0x6651, None, 1, CpuAVX512DQ, Modrm|EVex=4|Masking=3|OpcodePrefix=2|VexVVVV|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
3837 vrangesd, 0x6651, None, 1, CpuAVX512DQ, Modrm|EVex=4|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, Imm8, RegXMM, RegXMM, RegXMM }
3838 vreducesd, 0x6657, None, 1, CpuAVX512DQ, Modrm|EVex=4|Masking=3|OpcodePrefix=2|VexVVVV|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
3839 vreducesd, 0x6657, None, 1, CpuAVX512DQ, Modrm|EVex=4|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, Imm8, RegXMM, RegXMM, RegXMM }
3840
3841 vrangess, 0x6651, None, 1, CpuAVX512DQ, Modrm|EVex=4|Masking=3|OpcodePrefix=2|VexVVVV|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
3842 vrangess, 0x6651, None, 1, CpuAVX512DQ, Modrm|EVex=4|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, Imm8, RegXMM, RegXMM, RegXMM }
3843 vreducess, 0x6657, None, 1, CpuAVX512DQ, Modrm|EVex=4|Masking=3|OpcodePrefix=2|VexVVVV|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
3844 vreducess, 0x6657, None, 1, CpuAVX512DQ, Modrm|EVex=4|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, Imm8, RegXMM, RegXMM, RegXMM }
3845
3846 // AVX512DQ instructions end.
3847
3848 // CLWB instructions.
3849
3850 clwb, 0x0fae, 0x6, 2, CpuCLWB, Prefix_0X66|Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex }
3851
3852 // CLWB instructions end.
3853
3854 // AVX512IFMA instructions
3855
3856 vpmadd52huq, 0x66B5, None, 1, CpuAVX512IFMA, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3857 vpmadd52luq, 0x66B4, None, 1, CpuAVX512IFMA, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3858
3859 // AVX512IFMA instructions end
3860
3861 // AVX512VBMI instructions
3862
3863 vpmultishiftqb, 0x6683, None, 1, CpuAVX512VBMI, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3864 vpermb, 0x668D, None, 1, CpuAVX512VBMI, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3865 vpermi2b, 0x6675, None, 1, CpuAVX512VBMI, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3866 vpermt2b, 0x667D, None, 1, CpuAVX512VBMI, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3867
3868 // AVX512VBMI instructions end
3869
3870 // AVX512_4FMAPS instructions
3871
3872 v4fmaddps, 0xf29a, None, 1, CpuAVX512_4FMAPS, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
3873 v4fnmaddps, 0xf2aa, None, 1, CpuAVX512_4FMAPS, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
3874 v4fmaddss, 0xf29b, None, 1, CpuAVX512_4FMAPS, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegXMM, RegXMM }
3875 v4fnmaddss, 0xf2ab, None, 1, CpuAVX512_4FMAPS, Modrm|EVex=4|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegXMM, RegXMM }
3876
3877 // AVX512_4FMAPS instructions end
3878
3879 // AVX512_4VNNIW instructions
3880
3881 vp4dpwssd, 0xf252, None, 1, CpuAVX512_4VNNIW, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
3882 vp4dpwssds, 0xf253, None, 1, CpuAVX512_4VNNIW, Modrm|EVex=1|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
3883
3884 // AVX512_4VNNIW instructions end
3885
3886 // AVX512_VPOPCNTDQ instructions
3887
3888 vpopcntd, 0x6655, None, 1, CpuAVX512_VPOPCNTDQ, Modrm|Masking=3|OpcodePrefix=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3889 vpopcntq, 0x6655, None, 1, CpuAVX512_VPOPCNTDQ, Modrm|Masking=3|OpcodePrefix=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3890
3891 // AVX512_VPOPCNTDQ instructions end
3892
3893 // AVX512_VBMI2 instructions
3894
3895 vpcompressb, 0x6663, None, 1, CpuAVX512_VBMI2, Modrm|MaskingMorZ|OpcodePrefix=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex }
3896 vpcompressw, 0x6663, None, 1, CpuAVX512_VBMI2, Modrm|MaskingMorZ|OpcodePrefix=1|VexW=2|Disp8MemShift=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex }
3897
3898 vpexpandb, 0x6662, None, 1, CpuAVX512_VBMI2, Modrm|Masking=3|OpcodePrefix=1|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3899 vpexpandw, 0x6662, None, 1, CpuAVX512_VBMI2, Modrm|Masking=3|OpcodePrefix=1|VexW=2|Disp8MemShift=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3900
3901 vpshldvd, 0x6671, None, 1, CpuAVX512_VBMI2, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3902 vpshrdvd, 0x6673, None, 1, CpuAVX512_VBMI2, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3903
3904 vpshldvq, 0x6671, None, 1, CpuAVX512_VBMI2, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3905 vpshrdvq, 0x6673, None, 1, CpuAVX512_VBMI2, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3906
3907 vpshldvw, 0x6670, None, 1, CpuAVX512_VBMI2, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3908 vpshrdvw, 0x6672, None, 1, CpuAVX512_VBMI2, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3909
3910 vpshldd, 0x6671, None, 1, CpuAVX512_VBMI2, Modrm|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3911 vpshrdd, 0x6673, None, 1, CpuAVX512_VBMI2, Modrm|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3912
3913 vpshldq, 0x6671, None, 1, CpuAVX512_VBMI2, Modrm|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3914 vpshrdq, 0x6673, None, 1, CpuAVX512_VBMI2, Modrm|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3915
3916 vpshldw, 0x6670, None, 1, CpuAVX512_VBMI2, Modrm|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3917 vpshrdw, 0x6672, None, 1, CpuAVX512_VBMI2, Modrm|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3918
3919 // AVX512_VBMI2 instructions end
3920
3921 // AVX_VNNI instructions
3922
3923 vpdpbusd, 0x6650, None, 1, CpuAVX_VNNI, Modrm|Vex|PseudoVexPrefix|OpcodePrefix=1|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
3924 vpdpwssd, 0x6652, None, 1, CpuAVX_VNNI, Modrm|Vex|PseudoVexPrefix|OpcodePrefix=1|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
3925
3926 vpdpbusds, 0x6651, None, 1, CpuAVX_VNNI, Modrm|Vex|PseudoVexPrefix|OpcodePrefix=1|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
3927 vpdpwssds, 0x6653, None, 1, CpuAVX_VNNI, Modrm|Vex|PseudoVexPrefix|OpcodePrefix=1|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
3928
3929 // AVX_VNNI instructions end
3930
3931 // AVX512_VNNI instructions
3932
3933 vpdpbusd, 0x6650, None, 1, CpuAVX512_VNNI, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3934 vpdpwssd, 0x6652, None, 1, CpuAVX512_VNNI, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3935
3936 vpdpbusds, 0x6651, None, 1, CpuAVX512_VNNI, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3937 vpdpwssds, 0x6653, None, 1, CpuAVX512_VNNI, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3938
3939 // AVX512_VNNI instructions end
3940
3941 // AVX512_BITALG instructions
3942
3943 vpopcntb, 0x6654, None, 1, CpuAVX512_BITALG, Modrm|Masking=3|OpcodePrefix=1|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3944 vpopcntw, 0x6654, None, 1, CpuAVX512_BITALG, Modrm|Masking=3|OpcodePrefix=1|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
3945
3946 vpshufbitqmb, 0x668f, None, 1, CpuAVX512_BITALG, Modrm|Masking=2|OpcodePrefix=1|VexVVVV=1|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
3947
3948 // AVX512_BITALG instructions end
3949
3950 // AVX512 + GFNI instructions
3951
3952 vgf2p8affineinvqb, 0x66cf, None, 1, CpuGFNI|CpuAVX512F, Modrm|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3953 vgf2p8affineqb, 0x66ce, None, 1, CpuGFNI|CpuAVX512F, Modrm|Masking=3|OpcodePrefix=2|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3954 vgf2p8mulb, 0x66cf, None, 1, CpuGFNI|CpuAVX512F, Modrm|Masking=3|OpcodePrefix=1|VexVVVV=1|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3955
3956 // AVX512 + GFNI instructions end
3957
3958 // AVX512 + VAES instructions
3959
3960 vaesdec, 0x66de, None, 1, CpuVAES|CpuAVX512F, Modrm|OpcodePrefix=1|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3961 vaesdeclast, 0x66df, None, 1, CpuVAES|CpuAVX512F, Modrm|OpcodePrefix=1|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3962 vaesenc, 0x66dc, None, 1, CpuVAES|CpuAVX512F, Modrm|OpcodePrefix=1|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3963 vaesenclast, 0x66dd, None, 1, CpuVAES|CpuAVX512F, Modrm|OpcodePrefix=1|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3964
3965 // AVX512 + VAES instructions end
3966
3967 // AVX512 + VPCLMULQDQ instructions
3968
3969 vpclmulqdq, 0x6644, None, 1, CpuVPCLMULQDQ|CpuAVX512F, Modrm|OpcodePrefix=2|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3970 vpclmullqlqdq, 0x6644, 0x00, 1, CpuVPCLMULQDQ|CpuAVX512F, Modrm|OpcodePrefix=2|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3971 vpclmulhqlqdq, 0x6644, 0x01, 1, CpuVPCLMULQDQ|CpuAVX512F, Modrm|OpcodePrefix=2|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3972 vpclmullqhqdq, 0x6644, 0x10, 1, CpuVPCLMULQDQ|CpuAVX512F, Modrm|OpcodePrefix=2|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3973 vpclmulhqhqdq, 0x6644, 0x11, 1, CpuVPCLMULQDQ|CpuAVX512F, Modrm|OpcodePrefix=2|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
3974
3975 // AVX512 + VPCLMULQDQ instructions end
3976
3977 // INVLPGB instructions
3978
3979 invlpgb, 0xf01fe, None, 3, CpuINVLPGB, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
3980 invlpgb, 0xf01fe, None, 3, CpuINVLPGB, AddrPrefixOpReg, { Acc|Word|Dword|Qword, RegD|Dword }
3981
3982 // INVLPGB instructions end
3983
3984 // TLBSYNC instructions
3985
3986 tlbsync, 0xf01ff, None, 3, CpuTLBSYNC, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
3987
3988 // TLBSYNC instructions end
3989
3990 // CLZERO instructions
3991
3992 clzero, 0xf01fc, None, 3, CpuCLZERO, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
3993 clzero, 0xf01fc, None, 3, CpuCLZERO, AddrPrefixOpReg, { Acc|Word|Dword|Qword }
3994
3995 // CLZERO instructions end
3996
3997 // MONITORX/MWAITX instructions
3998
3999 monitorx, 0xf01fa, None, 3, CpuMWAITX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
4000 monitorx, 0xf01fa, None, 3, CpuMWAITX, AddrPrefixOpReg, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword }
4001 // The 64-bit form exists only for compatibility with older gas.
4002 monitorx, 0xf01fa, None, 3, CpuMWAITX|Cpu64, AddrPrefixOpReg, { Acc|Dword|Qword, RegC|Qword, RegD|Qword }
4003
4004 mwaitx, 0xf01fb, None, 3, CpuMWAITX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
4005 // The 64-bit form exists only for compatibility with older gas.
4006 mwaitx, 0xf01fb, None, 3, CpuMWAITX, CheckRegSize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Acc|Dword|Qword, RegC|Dword|Qword, RegB|Dword|Qword }
4007
4008 // MONITORX/MWAITX instructions end
4009
4010 // OSPKE instructions.
4011
4012 rdpkru, 0xf01ee, None, 3, CpuOSPKE, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
4013 wrpkru, 0xf01ef, None, 3, CpuOSPKE, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
4014
4015 // OSPKE instructions end.
4016
4017 // RDPID instructions.
4018
4019 rdpid, 0x0fc7, 0x7, 2, CpuRDPID|CpuNo64, Prefix_0XF3|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32 }
4020 rdpid, 0x0fc7, 0x7, 2, CpuRDPID|Cpu64, Prefix_0XF3|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64 }
4021
4022 // RDPID instructions end.
4023
4024 // PTWRITE instructions.
4025
4026 ptwrite, 0x0fae, 0x4, 2, CpuPTWRITE|CpuNo64, Prefix_0XF3|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex }
4027 ptwrite, 0x0fae, 0x4, 2, CpuPTWRITE|Cpu64, Prefix_0XF3|Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Unspecified|BaseIndex }
4028
4029 // PTWRITE instructions end.
4030
4031 // CET instructions.
4032
4033 incsspd, 0x0fae, 0x5, 2, CpuSHSTK, Prefix_0XF3|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32 }
4034 incsspq, 0x0fae, 0x5, 2, CpuSHSTK|Cpu64, Prefix_0XF3|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg64 }
4035 rdsspd, 0x0f1e, 0x1, 2, CpuSHSTK, Prefix_0XF3|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32 }
4036 rdsspq, 0x0f1e, 0x1, 2, CpuSHSTK|Cpu64, Prefix_0XF3|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg64 }
4037 saveprevssp, 0x0f01ea, None, 3, CpuSHSTK, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
4038 rstorssp, 0x0f01, 0x5, 2, CpuSHSTK, Prefix_0XF3|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex }
4039 wrssd, 0x0f38f6, None, 3, CpuSHSTK, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, Dword|Unspecified|BaseIndex }
4040 wrssq, 0x0f38f6, None, 3, CpuSHSTK|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64, Qword|Unspecified|BaseIndex }
4041 wrussd, 0x0f38f5, None, 3, CpuSHSTK, Prefix_0X66|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, Dword|Unspecified|BaseIndex }
4042 wrussq, 0x0f38f5, None, 3, CpuSHSTK|Cpu64, Prefix_0X66|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64, Qword|Unspecified|BaseIndex }
4043 setssbsy, 0x0f01e8, None, 3, CpuSHSTK, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
4044 clrssbsy, 0x0fae, 0x6, 2, CpuSHSTK, Prefix_0XF3|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex }
4045 endbr64, 0x0f1efa, None, 3, CpuIBT, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
4046 endbr32, 0x0f1efb, None, 3, CpuIBT, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
4047
4048 // notrack prefix
4049 notrack, 0x3e, None, 1, CpuIBT, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {}
4050
4051 // CET instructions end.
4052
4053 // WBNOINVD instruction.
4054
4055 wbnoinvd, 0x0f09, None, 2, CpuWBNOINVD, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
4056
4057 // WBNOINVD instruction end.
4058
4059 // PCONFIG instruction.
4060
4061 pconfig, 0x0f01c5, None, 3, CpuPCONFIG, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
4062
4063 // PCONFIG instruction end.
4064
4065 // WAITPKG instructions.
4066
4067 umonitor, 0x0fae, 0x6, 2, CpuWAITPKG, Prefix_0XF3|Modrm|AddrPrefixOpReg, { Reg16|Reg32|Reg64 }
4068 tpause, 0x0fae, 0x6, 2, CpuWAITPKG, Prefix_0X66|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32 }
4069 tpause, 0x0fae, 0x6, 2, CpuWAITPKG, Prefix_0X66|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegD|Dword, Acc|Dword }
4070 umwait, 0x0fae, 0x6, 2, CpuWAITPKG, Prefix_0XF2|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32 }
4071 umwait, 0x0fae, 0x6, 2, CpuWAITPKG, Prefix_0XF2|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegD|Dword, Acc|Dword }
4072
4073 // WAITPKG instructions end.
4074
4075 // CLDEMOTE instructions.
4076
4077 cldemote, 0x0f1c, 0x0, 2, CpuCLDEMOTE, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex }
4078
4079 // CLDEMOTE instructions end.
4080
4081 // MOVDIR[I,64B] instructions.
4082
4083 movdiri, 0xf38f9, None, 3, CpuMOVDIRI, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
4084 movdir64b, 0x0f38f8, None, 3, CpuMOVDIR64B, Prefix_0X66|Modrm|AddrPrefixOpReg, { Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
4085
4086 // MOVEDIR instructions end.
4087
4088 // AVX512_BF16 instructions.
4089
4090 vcvtne2ps2bf16, 0xf272, None, 1, CpuAVX512_BF16, Modrm|OpcodePrefix|VexVVVV|Masking=3|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
4091
4092 vcvtneps2bf16, 0xf372, None, 1, CpuAVX512_BF16, Modrm|OpcodePrefix|EVex512|Masking=3|VexW0|Broadcast|Disp8MemShift=6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Dword|Unspecified|BaseIndex, RegYMM }
4093 vcvtneps2bf16, 0xf372, None, 1, CpuAVX512_BF16|CpuAVX512VL, Modrm|OpcodePrefix|Masking=3|VexW0|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { RegXMM|RegYMM|Dword|Unspecified|BaseIndex, RegXMM }
4094 vcvtneps2bf16, 0xf372, None, 1, CpuAVX512_BF16|CpuAVX512VL, Modrm|OpcodePrefix|Masking=3|VexW0|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|RegYMM|Dword|BaseIndex, RegXMM }
4095 vcvtneps2bf16x, 0xf372, None, 1, CpuAVX512_BF16|CpuAVX512VL, Modrm|OpcodePrefix|EVex128|Masking=3|VexW0|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM }
4096 vcvtneps2bf16y, 0xf372, None, 1, CpuAVX512_BF16|CpuAVX512VL, Modrm|OpcodePrefix|EVex256|Masking=3|VexW0|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { RegYMM|Dword|Unspecified|BaseIndex, RegXMM }
4097
4098 vdpbf16ps, 0xf352, None, 1, CpuAVX512_BF16, Modrm|OpcodePrefix|VexVVVV|Masking=3|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
4099
4100 // AVX512_BF16 instructions end.
4101
4102 // ENQCMD instructions.
4103
4104 enqcmd, 0x0f38f8, None, 3, CpuENQCMD, Prefix_0XF2|Modrm|AddrPrefixOpReg, { Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
4105 enqcmds, 0x0f38f8, None, 3, CpuENQCMD, Prefix_0XF3|Modrm|AddrPrefixOpReg, { Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
4106
4107 // ENQCMD instructions end.
4108
4109 // VP2INTERSECT instructions.
4110
4111 vp2intersectd, 0xf268, None, 1, CpuAVX512_VP2INTERSECT, Modrm|OpcodePrefix|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
4112 vp2intersectq, 0xf268, None, 1, CpuAVX512_VP2INTERSECT, Modrm|OpcodePrefix|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
4113
4114 // VP2INTERSECT instructions end.
4115
4116 // MCOMMIT instruction
4117
4118 mcommit, 0x0f01fa, None, 3, CpuMCOMMIT, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
4119
4120 // MCOMMIT instruction end
4121
4122 // SNP instructions
4123
4124 psmash, 0xf01ff, None, 3, CpuSNP|Cpu64, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
4125 psmash, 0xf01ff, None, 3, CpuSNP|Cpu64, AddrPrefixOpReg|Prefix_0XF3, { Acc|Dword|Qword }
4126 pvalidate, 0xf01ff, None, 3, CpuSNP, Prefix_0XF2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
4127 pvalidate, 0xf01ff, None, 3, CpuSNP, AddrPrefixOpReg|Prefix_0XF2, { Acc|Word|Dword|Qword }
4128 rmpupdate, 0xf01fe, None, 3, CpuSNP|Cpu64, Prefix_0XF2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
4129 rmpupdate, 0xf01fe, None, 3, CpuSNP|Cpu64, AddrPrefixOpReg|Prefix_0XF2, { Acc|Dword|Qword }
4130 rmpadjust, 0xf01fe, None, 3, CpuSNP|Cpu64, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
4131 rmpadjust, 0xf01fe, None, 3, CpuSNP|Cpu64, AddrPrefixOpReg|Prefix_0XF3, { Acc|Dword|Qword }
4132
4133 // SNP instructions end
4134
4135 // RDPRU instruction
4136
4137 rdpru, 0x0f01fd, None, 3, CpuRDPRU, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
4138
4139 // RDPRU instruction end
4140
4141 // SERIALIZE instruction.
4142
4143 serialize, 0x0f01e8, None, 3, CpuSERIALIZE, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
4144
4145 // SERIALIZE instruction end.
4146
4147 // TSXLDTRK instructions.
4148
4149 xsusldtrk, 0x0f01e8, None, 3, CpuTSXLDTRK, Prefix_0XF2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
4150 xresldtrk, 0x0f01e9, None, 3, CpuTSXLDTRK, Prefix_0XF2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
4151
4152 // TSXLDTRK instructions end.
4153
4154 // AMX instructions.
4155
4156 ldtilecfg, 0x49, None, 1, CpuAMX_TILE|Cpu64, Modrm|Vex128|OpcodePrefix=1|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex }
4157 sttilecfg, 0x6649, None, 1, CpuAMX_TILE|Cpu64, Modrm|Vex128|OpcodePrefix=1|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex }
4158
4159 tdpbf16ps, 0xf35c, None, 1, CpuAMX_BF16|Cpu64, Modrm|Vex128|OpcodePrefix=1|VexVVVV=1|VexW0|SwapSources|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegTMM, RegTMM, RegTMM }
4160 tdpbssd, 0xf25e, None, 1, CpuAMX_INT8|Cpu64, Modrm|Vex128|OpcodePrefix=1|VexVVVV=1|VexW0|SwapSources|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegTMM, RegTMM, RegTMM }
4161 tdpbuud, 0x5e,   None, 1, CpuAMX_INT8|Cpu64, Modrm|Vex128|OpcodePrefix=1|VexVVVV=1|VexW0|SwapSources|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegTMM, RegTMM, RegTMM }
4162 tdpbusd, 0x665e, None, 1, CpuAMX_INT8|Cpu64, Modrm|Vex128|OpcodePrefix=1|VexVVVV=1|VexW0|SwapSources|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegTMM, RegTMM, RegTMM }
4163 tdpbsud, 0xf35e, None, 1, CpuAMX_INT8|Cpu64, Modrm|Vex128|OpcodePrefix=1|VexVVVV=1|VexW0|SwapSources|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegTMM, RegTMM, RegTMM }
4164
4165 tileloadd, 0xf24b, None, 1, CpuAMX_TILE|Cpu64, Sibmem|Vex128|OpcodePrefix=1|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex, RegTMM }
4166 tileloaddt1, 0x664b, None, 1, CpuAMX_TILE|Cpu64, Sibmem|Vex128|OpcodePrefix=1|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex, RegTMM }
4167 tilestored, 0xf34b, None, 1, CpuAMX_TILE|Cpu64, Sibmem|Vex128|OpcodePrefix=1|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegTMM, Unspecified|BaseIndex }
4168
4169 tilerelease, 0x49c0, None, 2, CpuAMX_TILE|Cpu64, Vex128|OpcodePrefix=1|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
4170
4171 tilezero, 0xf249, None, 1, CpuAMX_TILE|Cpu64, Modrm|Vex128|OpcodePrefix=1|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegTMM }
4172
4173 // AMX instructions end.
4174
4175 // KEYLOCKER instructions.
4176
4177 loadiwkey, 0x0f38dc, None, 3, CpuKL, Prefix_0XF3|Load|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegXMM, RegXMM }
4178 encodekey128, 0x0f38fa, None, 3, CpuKL, Prefix_0XF3|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg32, Reg32 }
4179 encodekey256, 0x0f38fb, None, 3, CpuKL, Prefix_0XF3|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg32, Reg32 }
4180 aesenc128kl, 0x0f38dc, None, 3, CpuKL, Prefix_0XF3|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex, RegXMM }
4181 aesdec128kl, 0x0f38dd, None, 3, CpuKL, Prefix_0XF3|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex, RegXMM }
4182 aesenc256kl, 0x0f38de, None, 3, CpuKL, Prefix_0XF3|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex, RegXMM }
4183 aesdec256kl, 0x0f38df, None, 3, CpuKL, Prefix_0XF3|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex, RegXMM }
4184 aesencwide128kl, 0x0f38d8, 0x0, 3, CpuWideKL, Prefix_0XF3|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex }
4185 aesdecwide128kl, 0x0f38d8, 0x1, 3, CpuWideKL, Prefix_0XF3|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex }
4186 aesencwide256kl, 0x0f38d8, 0x2, 3, CpuWideKL, Prefix_0XF3|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex }
4187 aesdecwide256kl, 0x0f38d8, 0x3, 3, CpuWideKL, Prefix_0XF3|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex }
4188
4189 // KEYLOCKER instructions end.
4190
4191 // TDX instructions.
4192
4193 tdcall, 0x0f01cc, None, 3, CpuTDX, Prefix_0X66|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
4194 seamret, 0x0f01cd, None, 3, CpuTDX|Cpu64, Prefix_0X66|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
4195 seamops, 0x0f01ce, None, 3, CpuTDX|Cpu64, Prefix_0X66|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
4196 seamcall, 0x0f01cf, None, 3, CpuTDX|Cpu64, Prefix_0X66|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
4197
4198 // TDX instructions end.
4199
4200 // UINTR instructions.
4201
4202 uiret, 0x0f01ec, None, 3, CpuUINTR|Cpu64, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
4203 clui, 0x0f01ee, None, 3, CpuUINTR|Cpu64, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
4204 stui, 0x0f01ef, None, 3, CpuUINTR|Cpu64, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
4205 testui, 0x0f01ed, None, 3, CpuUINTR|Cpu64, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
4206 senduipi, 0x0fc7, 0x6, 2, CpuUINTR|Cpu64, Prefix_0XF3|Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64 }
4207
4208 // UINTR instructions end.
4209
4210 // HRESET instructions.
4211
4212 hreset, 0x0f3af0c0, None, 4, CpuHRESET, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8 }
4213
4214 // HRESET instructions end.