1 /* Disassembler for the i860.
2 Copyright 2000, 2003 Free Software Foundation, Inc.
4 Contributed by Jason Eckhardt <jle@cygnus.com>.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
21 #include "opcode/i860.h"
23 /* Later we should probably choose the prefix based on which OS flavor. */
24 #define I860_REG_PREFIX "%"
26 /* Integer register names (encoded as 0..31 in the instruction). */
27 static const char *const grnames
[] =
28 {"r0", "r1", "sp", "fp", "r4", "r5", "r6", "r7",
29 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
30 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
31 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"};
33 /* FP register names (encoded as 0..31 in the instruction). */
34 static const char *const frnames
[] =
35 {"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
36 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
37 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
38 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"};
40 /* Control/status register names (encoded as 0..11 in the instruction).
41 Registers bear, ccr, p0, p1, p2 and p3 are XP only. */
42 static const char *const crnames
[] =
43 {"fir", "psr", "dirbase", "db", "fsr", "epsr", "bear", "ccr",
44 "p0", "p1", "p2", "p3", "--", "--", "--", "--" };
48 /* True if opcode is xor, xorh, and, andh, or, orh, andnot, andnoth. */
49 #define BITWISE_OP(op) ((op) == 0x30 || (op) == 0x31 \
50 || (op) == 0x34 || (op) == 0x35 \
51 || (op) == 0x38 || (op) == 0x39 \
52 || (op) == 0x3c || (op) == 0x3d \
53 || (op) == 0x33 || (op) == 0x37 \
54 || (op) == 0x3b || (op) == 0x3f)
57 /* Sign extend N-bit number. */
59 sign_ext (unsigned int x
, int n
)
68 /* Print a PC-relative branch offset. VAL is the sign extended value
69 from the branch instruction. */
71 print_br_address (disassemble_info
*info
, bfd_vma memaddr
, long val
)
74 long adj
= (long)memaddr
+ 4 + (val
<< 2);
76 (*info
->fprintf_func
) (info
->stream
, "0x%08x", adj
);
78 /* Attempt to obtain a symbol for the target address. */
80 if (info
->print_address_func
&& adj
!= 0)
82 (*info
->fprintf_func
) (info
->stream
, "\t// ");
83 (*info
->print_address_func
) (adj
, info
);
88 /* Print one instruction. */
90 print_insn_i860 (bfd_vma memaddr
, disassemble_info
*info
)
95 const struct i860_opcode
*opcode
= 0;
97 status
= (*info
->read_memory_func
) (memaddr
, buff
, sizeof (buff
), info
);
100 (*info
->memory_error_func
) (status
, memaddr
, info
);
104 /* Note that i860 instructions are always accessed as little endian
105 data, regardless of the endian mode of the i860. */
106 insn
= bfd_getl32 (buff
);
110 while (i860_opcodes
[i
].name
!= NULL
)
112 opcode
= &i860_opcodes
[i
];
113 if ((insn
& opcode
->match
) == opcode
->match
114 && (insn
& opcode
->lose
) == 0)
124 /* Instruction not in opcode table. */
125 (*info
->fprintf_func
) (info
->stream
, ".long %#08x", insn
);
132 /* If this a flop (or a shrd) and its dual bit is set,
134 if (((insn
& 0xfc000000) == 0x48000000
135 || (insn
& 0xfc000000) == 0xb0000000)
137 (*info
->fprintf_func
) (info
->stream
, "d.%s\t", opcode
->name
);
139 (*info
->fprintf_func
) (info
->stream
, "%s\t", opcode
->name
);
141 for (s
= opcode
->args
; *s
; s
++)
145 /* Integer register (src1). */
147 (*info
->fprintf_func
) (info
->stream
, "%s%s", I860_REG_PREFIX
,
148 grnames
[(insn
>> 11) & 0x1f]);
151 /* Integer register (src2). */
153 (*info
->fprintf_func
) (info
->stream
, "%s%s", I860_REG_PREFIX
,
154 grnames
[(insn
>> 21) & 0x1f]);
157 /* Integer destination register. */
159 (*info
->fprintf_func
) (info
->stream
, "%s%s", I860_REG_PREFIX
,
160 grnames
[(insn
>> 16) & 0x1f]);
163 /* Floating-point register (src1). */
165 (*info
->fprintf_func
) (info
->stream
, "%s%s", I860_REG_PREFIX
,
166 frnames
[(insn
>> 11) & 0x1f]);
169 /* Floating-point register (src2). */
171 (*info
->fprintf_func
) (info
->stream
, "%s%s", I860_REG_PREFIX
,
172 frnames
[(insn
>> 21) & 0x1f]);
175 /* Floating-point destination register. */
177 (*info
->fprintf_func
) (info
->stream
, "%s%s", I860_REG_PREFIX
,
178 frnames
[(insn
>> 16) & 0x1f]);
181 /* Control register. */
183 (*info
->fprintf_func
) (info
->stream
, "%s%s", I860_REG_PREFIX
,
184 crnames
[(insn
>> 21) & 0xf]);
187 /* 16-bit immediate (sign extend, except for bitwise ops). */
189 if (BITWISE_OP ((insn
& 0xfc000000) >> 26))
190 (*info
->fprintf_func
) (info
->stream
, "0x%04x",
191 (unsigned int) (insn
& 0xffff));
193 (*info
->fprintf_func
) (info
->stream
, "%d",
194 sign_ext ((insn
& 0xffff), 16));
197 /* 16-bit immediate, aligned (2^0, ld.b). */
199 (*info
->fprintf_func
) (info
->stream
, "%d",
200 sign_ext ((insn
& 0xffff), 16));
203 /* 16-bit immediate, aligned (2^1, ld.s). */
205 (*info
->fprintf_func
) (info
->stream
, "%d",
206 sign_ext ((insn
& 0xfffe), 16));
209 /* 16-bit immediate, aligned (2^2, ld.l, {p}fld.l, fst.l). */
211 (*info
->fprintf_func
) (info
->stream
, "%d",
212 sign_ext ((insn
& 0xfffc), 16));
215 /* 16-bit immediate, aligned (2^3, {p}fld.d, fst.d). */
217 (*info
->fprintf_func
) (info
->stream
, "%d",
218 sign_ext ((insn
& 0xfff8), 16));
221 /* 16-bit immediate, aligned (2^4, {p}fld.q, fst.q). */
223 (*info
->fprintf_func
) (info
->stream
, "%d",
224 sign_ext ((insn
& 0xfff0), 16));
227 /* 5-bit immediate (zero extend). */
229 (*info
->fprintf_func
) (info
->stream
, "%d",
230 ((insn
>> 11) & 0x1f));
233 /* Split 16 bit immediate (20..16:10..0). */
235 val
= ((insn
>> 5) & 0xf800) | (insn
& 0x07ff);
236 (*info
->fprintf_func
) (info
->stream
, "%d",
240 /* Split 16 bit immediate, aligned. (2^0, st.b). */
242 val
= ((insn
>> 5) & 0xf800) | (insn
& 0x07ff);
243 (*info
->fprintf_func
) (info
->stream
, "%d",
247 /* Split 16 bit immediate, aligned. (2^1, st.s). */
249 val
= ((insn
>> 5) & 0xf800) | (insn
& 0x07fe);
250 (*info
->fprintf_func
) (info
->stream
, "%d",
254 /* Split 16 bit immediate, aligned. (2^2, st.l). */
256 val
= ((insn
>> 5) & 0xf800) | (insn
& 0x07fc);
257 (*info
->fprintf_func
) (info
->stream
, "%d",
261 /* 26-bit PC relative immediate (lbroff). */
263 val
= sign_ext ((insn
& 0x03ffffff), 26);
264 print_br_address (info
, memaddr
, val
);
267 /* 16-bit PC relative immediate (sbroff). */
269 val
= sign_ext ((((insn
>> 5) & 0xf800) | (insn
& 0x07ff)), 16);
270 print_br_address (info
, memaddr
, val
);
274 (*info
->fprintf_func
) (info
->stream
, "%c", *s
);
280 return sizeof (insn
);
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