1 /* Disassembler for the i860.
2 Copyright 2000, 2003, 2005, 2007, 2012 Free Software Foundation, Inc.
4 Contributed by Jason Eckhardt <jle@cygnus.com>.
6 This file is part of the GNU opcodes library.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
25 #include "opcode/i860.h"
27 /* Later we should probably choose the prefix based on which OS flavor. */
28 #define I860_REG_PREFIX "%"
30 /* Integer register names (encoded as 0..31 in the instruction). */
31 static const char *const grnames
[] =
32 {"r0", "r1", "sp", "fp", "r4", "r5", "r6", "r7",
33 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
34 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
35 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"};
37 /* FP register names (encoded as 0..31 in the instruction). */
38 static const char *const frnames
[] =
39 {"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
40 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
41 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
42 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"};
44 /* Control/status register names (encoded as 0..11 in the instruction).
45 Registers bear, ccr, p0, p1, p2 and p3 are XP only. */
46 static const char *const crnames
[] =
47 {"fir", "psr", "dirbase", "db", "fsr", "epsr", "bear", "ccr",
48 "p0", "p1", "p2", "p3", "--", "--", "--", "--" };
52 /* True if opcode is xor, xorh, and, andh, or, orh, andnot, andnoth. */
53 #define BITWISE_OP(op) ((op) == 0x30 || (op) == 0x31 \
54 || (op) == 0x34 || (op) == 0x35 \
55 || (op) == 0x38 || (op) == 0x39 \
56 || (op) == 0x3c || (op) == 0x3d \
57 || (op) == 0x33 || (op) == 0x37 \
58 || (op) == 0x3b || (op) == 0x3f)
61 /* Sign extend N-bit number. */
63 sign_ext (unsigned int x
, int n
)
72 /* Print a PC-relative branch offset. VAL is the sign extended value
73 from the branch instruction. */
75 print_br_address (disassemble_info
*info
, bfd_vma memaddr
, long val
)
78 long adj
= (long)memaddr
+ 4 + (val
<< 2);
80 (*info
->fprintf_func
) (info
->stream
, "0x%08lx", adj
);
82 /* Attempt to obtain a symbol for the target address. */
84 if (info
->print_address_func
&& adj
!= 0)
86 (*info
->fprintf_func
) (info
->stream
, "\t// ");
87 (*info
->print_address_func
) (adj
, info
);
92 /* Print one instruction. */
94 print_insn_i860 (bfd_vma memaddr
, disassemble_info
*info
)
99 const struct i860_opcode
*opcode
= 0;
101 status
= (*info
->read_memory_func
) (memaddr
, buff
, sizeof (buff
), info
);
104 (*info
->memory_error_func
) (status
, memaddr
, info
);
108 /* Note that i860 instructions are always accessed as little endian
109 data, regardless of the endian mode of the i860. */
110 insn
= bfd_getl32 (buff
);
114 while (i860_opcodes
[i
].name
!= NULL
)
116 opcode
= &i860_opcodes
[i
];
117 if ((insn
& opcode
->match
) == opcode
->match
118 && (insn
& opcode
->lose
) == 0)
128 /* Instruction not in opcode table. */
129 (*info
->fprintf_func
) (info
->stream
, ".long %#08x", insn
);
136 /* If this a flop (or a shrd) and its dual bit is set,
138 if (((insn
& 0xfc000000) == 0x48000000
139 || (insn
& 0xfc000000) == 0xb0000000)
141 (*info
->fprintf_func
) (info
->stream
, "d.%s\t", opcode
->name
);
143 (*info
->fprintf_func
) (info
->stream
, "%s\t", opcode
->name
);
145 for (s
= opcode
->args
; *s
; s
++)
149 /* Integer register (src1). */
151 (*info
->fprintf_func
) (info
->stream
, "%s%s", I860_REG_PREFIX
,
152 grnames
[(insn
>> 11) & 0x1f]);
155 /* Integer register (src2). */
157 (*info
->fprintf_func
) (info
->stream
, "%s%s", I860_REG_PREFIX
,
158 grnames
[(insn
>> 21) & 0x1f]);
161 /* Integer destination register. */
163 (*info
->fprintf_func
) (info
->stream
, "%s%s", I860_REG_PREFIX
,
164 grnames
[(insn
>> 16) & 0x1f]);
167 /* Floating-point register (src1). */
169 (*info
->fprintf_func
) (info
->stream
, "%s%s", I860_REG_PREFIX
,
170 frnames
[(insn
>> 11) & 0x1f]);
173 /* Floating-point register (src2). */
175 (*info
->fprintf_func
) (info
->stream
, "%s%s", I860_REG_PREFIX
,
176 frnames
[(insn
>> 21) & 0x1f]);
179 /* Floating-point destination register. */
181 (*info
->fprintf_func
) (info
->stream
, "%s%s", I860_REG_PREFIX
,
182 frnames
[(insn
>> 16) & 0x1f]);
185 /* Control register. */
187 (*info
->fprintf_func
) (info
->stream
, "%s%s", I860_REG_PREFIX
,
188 crnames
[(insn
>> 21) & 0xf]);
191 /* 16-bit immediate (sign extend, except for bitwise ops). */
193 if (BITWISE_OP ((insn
& 0xfc000000) >> 26))
194 (*info
->fprintf_func
) (info
->stream
, "0x%04x",
195 (unsigned int) (insn
& 0xffff));
197 (*info
->fprintf_func
) (info
->stream
, "%d",
198 sign_ext ((insn
& 0xffff), 16));
201 /* 16-bit immediate, aligned (2^0, ld.b). */
203 (*info
->fprintf_func
) (info
->stream
, "%d",
204 sign_ext ((insn
& 0xffff), 16));
207 /* 16-bit immediate, aligned (2^1, ld.s). */
209 (*info
->fprintf_func
) (info
->stream
, "%d",
210 sign_ext ((insn
& 0xfffe), 16));
213 /* 16-bit immediate, aligned (2^2, ld.l, {p}fld.l, fst.l). */
215 (*info
->fprintf_func
) (info
->stream
, "%d",
216 sign_ext ((insn
& 0xfffc), 16));
219 /* 16-bit immediate, aligned (2^3, {p}fld.d, fst.d). */
221 (*info
->fprintf_func
) (info
->stream
, "%d",
222 sign_ext ((insn
& 0xfff8), 16));
225 /* 16-bit immediate, aligned (2^4, {p}fld.q, fst.q). */
227 (*info
->fprintf_func
) (info
->stream
, "%d",
228 sign_ext ((insn
& 0xfff0), 16));
231 /* 5-bit immediate (zero extend). */
233 (*info
->fprintf_func
) (info
->stream
, "%d",
234 ((insn
>> 11) & 0x1f));
237 /* Split 16 bit immediate (20..16:10..0). */
239 val
= ((insn
>> 5) & 0xf800) | (insn
& 0x07ff);
240 (*info
->fprintf_func
) (info
->stream
, "%d",
244 /* Split 16 bit immediate, aligned. (2^0, st.b). */
246 val
= ((insn
>> 5) & 0xf800) | (insn
& 0x07ff);
247 (*info
->fprintf_func
) (info
->stream
, "%d",
251 /* Split 16 bit immediate, aligned. (2^1, st.s). */
253 val
= ((insn
>> 5) & 0xf800) | (insn
& 0x07fe);
254 (*info
->fprintf_func
) (info
->stream
, "%d",
258 /* Split 16 bit immediate, aligned. (2^2, st.l). */
260 val
= ((insn
>> 5) & 0xf800) | (insn
& 0x07fc);
261 (*info
->fprintf_func
) (info
->stream
, "%d",
265 /* 26-bit PC relative immediate (lbroff). */
267 val
= sign_ext ((insn
& 0x03ffffff), 26);
268 print_br_address (info
, memaddr
, val
);
271 /* 16-bit PC relative immediate (sbroff). */
273 val
= sign_ext ((((insn
>> 5) & 0xf800) | (insn
& 0x07ff)), 16);
274 print_br_address (info
, memaddr
, val
);
278 (*info
->fprintf_func
) (info
->stream
, "%c", *s
);
284 return sizeof (insn
);
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