1 /* Disassemble i80960 instructions.
2 Copyright (C) 1990, 1991 Free Software Foundation, Inc.
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2, or (at your option)
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
14 You should have received a copy of the GNU General Public License
15 along with this program; see the file COPYING. If not, write to
16 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
20 static const char *const reg_names
[] = {
21 /* 0 */ "pfp", "sp", "rip", "r3", "r4", "r5", "r6", "r7",
22 /* 8 */ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
23 /* 16 */ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
24 /* 24 */ "g8", "g9", "g10", "g11", "g12", "g13", "g14", "fp",
25 /* 32 */ "pc", "ac", "ip", "tc", "fp0", "fp1", "fp2", "fp3"
29 static FILE *stream
; /* Output goes here */
30 static struct disassemble_info
*info
;
31 static void print_addr();
39 static void invalid();
41 static void put_abs();
44 /* Print the i960 instruction at address 'memaddr' in debugged memory,
45 on INFO->STREAM. Returns length of the instruction, in bytes. */
48 print_insn_i960 (memaddr
, info_arg
)
50 struct disassemble_info
*info_arg
;
52 unsigned int word1
, word2
= 0xdeadbeef;
57 stream
= info
->stream
;
59 /* Read word1. Only read word2 if the instruction
60 needs it, to prevent reading past the end of a section. */
62 status
= (*info
->read_memory_func
) (memaddr
, (bfd_byte
*) buffer
, 4, info
);
65 (*info
->memory_error_func
) (status
, memaddr
, info
);
69 word1
= bfd_getl32 (buffer
);
71 /* Divide instruction set into classes based on high 4 bits of opcode. */
72 switch ( (word1
>> 28) & 0xf )
82 status
= (*info
->read_memory_func
)
83 (memaddr
+ 4, (bfd_byte
*) (buffer
+ 4), 4, info
);
86 (*info
->memory_error_func
) (status
, memaddr
, info
);
89 word2
= bfd_getl32 (buffer
+ 4);
93 return pinsn( memaddr
, word1
, word2
);
98 /*****************************************************************************
99 * All code below this point should be identical with that of
100 * the disassembler in gdmp960.
102 A noble sentiment, but at least in cosmetic ways (info->fprintf_func), it
103 just ain't so. -kingdon, 31 Mar 93
104 *****************************************************************************/
111 struct sparse_tabent
{
118 pinsn( memaddr
, word1
, word2
)
119 unsigned long memaddr
;
120 unsigned long word1
, word2
;
125 put_abs( word1
, word2
);
127 /* Divide instruction set into classes based on high 4 bits of opcode*/
128 switch ( (word1
>> 28) & 0xf ){
131 ctrl( memaddr
, word1
, word2
);
135 cobr( memaddr
, word1
, word2
);
147 instr_len
= mem( memaddr
, word1
, word2
, 0 );
150 /* invalid instruction, print as data word */
157 /****************************************/
159 /****************************************/
161 ctrl( memaddr
, word1
, word2
)
162 unsigned long memaddr
;
163 unsigned long word1
, word2
;
166 static const struct tabent ctrl_tab
[] = {
176 "call", 1, /* 0x09 */
191 "faultno", 0, /* 0x18 */
192 "faultg", 0, /* 0x19 */
193 "faulte", 0, /* 0x1a */
194 "faultge", 0, /* 0x1b */
195 "faultl", 0, /* 0x1c */
196 "faultne", 0, /* 0x1d */
197 "faultle", 0, /* 0x1e */
198 "faulto", 0, /* 0x1f */
201 i
= (word1
>> 24) & 0xff;
202 if ( (ctrl_tab
[i
].name
== NULL
) || ((word1
& 1) != 0) ){
207 (*info
->fprintf_func
) ( stream
, ctrl_tab
[i
].name
);
208 if ( word1
& 2 ){ /* Predicts branch not taken */
209 (*info
->fprintf_func
) ( stream
, ".f" );
212 if ( ctrl_tab
[i
].numops
== 1 ){
213 /* EXTRACT DISPLACEMENT AND CONVERT TO ADDRESS */
215 if ( word1
& 0x00800000 ){ /* Sign bit is set */
216 word1
|= (-1 & ~0xffffff); /* Sign extend */
218 (*info
->fprintf_func
)( stream
, "\t" );
219 print_addr( word1
+ memaddr
);
223 /****************************************/
225 /****************************************/
227 cobr( memaddr
, word1
, word2
)
228 unsigned long memaddr
;
229 unsigned long word1
, word2
;
235 static const struct tabent cobr_tab
[] = {
236 "testno", 1, /* 0x20 */
237 "testg", 1, /* 0x21 */
238 "teste", 1, /* 0x22 */
239 "testge", 1, /* 0x23 */
240 "testl", 1, /* 0x24 */
241 "testne", 1, /* 0x25 */
242 "testle", 1, /* 0x26 */
243 "testo", 1, /* 0x27 */
253 "cmpobg", 3, /* 0x31 */
254 "cmpobe", 3, /* 0x32 */
255 "cmpobge", 3, /* 0x33 */
256 "cmpobl", 3, /* 0x34 */
257 "cmpobne", 3, /* 0x35 */
258 "cmpoble", 3, /* 0x36 */
260 "cmpibno", 3, /* 0x38 */
261 "cmpibg", 3, /* 0x39 */
262 "cmpibe", 3, /* 0x3a */
263 "cmpibge", 3, /* 0x3b */
264 "cmpibl", 3, /* 0x3c */
265 "cmpibne", 3, /* 0x3d */
266 "cmpible", 3, /* 0x3e */
267 "cmpibo", 3, /* 0x3f */
270 i
= ((word1
>> 24) & 0xff) - 0x20;
271 if ( cobr_tab
[i
].name
== NULL
){
276 (*info
->fprintf_func
) ( stream
, cobr_tab
[i
].name
);
277 if ( word1
& 2 ){ /* Predicts branch not taken */
278 (*info
->fprintf_func
) ( stream
, ".f" );
280 (*info
->fprintf_func
)( stream
, "\t" );
282 src1
= (word1
>> 19) & 0x1f;
283 src2
= (word1
>> 14) & 0x1f;
285 if ( word1
& 0x02000 ){ /* M1 is 1 */
286 (*info
->fprintf_func
)( stream
, "%d", src1
);
287 } else { /* M1 is 0 */
288 (*info
->fprintf_func
)( stream
, reg_names
[src1
] );
291 if ( cobr_tab
[i
].numops
> 1 ){
292 if ( word1
& 1 ){ /* S2 is 1 */
293 (*info
->fprintf_func
)( stream
, ",sf%d,", src2
);
294 } else { /* S1 is 0 */
295 (*info
->fprintf_func
)( stream
, ",%s,", reg_names
[src2
] );
298 /* Extract displacement and convert to address
301 if ( word1
& 0x00001000 ){ /* Negative displacement */
302 word1
|= (-1 & ~0x1fff); /* Sign extend */
304 print_addr( memaddr
+ word1
);
308 /****************************************/
310 /****************************************/
311 static int /* returns instruction length: 4 or 8 */
312 mem( memaddr
, word1
, word2
, noprint
)
313 unsigned long memaddr
;
314 unsigned long word1
, word2
;
315 int noprint
; /* If TRUE, return instruction length, but
316 * don't output any text.
323 const char *reg1
, *reg2
, *reg3
;
325 /* This lookup table is too sparse to make it worth typing in, but not
326 so large as to make a sparse array necessary. We create the table
330 * NOTE: In this table, the meaning of 'numops' is:
332 * 2: 2 operands, load instruction
333 * -2: 2 operands, store instruction
335 static struct tabent
*mem_tab
;
336 /* Opcodes of 0x8X, 9X, aX, bX, and cX must be in the table. */
339 #define MEM_SIZ ( * sizeof(struct tabent))
341 static const struct sparse_tabent mem_init
[] = {
364 static struct tabent mem_tab_buf
[MEM_MAX
- MEM_MIN
+ 1];
366 if ( mem_tab
== NULL
){
367 mem_tab
= mem_tab_buf
;
368 for ( i
= 0; mem_init
[i
].opcode
!= 0; i
++ ){
369 j
= mem_init
[i
].opcode
- MEM_MIN
;
370 mem_tab
[j
].name
= mem_init
[i
].name
;
371 mem_tab
[j
].numops
= mem_init
[i
].numops
;
375 i
= ((word1
>> 24) & 0xff) - MEM_MIN
;
376 mode
= (word1
>> 10) & 0xf;
378 if ( (mem_tab
[i
].name
!= NULL
) /* Valid instruction */
379 && ((mode
== 5) || (mode
>=12)) ){ /* With 32-bit displacement */
389 if ( (mem_tab
[i
].name
== NULL
) || (mode
== 6) ){
394 (*info
->fprintf_func
)( stream
, "%s\t", mem_tab
[i
].name
);
396 reg1
= reg_names
[ (word1
>> 19) & 0x1f ]; /* MEMB only */
397 reg2
= reg_names
[ (word1
>> 14) & 0x1f ];
398 reg3
= reg_names
[ word1
& 0x1f ]; /* MEMB only */
399 offset
= word1
& 0xfff; /* MEMA only */
401 switch ( mem_tab
[i
].numops
){
403 case 2: /* LOAD INSTRUCTION */
404 if ( mode
& 4 ){ /* MEMB FORMAT */
405 ea( memaddr
, mode
, reg2
, reg3
, word1
, word2
);
406 (*info
->fprintf_func
)( stream
, ",%s", reg1
);
407 } else { /* MEMA FORMAT */
408 (*info
->fprintf_func
)( stream
, "0x%x", (unsigned) offset
);
410 (*info
->fprintf_func
)( stream
, "(%s)", reg2
);
412 (*info
->fprintf_func
)( stream
, ",%s", reg1
);
416 case -2: /* STORE INSTRUCTION */
417 if ( mode
& 4 ){ /* MEMB FORMAT */
418 (*info
->fprintf_func
)( stream
, "%s,", reg1
);
419 ea( memaddr
, mode
, reg2
, reg3
, word1
, word2
);
420 } else { /* MEMA FORMAT */
421 (*info
->fprintf_func
)( stream
, "%s,0x%x", reg1
, (unsigned) offset
);
423 (*info
->fprintf_func
)( stream
, "(%s)", reg2
);
428 case 1: /* BX/CALLX INSTRUCTION */
429 if ( mode
& 4 ){ /* MEMB FORMAT */
430 ea( memaddr
, mode
, reg2
, reg3
, word1
, word2
);
431 } else { /* MEMA FORMAT */
432 (*info
->fprintf_func
)( stream
, "0x%x", (unsigned) offset
);
434 (*info
->fprintf_func
)( stream
, "(%s)", reg2
);
443 /****************************************/
445 /****************************************/
458 /* This lookup table is too sparse to make it worth typing in, but not
459 so large as to make a sparse array necessary. We create the table
463 * NOTE: In this table, the meaning of 'numops' is:
464 * 1: single operand, which is NOT a destination.
465 * -1: single operand, which IS a destination.
466 * 2: 2 operands, the 2nd of which is NOT a destination.
467 * -2: 2 operands, the 2nd of which IS a destination.
470 * If an opcode mnemonic begins with "F", it is a floating-point
471 * opcode (the "F" is not printed).
474 static struct tabent
*reg_tab
;
475 static const struct sparse_tabent reg_init
[] = {
476 #define REG_MIN 0x580
491 0x58f, "alterbit", 3,
496 0x594, "cmpob", 2, /* xl */
497 0x595, "cmpib", 2, /* xl */
498 0x596, "cmpos", 2, /* xl */
499 0x597, "cmpis", 2, /* xl */
514 0x5ac, "scanbyte", 2,
515 0x5ad, "bswap", -2, /* xl */
519 0x5b4, "intdis", 0, /* xl */
520 0x5b5, "inten", 0, /* xl */
534 0x613, "inspacc", -2,
540 0x640, "spanbit", -2,
541 0x641, "scanbit", -2,
546 0x646, "condrec", -2,
551 0x656, "receive", -2,
552 0x658, "intctl", -2, /* xl */
554 0x65b, "icctl", 3, /* xl */
555 0x65c, "dcctl", 3, /* xl */
556 0x65d, "halt", 0, /* xl */
559 0x663, "sendserv", 1,
560 0x664, "resumprcs", 1,
561 0x665, "schedprcs", 1,
562 0x666, "saveprcs", 0,
563 0x668, "condwait", 1,
568 0x66d, "flushreg", 0,
574 0x675, "Fcvtilr", -2,
575 0x676, "Fscalerl", 3,
585 0x68a, "Flogbnr", -2,
586 0x68b, "Froundr", -2,
592 0x691, "Flogeprl", 3,
597 0x698, "Fsqrtrl", -2,
599 0x69a, "Flogbnrl", -2,
600 0x69b, "Froundrl", -2,
604 0x69f, "Fclassrl", 1,
606 0x6c1, "Fcvtril", -2,
607 0x6c2, "Fcvtzri", -2,
608 0x6c3, "Fcvtzril", -2,
613 0x6e3, "Fcpyrsre", 3,
621 0x780, "addono", 3, /* xl */
622 0x781, "addino", 3, /* xl */
623 0x782, "subono", 3, /* xl */
624 0x783, "subino", 3, /* xl */
625 0x784, "selno", 3, /* xl */
630 0x790, "addog", 3, /* xl */
631 0x791, "addig", 3, /* xl */
632 0x792, "subog", 3, /* xl */
633 0x793, "subig", 3, /* xl */
634 0x794, "selg", 3, /* xl */
639 #define REG_MAX 0x79f
640 0x7a0, "addoe", 3, /* xl */
641 0x7a1, "addie", 3, /* xl */
642 0x7a2, "suboe", 3, /* xl */
643 0x7a3, "subie", 3, /* xl */
644 0x7a4, "sele", 3, /* xl */
645 0x7b0, "addoge", 3, /* xl */
646 0x7b1, "addige", 3, /* xl */
647 0x7b2, "suboge", 3, /* xl */
648 0x7b3, "subige", 3, /* xl */
649 0x7b4, "selge", 3, /* xl */
650 0x7c0, "addol", 3, /* xl */
651 0x7c1, "addil", 3, /* xl */
652 0x7c2, "subol", 3, /* xl */
653 0x7c3, "subil", 3, /* xl */
654 0x7c4, "sell", 3, /* xl */
655 0x7d0, "addone", 3, /* xl */
656 0x7d1, "addine", 3, /* xl */
657 0x7d2, "subone", 3, /* xl */
658 0x7d3, "subine", 3, /* xl */
659 0x7d4, "selne", 3, /* xl */
660 0x7e0, "addole", 3, /* xl */
661 0x7e1, "addile", 3, /* xl */
662 0x7e2, "subole", 3, /* xl */
663 0x7e3, "subile", 3, /* xl */
664 0x7e4, "selle", 3, /* xl */
665 0x7f0, "addoo", 3, /* xl */
666 0x7f1, "addio", 3, /* xl */
667 0x7f2, "suboo", 3, /* xl */
668 0x7f3, "subio", 3, /* xl */
669 0x7f4, "selo", 3, /* xl */
670 #undef REG_MAX /* xl */
671 #define REG_MAX 0x7f4 /* xl */
674 static struct tabent reg_tab_buf
[REG_MAX
- REG_MIN
+ 1];
676 if ( reg_tab
== NULL
){
677 reg_tab
= reg_tab_buf
;
678 for ( i
= 0; reg_init
[i
].opcode
!= 0; i
++ ){
679 j
= reg_init
[i
].opcode
- REG_MIN
;
680 reg_tab
[j
].name
= reg_init
[i
].name
;
681 reg_tab
[j
].numops
= reg_init
[i
].numops
;
685 opcode
= ((word1
>> 20) & 0xff0) | ((word1
>> 7) & 0xf);
686 i
= opcode
- REG_MIN
;
688 if ( (opcode
<REG_MIN
) || (opcode
>REG_MAX
) || (reg_tab
[i
].name
==NULL
) ){
693 mnemp
= reg_tab
[i
].name
;
694 if ( *mnemp
== 'F' ){
701 (*info
->fprintf_func
)( stream
, mnemp
);
703 s1
= (word1
>> 5) & 1;
704 s2
= (word1
>> 6) & 1;
705 m1
= (word1
>> 11) & 1;
706 m2
= (word1
>> 12) & 1;
707 m3
= (word1
>> 13) & 1;
709 src2
= (word1
>> 14) & 0x1f;
710 dst
= (word1
>> 19) & 0x1f;
712 if ( reg_tab
[i
].numops
!= 0 ){
713 (*info
->fprintf_func
)( stream
, "\t" );
715 switch ( reg_tab
[i
].numops
){
717 regop( m1
, s1
, src
, fp
);
720 dstop( m3
, dst
, fp
);
723 regop( m1
, s1
, src
, fp
);
724 (*info
->fprintf_func
)( stream
, "," );
725 regop( m2
, s2
, src2
, fp
);
728 regop( m1
, s1
, src
, fp
);
729 (*info
->fprintf_func
)( stream
, "," );
730 dstop( m3
, dst
, fp
);
733 regop( m1
, s1
, src
, fp
);
734 (*info
->fprintf_func
)( stream
, "," );
735 regop( m2
, s2
, src2
, fp
);
736 (*info
->fprintf_func
)( stream
, "," );
737 dstop( m3
, dst
, fp
);
745 * Print out effective address for memb instructions.
748 ea( memaddr
, mode
, reg2
, reg3
, word1
, word2
)
749 unsigned long memaddr
;
756 static const int scale_tab
[] = { 1, 2, 4, 8, 16 };
758 scale
= (word1
>> 7) & 0x07;
759 if ( (scale
> 4) || ((word1
>> 5) & 0x03 != 0) ){
763 scale
= scale_tab
[scale
];
767 (*info
->fprintf_func
)( stream
, "(%s)", reg2
);
769 case 5: /* displ+8(ip) */
770 print_addr( word2
+8+memaddr
);
772 case 7: /* (reg)[index*scale] */
774 (*info
->fprintf_func
)( stream
, "(%s)[%s]", reg2
, reg3
);
776 (*info
->fprintf_func
)( stream
, "(%s)[%s*%d]",reg2
,reg3
,scale
);
779 case 12: /* displacement */
782 case 13: /* displ(reg) */
784 (*info
->fprintf_func
)( stream
, "(%s)", reg2
);
786 case 14: /* displ[index*scale] */
789 (*info
->fprintf_func
)( stream
, "[%s]", reg3
);
791 (*info
->fprintf_func
)( stream
, "[%s*%d]", reg3
, scale
);
794 case 15: /* displ(reg)[index*scale] */
797 (*info
->fprintf_func
)( stream
, "(%s)[%s]", reg2
, reg3
);
799 (*info
->fprintf_func
)( stream
, "(%s)[%s*%d]",reg2
,reg3
,scale
);
809 /************************************************/
810 /* Register Instruction Operand */
811 /************************************************/
813 regop( mode
, spec
, reg
, fp
)
814 int mode
, spec
, reg
, fp
;
816 if ( fp
){ /* FLOATING POINT INSTRUCTION */
817 if ( mode
== 1 ){ /* FP operand */
819 case 0: (*info
->fprintf_func
)( stream
, "fp0" );
821 case 1: (*info
->fprintf_func
)( stream
, "fp1" );
823 case 2: (*info
->fprintf_func
)( stream
, "fp2" );
825 case 3: (*info
->fprintf_func
)( stream
, "fp3" );
827 case 16: (*info
->fprintf_func
)( stream
, "0f0.0" );
829 case 22: (*info
->fprintf_func
)( stream
, "0f1.0" );
831 default: (*info
->fprintf_func
)( stream
, "?" );
834 } else { /* Non-FP register */
835 (*info
->fprintf_func
)( stream
, reg_names
[reg
] );
837 } else { /* NOT FLOATING POINT */
838 if ( mode
== 1 ){ /* Literal */
839 (*info
->fprintf_func
)( stream
, "%d", reg
);
840 } else { /* Register */
842 (*info
->fprintf_func
)( stream
, reg_names
[reg
] );
844 (*info
->fprintf_func
)( stream
, "sf%d", reg
);
850 /************************************************/
851 /* Register Instruction Destination Operand */
852 /************************************************/
854 dstop( mode
, reg
, fp
)
857 /* 'dst' operand can't be a literal. On non-FP instructions, register
858 * mode is assumed and "m3" acts as if were "s3"; on FP-instructions,
859 * sf registers are not allowed so m3 acts normally.
862 regop( mode
, 0, reg
, fp
);
864 regop( 0, mode
, reg
, fp
);
873 (*info
->fprintf_func
)( stream
, ".word\t0x%08x", (unsigned) word1
);
880 (*info
->print_address_func
) ((bfd_vma
) a
, info
);
884 put_abs( word1
, word2
)
885 unsigned long word1
, word2
;
892 switch ( (word1
>> 28) & 0xf ){
898 /* MEM format instruction */
899 len
= mem( 0, word1
, word2
, 1 );
907 (*info
->fprintf_func
)( stream
, "%08x %08x\t", word1
, word2
);
909 (*info
->fprintf_func
)( stream
, "%08x \t", word1
);
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