1 /* Generic opcode table support for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
4 THIS FILE IS USED TO GENERATE i960c-opc.c.
6 Copyright (C) 1998 Free Software Foundation, Inc.
8 This file is part of the GNU Binutils and GDB, the GNU debugger.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software Foundation, Inc.,
22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
27 #include "libiberty.h"
30 #include "i960c-opc.h"
33 /* Used by the ifield rtx function. */
34 #define FLD(f) (fields->f)
36 /* The hash functions are recorded here to help keep assembler code out of
37 the disassembler and vice versa. */
39 static int asm_hash_insn_p
PARAMS ((const CGEN_INSN
*));
40 static unsigned int asm_hash_insn
PARAMS ((const char *));
41 static int dis_hash_insn_p
PARAMS ((const CGEN_INSN
*));
42 static unsigned int dis_hash_insn
PARAMS ((const char *, CGEN_INSN_INT
));
44 /* Look up instruction INSN_VALUE and extract its fields.
45 INSN, if non-null, is the insn table entry.
46 Otherwise INSN_VALUE is examined to compute it.
47 LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
48 0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'.
49 If INSN != NULL, LENGTH must be valid.
50 ALIAS_P is non-zero if alias insns are to be included in the search.
52 The result is a pointer to the insn table entry, or NULL if the instruction
56 i960_cgen_lookup_insn (od
, insn
, insn_value
, length
, fields
, alias_p
)
58 const CGEN_INSN
*insn
;
59 CGEN_INSN_BYTES insn_value
;
64 unsigned char buf
[CGEN_MAX_INSN_SIZE
];
66 CGEN_INSN_INT base_insn
;
68 CGEN_EXTRACT_INFO
*info
= NULL
;
70 CGEN_EXTRACT_INFO ex_info
;
71 CGEN_EXTRACT_INFO
*info
= &ex_info
;
75 cgen_put_insn_value (od
, buf
, length
, insn_value
);
77 base_insn
= insn_value
; /*???*/
79 ex_info
.dis_info
= NULL
;
80 ex_info
.insn_bytes
= insn_value
;
82 base_insn
= cgen_get_insn_value (od
, buf
, length
);
88 const CGEN_INSN_LIST
*insn_list
;
90 /* The instructions are stored in hash lists.
91 Pick the first one and keep trying until we find the right one. */
93 insn_list
= CGEN_DIS_LOOKUP_INSN (od
, bufp
, base_insn
);
94 while (insn_list
!= NULL
)
96 insn
= insn_list
->insn
;
99 || ! CGEN_INSN_ATTR (insn
, CGEN_INSN_ALIAS
))
101 /* Basic bit mask must be correct. */
102 /* ??? May wish to allow target to defer this check until the
104 if ((base_insn
& CGEN_INSN_BASE_MASK (insn
))
105 == CGEN_INSN_BASE_VALUE (insn
))
107 /* ??? 0 is passed for `pc' */
108 int elength
= (*CGEN_EXTRACT_FN (insn
)) (od
, insn
, info
,
114 if (length
!= 0 && length
!= elength
)
121 insn_list
= CGEN_DIS_NEXT_INSN (insn_list
);
126 /* Sanity check: can't pass an alias insn if ! alias_p. */
128 && CGEN_INSN_ATTR (insn
, CGEN_INSN_ALIAS
))
130 /* Sanity check: length must be correct. */
131 if (length
!= CGEN_INSN_BITSIZE (insn
))
134 /* ??? 0 is passed for `pc' */
135 length
= (*CGEN_EXTRACT_FN (insn
)) (od
, insn
, info
, base_insn
, fields
,
137 /* Sanity check: must succeed.
138 Could relax this later if it ever proves useful. */
147 /* Fill in the operand instances used by INSN whose operands are FIELDS.
148 INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
152 i960_cgen_get_insn_operands (od
, insn
, fields
, indices
)
154 const CGEN_INSN
* insn
;
155 const CGEN_FIELDS
* fields
;
158 const CGEN_OPERAND_INSTANCE
*opinst
;
161 for (i
= 0, opinst
= CGEN_INSN_OPERANDS (insn
);
163 && CGEN_OPERAND_INSTANCE_TYPE (opinst
) != CGEN_OPERAND_INSTANCE_END
;
166 const CGEN_OPERAND
*op
= CGEN_OPERAND_INSTANCE_OPERAND (opinst
);
168 indices
[i
] = CGEN_OPERAND_INSTANCE_INDEX (opinst
);
170 indices
[i
] = i960_cgen_get_int_operand (CGEN_OPERAND_INDEX (op
),
175 /* Cover function to i960_cgen_get_insn_operands when either INSN or FIELDS
177 The INSN, INSN_VALUE, and LENGTH arguments are passed to
178 i960_cgen_lookup_insn unchanged.
180 The result is the insn table entry or NULL if the instruction wasn't
184 i960_cgen_lookup_get_insn_operands (od
, insn
, insn_value
, length
, indices
)
186 const CGEN_INSN
*insn
;
187 CGEN_INSN_BYTES insn_value
;
193 /* Pass non-zero for ALIAS_P only if INSN != NULL.
194 If INSN == NULL, we want a real insn. */
195 insn
= i960_cgen_lookup_insn (od
, insn
, insn_value
, length
, &fields
,
200 i960_cgen_get_insn_operands (od
, insn
, &fields
, indices
);
205 static const CGEN_ATTR_ENTRY MACH_attr
[] =
207 { "base", MACH_BASE
},
208 { "i960_ka_sa", MACH_I960_KA_SA
},
209 { "i960_ca", MACH_I960_CA
},
214 const CGEN_ATTR_TABLE i960_cgen_hardware_attr_table
[] =
216 { "CACHE-ADDR", NULL
},
222 const CGEN_ATTR_TABLE i960_cgen_operand_attr_table
[] =
224 { "ABS-ADDR", NULL
},
225 { "NEGATIVE", NULL
},
226 { "PCREL-ADDR", NULL
},
229 { "SEM-ONLY", NULL
},
230 { "SIGN-OPT", NULL
},
231 { "UNSIGNED", NULL
},
235 const CGEN_ATTR_TABLE i960_cgen_insn_attr_table
[] =
238 { "COND-CTI", NULL
},
239 { "DELAY-SLOT", NULL
},
242 { "RELAXABLE", NULL
},
243 { "SKIP-CTI", NULL
},
244 { "UNCOND-CTI", NULL
},
249 CGEN_KEYWORD_ENTRY i960_cgen_opval_h_gr_entries
[] =
287 CGEN_KEYWORD i960_cgen_opval_h_gr
=
289 & i960_cgen_opval_h_gr_entries
[0],
293 CGEN_KEYWORD_ENTRY i960_cgen_opval_h_cc_entries
[] =
298 CGEN_KEYWORD i960_cgen_opval_h_cc
=
300 & i960_cgen_opval_h_cc_entries
[0],
305 /* The hardware table. */
307 #define HW_ENT(n) i960_cgen_hw_entries[n]
308 static const CGEN_HW_ENTRY i960_cgen_hw_entries
[] =
310 { HW_H_PC
, & HW_ENT (HW_H_PC
+ 1), "h-pc", CGEN_ASM_KEYWORD
, (PTR
) 0, { 0, 0|(1<<CGEN_HW_PROFILE
)|(1<<CGEN_HW_PC
), { 0 } } },
311 { HW_H_MEMORY
, & HW_ENT (HW_H_MEMORY
+ 1), "h-memory", CGEN_ASM_KEYWORD
, (PTR
) 0, { 0, 0, { 0 } } },
312 { HW_H_SINT
, & HW_ENT (HW_H_SINT
+ 1), "h-sint", CGEN_ASM_KEYWORD
, (PTR
) 0, { 0, 0, { 0 } } },
313 { HW_H_UINT
, & HW_ENT (HW_H_UINT
+ 1), "h-uint", CGEN_ASM_KEYWORD
, (PTR
) 0, { 0, 0, { 0 } } },
314 { HW_H_ADDR
, & HW_ENT (HW_H_ADDR
+ 1), "h-addr", CGEN_ASM_KEYWORD
, (PTR
) 0, { 0, 0, { 0 } } },
315 { HW_H_IADDR
, & HW_ENT (HW_H_IADDR
+ 1), "h-iaddr", CGEN_ASM_KEYWORD
, (PTR
) 0, { 0, 0, { 0 } } },
316 { HW_H_GR
, & HW_ENT (HW_H_GR
+ 1), "h-gr", CGEN_ASM_KEYWORD
, (PTR
) & i960_cgen_opval_h_gr
, { 0, 0|(1<<CGEN_HW_CACHE_ADDR
)|(1<<CGEN_HW_PROFILE
), { 0 } } },
317 { HW_H_CC
, & HW_ENT (HW_H_CC
+ 1), "h-cc", CGEN_ASM_KEYWORD
, (PTR
) & i960_cgen_opval_h_cc
, { 0, 0|(1<<CGEN_HW_CACHE_ADDR
)|(1<<CGEN_HW_PROFILE
), { 0 } } },
321 /* The instruction field table. */
323 static const CGEN_IFLD i960_cgen_ifld_table
[] =
325 { I960_F_NIL
, "f-nil", 0, 0, 0, 0, { 0, 0, { 0 } } },
326 { I960_F_OPCODE
, "f-opcode", 0, 32, 0, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
327 { I960_F_SRCDST
, "f-srcdst", 0, 32, 8, 5, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
328 { I960_F_SRC2
, "f-src2", 0, 32, 13, 5, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
329 { I960_F_M3
, "f-m3", 0, 32, 18, 1, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
330 { I960_F_M2
, "f-m2", 0, 32, 19, 1, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
331 { I960_F_M1
, "f-m1", 0, 32, 20, 1, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
332 { I960_F_OPCODE2
, "f-opcode2", 0, 32, 21, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
333 { I960_F_ZERO
, "f-zero", 0, 32, 25, 2, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
334 { I960_F_SRC1
, "f-src1", 0, 32, 27, 5, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
335 { I960_F_ABASE
, "f-abase", 0, 32, 13, 5, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
336 { I960_F_MODEA
, "f-modea", 0, 32, 18, 1, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
337 { I960_F_ZEROA
, "f-zeroa", 0, 32, 19, 1, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
338 { I960_F_OFFSET
, "f-offset", 0, 32, 20, 12, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
339 { I960_F_MODEB
, "f-modeb", 0, 32, 18, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
340 { I960_F_SCALE
, "f-scale", 0, 32, 22, 3, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
341 { I960_F_ZEROB
, "f-zerob", 0, 32, 25, 2, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
342 { I960_F_INDEX
, "f-index", 0, 32, 27, 5, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
343 { I960_F_OPTDISP
, "f-optdisp", 32, 32, 0, 32, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
344 { I960_F_BR_SRC1
, "f-br-src1", 0, 32, 8, 5, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
345 { I960_F_BR_SRC2
, "f-br-src2", 0, 32, 13, 5, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
346 { I960_F_BR_M1
, "f-br-m1", 0, 32, 18, 1, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
347 { I960_F_BR_DISP
, "f-br-disp", 0, 32, 19, 11, { 0, 0|(1<<CGEN_IFLD_RELOC
)|(1<<CGEN_IFLD_PCREL_ADDR
), { 0 } } },
348 { I960_F_BR_ZERO
, "f-br-zero", 0, 32, 30, 2, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
349 { I960_F_CTRL_DISP
, "f-ctrl-disp", 0, 32, 8, 22, { 0, 0|(1<<CGEN_IFLD_RELOC
)|(1<<CGEN_IFLD_PCREL_ADDR
), { 0 } } },
350 { I960_F_CTRL_ZERO
, "f-ctrl-zero", 0, 32, 30, 2, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
354 /* The operand table. */
356 #define OPERAND(op) CONCAT2 (I960_OPERAND_,op)
357 #define OP_ENT(op) i960_cgen_operand_table[OPERAND (op)]
359 const CGEN_OPERAND i960_cgen_operand_table
[MAX_OPERANDS
] =
361 /* pc: program counter */
362 { "pc", & HW_ENT (HW_H_PC
), 0, 0,
363 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY
), { 0 } } },
364 /* src1: source register 1 */
365 { "src1", & HW_ENT (HW_H_GR
), 27, 5,
366 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
367 /* src2: source register 2 */
368 { "src2", & HW_ENT (HW_H_GR
), 13, 5,
369 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
370 /* dst: source/dest register */
371 { "dst", & HW_ENT (HW_H_GR
), 8, 5,
372 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
373 /* lit1: literal 1 */
374 { "lit1", & HW_ENT (HW_H_UINT
), 27, 5,
375 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
376 /* lit2: literal 2 */
377 { "lit2", & HW_ENT (HW_H_UINT
), 13, 5,
378 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
379 /* st_src: store src */
380 { "st_src", & HW_ENT (HW_H_GR
), 8, 5,
381 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
383 { "abase", & HW_ENT (HW_H_GR
), 13, 5,
384 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
386 { "offset", & HW_ENT (HW_H_UINT
), 20, 12,
387 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
389 { "scale", & HW_ENT (HW_H_UINT
), 22, 3,
390 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
392 { "index", & HW_ENT (HW_H_GR
), 27, 5,
393 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
394 /* optdisp: optional displacement */
395 { "optdisp", & HW_ENT (HW_H_UINT
), 0, 32,
396 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
397 /* br_src1: branch src1 */
398 { "br_src1", & HW_ENT (HW_H_GR
), 8, 5,
399 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
400 /* br_src2: branch src2 */
401 { "br_src2", & HW_ENT (HW_H_GR
), 13, 5,
402 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
403 /* br_disp: branch displacement */
404 { "br_disp", & HW_ENT (HW_H_IADDR
), 19, 11,
405 { 0, 0|(1<<CGEN_OPERAND_RELOC
)|(1<<CGEN_OPERAND_PCREL_ADDR
), { 0 } } },
406 /* br_lit1: branch literal 1 */
407 { "br_lit1", & HW_ENT (HW_H_UINT
), 8, 5,
408 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
409 /* ctrl_disp: ctrl branch disp */
410 { "ctrl_disp", & HW_ENT (HW_H_IADDR
), 8, 22,
411 { 0, 0|(1<<CGEN_OPERAND_RELOC
)|(1<<CGEN_OPERAND_PCREL_ADDR
), { 0 } } },
414 /* Operand references. */
416 #define INPUT CGEN_OPERAND_INSTANCE_INPUT
417 #define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
418 #define COND_REF CGEN_OPERAND_INSTANCE_COND_REF
420 static const CGEN_OPERAND_INSTANCE fmt_mulo_ops
[] = {
421 { INPUT
, "src1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0, 0 },
422 { INPUT
, "src2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0, 0 },
423 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
427 static const CGEN_OPERAND_INSTANCE fmt_mulo1_ops
[] = {
428 { INPUT
, "lit1", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (LIT1
), 0, 0 },
429 { INPUT
, "src2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0, 0 },
430 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
434 static const CGEN_OPERAND_INSTANCE fmt_mulo2_ops
[] = {
435 { INPUT
, "src1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0, 0 },
436 { INPUT
, "lit2", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (LIT2
), 0, 0 },
437 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
441 static const CGEN_OPERAND_INSTANCE fmt_mulo3_ops
[] = {
442 { INPUT
, "lit1", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (LIT1
), 0, 0 },
443 { INPUT
, "lit2", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (LIT2
), 0, 0 },
444 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
448 static const CGEN_OPERAND_INSTANCE fmt_remo_ops
[] = {
449 { INPUT
, "src2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0, 0 },
450 { INPUT
, "src1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0, 0 },
451 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
455 static const CGEN_OPERAND_INSTANCE fmt_remo1_ops
[] = {
456 { INPUT
, "src2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0, 0 },
457 { INPUT
, "lit1", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (LIT1
), 0, 0 },
458 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
462 static const CGEN_OPERAND_INSTANCE fmt_remo2_ops
[] = {
463 { INPUT
, "lit2", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (LIT2
), 0, 0 },
464 { INPUT
, "src1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0, 0 },
465 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
469 static const CGEN_OPERAND_INSTANCE fmt_remo3_ops
[] = {
470 { INPUT
, "lit2", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (LIT2
), 0, 0 },
471 { INPUT
, "lit1", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (LIT1
), 0, 0 },
472 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
476 static const CGEN_OPERAND_INSTANCE fmt_not_ops
[] = {
477 { INPUT
, "src1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0, 0 },
478 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
482 static const CGEN_OPERAND_INSTANCE fmt_not1_ops
[] = {
483 { INPUT
, "lit1", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (LIT1
), 0, 0 },
484 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
488 static const CGEN_OPERAND_INSTANCE fmt_not2_ops
[] = {
489 { INPUT
, "src1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0, 0 },
490 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
494 static const CGEN_OPERAND_INSTANCE fmt_not3_ops
[] = {
495 { INPUT
, "lit1", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (LIT1
), 0, 0 },
496 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
500 static const CGEN_OPERAND_INSTANCE fmt_emul_ops
[] = {
501 { INPUT
, "src1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0, 0 },
502 { INPUT
, "src2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0, 0 },
503 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
504 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
505 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
509 static const CGEN_OPERAND_INSTANCE fmt_emul1_ops
[] = {
510 { INPUT
, "lit1", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (LIT1
), 0, 0 },
511 { INPUT
, "src2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0, 0 },
512 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
513 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
514 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
518 static const CGEN_OPERAND_INSTANCE fmt_emul2_ops
[] = {
519 { INPUT
, "src1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0, 0 },
520 { INPUT
, "lit2", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (LIT2
), 0, 0 },
521 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
522 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
523 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
527 static const CGEN_OPERAND_INSTANCE fmt_emul3_ops
[] = {
528 { INPUT
, "lit1", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (LIT1
), 0, 0 },
529 { INPUT
, "lit2", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (LIT2
), 0, 0 },
530 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
531 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
532 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
536 static const CGEN_OPERAND_INSTANCE fmt_movl_ops
[] = {
537 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
538 { INPUT
, "f_src1", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
539 { INPUT
, "src1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0, 0 },
540 { INPUT
, "h_gr_add__VM_index_of_src1_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
541 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
542 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
546 static const CGEN_OPERAND_INSTANCE fmt_movl1_ops
[] = {
547 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
548 { INPUT
, "lit1", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (LIT1
), 0, 0 },
549 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
550 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
554 static const CGEN_OPERAND_INSTANCE fmt_movt_ops
[] = {
555 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
556 { INPUT
, "f_src1", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
557 { INPUT
, "src1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0, 0 },
558 { INPUT
, "h_gr_add__VM_index_of_src1_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
559 { INPUT
, "h_gr_add__VM_index_of_src1_const__WI_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
560 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
561 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
562 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
566 static const CGEN_OPERAND_INSTANCE fmt_movt1_ops
[] = {
567 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
568 { INPUT
, "lit1", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (LIT1
), 0, 0 },
569 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
570 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
571 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
575 static const CGEN_OPERAND_INSTANCE fmt_movq_ops
[] = {
576 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
577 { INPUT
, "f_src1", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
578 { INPUT
, "src1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0, 0 },
579 { INPUT
, "h_gr_add__VM_index_of_src1_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
580 { INPUT
, "h_gr_add__VM_index_of_src1_const__WI_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
581 { INPUT
, "h_gr_add__VM_index_of_src1_const__WI_3", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
582 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
583 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
584 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
585 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
589 static const CGEN_OPERAND_INSTANCE fmt_movq1_ops
[] = {
590 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
591 { INPUT
, "lit1", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (LIT1
), 0, 0 },
592 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
593 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
594 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
595 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
599 static const CGEN_OPERAND_INSTANCE fmt_modpc_ops
[] = {
600 { INPUT
, "src2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0, 0 },
601 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
605 static const CGEN_OPERAND_INSTANCE fmt_lda_offset_ops
[] = {
606 { INPUT
, "offset", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OFFSET
), 0, 0 },
607 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
611 static const CGEN_OPERAND_INSTANCE fmt_lda_indirect_offset_ops
[] = {
612 { INPUT
, "offset", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OFFSET
), 0, 0 },
613 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
614 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
618 static const CGEN_OPERAND_INSTANCE fmt_lda_indirect_ops
[] = {
619 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
620 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
624 static const CGEN_OPERAND_INSTANCE fmt_lda_indirect_index_ops
[] = {
625 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
626 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
627 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
628 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
632 static const CGEN_OPERAND_INSTANCE fmt_lda_disp_ops
[] = {
633 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
634 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
638 static const CGEN_OPERAND_INSTANCE fmt_lda_indirect_disp_ops
[] = {
639 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
640 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
641 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
645 static const CGEN_OPERAND_INSTANCE fmt_lda_index_disp_ops
[] = {
646 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
647 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
648 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
649 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
653 static const CGEN_OPERAND_INSTANCE fmt_lda_indirect_index_disp_ops
[] = {
654 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
655 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
656 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
657 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
658 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
662 static const CGEN_OPERAND_INSTANCE fmt_ld_offset_ops
[] = {
663 { INPUT
, "offset", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OFFSET
), 0, 0 },
664 { INPUT
, "h_memory_offset", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
665 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
669 static const CGEN_OPERAND_INSTANCE fmt_ld_indirect_offset_ops
[] = {
670 { INPUT
, "offset", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OFFSET
), 0, 0 },
671 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
672 { INPUT
, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
673 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
677 static const CGEN_OPERAND_INSTANCE fmt_ld_indirect_ops
[] = {
678 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_USI
, & OP_ENT (ABASE
), 0, 0 },
679 { INPUT
, "h_memory_abase", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
680 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
684 static const CGEN_OPERAND_INSTANCE fmt_ld_indirect_index_ops
[] = {
685 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
686 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
687 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
688 { INPUT
, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
689 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
693 static const CGEN_OPERAND_INSTANCE fmt_ld_disp_ops
[] = {
694 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
695 { INPUT
, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
696 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
700 static const CGEN_OPERAND_INSTANCE fmt_ld_indirect_disp_ops
[] = {
701 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
702 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
703 { INPUT
, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
704 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
708 static const CGEN_OPERAND_INSTANCE fmt_ld_index_disp_ops
[] = {
709 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
710 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
711 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
712 { INPUT
, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
713 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
717 static const CGEN_OPERAND_INSTANCE fmt_ld_indirect_index_disp_ops
[] = {
718 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
719 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
720 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
721 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
722 { INPUT
, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
723 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
727 static const CGEN_OPERAND_INSTANCE fmt_ldob_offset_ops
[] = {
728 { INPUT
, "offset", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OFFSET
), 0, 0 },
729 { INPUT
, "h_memory_offset", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_UQI
, 0, 0, 0 },
730 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
734 static const CGEN_OPERAND_INSTANCE fmt_ldob_indirect_offset_ops
[] = {
735 { INPUT
, "offset", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OFFSET
), 0, 0 },
736 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
737 { INPUT
, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_UQI
, 0, 0, 0 },
738 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
742 static const CGEN_OPERAND_INSTANCE fmt_ldob_indirect_ops
[] = {
743 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_USI
, & OP_ENT (ABASE
), 0, 0 },
744 { INPUT
, "h_memory_abase", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_UQI
, 0, 0, 0 },
745 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
749 static const CGEN_OPERAND_INSTANCE fmt_ldob_indirect_index_ops
[] = {
750 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
751 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
752 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
753 { INPUT
, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_UQI
, 0, 0, 0 },
754 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
758 static const CGEN_OPERAND_INSTANCE fmt_ldob_disp_ops
[] = {
759 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
760 { INPUT
, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_UQI
, 0, 0, 0 },
761 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
765 static const CGEN_OPERAND_INSTANCE fmt_ldob_indirect_disp_ops
[] = {
766 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
767 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
768 { INPUT
, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_UQI
, 0, 0, 0 },
769 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
773 static const CGEN_OPERAND_INSTANCE fmt_ldob_index_disp_ops
[] = {
774 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
775 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
776 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
777 { INPUT
, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_UQI
, 0, 0, 0 },
778 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
782 static const CGEN_OPERAND_INSTANCE fmt_ldob_indirect_index_disp_ops
[] = {
783 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
784 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
785 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
786 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
787 { INPUT
, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_UQI
, 0, 0, 0 },
788 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
792 static const CGEN_OPERAND_INSTANCE fmt_ldos_offset_ops
[] = {
793 { INPUT
, "offset", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OFFSET
), 0, 0 },
794 { INPUT
, "h_memory_offset", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_UHI
, 0, 0, 0 },
795 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
799 static const CGEN_OPERAND_INSTANCE fmt_ldos_indirect_offset_ops
[] = {
800 { INPUT
, "offset", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OFFSET
), 0, 0 },
801 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
802 { INPUT
, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_UHI
, 0, 0, 0 },
803 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
807 static const CGEN_OPERAND_INSTANCE fmt_ldos_indirect_ops
[] = {
808 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_USI
, & OP_ENT (ABASE
), 0, 0 },
809 { INPUT
, "h_memory_abase", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_UHI
, 0, 0, 0 },
810 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
814 static const CGEN_OPERAND_INSTANCE fmt_ldos_indirect_index_ops
[] = {
815 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
816 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
817 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
818 { INPUT
, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_UHI
, 0, 0, 0 },
819 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
823 static const CGEN_OPERAND_INSTANCE fmt_ldos_disp_ops
[] = {
824 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
825 { INPUT
, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_UHI
, 0, 0, 0 },
826 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
830 static const CGEN_OPERAND_INSTANCE fmt_ldos_indirect_disp_ops
[] = {
831 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
832 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
833 { INPUT
, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_UHI
, 0, 0, 0 },
834 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
838 static const CGEN_OPERAND_INSTANCE fmt_ldos_index_disp_ops
[] = {
839 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
840 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
841 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
842 { INPUT
, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_UHI
, 0, 0, 0 },
843 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
847 static const CGEN_OPERAND_INSTANCE fmt_ldos_indirect_index_disp_ops
[] = {
848 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
849 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
850 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
851 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
852 { INPUT
, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_UHI
, 0, 0, 0 },
853 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
857 static const CGEN_OPERAND_INSTANCE fmt_ldib_offset_ops
[] = {
858 { INPUT
, "offset", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OFFSET
), 0, 0 },
859 { INPUT
, "h_memory_offset", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0, 0 },
860 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
864 static const CGEN_OPERAND_INSTANCE fmt_ldib_indirect_offset_ops
[] = {
865 { INPUT
, "offset", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OFFSET
), 0, 0 },
866 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
867 { INPUT
, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0, 0 },
868 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
872 static const CGEN_OPERAND_INSTANCE fmt_ldib_indirect_ops
[] = {
873 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_USI
, & OP_ENT (ABASE
), 0, 0 },
874 { INPUT
, "h_memory_abase", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0, 0 },
875 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
879 static const CGEN_OPERAND_INSTANCE fmt_ldib_indirect_index_ops
[] = {
880 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
881 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
882 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
883 { INPUT
, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0, 0 },
884 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
888 static const CGEN_OPERAND_INSTANCE fmt_ldib_disp_ops
[] = {
889 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
890 { INPUT
, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0, 0 },
891 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
895 static const CGEN_OPERAND_INSTANCE fmt_ldib_indirect_disp_ops
[] = {
896 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
897 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
898 { INPUT
, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0, 0 },
899 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
903 static const CGEN_OPERAND_INSTANCE fmt_ldib_index_disp_ops
[] = {
904 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
905 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
906 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
907 { INPUT
, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0, 0 },
908 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
912 static const CGEN_OPERAND_INSTANCE fmt_ldib_indirect_index_disp_ops
[] = {
913 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
914 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
915 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
916 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
917 { INPUT
, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0, 0 },
918 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
922 static const CGEN_OPERAND_INSTANCE fmt_ldis_offset_ops
[] = {
923 { INPUT
, "offset", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OFFSET
), 0, 0 },
924 { INPUT
, "h_memory_offset", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_HI
, 0, 0, 0 },
925 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
929 static const CGEN_OPERAND_INSTANCE fmt_ldis_indirect_offset_ops
[] = {
930 { INPUT
, "offset", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OFFSET
), 0, 0 },
931 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
932 { INPUT
, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_HI
, 0, 0, 0 },
933 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
937 static const CGEN_OPERAND_INSTANCE fmt_ldis_indirect_ops
[] = {
938 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_USI
, & OP_ENT (ABASE
), 0, 0 },
939 { INPUT
, "h_memory_abase", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_HI
, 0, 0, 0 },
940 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
944 static const CGEN_OPERAND_INSTANCE fmt_ldis_indirect_index_ops
[] = {
945 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
946 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
947 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
948 { INPUT
, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_HI
, 0, 0, 0 },
949 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
953 static const CGEN_OPERAND_INSTANCE fmt_ldis_disp_ops
[] = {
954 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
955 { INPUT
, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_HI
, 0, 0, 0 },
956 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
960 static const CGEN_OPERAND_INSTANCE fmt_ldis_indirect_disp_ops
[] = {
961 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
962 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
963 { INPUT
, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_HI
, 0, 0, 0 },
964 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
968 static const CGEN_OPERAND_INSTANCE fmt_ldis_index_disp_ops
[] = {
969 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
970 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
971 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
972 { INPUT
, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_HI
, 0, 0, 0 },
973 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
977 static const CGEN_OPERAND_INSTANCE fmt_ldis_indirect_index_disp_ops
[] = {
978 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
979 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
980 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
981 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
982 { INPUT
, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_HI
, 0, 0, 0 },
983 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
987 static const CGEN_OPERAND_INSTANCE fmt_ldl_offset_ops
[] = {
988 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
989 { INPUT
, "offset", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OFFSET
), 0, 0 },
990 { INPUT
, "h_memory_temp", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
991 { INPUT
, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
992 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
993 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
997 static const CGEN_OPERAND_INSTANCE fmt_ldl_indirect_offset_ops
[] = {
998 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
999 { INPUT
, "offset", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OFFSET
), 0, 0 },
1000 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1001 { INPUT
, "h_memory_temp", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1002 { INPUT
, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1003 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
1004 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1008 static const CGEN_OPERAND_INSTANCE fmt_ldl_indirect_ops
[] = {
1009 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1010 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1011 { INPUT
, "h_memory_temp", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1012 { INPUT
, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1013 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
1014 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1018 static const CGEN_OPERAND_INSTANCE fmt_ldl_indirect_index_ops
[] = {
1019 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1020 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1021 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
1022 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
1023 { INPUT
, "h_memory_temp", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1024 { INPUT
, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1025 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
1026 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1030 static const CGEN_OPERAND_INSTANCE fmt_ldl_disp_ops
[] = {
1031 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1032 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
1033 { INPUT
, "h_memory_temp", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1034 { INPUT
, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1035 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
1036 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1040 static const CGEN_OPERAND_INSTANCE fmt_ldl_indirect_disp_ops
[] = {
1041 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1042 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
1043 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1044 { INPUT
, "h_memory_temp", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1045 { INPUT
, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1046 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
1047 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1051 static const CGEN_OPERAND_INSTANCE fmt_ldl_index_disp_ops
[] = {
1052 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1053 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
1054 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
1055 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
1056 { INPUT
, "h_memory_temp", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1057 { INPUT
, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1058 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
1059 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1063 static const CGEN_OPERAND_INSTANCE fmt_ldl_indirect_index_disp_ops
[] = {
1064 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1065 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
1066 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1067 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
1068 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
1069 { INPUT
, "h_memory_temp", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1070 { INPUT
, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1071 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
1072 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1076 static const CGEN_OPERAND_INSTANCE fmt_ldt_offset_ops
[] = {
1077 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1078 { INPUT
, "offset", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OFFSET
), 0, 0 },
1079 { INPUT
, "h_memory_temp", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1080 { INPUT
, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1081 { INPUT
, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1082 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
1083 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1084 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1088 static const CGEN_OPERAND_INSTANCE fmt_ldt_indirect_offset_ops
[] = {
1089 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1090 { INPUT
, "offset", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OFFSET
), 0, 0 },
1091 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1092 { INPUT
, "h_memory_temp", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1093 { INPUT
, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1094 { INPUT
, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1095 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
1096 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1097 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1101 static const CGEN_OPERAND_INSTANCE fmt_ldt_indirect_ops
[] = {
1102 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1103 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1104 { INPUT
, "h_memory_temp", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1105 { INPUT
, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1106 { INPUT
, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1107 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
1108 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1109 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1113 static const CGEN_OPERAND_INSTANCE fmt_ldt_indirect_index_ops
[] = {
1114 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1115 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1116 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
1117 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
1118 { INPUT
, "h_memory_temp", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1119 { INPUT
, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1120 { INPUT
, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1121 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
1122 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1123 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1127 static const CGEN_OPERAND_INSTANCE fmt_ldt_disp_ops
[] = {
1128 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1129 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
1130 { INPUT
, "h_memory_temp", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1131 { INPUT
, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1132 { INPUT
, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1133 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
1134 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1135 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1139 static const CGEN_OPERAND_INSTANCE fmt_ldt_indirect_disp_ops
[] = {
1140 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1141 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
1142 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1143 { INPUT
, "h_memory_temp", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1144 { INPUT
, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1145 { INPUT
, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1146 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
1147 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1148 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1152 static const CGEN_OPERAND_INSTANCE fmt_ldt_index_disp_ops
[] = {
1153 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1154 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
1155 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
1156 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
1157 { INPUT
, "h_memory_temp", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1158 { INPUT
, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1159 { INPUT
, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1160 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
1161 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1162 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1166 static const CGEN_OPERAND_INSTANCE fmt_ldt_indirect_index_disp_ops
[] = {
1167 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1168 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
1169 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1170 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
1171 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
1172 { INPUT
, "h_memory_temp", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1173 { INPUT
, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1174 { INPUT
, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1175 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
1176 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1177 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1181 static const CGEN_OPERAND_INSTANCE fmt_ldq_offset_ops
[] = {
1182 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1183 { INPUT
, "offset", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OFFSET
), 0, 0 },
1184 { INPUT
, "h_memory_temp", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1185 { INPUT
, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1186 { INPUT
, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1187 { INPUT
, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1188 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
1189 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1190 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1191 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1195 static const CGEN_OPERAND_INSTANCE fmt_ldq_indirect_offset_ops
[] = {
1196 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1197 { INPUT
, "offset", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OFFSET
), 0, 0 },
1198 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1199 { INPUT
, "h_memory_temp", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1200 { INPUT
, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1201 { INPUT
, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1202 { INPUT
, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1203 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
1204 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1205 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1206 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1210 static const CGEN_OPERAND_INSTANCE fmt_ldq_indirect_ops
[] = {
1211 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1212 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1213 { INPUT
, "h_memory_temp", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1214 { INPUT
, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1215 { INPUT
, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1216 { INPUT
, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1217 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
1218 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1219 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1220 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1224 static const CGEN_OPERAND_INSTANCE fmt_ldq_indirect_index_ops
[] = {
1225 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1226 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1227 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
1228 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
1229 { INPUT
, "h_memory_temp", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1230 { INPUT
, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1231 { INPUT
, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1232 { INPUT
, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1233 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
1234 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1235 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1236 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1240 static const CGEN_OPERAND_INSTANCE fmt_ldq_disp_ops
[] = {
1241 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1242 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
1243 { INPUT
, "h_memory_temp", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1244 { INPUT
, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1245 { INPUT
, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1246 { INPUT
, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1247 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
1248 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1249 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1250 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1254 static const CGEN_OPERAND_INSTANCE fmt_ldq_indirect_disp_ops
[] = {
1255 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1256 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
1257 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1258 { INPUT
, "h_memory_temp", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1259 { INPUT
, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1260 { INPUT
, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1261 { INPUT
, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1262 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
1263 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1264 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1265 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1269 static const CGEN_OPERAND_INSTANCE fmt_ldq_index_disp_ops
[] = {
1270 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1271 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
1272 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
1273 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
1274 { INPUT
, "h_memory_temp", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1275 { INPUT
, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1276 { INPUT
, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1277 { INPUT
, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1278 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
1279 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1280 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1281 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1285 static const CGEN_OPERAND_INSTANCE fmt_ldq_indirect_index_disp_ops
[] = {
1286 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1287 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
1288 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1289 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
1290 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
1291 { INPUT
, "h_memory_temp", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1292 { INPUT
, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1293 { INPUT
, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1294 { INPUT
, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1295 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
1296 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1297 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1298 { OUTPUT
, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1302 static const CGEN_OPERAND_INSTANCE fmt_st_offset_ops
[] = {
1303 { INPUT
, "offset", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OFFSET
), 0, 0 },
1304 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1305 { OUTPUT
, "h_memory_offset", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1309 static const CGEN_OPERAND_INSTANCE fmt_st_indirect_offset_ops
[] = {
1310 { INPUT
, "offset", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OFFSET
), 0, 0 },
1311 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1312 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1313 { OUTPUT
, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1317 static const CGEN_OPERAND_INSTANCE fmt_st_indirect_ops
[] = {
1318 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_USI
, & OP_ENT (ABASE
), 0, 0 },
1319 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1320 { OUTPUT
, "h_memory_abase", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1324 static const CGEN_OPERAND_INSTANCE fmt_st_indirect_index_ops
[] = {
1325 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1326 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
1327 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
1328 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1329 { OUTPUT
, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1333 static const CGEN_OPERAND_INSTANCE fmt_st_disp_ops
[] = {
1334 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
1335 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1336 { OUTPUT
, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1340 static const CGEN_OPERAND_INSTANCE fmt_st_indirect_disp_ops
[] = {
1341 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
1342 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1343 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1344 { OUTPUT
, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1348 static const CGEN_OPERAND_INSTANCE fmt_st_index_disp_ops
[] = {
1349 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
1350 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
1351 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
1352 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1353 { OUTPUT
, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1357 static const CGEN_OPERAND_INSTANCE fmt_st_indirect_index_disp_ops
[] = {
1358 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
1359 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1360 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
1361 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
1362 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1363 { OUTPUT
, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1367 static const CGEN_OPERAND_INSTANCE fmt_stob_offset_ops
[] = {
1368 { INPUT
, "offset", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OFFSET
), 0, 0 },
1369 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1370 { OUTPUT
, "h_memory_offset", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0, 0 },
1374 static const CGEN_OPERAND_INSTANCE fmt_stob_indirect_offset_ops
[] = {
1375 { INPUT
, "offset", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OFFSET
), 0, 0 },
1376 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1377 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1378 { OUTPUT
, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0, 0 },
1382 static const CGEN_OPERAND_INSTANCE fmt_stob_indirect_ops
[] = {
1383 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_USI
, & OP_ENT (ABASE
), 0, 0 },
1384 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1385 { OUTPUT
, "h_memory_abase", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0, 0 },
1389 static const CGEN_OPERAND_INSTANCE fmt_stob_indirect_index_ops
[] = {
1390 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1391 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
1392 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
1393 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1394 { OUTPUT
, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0, 0 },
1398 static const CGEN_OPERAND_INSTANCE fmt_stob_disp_ops
[] = {
1399 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
1400 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1401 { OUTPUT
, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0, 0 },
1405 static const CGEN_OPERAND_INSTANCE fmt_stob_indirect_disp_ops
[] = {
1406 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
1407 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1408 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1409 { OUTPUT
, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0, 0 },
1413 static const CGEN_OPERAND_INSTANCE fmt_stob_index_disp_ops
[] = {
1414 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
1415 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
1416 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
1417 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1418 { OUTPUT
, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0, 0 },
1422 static const CGEN_OPERAND_INSTANCE fmt_stob_indirect_index_disp_ops
[] = {
1423 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
1424 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1425 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
1426 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
1427 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1428 { OUTPUT
, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0, 0 },
1432 static const CGEN_OPERAND_INSTANCE fmt_stos_offset_ops
[] = {
1433 { INPUT
, "offset", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OFFSET
), 0, 0 },
1434 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1435 { OUTPUT
, "h_memory_offset", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_HI
, 0, 0, 0 },
1439 static const CGEN_OPERAND_INSTANCE fmt_stos_indirect_offset_ops
[] = {
1440 { INPUT
, "offset", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OFFSET
), 0, 0 },
1441 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1442 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1443 { OUTPUT
, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_HI
, 0, 0, 0 },
1447 static const CGEN_OPERAND_INSTANCE fmt_stos_indirect_ops
[] = {
1448 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_USI
, & OP_ENT (ABASE
), 0, 0 },
1449 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1450 { OUTPUT
, "h_memory_abase", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_HI
, 0, 0, 0 },
1454 static const CGEN_OPERAND_INSTANCE fmt_stos_indirect_index_ops
[] = {
1455 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1456 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
1457 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
1458 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1459 { OUTPUT
, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_HI
, 0, 0, 0 },
1463 static const CGEN_OPERAND_INSTANCE fmt_stos_disp_ops
[] = {
1464 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
1465 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1466 { OUTPUT
, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_HI
, 0, 0, 0 },
1470 static const CGEN_OPERAND_INSTANCE fmt_stos_indirect_disp_ops
[] = {
1471 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
1472 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1473 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1474 { OUTPUT
, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_HI
, 0, 0, 0 },
1478 static const CGEN_OPERAND_INSTANCE fmt_stos_index_disp_ops
[] = {
1479 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
1480 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
1481 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
1482 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1483 { OUTPUT
, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_HI
, 0, 0, 0 },
1487 static const CGEN_OPERAND_INSTANCE fmt_stos_indirect_index_disp_ops
[] = {
1488 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
1489 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1490 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
1491 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
1492 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1493 { OUTPUT
, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_HI
, 0, 0, 0 },
1497 static const CGEN_OPERAND_INSTANCE fmt_stl_offset_ops
[] = {
1498 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1499 { INPUT
, "offset", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OFFSET
), 0, 0 },
1500 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1501 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1502 { OUTPUT
, "h_memory_offset", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1503 { OUTPUT
, "h_memory_add__VM_offset_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1507 static const CGEN_OPERAND_INSTANCE fmt_stl_indirect_offset_ops
[] = {
1508 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1509 { INPUT
, "offset", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OFFSET
), 0, 0 },
1510 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1511 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1512 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1513 { OUTPUT
, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1514 { OUTPUT
, "h_memory_add__VM_add__VM_offset_abase_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1518 static const CGEN_OPERAND_INSTANCE fmt_stl_indirect_ops
[] = {
1519 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1520 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_USI
, & OP_ENT (ABASE
), 0, 0 },
1521 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1522 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1523 { OUTPUT
, "h_memory_abase", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1524 { OUTPUT
, "h_memory_add__VM_abase_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1528 static const CGEN_OPERAND_INSTANCE fmt_stl_indirect_index_ops
[] = {
1529 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1530 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1531 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
1532 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
1533 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1534 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1535 { OUTPUT
, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1536 { OUTPUT
, "h_memory_add__VM_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1540 static const CGEN_OPERAND_INSTANCE fmt_stl_disp_ops
[] = {
1541 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1542 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
1543 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1544 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1545 { OUTPUT
, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1546 { OUTPUT
, "h_memory_add__VM_optdisp_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1550 static const CGEN_OPERAND_INSTANCE fmt_stl_indirect_disp_ops
[] = {
1551 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1552 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
1553 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1554 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1555 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1556 { OUTPUT
, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1557 { OUTPUT
, "h_memory_add__VM_add__VM_optdisp_abase_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1561 static const CGEN_OPERAND_INSTANCE fmt_stl_index_disp_ops
[] = {
1562 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1563 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
1564 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
1565 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
1566 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1567 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1568 { OUTPUT
, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1569 { OUTPUT
, "h_memory_add__VM_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1573 static const CGEN_OPERAND_INSTANCE fmt_stl_indirect_index_disp_ops
[] = {
1574 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1575 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
1576 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1577 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
1578 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
1579 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1580 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1581 { OUTPUT
, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1582 { OUTPUT
, "h_memory_add__VM_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1586 static const CGEN_OPERAND_INSTANCE fmt_stt_offset_ops
[] = {
1587 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1588 { INPUT
, "offset", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OFFSET
), 0, 0 },
1589 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1590 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1591 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1592 { OUTPUT
, "h_memory_offset", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1593 { OUTPUT
, "h_memory_add__VM_offset_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1594 { OUTPUT
, "h_memory_add__VM_offset_const__WI_8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1598 static const CGEN_OPERAND_INSTANCE fmt_stt_indirect_offset_ops
[] = {
1599 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1600 { INPUT
, "offset", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OFFSET
), 0, 0 },
1601 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1602 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1603 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1604 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1605 { OUTPUT
, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1606 { OUTPUT
, "h_memory_add__VM_add__VM_offset_abase_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1607 { OUTPUT
, "h_memory_add__VM_add__VM_offset_abase_const__WI_8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1611 static const CGEN_OPERAND_INSTANCE fmt_stt_indirect_ops
[] = {
1612 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1613 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_USI
, & OP_ENT (ABASE
), 0, 0 },
1614 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1615 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1616 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1617 { OUTPUT
, "h_memory_abase", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1618 { OUTPUT
, "h_memory_add__VM_abase_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1619 { OUTPUT
, "h_memory_add__VM_abase_const__WI_8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1623 static const CGEN_OPERAND_INSTANCE fmt_stt_indirect_index_ops
[] = {
1624 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1625 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1626 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
1627 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
1628 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1629 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1630 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1631 { OUTPUT
, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1632 { OUTPUT
, "h_memory_add__VM_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1633 { OUTPUT
, "h_memory_add__VM_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1637 static const CGEN_OPERAND_INSTANCE fmt_stt_disp_ops
[] = {
1638 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1639 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
1640 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1641 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1642 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1643 { OUTPUT
, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1644 { OUTPUT
, "h_memory_add__VM_optdisp_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1645 { OUTPUT
, "h_memory_add__VM_optdisp_const__WI_8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1649 static const CGEN_OPERAND_INSTANCE fmt_stt_indirect_disp_ops
[] = {
1650 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1651 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
1652 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1653 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1654 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1655 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1656 { OUTPUT
, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1657 { OUTPUT
, "h_memory_add__VM_add__VM_optdisp_abase_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1658 { OUTPUT
, "h_memory_add__VM_add__VM_optdisp_abase_const__WI_8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1662 static const CGEN_OPERAND_INSTANCE fmt_stt_index_disp_ops
[] = {
1663 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1664 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
1665 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
1666 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
1667 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1668 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1669 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1670 { OUTPUT
, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1671 { OUTPUT
, "h_memory_add__VM_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1672 { OUTPUT
, "h_memory_add__VM_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1676 static const CGEN_OPERAND_INSTANCE fmt_stt_indirect_index_disp_ops
[] = {
1677 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1678 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
1679 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1680 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
1681 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
1682 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1683 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1684 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1685 { OUTPUT
, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1686 { OUTPUT
, "h_memory_add__VM_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1687 { OUTPUT
, "h_memory_add__VM_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1691 static const CGEN_OPERAND_INSTANCE fmt_stq_offset_ops
[] = {
1692 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1693 { INPUT
, "offset", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OFFSET
), 0, 0 },
1694 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1695 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1696 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1697 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1698 { OUTPUT
, "h_memory_offset", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1699 { OUTPUT
, "h_memory_add__VM_offset_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1700 { OUTPUT
, "h_memory_add__VM_offset_const__WI_8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1701 { OUTPUT
, "h_memory_add__VM_offset_const__WI_12", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1705 static const CGEN_OPERAND_INSTANCE fmt_stq_indirect_offset_ops
[] = {
1706 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1707 { INPUT
, "offset", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OFFSET
), 0, 0 },
1708 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1709 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1710 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1711 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1712 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1713 { OUTPUT
, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1714 { OUTPUT
, "h_memory_add__VM_add__VM_offset_abase_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1715 { OUTPUT
, "h_memory_add__VM_add__VM_offset_abase_const__WI_8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1716 { OUTPUT
, "h_memory_add__VM_add__VM_offset_abase_const__WI_12", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1720 static const CGEN_OPERAND_INSTANCE fmt_stq_indirect_ops
[] = {
1721 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1722 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_USI
, & OP_ENT (ABASE
), 0, 0 },
1723 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1724 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1725 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1726 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1727 { OUTPUT
, "h_memory_abase", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1728 { OUTPUT
, "h_memory_add__VM_abase_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1729 { OUTPUT
, "h_memory_add__VM_abase_const__WI_8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1730 { OUTPUT
, "h_memory_add__VM_abase_const__WI_12", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1734 static const CGEN_OPERAND_INSTANCE fmt_stq_indirect_index_ops
[] = {
1735 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1736 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1737 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
1738 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
1739 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1740 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1741 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1742 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1743 { OUTPUT
, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1744 { OUTPUT
, "h_memory_add__VM_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1745 { OUTPUT
, "h_memory_add__VM_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1746 { OUTPUT
, "h_memory_add__VM_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_12", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1750 static const CGEN_OPERAND_INSTANCE fmt_stq_disp_ops
[] = {
1751 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1752 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
1753 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1754 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1755 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1756 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1757 { OUTPUT
, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1758 { OUTPUT
, "h_memory_add__VM_optdisp_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1759 { OUTPUT
, "h_memory_add__VM_optdisp_const__WI_8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1760 { OUTPUT
, "h_memory_add__VM_optdisp_const__WI_12", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1764 static const CGEN_OPERAND_INSTANCE fmt_stq_indirect_disp_ops
[] = {
1765 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1766 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
1767 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1768 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1769 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1770 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1771 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1772 { OUTPUT
, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1773 { OUTPUT
, "h_memory_add__VM_add__VM_optdisp_abase_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1774 { OUTPUT
, "h_memory_add__VM_add__VM_optdisp_abase_const__WI_8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1775 { OUTPUT
, "h_memory_add__VM_add__VM_optdisp_abase_const__WI_12", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1779 static const CGEN_OPERAND_INSTANCE fmt_stq_index_disp_ops
[] = {
1780 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1781 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
1782 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
1783 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
1784 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1785 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1786 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1787 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1788 { OUTPUT
, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1789 { OUTPUT
, "h_memory_add__VM_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1790 { OUTPUT
, "h_memory_add__VM_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1791 { OUTPUT
, "h_memory_add__VM_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_12", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1795 static const CGEN_OPERAND_INSTANCE fmt_stq_indirect_index_disp_ops
[] = {
1796 { INPUT
, "f_srcdst", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1797 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
1798 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1799 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
1800 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
1801 { INPUT
, "st_src", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ST_SRC
), 0, 0 },
1802 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1803 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1804 { INPUT
, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1805 { OUTPUT
, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1806 { OUTPUT
, "h_memory_add__VM_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1807 { OUTPUT
, "h_memory_add__VM_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1808 { OUTPUT
, "h_memory_add__VM_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_12", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1812 static const CGEN_OPERAND_INSTANCE fmt_cmpobe_reg_ops
[] = {
1813 { INPUT
, "br_src1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (BR_SRC1
), 0, 0 },
1814 { INPUT
, "br_src2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (BR_SRC2
), 0, 0 },
1815 { INPUT
, "br_disp", & HW_ENT (HW_H_IADDR
), CGEN_MODE_USI
, & OP_ENT (BR_DISP
), 0, COND_REF
},
1816 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1820 static const CGEN_OPERAND_INSTANCE fmt_cmpobe_lit_ops
[] = {
1821 { INPUT
, "br_lit1", & HW_ENT (HW_H_UINT
), CGEN_MODE_SI
, & OP_ENT (BR_LIT1
), 0, 0 },
1822 { INPUT
, "br_src2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (BR_SRC2
), 0, 0 },
1823 { INPUT
, "br_disp", & HW_ENT (HW_H_IADDR
), CGEN_MODE_USI
, & OP_ENT (BR_DISP
), 0, COND_REF
},
1824 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1828 static const CGEN_OPERAND_INSTANCE fmt_cmpobl_reg_ops
[] = {
1829 { INPUT
, "br_src1", & HW_ENT (HW_H_GR
), CGEN_MODE_USI
, & OP_ENT (BR_SRC1
), 0, 0 },
1830 { INPUT
, "br_src2", & HW_ENT (HW_H_GR
), CGEN_MODE_USI
, & OP_ENT (BR_SRC2
), 0, 0 },
1831 { INPUT
, "br_disp", & HW_ENT (HW_H_IADDR
), CGEN_MODE_USI
, & OP_ENT (BR_DISP
), 0, COND_REF
},
1832 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1836 static const CGEN_OPERAND_INSTANCE fmt_cmpobl_lit_ops
[] = {
1837 { INPUT
, "br_lit1", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (BR_LIT1
), 0, 0 },
1838 { INPUT
, "br_src2", & HW_ENT (HW_H_GR
), CGEN_MODE_USI
, & OP_ENT (BR_SRC2
), 0, 0 },
1839 { INPUT
, "br_disp", & HW_ENT (HW_H_IADDR
), CGEN_MODE_USI
, & OP_ENT (BR_DISP
), 0, COND_REF
},
1840 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1844 static const CGEN_OPERAND_INSTANCE fmt_bbc_lit_ops
[] = {
1845 { INPUT
, "br_lit1", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (BR_LIT1
), 0, 0 },
1846 { INPUT
, "br_src2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (BR_SRC2
), 0, 0 },
1847 { INPUT
, "br_disp", & HW_ENT (HW_H_IADDR
), CGEN_MODE_USI
, & OP_ENT (BR_DISP
), 0, COND_REF
},
1848 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1852 static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops
[] = {
1853 { INPUT
, "src1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0, 0 },
1854 { INPUT
, "src2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0, 0 },
1855 { OUTPUT
, "h_cc_0", & HW_ENT (HW_H_CC
), CGEN_MODE_SI
, 0, 0, 0 },
1859 static const CGEN_OPERAND_INSTANCE fmt_cmpi1_ops
[] = {
1860 { INPUT
, "lit1", & HW_ENT (HW_H_UINT
), CGEN_MODE_SI
, & OP_ENT (LIT1
), 0, 0 },
1861 { INPUT
, "src2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0, 0 },
1862 { OUTPUT
, "h_cc_0", & HW_ENT (HW_H_CC
), CGEN_MODE_SI
, 0, 0, 0 },
1866 static const CGEN_OPERAND_INSTANCE fmt_cmpi2_ops
[] = {
1867 { INPUT
, "src1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0, 0 },
1868 { INPUT
, "lit2", & HW_ENT (HW_H_UINT
), CGEN_MODE_SI
, & OP_ENT (LIT2
), 0, 0 },
1869 { OUTPUT
, "h_cc_0", & HW_ENT (HW_H_CC
), CGEN_MODE_SI
, 0, 0, 0 },
1873 static const CGEN_OPERAND_INSTANCE fmt_cmpi3_ops
[] = {
1874 { INPUT
, "lit1", & HW_ENT (HW_H_UINT
), CGEN_MODE_SI
, & OP_ENT (LIT1
), 0, 0 },
1875 { INPUT
, "lit2", & HW_ENT (HW_H_UINT
), CGEN_MODE_SI
, & OP_ENT (LIT2
), 0, 0 },
1876 { OUTPUT
, "h_cc_0", & HW_ENT (HW_H_CC
), CGEN_MODE_SI
, 0, 0, 0 },
1880 static const CGEN_OPERAND_INSTANCE fmt_testno_reg_ops
[] = {
1881 { INPUT
, "h_cc_0", & HW_ENT (HW_H_CC
), CGEN_MODE_SI
, 0, 0, 0 },
1882 { OUTPUT
, "br_src1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (BR_SRC1
), 0, 0 },
1886 static const CGEN_OPERAND_INSTANCE fmt_bno_ops
[] = {
1887 { INPUT
, "h_cc_0", & HW_ENT (HW_H_CC
), CGEN_MODE_SI
, 0, 0, 0 },
1888 { INPUT
, "ctrl_disp", & HW_ENT (HW_H_IADDR
), CGEN_MODE_USI
, & OP_ENT (CTRL_DISP
), 0, COND_REF
},
1889 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1893 static const CGEN_OPERAND_INSTANCE fmt_b_ops
[] = {
1894 { INPUT
, "ctrl_disp", & HW_ENT (HW_H_IADDR
), CGEN_MODE_USI
, & OP_ENT (CTRL_DISP
), 0, 0 },
1895 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0, 0 },
1899 static const CGEN_OPERAND_INSTANCE fmt_bx_indirect_offset_ops
[] = {
1900 { INPUT
, "offset", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OFFSET
), 0, 0 },
1901 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1902 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0, 0 },
1906 static const CGEN_OPERAND_INSTANCE fmt_bx_indirect_ops
[] = {
1907 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1908 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0, 0 },
1912 static const CGEN_OPERAND_INSTANCE fmt_bx_indirect_index_ops
[] = {
1913 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1914 { INPUT
, "index", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (INDEX
), 0, 0 },
1915 { INPUT
, "scale", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (SCALE
), 0, 0 },
1916 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0, 0 },
1920 static const CGEN_OPERAND_INSTANCE fmt_bx_disp_ops
[] = {
1921 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
1922 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0, 0 },
1926 static const CGEN_OPERAND_INSTANCE fmt_bx_indirect_disp_ops
[] = {
1927 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
1928 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
1929 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0, 0 },
1933 static const CGEN_OPERAND_INSTANCE fmt_callx_disp_ops
[] = {
1934 { INPUT
, "h_gr_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 1, 0 },
1935 { INPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0, 0 },
1936 { INPUT
, "h_gr_31", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 31, 0 },
1937 { INPUT
, "h_gr_0", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1938 { INPUT
, "h_gr_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 2, 0 },
1939 { INPUT
, "h_gr_3", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 3, 0 },
1940 { INPUT
, "h_gr_4", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 4, 0 },
1941 { INPUT
, "h_gr_5", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 5, 0 },
1942 { INPUT
, "h_gr_6", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 6, 0 },
1943 { INPUT
, "h_gr_7", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 7, 0 },
1944 { INPUT
, "h_gr_8", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 8, 0 },
1945 { INPUT
, "h_gr_9", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 9, 0 },
1946 { INPUT
, "h_gr_10", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 10, 0 },
1947 { INPUT
, "h_gr_11", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 11, 0 },
1948 { INPUT
, "h_gr_12", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 12, 0 },
1949 { INPUT
, "h_gr_13", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 13, 0 },
1950 { INPUT
, "h_gr_14", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 14, 0 },
1951 { INPUT
, "h_gr_15", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 15, 0 },
1952 { INPUT
, "optdisp", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OPTDISP
), 0, 0 },
1953 { OUTPUT
, "h_gr_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 2, 0 },
1954 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_0", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1955 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1956 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1957 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_12", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1958 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_16", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1959 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_20", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1960 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_24", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1961 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_28", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1962 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_32", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1963 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_36", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1964 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_40", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1965 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_44", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1966 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_48", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1967 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_52", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1968 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_56", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1969 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_60", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1970 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0, 0 },
1971 { OUTPUT
, "h_gr_0", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1972 { OUTPUT
, "h_gr_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 1, 0 },
1973 { OUTPUT
, "h_gr_3", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 3, 0 },
1974 { OUTPUT
, "h_gr_4", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 4, 0 },
1975 { OUTPUT
, "h_gr_5", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 5, 0 },
1976 { OUTPUT
, "h_gr_6", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 6, 0 },
1977 { OUTPUT
, "h_gr_7", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 7, 0 },
1978 { OUTPUT
, "h_gr_8", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 8, 0 },
1979 { OUTPUT
, "h_gr_9", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 9, 0 },
1980 { OUTPUT
, "h_gr_10", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 10, 0 },
1981 { OUTPUT
, "h_gr_11", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 11, 0 },
1982 { OUTPUT
, "h_gr_12", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 12, 0 },
1983 { OUTPUT
, "h_gr_13", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 13, 0 },
1984 { OUTPUT
, "h_gr_14", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 14, 0 },
1985 { OUTPUT
, "h_gr_15", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 15, 0 },
1986 { OUTPUT
, "h_gr_31", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 31, 0 },
1990 static const CGEN_OPERAND_INSTANCE fmt_callx_indirect_ops
[] = {
1991 { INPUT
, "h_gr_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 1, 0 },
1992 { INPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0, 0 },
1993 { INPUT
, "h_gr_31", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 31, 0 },
1994 { INPUT
, "h_gr_0", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
1995 { INPUT
, "h_gr_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 2, 0 },
1996 { INPUT
, "h_gr_3", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 3, 0 },
1997 { INPUT
, "h_gr_4", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 4, 0 },
1998 { INPUT
, "h_gr_5", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 5, 0 },
1999 { INPUT
, "h_gr_6", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 6, 0 },
2000 { INPUT
, "h_gr_7", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 7, 0 },
2001 { INPUT
, "h_gr_8", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 8, 0 },
2002 { INPUT
, "h_gr_9", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 9, 0 },
2003 { INPUT
, "h_gr_10", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 10, 0 },
2004 { INPUT
, "h_gr_11", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 11, 0 },
2005 { INPUT
, "h_gr_12", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 12, 0 },
2006 { INPUT
, "h_gr_13", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 13, 0 },
2007 { INPUT
, "h_gr_14", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 14, 0 },
2008 { INPUT
, "h_gr_15", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 15, 0 },
2009 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
2010 { OUTPUT
, "h_gr_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 2, 0 },
2011 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_0", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2012 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2013 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2014 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_12", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2015 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_16", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2016 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_20", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2017 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_24", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2018 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_28", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2019 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_32", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2020 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_36", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2021 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_40", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2022 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_44", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2023 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_48", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2024 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_52", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2025 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_56", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2026 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_60", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2027 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0, 0 },
2028 { OUTPUT
, "h_gr_0", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
2029 { OUTPUT
, "h_gr_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 1, 0 },
2030 { OUTPUT
, "h_gr_3", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 3, 0 },
2031 { OUTPUT
, "h_gr_4", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 4, 0 },
2032 { OUTPUT
, "h_gr_5", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 5, 0 },
2033 { OUTPUT
, "h_gr_6", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 6, 0 },
2034 { OUTPUT
, "h_gr_7", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 7, 0 },
2035 { OUTPUT
, "h_gr_8", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 8, 0 },
2036 { OUTPUT
, "h_gr_9", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 9, 0 },
2037 { OUTPUT
, "h_gr_10", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 10, 0 },
2038 { OUTPUT
, "h_gr_11", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 11, 0 },
2039 { OUTPUT
, "h_gr_12", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 12, 0 },
2040 { OUTPUT
, "h_gr_13", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 13, 0 },
2041 { OUTPUT
, "h_gr_14", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 14, 0 },
2042 { OUTPUT
, "h_gr_15", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 15, 0 },
2043 { OUTPUT
, "h_gr_31", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 31, 0 },
2047 static const CGEN_OPERAND_INSTANCE fmt_callx_indirect_offset_ops
[] = {
2048 { INPUT
, "h_gr_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 1, 0 },
2049 { INPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0, 0 },
2050 { INPUT
, "h_gr_31", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 31, 0 },
2051 { INPUT
, "h_gr_0", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
2052 { INPUT
, "h_gr_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 2, 0 },
2053 { INPUT
, "h_gr_3", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 3, 0 },
2054 { INPUT
, "h_gr_4", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 4, 0 },
2055 { INPUT
, "h_gr_5", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 5, 0 },
2056 { INPUT
, "h_gr_6", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 6, 0 },
2057 { INPUT
, "h_gr_7", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 7, 0 },
2058 { INPUT
, "h_gr_8", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 8, 0 },
2059 { INPUT
, "h_gr_9", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 9, 0 },
2060 { INPUT
, "h_gr_10", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 10, 0 },
2061 { INPUT
, "h_gr_11", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 11, 0 },
2062 { INPUT
, "h_gr_12", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 12, 0 },
2063 { INPUT
, "h_gr_13", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 13, 0 },
2064 { INPUT
, "h_gr_14", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 14, 0 },
2065 { INPUT
, "h_gr_15", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 15, 0 },
2066 { INPUT
, "offset", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (OFFSET
), 0, 0 },
2067 { INPUT
, "abase", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (ABASE
), 0, 0 },
2068 { OUTPUT
, "h_gr_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 2, 0 },
2069 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_0", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2070 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2071 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2072 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_12", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2073 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_16", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2074 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_20", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2075 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_24", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2076 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_28", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2077 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_32", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2078 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_36", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2079 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_40", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2080 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_44", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2081 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_48", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2082 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_52", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2083 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_56", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2084 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_60", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2085 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0, 0 },
2086 { OUTPUT
, "h_gr_0", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
2087 { OUTPUT
, "h_gr_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 1, 0 },
2088 { OUTPUT
, "h_gr_3", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 3, 0 },
2089 { OUTPUT
, "h_gr_4", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 4, 0 },
2090 { OUTPUT
, "h_gr_5", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 5, 0 },
2091 { OUTPUT
, "h_gr_6", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 6, 0 },
2092 { OUTPUT
, "h_gr_7", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 7, 0 },
2093 { OUTPUT
, "h_gr_8", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 8, 0 },
2094 { OUTPUT
, "h_gr_9", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 9, 0 },
2095 { OUTPUT
, "h_gr_10", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 10, 0 },
2096 { OUTPUT
, "h_gr_11", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 11, 0 },
2097 { OUTPUT
, "h_gr_12", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 12, 0 },
2098 { OUTPUT
, "h_gr_13", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 13, 0 },
2099 { OUTPUT
, "h_gr_14", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 14, 0 },
2100 { OUTPUT
, "h_gr_15", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 15, 0 },
2101 { OUTPUT
, "h_gr_31", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 31, 0 },
2105 static const CGEN_OPERAND_INSTANCE fmt_ret_ops
[] = {
2106 { INPUT
, "h_gr_0", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
2107 { INPUT
, "h_gr_31", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 31, 0 },
2108 { INPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_0", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2109 { INPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2110 { INPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2111 { INPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_12", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2112 { INPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_16", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2113 { INPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_20", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2114 { INPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_24", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2115 { INPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_28", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2116 { INPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_32", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2117 { INPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_36", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2118 { INPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_40", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2119 { INPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_44", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2120 { INPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_48", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2121 { INPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_52", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2122 { INPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_56", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2123 { INPUT
, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_60", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
2124 { INPUT
, "h_gr_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 2, 0 },
2125 { OUTPUT
, "h_gr_31", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 31, 0 },
2126 { OUTPUT
, "h_gr_0", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, 0 },
2127 { OUTPUT
, "h_gr_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 1, 0 },
2128 { OUTPUT
, "h_gr_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 2, 0 },
2129 { OUTPUT
, "h_gr_3", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 3, 0 },
2130 { OUTPUT
, "h_gr_4", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 4, 0 },
2131 { OUTPUT
, "h_gr_5", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 5, 0 },
2132 { OUTPUT
, "h_gr_6", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 6, 0 },
2133 { OUTPUT
, "h_gr_7", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 7, 0 },
2134 { OUTPUT
, "h_gr_8", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 8, 0 },
2135 { OUTPUT
, "h_gr_9", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 9, 0 },
2136 { OUTPUT
, "h_gr_10", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 10, 0 },
2137 { OUTPUT
, "h_gr_11", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 11, 0 },
2138 { OUTPUT
, "h_gr_12", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 12, 0 },
2139 { OUTPUT
, "h_gr_13", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 13, 0 },
2140 { OUTPUT
, "h_gr_14", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 14, 0 },
2141 { OUTPUT
, "h_gr_15", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 15, 0 },
2142 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0, 0 },
2146 static const CGEN_OPERAND_INSTANCE fmt_calls_ops
[] = {
2147 { INPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_SI
, 0, 0, 0 },
2148 { INPUT
, "src1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0, 0 },
2149 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_SI
, 0, 0, 0 },
2153 static const CGEN_OPERAND_INSTANCE fmt_fmark_ops
[] = {
2154 { INPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_SI
, 0, 0, 0 },
2155 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_SI
, 0, 0, 0 },
2159 static const CGEN_OPERAND_INSTANCE fmt_flushreg_ops
[] = {
2160 { INPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
2161 { OUTPUT
, "dst", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DST
), 0, 0 },
2169 /* Instruction formats. */
2171 #define F(f) & i960_cgen_ifld_table[CONCAT2 (I960_,f)]
2173 static const CGEN_IFMT fmt_mulo
= {
2174 32, 32, 0xff003fe0, { F (F_OPCODE
), F (F_SRCDST
), F (F_SRC2
), F (F_M3
), F (F_M2
), F (F_M1
), F (F_OPCODE2
), F (F_ZERO
), F (F_SRC1
), 0 }
2177 static const CGEN_IFMT fmt_mulo1
= {
2178 32, 32, 0xff003fe0, { F (F_OPCODE
), F (F_SRCDST
), F (F_SRC2
), F (F_M3
), F (F_M2
), F (F_M1
), F (F_OPCODE2
), F (F_ZERO
), F (F_SRC1
), 0 }
2181 static const CGEN_IFMT fmt_mulo2
= {
2182 32, 32, 0xff003fe0, { F (F_OPCODE
), F (F_SRCDST
), F (F_SRC2
), F (F_M3
), F (F_M2
), F (F_M1
), F (F_OPCODE2
), F (F_ZERO
), F (F_SRC1
), 0 }
2185 static const CGEN_IFMT fmt_mulo3
= {
2186 32, 32, 0xff003fe0, { F (F_OPCODE
), F (F_SRCDST
), F (F_SRC2
), F (F_M3
), F (F_M2
), F (F_M1
), F (F_OPCODE2
), F (F_ZERO
), F (F_SRC1
), 0 }
2189 static const CGEN_IFMT fmt_remo
= {
2190 32, 32, 0xff003fe0, { F (F_OPCODE
), F (F_SRCDST
), F (F_SRC2
), F (F_M3
), F (F_M2
), F (F_M1
), F (F_OPCODE2
), F (F_ZERO
), F (F_SRC1
), 0 }
2193 static const CGEN_IFMT fmt_remo1
= {
2194 32, 32, 0xff003fe0, { F (F_OPCODE
), F (F_SRCDST
), F (F_SRC2
), F (F_M3
), F (F_M2
), F (F_M1
), F (F_OPCODE2
), F (F_ZERO
), F (F_SRC1
), 0 }
2197 static const CGEN_IFMT fmt_remo2
= {
2198 32, 32, 0xff003fe0, { F (F_OPCODE
), F (F_SRCDST
), F (F_SRC2
), F (F_M3
), F (F_M2
), F (F_M1
), F (F_OPCODE2
), F (F_ZERO
), F (F_SRC1
), 0 }
2201 static const CGEN_IFMT fmt_remo3
= {
2202 32, 32, 0xff003fe0, { F (F_OPCODE
), F (F_SRCDST
), F (F_SRC2
), F (F_M3
), F (F_M2
), F (F_M1
), F (F_OPCODE2
), F (F_ZERO
), F (F_SRC1
), 0 }
2205 static const CGEN_IFMT fmt_not
= {
2206 32, 32, 0xff003fe0, { F (F_OPCODE
), F (F_SRCDST
), F (F_SRC2
), F (F_M3
), F (F_M2
), F (F_M1
), F (F_OPCODE2
), F (F_ZERO
), F (F_SRC1
), 0 }
2209 static const CGEN_IFMT fmt_not1
= {
2210 32, 32, 0xff003fe0, { F (F_OPCODE
), F (F_SRCDST
), F (F_SRC2
), F (F_M3
), F (F_M2
), F (F_M1
), F (F_OPCODE2
), F (F_ZERO
), F (F_SRC1
), 0 }
2213 static const CGEN_IFMT fmt_not2
= {
2214 32, 32, 0xff003fe0, { F (F_OPCODE
), F (F_SRCDST
), F (F_SRC2
), F (F_M3
), F (F_M2
), F (F_M1
), F (F_OPCODE2
), F (F_ZERO
), F (F_SRC1
), 0 }
2217 static const CGEN_IFMT fmt_not3
= {
2218 32, 32, 0xff003fe0, { F (F_OPCODE
), F (F_SRCDST
), F (F_SRC2
), F (F_M3
), F (F_M2
), F (F_M1
), F (F_OPCODE2
), F (F_ZERO
), F (F_SRC1
), 0 }
2221 static const CGEN_IFMT fmt_emul
= {
2222 32, 32, 0xff003fe0, { F (F_OPCODE
), F (F_SRCDST
), F (F_SRC2
), F (F_M3
), F (F_M2
), F (F_M1
), F (F_OPCODE2
), F (F_ZERO
), F (F_SRC1
), 0 }
2225 static const CGEN_IFMT fmt_emul1
= {
2226 32, 32, 0xff003fe0, { F (F_OPCODE
), F (F_SRCDST
), F (F_SRC2
), F (F_M3
), F (F_M2
), F (F_M1
), F (F_OPCODE2
), F (F_ZERO
), F (F_SRC1
), 0 }
2229 static const CGEN_IFMT fmt_emul2
= {
2230 32, 32, 0xff003fe0, { F (F_OPCODE
), F (F_SRCDST
), F (F_SRC2
), F (F_M3
), F (F_M2
), F (F_M1
), F (F_OPCODE2
), F (F_ZERO
), F (F_SRC1
), 0 }
2233 static const CGEN_IFMT fmt_emul3
= {
2234 32, 32, 0xff003fe0, { F (F_OPCODE
), F (F_SRCDST
), F (F_SRC2
), F (F_M3
), F (F_M2
), F (F_M1
), F (F_OPCODE2
), F (F_ZERO
), F (F_SRC1
), 0 }
2237 static const CGEN_IFMT fmt_movl
= {
2238 32, 32, 0xff003fe0, { F (F_OPCODE
), F (F_SRCDST
), F (F_SRC2
), F (F_M3
), F (F_M2
), F (F_M1
), F (F_OPCODE2
), F (F_ZERO
), F (F_SRC1
), 0 }
2241 static const CGEN_IFMT fmt_movl1
= {
2242 32, 32, 0xff003fe0, { F (F_OPCODE
), F (F_SRCDST
), F (F_SRC2
), F (F_M3
), F (F_M2
), F (F_M1
), F (F_OPCODE2
), F (F_ZERO
), F (F_SRC1
), 0 }
2245 static const CGEN_IFMT fmt_movt
= {
2246 32, 32, 0xff003fe0, { F (F_OPCODE
), F (F_SRCDST
), F (F_SRC2
), F (F_M3
), F (F_M2
), F (F_M1
), F (F_OPCODE2
), F (F_ZERO
), F (F_SRC1
), 0 }
2249 static const CGEN_IFMT fmt_movt1
= {
2250 32, 32, 0xff003fe0, { F (F_OPCODE
), F (F_SRCDST
), F (F_SRC2
), F (F_M3
), F (F_M2
), F (F_M1
), F (F_OPCODE2
), F (F_ZERO
), F (F_SRC1
), 0 }
2253 static const CGEN_IFMT fmt_movq
= {
2254 32, 32, 0xff003fe0, { F (F_OPCODE
), F (F_SRCDST
), F (F_SRC2
), F (F_M3
), F (F_M2
), F (F_M1
), F (F_OPCODE2
), F (F_ZERO
), F (F_SRC1
), 0 }
2257 static const CGEN_IFMT fmt_movq1
= {
2258 32, 32, 0xff003fe0, { F (F_OPCODE
), F (F_SRCDST
), F (F_SRC2
), F (F_M3
), F (F_M2
), F (F_M1
), F (F_OPCODE2
), F (F_ZERO
), F (F_SRC1
), 0 }
2261 static const CGEN_IFMT fmt_modpc
= {
2262 32, 32, 0xff003fe0, { F (F_OPCODE
), F (F_SRCDST
), F (F_SRC2
), F (F_M3
), F (F_M2
), F (F_M1
), F (F_OPCODE2
), F (F_ZERO
), F (F_SRC1
), 0 }
2265 static const CGEN_IFMT fmt_lda_offset
= {
2266 32, 32, 0xff003000, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEA
), F (F_ZEROA
), F (F_OFFSET
), 0 }
2269 static const CGEN_IFMT fmt_lda_indirect_offset
= {
2270 32, 32, 0xff003000, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEA
), F (F_ZEROA
), F (F_OFFSET
), 0 }
2273 static const CGEN_IFMT fmt_lda_indirect
= {
2274 32, 32, 0xff003c60, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2277 static const CGEN_IFMT fmt_lda_indirect_index
= {
2278 32, 32, 0xff003c60, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2281 static const CGEN_IFMT fmt_lda_disp
= {
2282 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2285 static const CGEN_IFMT fmt_lda_indirect_disp
= {
2286 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2289 static const CGEN_IFMT fmt_lda_index_disp
= {
2290 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2293 static const CGEN_IFMT fmt_lda_indirect_index_disp
= {
2294 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2297 static const CGEN_IFMT fmt_ld_offset
= {
2298 32, 32, 0xff003000, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEA
), F (F_ZEROA
), F (F_OFFSET
), 0 }
2301 static const CGEN_IFMT fmt_ld_indirect_offset
= {
2302 32, 32, 0xff003000, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEA
), F (F_ZEROA
), F (F_OFFSET
), 0 }
2305 static const CGEN_IFMT fmt_ld_indirect
= {
2306 32, 32, 0xff003c60, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2309 static const CGEN_IFMT fmt_ld_indirect_index
= {
2310 32, 32, 0xff003c60, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2313 static const CGEN_IFMT fmt_ld_disp
= {
2314 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2317 static const CGEN_IFMT fmt_ld_indirect_disp
= {
2318 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2321 static const CGEN_IFMT fmt_ld_index_disp
= {
2322 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2325 static const CGEN_IFMT fmt_ld_indirect_index_disp
= {
2326 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2329 static const CGEN_IFMT fmt_ldob_offset
= {
2330 32, 32, 0xff003000, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEA
), F (F_ZEROA
), F (F_OFFSET
), 0 }
2333 static const CGEN_IFMT fmt_ldob_indirect_offset
= {
2334 32, 32, 0xff003000, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEA
), F (F_ZEROA
), F (F_OFFSET
), 0 }
2337 static const CGEN_IFMT fmt_ldob_indirect
= {
2338 32, 32, 0xff003c60, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2341 static const CGEN_IFMT fmt_ldob_indirect_index
= {
2342 32, 32, 0xff003c60, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2345 static const CGEN_IFMT fmt_ldob_disp
= {
2346 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2349 static const CGEN_IFMT fmt_ldob_indirect_disp
= {
2350 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2353 static const CGEN_IFMT fmt_ldob_index_disp
= {
2354 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2357 static const CGEN_IFMT fmt_ldob_indirect_index_disp
= {
2358 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2361 static const CGEN_IFMT fmt_ldos_offset
= {
2362 32, 32, 0xff003000, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEA
), F (F_ZEROA
), F (F_OFFSET
), 0 }
2365 static const CGEN_IFMT fmt_ldos_indirect_offset
= {
2366 32, 32, 0xff003000, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEA
), F (F_ZEROA
), F (F_OFFSET
), 0 }
2369 static const CGEN_IFMT fmt_ldos_indirect
= {
2370 32, 32, 0xff003c60, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2373 static const CGEN_IFMT fmt_ldos_indirect_index
= {
2374 32, 32, 0xff003c60, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2377 static const CGEN_IFMT fmt_ldos_disp
= {
2378 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2381 static const CGEN_IFMT fmt_ldos_indirect_disp
= {
2382 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2385 static const CGEN_IFMT fmt_ldos_index_disp
= {
2386 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2389 static const CGEN_IFMT fmt_ldos_indirect_index_disp
= {
2390 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2393 static const CGEN_IFMT fmt_ldib_offset
= {
2394 32, 32, 0xff003000, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEA
), F (F_ZEROA
), F (F_OFFSET
), 0 }
2397 static const CGEN_IFMT fmt_ldib_indirect_offset
= {
2398 32, 32, 0xff003000, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEA
), F (F_ZEROA
), F (F_OFFSET
), 0 }
2401 static const CGEN_IFMT fmt_ldib_indirect
= {
2402 32, 32, 0xff003c60, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2405 static const CGEN_IFMT fmt_ldib_indirect_index
= {
2406 32, 32, 0xff003c60, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2409 static const CGEN_IFMT fmt_ldib_disp
= {
2410 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2413 static const CGEN_IFMT fmt_ldib_indirect_disp
= {
2414 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2417 static const CGEN_IFMT fmt_ldib_index_disp
= {
2418 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2421 static const CGEN_IFMT fmt_ldib_indirect_index_disp
= {
2422 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2425 static const CGEN_IFMT fmt_ldis_offset
= {
2426 32, 32, 0xff003000, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEA
), F (F_ZEROA
), F (F_OFFSET
), 0 }
2429 static const CGEN_IFMT fmt_ldis_indirect_offset
= {
2430 32, 32, 0xff003000, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEA
), F (F_ZEROA
), F (F_OFFSET
), 0 }
2433 static const CGEN_IFMT fmt_ldis_indirect
= {
2434 32, 32, 0xff003c60, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2437 static const CGEN_IFMT fmt_ldis_indirect_index
= {
2438 32, 32, 0xff003c60, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2441 static const CGEN_IFMT fmt_ldis_disp
= {
2442 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2445 static const CGEN_IFMT fmt_ldis_indirect_disp
= {
2446 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2449 static const CGEN_IFMT fmt_ldis_index_disp
= {
2450 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2453 static const CGEN_IFMT fmt_ldis_indirect_index_disp
= {
2454 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2457 static const CGEN_IFMT fmt_ldl_offset
= {
2458 32, 32, 0xff003000, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEA
), F (F_ZEROA
), F (F_OFFSET
), 0 }
2461 static const CGEN_IFMT fmt_ldl_indirect_offset
= {
2462 32, 32, 0xff003000, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEA
), F (F_ZEROA
), F (F_OFFSET
), 0 }
2465 static const CGEN_IFMT fmt_ldl_indirect
= {
2466 32, 32, 0xff003c60, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2469 static const CGEN_IFMT fmt_ldl_indirect_index
= {
2470 32, 32, 0xff003c60, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2473 static const CGEN_IFMT fmt_ldl_disp
= {
2474 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2477 static const CGEN_IFMT fmt_ldl_indirect_disp
= {
2478 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2481 static const CGEN_IFMT fmt_ldl_index_disp
= {
2482 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2485 static const CGEN_IFMT fmt_ldl_indirect_index_disp
= {
2486 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2489 static const CGEN_IFMT fmt_ldt_offset
= {
2490 32, 32, 0xff003000, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEA
), F (F_ZEROA
), F (F_OFFSET
), 0 }
2493 static const CGEN_IFMT fmt_ldt_indirect_offset
= {
2494 32, 32, 0xff003000, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEA
), F (F_ZEROA
), F (F_OFFSET
), 0 }
2497 static const CGEN_IFMT fmt_ldt_indirect
= {
2498 32, 32, 0xff003c60, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2501 static const CGEN_IFMT fmt_ldt_indirect_index
= {
2502 32, 32, 0xff003c60, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2505 static const CGEN_IFMT fmt_ldt_disp
= {
2506 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2509 static const CGEN_IFMT fmt_ldt_indirect_disp
= {
2510 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2513 static const CGEN_IFMT fmt_ldt_index_disp
= {
2514 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2517 static const CGEN_IFMT fmt_ldt_indirect_index_disp
= {
2518 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2521 static const CGEN_IFMT fmt_ldq_offset
= {
2522 32, 32, 0xff003000, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEA
), F (F_ZEROA
), F (F_OFFSET
), 0 }
2525 static const CGEN_IFMT fmt_ldq_indirect_offset
= {
2526 32, 32, 0xff003000, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEA
), F (F_ZEROA
), F (F_OFFSET
), 0 }
2529 static const CGEN_IFMT fmt_ldq_indirect
= {
2530 32, 32, 0xff003c60, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2533 static const CGEN_IFMT fmt_ldq_indirect_index
= {
2534 32, 32, 0xff003c60, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2537 static const CGEN_IFMT fmt_ldq_disp
= {
2538 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2541 static const CGEN_IFMT fmt_ldq_indirect_disp
= {
2542 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2545 static const CGEN_IFMT fmt_ldq_index_disp
= {
2546 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2549 static const CGEN_IFMT fmt_ldq_indirect_index_disp
= {
2550 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2553 static const CGEN_IFMT fmt_st_offset
= {
2554 32, 32, 0xff003000, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEA
), F (F_ZEROA
), F (F_OFFSET
), 0 }
2557 static const CGEN_IFMT fmt_st_indirect_offset
= {
2558 32, 32, 0xff003000, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEA
), F (F_ZEROA
), F (F_OFFSET
), 0 }
2561 static const CGEN_IFMT fmt_st_indirect
= {
2562 32, 32, 0xff003c60, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2565 static const CGEN_IFMT fmt_st_indirect_index
= {
2566 32, 32, 0xff003c60, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2569 static const CGEN_IFMT fmt_st_disp
= {
2570 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2573 static const CGEN_IFMT fmt_st_indirect_disp
= {
2574 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2577 static const CGEN_IFMT fmt_st_index_disp
= {
2578 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2581 static const CGEN_IFMT fmt_st_indirect_index_disp
= {
2582 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2585 static const CGEN_IFMT fmt_stob_offset
= {
2586 32, 32, 0xff003000, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEA
), F (F_ZEROA
), F (F_OFFSET
), 0 }
2589 static const CGEN_IFMT fmt_stob_indirect_offset
= {
2590 32, 32, 0xff003000, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEA
), F (F_ZEROA
), F (F_OFFSET
), 0 }
2593 static const CGEN_IFMT fmt_stob_indirect
= {
2594 32, 32, 0xff003c60, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2597 static const CGEN_IFMT fmt_stob_indirect_index
= {
2598 32, 32, 0xff003c60, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2601 static const CGEN_IFMT fmt_stob_disp
= {
2602 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2605 static const CGEN_IFMT fmt_stob_indirect_disp
= {
2606 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2609 static const CGEN_IFMT fmt_stob_index_disp
= {
2610 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2613 static const CGEN_IFMT fmt_stob_indirect_index_disp
= {
2614 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2617 static const CGEN_IFMT fmt_stos_offset
= {
2618 32, 32, 0xff003000, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEA
), F (F_ZEROA
), F (F_OFFSET
), 0 }
2621 static const CGEN_IFMT fmt_stos_indirect_offset
= {
2622 32, 32, 0xff003000, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEA
), F (F_ZEROA
), F (F_OFFSET
), 0 }
2625 static const CGEN_IFMT fmt_stos_indirect
= {
2626 32, 32, 0xff003c60, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2629 static const CGEN_IFMT fmt_stos_indirect_index
= {
2630 32, 32, 0xff003c60, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2633 static const CGEN_IFMT fmt_stos_disp
= {
2634 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2637 static const CGEN_IFMT fmt_stos_indirect_disp
= {
2638 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2641 static const CGEN_IFMT fmt_stos_index_disp
= {
2642 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2645 static const CGEN_IFMT fmt_stos_indirect_index_disp
= {
2646 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2649 static const CGEN_IFMT fmt_stl_offset
= {
2650 32, 32, 0xff003000, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEA
), F (F_ZEROA
), F (F_OFFSET
), 0 }
2653 static const CGEN_IFMT fmt_stl_indirect_offset
= {
2654 32, 32, 0xff003000, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEA
), F (F_ZEROA
), F (F_OFFSET
), 0 }
2657 static const CGEN_IFMT fmt_stl_indirect
= {
2658 32, 32, 0xff003c60, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2661 static const CGEN_IFMT fmt_stl_indirect_index
= {
2662 32, 32, 0xff003c60, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2665 static const CGEN_IFMT fmt_stl_disp
= {
2666 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2669 static const CGEN_IFMT fmt_stl_indirect_disp
= {
2670 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2673 static const CGEN_IFMT fmt_stl_index_disp
= {
2674 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2677 static const CGEN_IFMT fmt_stl_indirect_index_disp
= {
2678 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2681 static const CGEN_IFMT fmt_stt_offset
= {
2682 32, 32, 0xff003000, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEA
), F (F_ZEROA
), F (F_OFFSET
), 0 }
2685 static const CGEN_IFMT fmt_stt_indirect_offset
= {
2686 32, 32, 0xff003000, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEA
), F (F_ZEROA
), F (F_OFFSET
), 0 }
2689 static const CGEN_IFMT fmt_stt_indirect
= {
2690 32, 32, 0xff003c60, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2693 static const CGEN_IFMT fmt_stt_indirect_index
= {
2694 32, 32, 0xff003c60, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2697 static const CGEN_IFMT fmt_stt_disp
= {
2698 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2701 static const CGEN_IFMT fmt_stt_indirect_disp
= {
2702 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2705 static const CGEN_IFMT fmt_stt_index_disp
= {
2706 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2709 static const CGEN_IFMT fmt_stt_indirect_index_disp
= {
2710 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2713 static const CGEN_IFMT fmt_stq_offset
= {
2714 32, 32, 0xff003000, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEA
), F (F_ZEROA
), F (F_OFFSET
), 0 }
2717 static const CGEN_IFMT fmt_stq_indirect_offset
= {
2718 32, 32, 0xff003000, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEA
), F (F_ZEROA
), F (F_OFFSET
), 0 }
2721 static const CGEN_IFMT fmt_stq_indirect
= {
2722 32, 32, 0xff003c60, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2725 static const CGEN_IFMT fmt_stq_indirect_index
= {
2726 32, 32, 0xff003c60, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2729 static const CGEN_IFMT fmt_stq_disp
= {
2730 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2733 static const CGEN_IFMT fmt_stq_indirect_disp
= {
2734 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2737 static const CGEN_IFMT fmt_stq_index_disp
= {
2738 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2741 static const CGEN_IFMT fmt_stq_indirect_index_disp
= {
2742 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2745 static const CGEN_IFMT fmt_cmpobe_reg
= {
2746 32, 32, 0xff002003, { F (F_OPCODE
), F (F_BR_SRC1
), F (F_BR_SRC2
), F (F_BR_M1
), F (F_BR_DISP
), F (F_BR_ZERO
), 0 }
2749 static const CGEN_IFMT fmt_cmpobe_lit
= {
2750 32, 32, 0xff002003, { F (F_OPCODE
), F (F_BR_SRC1
), F (F_BR_SRC2
), F (F_BR_M1
), F (F_BR_DISP
), F (F_BR_ZERO
), 0 }
2753 static const CGEN_IFMT fmt_cmpobl_reg
= {
2754 32, 32, 0xff002003, { F (F_OPCODE
), F (F_BR_SRC1
), F (F_BR_SRC2
), F (F_BR_M1
), F (F_BR_DISP
), F (F_BR_ZERO
), 0 }
2757 static const CGEN_IFMT fmt_cmpobl_lit
= {
2758 32, 32, 0xff002003, { F (F_OPCODE
), F (F_BR_SRC1
), F (F_BR_SRC2
), F (F_BR_M1
), F (F_BR_DISP
), F (F_BR_ZERO
), 0 }
2761 static const CGEN_IFMT fmt_bbc_lit
= {
2762 32, 32, 0xff002003, { F (F_OPCODE
), F (F_BR_SRC1
), F (F_BR_SRC2
), F (F_BR_M1
), F (F_BR_DISP
), F (F_BR_ZERO
), 0 }
2765 static const CGEN_IFMT fmt_cmpi
= {
2766 32, 32, 0xff003fe0, { F (F_OPCODE
), F (F_SRCDST
), F (F_SRC2
), F (F_M3
), F (F_M2
), F (F_M1
), F (F_OPCODE2
), F (F_ZERO
), F (F_SRC1
), 0 }
2769 static const CGEN_IFMT fmt_cmpi1
= {
2770 32, 32, 0xff003fe0, { F (F_OPCODE
), F (F_SRCDST
), F (F_SRC2
), F (F_M3
), F (F_M2
), F (F_M1
), F (F_OPCODE2
), F (F_ZERO
), F (F_SRC1
), 0 }
2773 static const CGEN_IFMT fmt_cmpi2
= {
2774 32, 32, 0xff003fe0, { F (F_OPCODE
), F (F_SRCDST
), F (F_SRC2
), F (F_M3
), F (F_M2
), F (F_M1
), F (F_OPCODE2
), F (F_ZERO
), F (F_SRC1
), 0 }
2777 static const CGEN_IFMT fmt_cmpi3
= {
2778 32, 32, 0xff003fe0, { F (F_OPCODE
), F (F_SRCDST
), F (F_SRC2
), F (F_M3
), F (F_M2
), F (F_M1
), F (F_OPCODE2
), F (F_ZERO
), F (F_SRC1
), 0 }
2781 static const CGEN_IFMT fmt_testno_reg
= {
2782 32, 32, 0xff002003, { F (F_OPCODE
), F (F_BR_SRC1
), F (F_BR_SRC2
), F (F_BR_M1
), F (F_BR_DISP
), F (F_BR_ZERO
), 0 }
2785 static const CGEN_IFMT fmt_bno
= {
2786 32, 32, 0xff000003, { F (F_OPCODE
), F (F_CTRL_DISP
), F (F_CTRL_ZERO
), 0 }
2789 static const CGEN_IFMT fmt_b
= {
2790 32, 32, 0xff000003, { F (F_OPCODE
), F (F_CTRL_DISP
), F (F_CTRL_ZERO
), 0 }
2793 static const CGEN_IFMT fmt_bx_indirect_offset
= {
2794 32, 32, 0xff003000, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEA
), F (F_ZEROA
), F (F_OFFSET
), 0 }
2797 static const CGEN_IFMT fmt_bx_indirect
= {
2798 32, 32, 0xff003c60, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2801 static const CGEN_IFMT fmt_bx_indirect_index
= {
2802 32, 32, 0xff003c60, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2805 static const CGEN_IFMT fmt_bx_disp
= {
2806 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2809 static const CGEN_IFMT fmt_bx_indirect_disp
= {
2810 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2813 static const CGEN_IFMT fmt_callx_disp
= {
2814 32, 64, 0xff003c60, { F (F_OPCODE
), F (F_OPTDISP
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2817 static const CGEN_IFMT fmt_callx_indirect
= {
2818 32, 32, 0xff003c60, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEB
), F (F_SCALE
), F (F_ZEROB
), F (F_INDEX
), 0 }
2821 static const CGEN_IFMT fmt_callx_indirect_offset
= {
2822 32, 32, 0xff003000, { F (F_OPCODE
), F (F_SRCDST
), F (F_ABASE
), F (F_MODEA
), F (F_ZEROA
), F (F_OFFSET
), 0 }
2825 static const CGEN_IFMT fmt_ret
= {
2826 32, 32, 0xff000003, { F (F_OPCODE
), F (F_CTRL_DISP
), F (F_CTRL_ZERO
), 0 }
2829 static const CGEN_IFMT fmt_calls
= {
2830 32, 32, 0xff003fe0, { F (F_OPCODE
), F (F_SRCDST
), F (F_SRC2
), F (F_M3
), F (F_M2
), F (F_M1
), F (F_OPCODE2
), F (F_ZERO
), F (F_SRC1
), 0 }
2833 static const CGEN_IFMT fmt_fmark
= {
2834 32, 32, 0xff003fe0, { F (F_OPCODE
), F (F_SRCDST
), F (F_SRC2
), F (F_M3
), F (F_M2
), F (F_M1
), F (F_OPCODE2
), F (F_ZERO
), F (F_SRC1
), 0 }
2837 static const CGEN_IFMT fmt_flushreg
= {
2838 32, 32, 0xff003fe0, { F (F_OPCODE
), F (F_SRCDST
), F (F_SRC2
), F (F_M3
), F (F_M2
), F (F_M1
), F (F_OPCODE2
), F (F_ZERO
), F (F_SRC1
), 0 }
2843 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
2844 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
2845 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
2847 /* The instruction table.
2848 This is currently non-static because the simulator accesses it
2851 const CGEN_INSN i960_cgen_insn_table_entries
[MAX_INSNS
] =
2853 /* Special null first entry.
2854 A `num' value of zero is thus invalid.
2855 Also, the special `invalid' insn resides here. */
2857 /* mulo $src1, $src2, $dst */
2860 I960_INSN_MULO
, "mulo", "mulo",
2861 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
2862 & fmt_mulo
, { 0x70000080 },
2863 (PTR
) & fmt_mulo_ops
[0],
2866 /* mulo $lit1, $src2, $dst */
2869 I960_INSN_MULO1
, "mulo1", "mulo",
2870 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
2871 & fmt_mulo1
, { 0x70000880 },
2872 (PTR
) & fmt_mulo1_ops
[0],
2875 /* mulo $src1, $lit2, $dst */
2878 I960_INSN_MULO2
, "mulo2", "mulo",
2879 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
2880 & fmt_mulo2
, { 0x70001080 },
2881 (PTR
) & fmt_mulo2_ops
[0],
2884 /* mulo $lit1, $lit2, $dst */
2887 I960_INSN_MULO3
, "mulo3", "mulo",
2888 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
2889 & fmt_mulo3
, { 0x70001880 },
2890 (PTR
) & fmt_mulo3_ops
[0],
2893 /* remo $src1, $src2, $dst */
2896 I960_INSN_REMO
, "remo", "remo",
2897 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
2898 & fmt_remo
, { 0x70000400 },
2899 (PTR
) & fmt_remo_ops
[0],
2902 /* remo $lit1, $src2, $dst */
2905 I960_INSN_REMO1
, "remo1", "remo",
2906 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
2907 & fmt_remo1
, { 0x70000c00 },
2908 (PTR
) & fmt_remo1_ops
[0],
2911 /* remo $src1, $lit2, $dst */
2914 I960_INSN_REMO2
, "remo2", "remo",
2915 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
2916 & fmt_remo2
, { 0x70001400 },
2917 (PTR
) & fmt_remo2_ops
[0],
2920 /* remo $lit1, $lit2, $dst */
2923 I960_INSN_REMO3
, "remo3", "remo",
2924 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
2925 & fmt_remo3
, { 0x70001c00 },
2926 (PTR
) & fmt_remo3_ops
[0],
2929 /* divo $src1, $src2, $dst */
2932 I960_INSN_DIVO
, "divo", "divo",
2933 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
2934 & fmt_remo
, { 0x70000580 },
2935 (PTR
) & fmt_remo_ops
[0],
2938 /* divo $lit1, $src2, $dst */
2941 I960_INSN_DIVO1
, "divo1", "divo",
2942 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
2943 & fmt_remo1
, { 0x70000d80 },
2944 (PTR
) & fmt_remo1_ops
[0],
2947 /* divo $src1, $lit2, $dst */
2950 I960_INSN_DIVO2
, "divo2", "divo",
2951 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
2952 & fmt_remo2
, { 0x70001580 },
2953 (PTR
) & fmt_remo2_ops
[0],
2956 /* divo $lit1, $lit2, $dst */
2959 I960_INSN_DIVO3
, "divo3", "divo",
2960 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
2961 & fmt_remo3
, { 0x70001d80 },
2962 (PTR
) & fmt_remo3_ops
[0],
2965 /* remi $src1, $src2, $dst */
2968 I960_INSN_REMI
, "remi", "remi",
2969 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
2970 & fmt_remo
, { 0x74000400 },
2971 (PTR
) & fmt_remo_ops
[0],
2974 /* remi $lit1, $src2, $dst */
2977 I960_INSN_REMI1
, "remi1", "remi",
2978 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
2979 & fmt_remo1
, { 0x74000c00 },
2980 (PTR
) & fmt_remo1_ops
[0],
2983 /* remi $src1, $lit2, $dst */
2986 I960_INSN_REMI2
, "remi2", "remi",
2987 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
2988 & fmt_remo2
, { 0x74001400 },
2989 (PTR
) & fmt_remo2_ops
[0],
2992 /* remi $lit1, $lit2, $dst */
2995 I960_INSN_REMI3
, "remi3", "remi",
2996 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
2997 & fmt_remo3
, { 0x74001c00 },
2998 (PTR
) & fmt_remo3_ops
[0],
3001 /* divi $src1, $src2, $dst */
3004 I960_INSN_DIVI
, "divi", "divi",
3005 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
3006 & fmt_remo
, { 0x74000580 },
3007 (PTR
) & fmt_remo_ops
[0],
3010 /* divi $lit1, $src2, $dst */
3013 I960_INSN_DIVI1
, "divi1", "divi",
3014 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
3015 & fmt_remo1
, { 0x74000d80 },
3016 (PTR
) & fmt_remo1_ops
[0],
3019 /* divi $src1, $lit2, $dst */
3022 I960_INSN_DIVI2
, "divi2", "divi",
3023 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
3024 & fmt_remo2
, { 0x74001580 },
3025 (PTR
) & fmt_remo2_ops
[0],
3028 /* divi $lit1, $lit2, $dst */
3031 I960_INSN_DIVI3
, "divi3", "divi",
3032 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
3033 & fmt_remo3
, { 0x74001d80 },
3034 (PTR
) & fmt_remo3_ops
[0],
3037 /* addo $src1, $src2, $dst */
3040 I960_INSN_ADDO
, "addo", "addo",
3041 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
3042 & fmt_mulo
, { 0x59000000 },
3043 (PTR
) & fmt_mulo_ops
[0],
3046 /* addo $lit1, $src2, $dst */
3049 I960_INSN_ADDO1
, "addo1", "addo",
3050 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
3051 & fmt_mulo1
, { 0x59000800 },
3052 (PTR
) & fmt_mulo1_ops
[0],
3055 /* addo $src1, $lit2, $dst */
3058 I960_INSN_ADDO2
, "addo2", "addo",
3059 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
3060 & fmt_mulo2
, { 0x59001000 },
3061 (PTR
) & fmt_mulo2_ops
[0],
3064 /* addo $lit1, $lit2, $dst */
3067 I960_INSN_ADDO3
, "addo3", "addo",
3068 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
3069 & fmt_mulo3
, { 0x59001800 },
3070 (PTR
) & fmt_mulo3_ops
[0],
3073 /* subo $src1, $src2, $dst */
3076 I960_INSN_SUBO
, "subo", "subo",
3077 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
3078 & fmt_remo
, { 0x59000100 },
3079 (PTR
) & fmt_remo_ops
[0],
3082 /* subo $lit1, $src2, $dst */
3085 I960_INSN_SUBO1
, "subo1", "subo",
3086 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
3087 & fmt_remo1
, { 0x59000900 },
3088 (PTR
) & fmt_remo1_ops
[0],
3091 /* subo $src1, $lit2, $dst */
3094 I960_INSN_SUBO2
, "subo2", "subo",
3095 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
3096 & fmt_remo2
, { 0x59001100 },
3097 (PTR
) & fmt_remo2_ops
[0],
3100 /* subo $lit1, $lit2, $dst */
3103 I960_INSN_SUBO3
, "subo3", "subo",
3104 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
3105 & fmt_remo3
, { 0x59001900 },
3106 (PTR
) & fmt_remo3_ops
[0],
3109 /* notbit $src1, $src2, $dst */
3112 I960_INSN_NOTBIT
, "notbit", "notbit",
3113 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
3114 & fmt_mulo
, { 0x58000000 },
3115 (PTR
) & fmt_mulo_ops
[0],
3118 /* notbit $lit1, $src2, $dst */
3121 I960_INSN_NOTBIT1
, "notbit1", "notbit",
3122 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
3123 & fmt_mulo1
, { 0x58000800 },
3124 (PTR
) & fmt_mulo1_ops
[0],
3127 /* notbit $src1, $lit2, $dst */
3130 I960_INSN_NOTBIT2
, "notbit2", "notbit",
3131 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
3132 & fmt_mulo2
, { 0x58001000 },
3133 (PTR
) & fmt_mulo2_ops
[0],
3136 /* notbit $lit1, $lit2, $dst */
3139 I960_INSN_NOTBIT3
, "notbit3", "notbit",
3140 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
3141 & fmt_mulo3
, { 0x58001800 },
3142 (PTR
) & fmt_mulo3_ops
[0],
3145 /* and $src1, $src2, $dst */
3148 I960_INSN_AND
, "and", "and",
3149 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
3150 & fmt_mulo
, { 0x58000080 },
3151 (PTR
) & fmt_mulo_ops
[0],
3154 /* and $lit1, $src2, $dst */
3157 I960_INSN_AND1
, "and1", "and",
3158 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
3159 & fmt_mulo1
, { 0x58000880 },
3160 (PTR
) & fmt_mulo1_ops
[0],
3163 /* and $src1, $lit2, $dst */
3166 I960_INSN_AND2
, "and2", "and",
3167 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
3168 & fmt_mulo2
, { 0x58001080 },
3169 (PTR
) & fmt_mulo2_ops
[0],
3172 /* and $lit1, $lit2, $dst */
3175 I960_INSN_AND3
, "and3", "and",
3176 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
3177 & fmt_mulo3
, { 0x58001880 },
3178 (PTR
) & fmt_mulo3_ops
[0],
3181 /* andnot $src1, $src2, $dst */
3184 I960_INSN_ANDNOT
, "andnot", "andnot",
3185 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
3186 & fmt_remo
, { 0x58000100 },
3187 (PTR
) & fmt_remo_ops
[0],
3190 /* andnot $lit1, $src2, $dst */
3193 I960_INSN_ANDNOT1
, "andnot1", "andnot",
3194 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
3195 & fmt_remo1
, { 0x58000900 },
3196 (PTR
) & fmt_remo1_ops
[0],
3199 /* andnot $src1, $lit2, $dst */
3202 I960_INSN_ANDNOT2
, "andnot2", "andnot",
3203 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
3204 & fmt_remo2
, { 0x58001100 },
3205 (PTR
) & fmt_remo2_ops
[0],
3208 /* andnot $lit1, $lit2, $dst */
3211 I960_INSN_ANDNOT3
, "andnot3", "andnot",
3212 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
3213 & fmt_remo3
, { 0x58001900 },
3214 (PTR
) & fmt_remo3_ops
[0],
3217 /* setbit $src1, $src2, $dst */
3220 I960_INSN_SETBIT
, "setbit", "setbit",
3221 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
3222 & fmt_mulo
, { 0x58000180 },
3223 (PTR
) & fmt_mulo_ops
[0],
3226 /* setbit $lit1, $src2, $dst */
3229 I960_INSN_SETBIT1
, "setbit1", "setbit",
3230 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
3231 & fmt_mulo1
, { 0x58000980 },
3232 (PTR
) & fmt_mulo1_ops
[0],
3235 /* setbit $src1, $lit2, $dst */
3238 I960_INSN_SETBIT2
, "setbit2", "setbit",
3239 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
3240 & fmt_mulo2
, { 0x58001180 },
3241 (PTR
) & fmt_mulo2_ops
[0],
3244 /* setbit $lit1, $lit2, $dst */
3247 I960_INSN_SETBIT3
, "setbit3", "setbit",
3248 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
3249 & fmt_mulo3
, { 0x58001980 },
3250 (PTR
) & fmt_mulo3_ops
[0],
3253 /* notand $src1, $src2, $dst */
3256 I960_INSN_NOTAND
, "notand", "notand",
3257 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
3258 & fmt_remo
, { 0x58000200 },
3259 (PTR
) & fmt_remo_ops
[0],
3262 /* notand $lit1, $src2, $dst */
3265 I960_INSN_NOTAND1
, "notand1", "notand",
3266 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
3267 & fmt_remo1
, { 0x58000a00 },
3268 (PTR
) & fmt_remo1_ops
[0],
3271 /* notand $src1, $lit2, $dst */
3274 I960_INSN_NOTAND2
, "notand2", "notand",
3275 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
3276 & fmt_remo2
, { 0x58001200 },
3277 (PTR
) & fmt_remo2_ops
[0],
3280 /* notand $lit1, $lit2, $dst */
3283 I960_INSN_NOTAND3
, "notand3", "notand",
3284 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
3285 & fmt_remo3
, { 0x58001a00 },
3286 (PTR
) & fmt_remo3_ops
[0],
3289 /* xor $src1, $src2, $dst */
3292 I960_INSN_XOR
, "xor", "xor",
3293 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
3294 & fmt_mulo
, { 0x58000300 },
3295 (PTR
) & fmt_mulo_ops
[0],
3298 /* xor $lit1, $src2, $dst */
3301 I960_INSN_XOR1
, "xor1", "xor",
3302 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
3303 & fmt_mulo1
, { 0x58000b00 },
3304 (PTR
) & fmt_mulo1_ops
[0],
3307 /* xor $src1, $lit2, $dst */
3310 I960_INSN_XOR2
, "xor2", "xor",
3311 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
3312 & fmt_mulo2
, { 0x58001300 },
3313 (PTR
) & fmt_mulo2_ops
[0],
3316 /* xor $lit1, $lit2, $dst */
3319 I960_INSN_XOR3
, "xor3", "xor",
3320 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
3321 & fmt_mulo3
, { 0x58001b00 },
3322 (PTR
) & fmt_mulo3_ops
[0],
3325 /* or $src1, $src2, $dst */
3328 I960_INSN_OR
, "or", "or",
3329 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
3330 & fmt_mulo
, { 0x58000380 },
3331 (PTR
) & fmt_mulo_ops
[0],
3334 /* or $lit1, $src2, $dst */
3337 I960_INSN_OR1
, "or1", "or",
3338 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
3339 & fmt_mulo1
, { 0x58000b80 },
3340 (PTR
) & fmt_mulo1_ops
[0],
3343 /* or $src1, $lit2, $dst */
3346 I960_INSN_OR2
, "or2", "or",
3347 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
3348 & fmt_mulo2
, { 0x58001380 },
3349 (PTR
) & fmt_mulo2_ops
[0],
3352 /* or $lit1, $lit2, $dst */
3355 I960_INSN_OR3
, "or3", "or",
3356 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
3357 & fmt_mulo3
, { 0x58001b80 },
3358 (PTR
) & fmt_mulo3_ops
[0],
3361 /* nor $src1, $src2, $dst */
3364 I960_INSN_NOR
, "nor", "nor",
3365 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
3366 & fmt_remo
, { 0x58000400 },
3367 (PTR
) & fmt_remo_ops
[0],
3370 /* nor $lit1, $src2, $dst */
3373 I960_INSN_NOR1
, "nor1", "nor",
3374 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
3375 & fmt_remo1
, { 0x58000c00 },
3376 (PTR
) & fmt_remo1_ops
[0],
3379 /* nor $src1, $lit2, $dst */
3382 I960_INSN_NOR2
, "nor2", "nor",
3383 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
3384 & fmt_remo2
, { 0x58001400 },
3385 (PTR
) & fmt_remo2_ops
[0],
3388 /* nor $lit1, $lit2, $dst */
3391 I960_INSN_NOR3
, "nor3", "nor",
3392 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
3393 & fmt_remo3
, { 0x58001c00 },
3394 (PTR
) & fmt_remo3_ops
[0],
3397 /* not $src1, $src2, $dst */
3400 I960_INSN_NOT
, "not", "not",
3401 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
3402 & fmt_not
, { 0x58000500 },
3403 (PTR
) & fmt_not_ops
[0],
3406 /* not $lit1, $src2, $dst */
3409 I960_INSN_NOT1
, "not1", "not",
3410 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
3411 & fmt_not1
, { 0x58000d00 },
3412 (PTR
) & fmt_not1_ops
[0],
3415 /* not $src1, $lit2, $dst */
3418 I960_INSN_NOT2
, "not2", "not",
3419 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
3420 & fmt_not2
, { 0x58001500 },
3421 (PTR
) & fmt_not2_ops
[0],
3424 /* not $lit1, $lit2, $dst */
3427 I960_INSN_NOT3
, "not3", "not",
3428 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
3429 & fmt_not3
, { 0x58001d00 },
3430 (PTR
) & fmt_not3_ops
[0],
3433 /* clrbit $src1, $src2, $dst */
3436 I960_INSN_CLRBIT
, "clrbit", "clrbit",
3437 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
3438 & fmt_mulo
, { 0x58000600 },
3439 (PTR
) & fmt_mulo_ops
[0],
3442 /* clrbit $lit1, $src2, $dst */
3445 I960_INSN_CLRBIT1
, "clrbit1", "clrbit",
3446 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
3447 & fmt_mulo1
, { 0x58000e00 },
3448 (PTR
) & fmt_mulo1_ops
[0],
3451 /* clrbit $src1, $lit2, $dst */
3454 I960_INSN_CLRBIT2
, "clrbit2", "clrbit",
3455 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
3456 & fmt_mulo2
, { 0x58001600 },
3457 (PTR
) & fmt_mulo2_ops
[0],
3460 /* clrbit $lit1, $lit2, $dst */
3463 I960_INSN_CLRBIT3
, "clrbit3", "clrbit",
3464 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
3465 & fmt_mulo3
, { 0x58001e00 },
3466 (PTR
) & fmt_mulo3_ops
[0],
3469 /* shlo $src1, $src2, $dst */
3472 I960_INSN_SHLO
, "shlo", "shlo",
3473 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
3474 & fmt_remo
, { 0x59000600 },
3475 (PTR
) & fmt_remo_ops
[0],
3478 /* shlo $lit1, $src2, $dst */
3481 I960_INSN_SHLO1
, "shlo1", "shlo",
3482 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
3483 & fmt_remo1
, { 0x59000e00 },
3484 (PTR
) & fmt_remo1_ops
[0],
3487 /* shlo $src1, $lit2, $dst */
3490 I960_INSN_SHLO2
, "shlo2", "shlo",
3491 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
3492 & fmt_remo2
, { 0x59001600 },
3493 (PTR
) & fmt_remo2_ops
[0],
3496 /* shlo $lit1, $lit2, $dst */
3499 I960_INSN_SHLO3
, "shlo3", "shlo",
3500 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
3501 & fmt_remo3
, { 0x59001e00 },
3502 (PTR
) & fmt_remo3_ops
[0],
3505 /* shro $src1, $src2, $dst */
3508 I960_INSN_SHRO
, "shro", "shro",
3509 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
3510 & fmt_remo
, { 0x59000400 },
3511 (PTR
) & fmt_remo_ops
[0],
3514 /* shro $lit1, $src2, $dst */
3517 I960_INSN_SHRO1
, "shro1", "shro",
3518 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
3519 & fmt_remo1
, { 0x59000c00 },
3520 (PTR
) & fmt_remo1_ops
[0],
3523 /* shro $src1, $lit2, $dst */
3526 I960_INSN_SHRO2
, "shro2", "shro",
3527 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
3528 & fmt_remo2
, { 0x59001400 },
3529 (PTR
) & fmt_remo2_ops
[0],
3532 /* shro $lit1, $lit2, $dst */
3535 I960_INSN_SHRO3
, "shro3", "shro",
3536 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
3537 & fmt_remo3
, { 0x59001c00 },
3538 (PTR
) & fmt_remo3_ops
[0],
3541 /* shli $src1, $src2, $dst */
3544 I960_INSN_SHLI
, "shli", "shli",
3545 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
3546 & fmt_remo
, { 0x59000700 },
3547 (PTR
) & fmt_remo_ops
[0],
3550 /* shli $lit1, $src2, $dst */
3553 I960_INSN_SHLI1
, "shli1", "shli",
3554 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
3555 & fmt_remo1
, { 0x59000f00 },
3556 (PTR
) & fmt_remo1_ops
[0],
3559 /* shli $src1, $lit2, $dst */
3562 I960_INSN_SHLI2
, "shli2", "shli",
3563 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
3564 & fmt_remo2
, { 0x59001700 },
3565 (PTR
) & fmt_remo2_ops
[0],
3568 /* shli $lit1, $lit2, $dst */
3571 I960_INSN_SHLI3
, "shli3", "shli",
3572 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
3573 & fmt_remo3
, { 0x59001f00 },
3574 (PTR
) & fmt_remo3_ops
[0],
3577 /* shri $src1, $src2, $dst */
3580 I960_INSN_SHRI
, "shri", "shri",
3581 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
3582 & fmt_remo
, { 0x59000580 },
3583 (PTR
) & fmt_remo_ops
[0],
3586 /* shri $lit1, $src2, $dst */
3589 I960_INSN_SHRI1
, "shri1", "shri",
3590 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
3591 & fmt_remo1
, { 0x59000d80 },
3592 (PTR
) & fmt_remo1_ops
[0],
3595 /* shri $src1, $lit2, $dst */
3598 I960_INSN_SHRI2
, "shri2", "shri",
3599 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
3600 & fmt_remo2
, { 0x59001580 },
3601 (PTR
) & fmt_remo2_ops
[0],
3604 /* shri $lit1, $lit2, $dst */
3607 I960_INSN_SHRI3
, "shri3", "shri",
3608 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
3609 & fmt_remo3
, { 0x59001d80 },
3610 (PTR
) & fmt_remo3_ops
[0],
3613 /* emul $src1, $src2, $dst */
3616 I960_INSN_EMUL
, "emul", "emul",
3617 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
3618 & fmt_emul
, { 0x67000000 },
3619 (PTR
) & fmt_emul_ops
[0],
3622 /* emul $lit1, $src2, $dst */
3625 I960_INSN_EMUL1
, "emul1", "emul",
3626 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
3627 & fmt_emul1
, { 0x67000800 },
3628 (PTR
) & fmt_emul1_ops
[0],
3631 /* emul $src1, $lit2, $dst */
3634 I960_INSN_EMUL2
, "emul2", "emul",
3635 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
3636 & fmt_emul2
, { 0x67001000 },
3637 (PTR
) & fmt_emul2_ops
[0],
3640 /* emul $lit1, $lit2, $dst */
3643 I960_INSN_EMUL3
, "emul3", "emul",
3644 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), ',', ' ', OP (DST
), 0 } },
3645 & fmt_emul3
, { 0x67001800 },
3646 (PTR
) & fmt_emul3_ops
[0],
3649 /* mov $src1, $dst */
3652 I960_INSN_MOV
, "mov", "mov",
3653 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (DST
), 0 } },
3654 & fmt_not2
, { 0x5c001600 },
3655 (PTR
) & fmt_not2_ops
[0],
3658 /* mov $lit1, $dst */
3661 I960_INSN_MOV1
, "mov1", "mov",
3662 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (DST
), 0 } },
3663 & fmt_not3
, { 0x5c001e00 },
3664 (PTR
) & fmt_not3_ops
[0],
3667 /* movl $src1, $dst */
3670 I960_INSN_MOVL
, "movl", "movl",
3671 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (DST
), 0 } },
3672 & fmt_movl
, { 0x5d001600 },
3673 (PTR
) & fmt_movl_ops
[0],
3676 /* movl $lit1, $dst */
3679 I960_INSN_MOVL1
, "movl1", "movl",
3680 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (DST
), 0 } },
3681 & fmt_movl1
, { 0x5d001e00 },
3682 (PTR
) & fmt_movl1_ops
[0],
3685 /* movt $src1, $dst */
3688 I960_INSN_MOVT
, "movt", "movt",
3689 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (DST
), 0 } },
3690 & fmt_movt
, { 0x5e001600 },
3691 (PTR
) & fmt_movt_ops
[0],
3694 /* movt $lit1, $dst */
3697 I960_INSN_MOVT1
, "movt1", "movt",
3698 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (DST
), 0 } },
3699 & fmt_movt1
, { 0x5e001e00 },
3700 (PTR
) & fmt_movt1_ops
[0],
3703 /* movq $src1, $dst */
3706 I960_INSN_MOVQ
, "movq", "movq",
3707 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (DST
), 0 } },
3708 & fmt_movq
, { 0x5f001600 },
3709 (PTR
) & fmt_movq_ops
[0],
3712 /* movq $lit1, $dst */
3715 I960_INSN_MOVQ1
, "movq1", "movq",
3716 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (DST
), 0 } },
3717 & fmt_movq1
, { 0x5f001e00 },
3718 (PTR
) & fmt_movq1_ops
[0],
3721 /* modpc $src1, $src2, $dst */
3724 I960_INSN_MODPC
, "modpc", "modpc",
3725 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
3726 & fmt_modpc
, { 0x65000280 },
3727 (PTR
) & fmt_modpc_ops
[0],
3730 /* modac $src1, $src2, $dst */
3733 I960_INSN_MODAC
, "modac", "modac",
3734 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), ',', ' ', OP (DST
), 0 } },
3735 & fmt_modpc
, { 0x64000280 },
3736 (PTR
) & fmt_modpc_ops
[0],
3739 /* lda $offset, $dst */
3742 I960_INSN_LDA_OFFSET
, "lda-offset", "lda",
3743 { { MNEM
, ' ', OP (OFFSET
), ',', ' ', OP (DST
), 0 } },
3744 & fmt_lda_offset
, { 0x8c000000 },
3745 (PTR
) & fmt_lda_offset_ops
[0],
3748 /* lda $offset($abase), $dst */
3751 I960_INSN_LDA_INDIRECT_OFFSET
, "lda-indirect-offset", "lda",
3752 { { MNEM
, ' ', OP (OFFSET
), '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
3753 & fmt_lda_indirect_offset
, { 0x8c002000 },
3754 (PTR
) & fmt_lda_indirect_offset_ops
[0],
3757 /* lda ($abase), $dst */
3760 I960_INSN_LDA_INDIRECT
, "lda-indirect", "lda",
3761 { { MNEM
, ' ', '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
3762 & fmt_lda_indirect
, { 0x8c001000 },
3763 (PTR
) & fmt_lda_indirect_ops
[0],
3766 /* lda ($abase)[$index*S$scale], $dst */
3769 I960_INSN_LDA_INDIRECT_INDEX
, "lda-indirect-index", "lda",
3770 { { MNEM
, ' ', '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
3771 & fmt_lda_indirect_index
, { 0x8c001c00 },
3772 (PTR
) & fmt_lda_indirect_index_ops
[0],
3775 /* lda $optdisp, $dst */
3778 I960_INSN_LDA_DISP
, "lda-disp", "lda",
3779 { { MNEM
, ' ', OP (OPTDISP
), ',', ' ', OP (DST
), 0 } },
3780 & fmt_lda_disp
, { 0x8c003000 },
3781 (PTR
) & fmt_lda_disp_ops
[0],
3784 /* lda $optdisp($abase), $dst */
3787 I960_INSN_LDA_INDIRECT_DISP
, "lda-indirect-disp", "lda",
3788 { { MNEM
, ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
3789 & fmt_lda_indirect_disp
, { 0x8c003400 },
3790 (PTR
) & fmt_lda_indirect_disp_ops
[0],
3793 /* lda $optdisp[$index*S$scale], $dst */
3796 I960_INSN_LDA_INDEX_DISP
, "lda-index-disp", "lda",
3797 { { MNEM
, ' ', OP (OPTDISP
), '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
3798 & fmt_lda_index_disp
, { 0x8c003800 },
3799 (PTR
) & fmt_lda_index_disp_ops
[0],
3802 /* lda $optdisp($abase)[$index*S$scale], $dst */
3805 I960_INSN_LDA_INDIRECT_INDEX_DISP
, "lda-indirect-index-disp", "lda",
3806 { { MNEM
, ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
3807 & fmt_lda_indirect_index_disp
, { 0x8c003c00 },
3808 (PTR
) & fmt_lda_indirect_index_disp_ops
[0],
3811 /* ld $offset, $dst */
3814 I960_INSN_LD_OFFSET
, "ld-offset", "ld",
3815 { { MNEM
, ' ', OP (OFFSET
), ',', ' ', OP (DST
), 0 } },
3816 & fmt_ld_offset
, { 0x90000000 },
3817 (PTR
) & fmt_ld_offset_ops
[0],
3820 /* ld $offset($abase), $dst */
3823 I960_INSN_LD_INDIRECT_OFFSET
, "ld-indirect-offset", "ld",
3824 { { MNEM
, ' ', OP (OFFSET
), '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
3825 & fmt_ld_indirect_offset
, { 0x90002000 },
3826 (PTR
) & fmt_ld_indirect_offset_ops
[0],
3829 /* ld ($abase), $dst */
3832 I960_INSN_LD_INDIRECT
, "ld-indirect", "ld",
3833 { { MNEM
, ' ', '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
3834 & fmt_ld_indirect
, { 0x90001000 },
3835 (PTR
) & fmt_ld_indirect_ops
[0],
3838 /* ld ($abase)[$index*S$scale], $dst */
3841 I960_INSN_LD_INDIRECT_INDEX
, "ld-indirect-index", "ld",
3842 { { MNEM
, ' ', '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
3843 & fmt_ld_indirect_index
, { 0x90001c00 },
3844 (PTR
) & fmt_ld_indirect_index_ops
[0],
3847 /* ld $optdisp, $dst */
3850 I960_INSN_LD_DISP
, "ld-disp", "ld",
3851 { { MNEM
, ' ', OP (OPTDISP
), ',', ' ', OP (DST
), 0 } },
3852 & fmt_ld_disp
, { 0x90003000 },
3853 (PTR
) & fmt_ld_disp_ops
[0],
3856 /* ld $optdisp($abase), $dst */
3859 I960_INSN_LD_INDIRECT_DISP
, "ld-indirect-disp", "ld",
3860 { { MNEM
, ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
3861 & fmt_ld_indirect_disp
, { 0x90003400 },
3862 (PTR
) & fmt_ld_indirect_disp_ops
[0],
3865 /* ld $optdisp[$index*S$scale], $dst */
3868 I960_INSN_LD_INDEX_DISP
, "ld-index-disp", "ld",
3869 { { MNEM
, ' ', OP (OPTDISP
), '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
3870 & fmt_ld_index_disp
, { 0x90003800 },
3871 (PTR
) & fmt_ld_index_disp_ops
[0],
3874 /* ld $optdisp($abase)[$index*S$scale], $dst */
3877 I960_INSN_LD_INDIRECT_INDEX_DISP
, "ld-indirect-index-disp", "ld",
3878 { { MNEM
, ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
3879 & fmt_ld_indirect_index_disp
, { 0x90003c00 },
3880 (PTR
) & fmt_ld_indirect_index_disp_ops
[0],
3883 /* ldob $offset, $dst */
3886 I960_INSN_LDOB_OFFSET
, "ldob-offset", "ldob",
3887 { { MNEM
, ' ', OP (OFFSET
), ',', ' ', OP (DST
), 0 } },
3888 & fmt_ldob_offset
, { 0x80000000 },
3889 (PTR
) & fmt_ldob_offset_ops
[0],
3892 /* ldob $offset($abase), $dst */
3895 I960_INSN_LDOB_INDIRECT_OFFSET
, "ldob-indirect-offset", "ldob",
3896 { { MNEM
, ' ', OP (OFFSET
), '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
3897 & fmt_ldob_indirect_offset
, { 0x80002000 },
3898 (PTR
) & fmt_ldob_indirect_offset_ops
[0],
3901 /* ldob ($abase), $dst */
3904 I960_INSN_LDOB_INDIRECT
, "ldob-indirect", "ldob",
3905 { { MNEM
, ' ', '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
3906 & fmt_ldob_indirect
, { 0x80001000 },
3907 (PTR
) & fmt_ldob_indirect_ops
[0],
3910 /* ldob ($abase)[$index*S$scale], $dst */
3913 I960_INSN_LDOB_INDIRECT_INDEX
, "ldob-indirect-index", "ldob",
3914 { { MNEM
, ' ', '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
3915 & fmt_ldob_indirect_index
, { 0x80001c00 },
3916 (PTR
) & fmt_ldob_indirect_index_ops
[0],
3919 /* ldob $optdisp, $dst */
3922 I960_INSN_LDOB_DISP
, "ldob-disp", "ldob",
3923 { { MNEM
, ' ', OP (OPTDISP
), ',', ' ', OP (DST
), 0 } },
3924 & fmt_ldob_disp
, { 0x80003000 },
3925 (PTR
) & fmt_ldob_disp_ops
[0],
3928 /* ldob $optdisp($abase), $dst */
3931 I960_INSN_LDOB_INDIRECT_DISP
, "ldob-indirect-disp", "ldob",
3932 { { MNEM
, ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
3933 & fmt_ldob_indirect_disp
, { 0x80003400 },
3934 (PTR
) & fmt_ldob_indirect_disp_ops
[0],
3937 /* ldob $optdisp[$index*S$scale], $dst */
3940 I960_INSN_LDOB_INDEX_DISP
, "ldob-index-disp", "ldob",
3941 { { MNEM
, ' ', OP (OPTDISP
), '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
3942 & fmt_ldob_index_disp
, { 0x80003800 },
3943 (PTR
) & fmt_ldob_index_disp_ops
[0],
3946 /* ldob $optdisp($abase)[$index*S$scale], $dst */
3949 I960_INSN_LDOB_INDIRECT_INDEX_DISP
, "ldob-indirect-index-disp", "ldob",
3950 { { MNEM
, ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
3951 & fmt_ldob_indirect_index_disp
, { 0x80003c00 },
3952 (PTR
) & fmt_ldob_indirect_index_disp_ops
[0],
3955 /* ldos $offset, $dst */
3958 I960_INSN_LDOS_OFFSET
, "ldos-offset", "ldos",
3959 { { MNEM
, ' ', OP (OFFSET
), ',', ' ', OP (DST
), 0 } },
3960 & fmt_ldos_offset
, { 0x88000000 },
3961 (PTR
) & fmt_ldos_offset_ops
[0],
3964 /* ldos $offset($abase), $dst */
3967 I960_INSN_LDOS_INDIRECT_OFFSET
, "ldos-indirect-offset", "ldos",
3968 { { MNEM
, ' ', OP (OFFSET
), '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
3969 & fmt_ldos_indirect_offset
, { 0x88002000 },
3970 (PTR
) & fmt_ldos_indirect_offset_ops
[0],
3973 /* ldos ($abase), $dst */
3976 I960_INSN_LDOS_INDIRECT
, "ldos-indirect", "ldos",
3977 { { MNEM
, ' ', '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
3978 & fmt_ldos_indirect
, { 0x88001000 },
3979 (PTR
) & fmt_ldos_indirect_ops
[0],
3982 /* ldos ($abase)[$index*S$scale], $dst */
3985 I960_INSN_LDOS_INDIRECT_INDEX
, "ldos-indirect-index", "ldos",
3986 { { MNEM
, ' ', '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
3987 & fmt_ldos_indirect_index
, { 0x88001c00 },
3988 (PTR
) & fmt_ldos_indirect_index_ops
[0],
3991 /* ldos $optdisp, $dst */
3994 I960_INSN_LDOS_DISP
, "ldos-disp", "ldos",
3995 { { MNEM
, ' ', OP (OPTDISP
), ',', ' ', OP (DST
), 0 } },
3996 & fmt_ldos_disp
, { 0x88003000 },
3997 (PTR
) & fmt_ldos_disp_ops
[0],
4000 /* ldos $optdisp($abase), $dst */
4003 I960_INSN_LDOS_INDIRECT_DISP
, "ldos-indirect-disp", "ldos",
4004 { { MNEM
, ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
4005 & fmt_ldos_indirect_disp
, { 0x88003400 },
4006 (PTR
) & fmt_ldos_indirect_disp_ops
[0],
4009 /* ldos $optdisp[$index*S$scale], $dst */
4012 I960_INSN_LDOS_INDEX_DISP
, "ldos-index-disp", "ldos",
4013 { { MNEM
, ' ', OP (OPTDISP
), '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
4014 & fmt_ldos_index_disp
, { 0x88003800 },
4015 (PTR
) & fmt_ldos_index_disp_ops
[0],
4018 /* ldos $optdisp($abase)[$index*S$scale], $dst */
4021 I960_INSN_LDOS_INDIRECT_INDEX_DISP
, "ldos-indirect-index-disp", "ldos",
4022 { { MNEM
, ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
4023 & fmt_ldos_indirect_index_disp
, { 0x88003c00 },
4024 (PTR
) & fmt_ldos_indirect_index_disp_ops
[0],
4027 /* ldib $offset, $dst */
4030 I960_INSN_LDIB_OFFSET
, "ldib-offset", "ldib",
4031 { { MNEM
, ' ', OP (OFFSET
), ',', ' ', OP (DST
), 0 } },
4032 & fmt_ldib_offset
, { 0xc0000000 },
4033 (PTR
) & fmt_ldib_offset_ops
[0],
4036 /* ldib $offset($abase), $dst */
4039 I960_INSN_LDIB_INDIRECT_OFFSET
, "ldib-indirect-offset", "ldib",
4040 { { MNEM
, ' ', OP (OFFSET
), '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
4041 & fmt_ldib_indirect_offset
, { 0xc0002000 },
4042 (PTR
) & fmt_ldib_indirect_offset_ops
[0],
4045 /* ldib ($abase), $dst */
4048 I960_INSN_LDIB_INDIRECT
, "ldib-indirect", "ldib",
4049 { { MNEM
, ' ', '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
4050 & fmt_ldib_indirect
, { 0xc0001000 },
4051 (PTR
) & fmt_ldib_indirect_ops
[0],
4054 /* ldib ($abase)[$index*S$scale], $dst */
4057 I960_INSN_LDIB_INDIRECT_INDEX
, "ldib-indirect-index", "ldib",
4058 { { MNEM
, ' ', '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
4059 & fmt_ldib_indirect_index
, { 0xc0001c00 },
4060 (PTR
) & fmt_ldib_indirect_index_ops
[0],
4063 /* ldib $optdisp, $dst */
4066 I960_INSN_LDIB_DISP
, "ldib-disp", "ldib",
4067 { { MNEM
, ' ', OP (OPTDISP
), ',', ' ', OP (DST
), 0 } },
4068 & fmt_ldib_disp
, { 0xc0003000 },
4069 (PTR
) & fmt_ldib_disp_ops
[0],
4072 /* ldib $optdisp($abase), $dst */
4075 I960_INSN_LDIB_INDIRECT_DISP
, "ldib-indirect-disp", "ldib",
4076 { { MNEM
, ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
4077 & fmt_ldib_indirect_disp
, { 0xc0003400 },
4078 (PTR
) & fmt_ldib_indirect_disp_ops
[0],
4081 /* ldib $optdisp[$index*S$scale], $dst */
4084 I960_INSN_LDIB_INDEX_DISP
, "ldib-index-disp", "ldib",
4085 { { MNEM
, ' ', OP (OPTDISP
), '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
4086 & fmt_ldib_index_disp
, { 0xc0003800 },
4087 (PTR
) & fmt_ldib_index_disp_ops
[0],
4090 /* ldib $optdisp($abase)[$index*S$scale], $dst */
4093 I960_INSN_LDIB_INDIRECT_INDEX_DISP
, "ldib-indirect-index-disp", "ldib",
4094 { { MNEM
, ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
4095 & fmt_ldib_indirect_index_disp
, { 0xc0003c00 },
4096 (PTR
) & fmt_ldib_indirect_index_disp_ops
[0],
4099 /* ldis $offset, $dst */
4102 I960_INSN_LDIS_OFFSET
, "ldis-offset", "ldis",
4103 { { MNEM
, ' ', OP (OFFSET
), ',', ' ', OP (DST
), 0 } },
4104 & fmt_ldis_offset
, { 0xc8000000 },
4105 (PTR
) & fmt_ldis_offset_ops
[0],
4108 /* ldis $offset($abase), $dst */
4111 I960_INSN_LDIS_INDIRECT_OFFSET
, "ldis-indirect-offset", "ldis",
4112 { { MNEM
, ' ', OP (OFFSET
), '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
4113 & fmt_ldis_indirect_offset
, { 0xc8002000 },
4114 (PTR
) & fmt_ldis_indirect_offset_ops
[0],
4117 /* ldis ($abase), $dst */
4120 I960_INSN_LDIS_INDIRECT
, "ldis-indirect", "ldis",
4121 { { MNEM
, ' ', '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
4122 & fmt_ldis_indirect
, { 0xc8001000 },
4123 (PTR
) & fmt_ldis_indirect_ops
[0],
4126 /* ldis ($abase)[$index*S$scale], $dst */
4129 I960_INSN_LDIS_INDIRECT_INDEX
, "ldis-indirect-index", "ldis",
4130 { { MNEM
, ' ', '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
4131 & fmt_ldis_indirect_index
, { 0xc8001c00 },
4132 (PTR
) & fmt_ldis_indirect_index_ops
[0],
4135 /* ldis $optdisp, $dst */
4138 I960_INSN_LDIS_DISP
, "ldis-disp", "ldis",
4139 { { MNEM
, ' ', OP (OPTDISP
), ',', ' ', OP (DST
), 0 } },
4140 & fmt_ldis_disp
, { 0xc8003000 },
4141 (PTR
) & fmt_ldis_disp_ops
[0],
4144 /* ldis $optdisp($abase), $dst */
4147 I960_INSN_LDIS_INDIRECT_DISP
, "ldis-indirect-disp", "ldis",
4148 { { MNEM
, ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
4149 & fmt_ldis_indirect_disp
, { 0xc8003400 },
4150 (PTR
) & fmt_ldis_indirect_disp_ops
[0],
4153 /* ldis $optdisp[$index*S$scale], $dst */
4156 I960_INSN_LDIS_INDEX_DISP
, "ldis-index-disp", "ldis",
4157 { { MNEM
, ' ', OP (OPTDISP
), '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
4158 & fmt_ldis_index_disp
, { 0xc8003800 },
4159 (PTR
) & fmt_ldis_index_disp_ops
[0],
4162 /* ldis $optdisp($abase)[$index*S$scale], $dst */
4165 I960_INSN_LDIS_INDIRECT_INDEX_DISP
, "ldis-indirect-index-disp", "ldis",
4166 { { MNEM
, ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
4167 & fmt_ldis_indirect_index_disp
, { 0xc8003c00 },
4168 (PTR
) & fmt_ldis_indirect_index_disp_ops
[0],
4171 /* ldl $offset, $dst */
4174 I960_INSN_LDL_OFFSET
, "ldl-offset", "ldl",
4175 { { MNEM
, ' ', OP (OFFSET
), ',', ' ', OP (DST
), 0 } },
4176 & fmt_ldl_offset
, { 0x98000000 },
4177 (PTR
) & fmt_ldl_offset_ops
[0],
4180 /* ldl $offset($abase), $dst */
4183 I960_INSN_LDL_INDIRECT_OFFSET
, "ldl-indirect-offset", "ldl",
4184 { { MNEM
, ' ', OP (OFFSET
), '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
4185 & fmt_ldl_indirect_offset
, { 0x98002000 },
4186 (PTR
) & fmt_ldl_indirect_offset_ops
[0],
4189 /* ldl ($abase), $dst */
4192 I960_INSN_LDL_INDIRECT
, "ldl-indirect", "ldl",
4193 { { MNEM
, ' ', '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
4194 & fmt_ldl_indirect
, { 0x98001000 },
4195 (PTR
) & fmt_ldl_indirect_ops
[0],
4198 /* ldl ($abase)[$index*S$scale], $dst */
4201 I960_INSN_LDL_INDIRECT_INDEX
, "ldl-indirect-index", "ldl",
4202 { { MNEM
, ' ', '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
4203 & fmt_ldl_indirect_index
, { 0x98001c00 },
4204 (PTR
) & fmt_ldl_indirect_index_ops
[0],
4207 /* ldl $optdisp, $dst */
4210 I960_INSN_LDL_DISP
, "ldl-disp", "ldl",
4211 { { MNEM
, ' ', OP (OPTDISP
), ',', ' ', OP (DST
), 0 } },
4212 & fmt_ldl_disp
, { 0x98003000 },
4213 (PTR
) & fmt_ldl_disp_ops
[0],
4216 /* ldl $optdisp($abase), $dst */
4219 I960_INSN_LDL_INDIRECT_DISP
, "ldl-indirect-disp", "ldl",
4220 { { MNEM
, ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
4221 & fmt_ldl_indirect_disp
, { 0x98003400 },
4222 (PTR
) & fmt_ldl_indirect_disp_ops
[0],
4225 /* ldl $optdisp[$index*S$scale], $dst */
4228 I960_INSN_LDL_INDEX_DISP
, "ldl-index-disp", "ldl",
4229 { { MNEM
, ' ', OP (OPTDISP
), '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
4230 & fmt_ldl_index_disp
, { 0x98003800 },
4231 (PTR
) & fmt_ldl_index_disp_ops
[0],
4234 /* ldl $optdisp($abase)[$index*S$scale], $dst */
4237 I960_INSN_LDL_INDIRECT_INDEX_DISP
, "ldl-indirect-index-disp", "ldl",
4238 { { MNEM
, ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
4239 & fmt_ldl_indirect_index_disp
, { 0x98003c00 },
4240 (PTR
) & fmt_ldl_indirect_index_disp_ops
[0],
4243 /* ldt $offset, $dst */
4246 I960_INSN_LDT_OFFSET
, "ldt-offset", "ldt",
4247 { { MNEM
, ' ', OP (OFFSET
), ',', ' ', OP (DST
), 0 } },
4248 & fmt_ldt_offset
, { 0xa0000000 },
4249 (PTR
) & fmt_ldt_offset_ops
[0],
4252 /* ldt $offset($abase), $dst */
4255 I960_INSN_LDT_INDIRECT_OFFSET
, "ldt-indirect-offset", "ldt",
4256 { { MNEM
, ' ', OP (OFFSET
), '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
4257 & fmt_ldt_indirect_offset
, { 0xa0002000 },
4258 (PTR
) & fmt_ldt_indirect_offset_ops
[0],
4261 /* ldt ($abase), $dst */
4264 I960_INSN_LDT_INDIRECT
, "ldt-indirect", "ldt",
4265 { { MNEM
, ' ', '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
4266 & fmt_ldt_indirect
, { 0xa0001000 },
4267 (PTR
) & fmt_ldt_indirect_ops
[0],
4270 /* ldt ($abase)[$index*S$scale], $dst */
4273 I960_INSN_LDT_INDIRECT_INDEX
, "ldt-indirect-index", "ldt",
4274 { { MNEM
, ' ', '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
4275 & fmt_ldt_indirect_index
, { 0xa0001c00 },
4276 (PTR
) & fmt_ldt_indirect_index_ops
[0],
4279 /* ldt $optdisp, $dst */
4282 I960_INSN_LDT_DISP
, "ldt-disp", "ldt",
4283 { { MNEM
, ' ', OP (OPTDISP
), ',', ' ', OP (DST
), 0 } },
4284 & fmt_ldt_disp
, { 0xa0003000 },
4285 (PTR
) & fmt_ldt_disp_ops
[0],
4288 /* ldt $optdisp($abase), $dst */
4291 I960_INSN_LDT_INDIRECT_DISP
, "ldt-indirect-disp", "ldt",
4292 { { MNEM
, ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
4293 & fmt_ldt_indirect_disp
, { 0xa0003400 },
4294 (PTR
) & fmt_ldt_indirect_disp_ops
[0],
4297 /* ldt $optdisp[$index*S$scale], $dst */
4300 I960_INSN_LDT_INDEX_DISP
, "ldt-index-disp", "ldt",
4301 { { MNEM
, ' ', OP (OPTDISP
), '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
4302 & fmt_ldt_index_disp
, { 0xa0003800 },
4303 (PTR
) & fmt_ldt_index_disp_ops
[0],
4306 /* ldt $optdisp($abase)[$index*S$scale], $dst */
4309 I960_INSN_LDT_INDIRECT_INDEX_DISP
, "ldt-indirect-index-disp", "ldt",
4310 { { MNEM
, ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
4311 & fmt_ldt_indirect_index_disp
, { 0xa0003c00 },
4312 (PTR
) & fmt_ldt_indirect_index_disp_ops
[0],
4315 /* ldq $offset, $dst */
4318 I960_INSN_LDQ_OFFSET
, "ldq-offset", "ldq",
4319 { { MNEM
, ' ', OP (OFFSET
), ',', ' ', OP (DST
), 0 } },
4320 & fmt_ldq_offset
, { 0xb0000000 },
4321 (PTR
) & fmt_ldq_offset_ops
[0],
4324 /* ldq $offset($abase), $dst */
4327 I960_INSN_LDQ_INDIRECT_OFFSET
, "ldq-indirect-offset", "ldq",
4328 { { MNEM
, ' ', OP (OFFSET
), '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
4329 & fmt_ldq_indirect_offset
, { 0xb0002000 },
4330 (PTR
) & fmt_ldq_indirect_offset_ops
[0],
4333 /* ldq ($abase), $dst */
4336 I960_INSN_LDQ_INDIRECT
, "ldq-indirect", "ldq",
4337 { { MNEM
, ' ', '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
4338 & fmt_ldq_indirect
, { 0xb0001000 },
4339 (PTR
) & fmt_ldq_indirect_ops
[0],
4342 /* ldq ($abase)[$index*S$scale], $dst */
4345 I960_INSN_LDQ_INDIRECT_INDEX
, "ldq-indirect-index", "ldq",
4346 { { MNEM
, ' ', '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
4347 & fmt_ldq_indirect_index
, { 0xb0001c00 },
4348 (PTR
) & fmt_ldq_indirect_index_ops
[0],
4351 /* ldq $optdisp, $dst */
4354 I960_INSN_LDQ_DISP
, "ldq-disp", "ldq",
4355 { { MNEM
, ' ', OP (OPTDISP
), ',', ' ', OP (DST
), 0 } },
4356 & fmt_ldq_disp
, { 0xb0003000 },
4357 (PTR
) & fmt_ldq_disp_ops
[0],
4360 /* ldq $optdisp($abase), $dst */
4363 I960_INSN_LDQ_INDIRECT_DISP
, "ldq-indirect-disp", "ldq",
4364 { { MNEM
, ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', ',', ' ', OP (DST
), 0 } },
4365 & fmt_ldq_indirect_disp
, { 0xb0003400 },
4366 (PTR
) & fmt_ldq_indirect_disp_ops
[0],
4369 /* ldq $optdisp[$index*S$scale], $dst */
4372 I960_INSN_LDQ_INDEX_DISP
, "ldq-index-disp", "ldq",
4373 { { MNEM
, ' ', OP (OPTDISP
), '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
4374 & fmt_ldq_index_disp
, { 0xb0003800 },
4375 (PTR
) & fmt_ldq_index_disp_ops
[0],
4378 /* ldq $optdisp($abase)[$index*S$scale], $dst */
4381 I960_INSN_LDQ_INDIRECT_INDEX_DISP
, "ldq-indirect-index-disp", "ldq",
4382 { { MNEM
, ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', ',', ' ', OP (DST
), 0 } },
4383 & fmt_ldq_indirect_index_disp
, { 0xb0003c00 },
4384 (PTR
) & fmt_ldq_indirect_index_disp_ops
[0],
4387 /* st $st_src, $offset */
4390 I960_INSN_ST_OFFSET
, "st-offset", "st",
4391 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OFFSET
), 0 } },
4392 & fmt_st_offset
, { 0x92000000 },
4393 (PTR
) & fmt_st_offset_ops
[0],
4396 /* st $st_src, $offset($abase) */
4399 I960_INSN_ST_INDIRECT_OFFSET
, "st-indirect-offset", "st",
4400 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OFFSET
), '(', OP (ABASE
), ')', 0 } },
4401 & fmt_st_indirect_offset
, { 0x92002000 },
4402 (PTR
) & fmt_st_indirect_offset_ops
[0],
4405 /* st $st_src, ($abase) */
4408 I960_INSN_ST_INDIRECT
, "st-indirect", "st",
4409 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', '(', OP (ABASE
), ')', 0 } },
4410 & fmt_st_indirect
, { 0x92001000 },
4411 (PTR
) & fmt_st_indirect_ops
[0],
4414 /* st $st_src, ($abase)[$index*S$scale] */
4417 I960_INSN_ST_INDIRECT_INDEX
, "st-indirect-index", "st",
4418 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', 0 } },
4419 & fmt_st_indirect_index
, { 0x92001c00 },
4420 (PTR
) & fmt_st_indirect_index_ops
[0],
4423 /* st $st_src, $optdisp */
4426 I960_INSN_ST_DISP
, "st-disp", "st",
4427 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), 0 } },
4428 & fmt_st_disp
, { 0x92003000 },
4429 (PTR
) & fmt_st_disp_ops
[0],
4432 /* st $st_src, $optdisp($abase) */
4435 I960_INSN_ST_INDIRECT_DISP
, "st-indirect-disp", "st",
4436 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', 0 } },
4437 & fmt_st_indirect_disp
, { 0x92003400 },
4438 (PTR
) & fmt_st_indirect_disp_ops
[0],
4441 /* st $st_src, $optdisp[$index*S$scale */
4444 I960_INSN_ST_INDEX_DISP
, "st-index-disp", "st",
4445 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), '[', OP (INDEX
), '*', 'S', OP (SCALE
), 0 } },
4446 & fmt_st_index_disp
, { 0x92003800 },
4447 (PTR
) & fmt_st_index_disp_ops
[0],
4450 /* st $st_src, $optdisp($abase)[$index*S$scale] */
4453 I960_INSN_ST_INDIRECT_INDEX_DISP
, "st-indirect-index-disp", "st",
4454 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', 0 } },
4455 & fmt_st_indirect_index_disp
, { 0x92003c00 },
4456 (PTR
) & fmt_st_indirect_index_disp_ops
[0],
4459 /* stob $st_src, $offset */
4462 I960_INSN_STOB_OFFSET
, "stob-offset", "stob",
4463 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OFFSET
), 0 } },
4464 & fmt_stob_offset
, { 0x82000000 },
4465 (PTR
) & fmt_stob_offset_ops
[0],
4468 /* stob $st_src, $offset($abase) */
4471 I960_INSN_STOB_INDIRECT_OFFSET
, "stob-indirect-offset", "stob",
4472 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OFFSET
), '(', OP (ABASE
), ')', 0 } },
4473 & fmt_stob_indirect_offset
, { 0x82002000 },
4474 (PTR
) & fmt_stob_indirect_offset_ops
[0],
4477 /* stob $st_src, ($abase) */
4480 I960_INSN_STOB_INDIRECT
, "stob-indirect", "stob",
4481 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', '(', OP (ABASE
), ')', 0 } },
4482 & fmt_stob_indirect
, { 0x82001000 },
4483 (PTR
) & fmt_stob_indirect_ops
[0],
4486 /* stob $st_src, ($abase)[$index*S$scale] */
4489 I960_INSN_STOB_INDIRECT_INDEX
, "stob-indirect-index", "stob",
4490 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', 0 } },
4491 & fmt_stob_indirect_index
, { 0x82001c00 },
4492 (PTR
) & fmt_stob_indirect_index_ops
[0],
4495 /* stob $st_src, $optdisp */
4498 I960_INSN_STOB_DISP
, "stob-disp", "stob",
4499 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), 0 } },
4500 & fmt_stob_disp
, { 0x82003000 },
4501 (PTR
) & fmt_stob_disp_ops
[0],
4504 /* stob $st_src, $optdisp($abase) */
4507 I960_INSN_STOB_INDIRECT_DISP
, "stob-indirect-disp", "stob",
4508 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', 0 } },
4509 & fmt_stob_indirect_disp
, { 0x82003400 },
4510 (PTR
) & fmt_stob_indirect_disp_ops
[0],
4513 /* stob $st_src, $optdisp[$index*S$scale */
4516 I960_INSN_STOB_INDEX_DISP
, "stob-index-disp", "stob",
4517 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), '[', OP (INDEX
), '*', 'S', OP (SCALE
), 0 } },
4518 & fmt_stob_index_disp
, { 0x82003800 },
4519 (PTR
) & fmt_stob_index_disp_ops
[0],
4522 /* stob $st_src, $optdisp($abase)[$index*S$scale] */
4525 I960_INSN_STOB_INDIRECT_INDEX_DISP
, "stob-indirect-index-disp", "stob",
4526 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', 0 } },
4527 & fmt_stob_indirect_index_disp
, { 0x82003c00 },
4528 (PTR
) & fmt_stob_indirect_index_disp_ops
[0],
4531 /* stos $st_src, $offset */
4534 I960_INSN_STOS_OFFSET
, "stos-offset", "stos",
4535 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OFFSET
), 0 } },
4536 & fmt_stos_offset
, { 0x8a000000 },
4537 (PTR
) & fmt_stos_offset_ops
[0],
4540 /* stos $st_src, $offset($abase) */
4543 I960_INSN_STOS_INDIRECT_OFFSET
, "stos-indirect-offset", "stos",
4544 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OFFSET
), '(', OP (ABASE
), ')', 0 } },
4545 & fmt_stos_indirect_offset
, { 0x8a002000 },
4546 (PTR
) & fmt_stos_indirect_offset_ops
[0],
4549 /* stos $st_src, ($abase) */
4552 I960_INSN_STOS_INDIRECT
, "stos-indirect", "stos",
4553 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', '(', OP (ABASE
), ')', 0 } },
4554 & fmt_stos_indirect
, { 0x8a001000 },
4555 (PTR
) & fmt_stos_indirect_ops
[0],
4558 /* stos $st_src, ($abase)[$index*S$scale] */
4561 I960_INSN_STOS_INDIRECT_INDEX
, "stos-indirect-index", "stos",
4562 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', 0 } },
4563 & fmt_stos_indirect_index
, { 0x8a001c00 },
4564 (PTR
) & fmt_stos_indirect_index_ops
[0],
4567 /* stos $st_src, $optdisp */
4570 I960_INSN_STOS_DISP
, "stos-disp", "stos",
4571 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), 0 } },
4572 & fmt_stos_disp
, { 0x8a003000 },
4573 (PTR
) & fmt_stos_disp_ops
[0],
4576 /* stos $st_src, $optdisp($abase) */
4579 I960_INSN_STOS_INDIRECT_DISP
, "stos-indirect-disp", "stos",
4580 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', 0 } },
4581 & fmt_stos_indirect_disp
, { 0x8a003400 },
4582 (PTR
) & fmt_stos_indirect_disp_ops
[0],
4585 /* stos $st_src, $optdisp[$index*S$scale */
4588 I960_INSN_STOS_INDEX_DISP
, "stos-index-disp", "stos",
4589 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), '[', OP (INDEX
), '*', 'S', OP (SCALE
), 0 } },
4590 & fmt_stos_index_disp
, { 0x8a003800 },
4591 (PTR
) & fmt_stos_index_disp_ops
[0],
4594 /* stos $st_src, $optdisp($abase)[$index*S$scale] */
4597 I960_INSN_STOS_INDIRECT_INDEX_DISP
, "stos-indirect-index-disp", "stos",
4598 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', 0 } },
4599 & fmt_stos_indirect_index_disp
, { 0x8a003c00 },
4600 (PTR
) & fmt_stos_indirect_index_disp_ops
[0],
4603 /* stl $st_src, $offset */
4606 I960_INSN_STL_OFFSET
, "stl-offset", "stl",
4607 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OFFSET
), 0 } },
4608 & fmt_stl_offset
, { 0x9a000000 },
4609 (PTR
) & fmt_stl_offset_ops
[0],
4612 /* stl $st_src, $offset($abase) */
4615 I960_INSN_STL_INDIRECT_OFFSET
, "stl-indirect-offset", "stl",
4616 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OFFSET
), '(', OP (ABASE
), ')', 0 } },
4617 & fmt_stl_indirect_offset
, { 0x9a002000 },
4618 (PTR
) & fmt_stl_indirect_offset_ops
[0],
4621 /* stl $st_src, ($abase) */
4624 I960_INSN_STL_INDIRECT
, "stl-indirect", "stl",
4625 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', '(', OP (ABASE
), ')', 0 } },
4626 & fmt_stl_indirect
, { 0x9a001000 },
4627 (PTR
) & fmt_stl_indirect_ops
[0],
4630 /* stl $st_src, ($abase)[$index*S$scale] */
4633 I960_INSN_STL_INDIRECT_INDEX
, "stl-indirect-index", "stl",
4634 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', 0 } },
4635 & fmt_stl_indirect_index
, { 0x9a001c00 },
4636 (PTR
) & fmt_stl_indirect_index_ops
[0],
4639 /* stl $st_src, $optdisp */
4642 I960_INSN_STL_DISP
, "stl-disp", "stl",
4643 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), 0 } },
4644 & fmt_stl_disp
, { 0x9a003000 },
4645 (PTR
) & fmt_stl_disp_ops
[0],
4648 /* stl $st_src, $optdisp($abase) */
4651 I960_INSN_STL_INDIRECT_DISP
, "stl-indirect-disp", "stl",
4652 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', 0 } },
4653 & fmt_stl_indirect_disp
, { 0x9a003400 },
4654 (PTR
) & fmt_stl_indirect_disp_ops
[0],
4657 /* stl $st_src, $optdisp[$index*S$scale */
4660 I960_INSN_STL_INDEX_DISP
, "stl-index-disp", "stl",
4661 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), '[', OP (INDEX
), '*', 'S', OP (SCALE
), 0 } },
4662 & fmt_stl_index_disp
, { 0x9a003800 },
4663 (PTR
) & fmt_stl_index_disp_ops
[0],
4666 /* stl $st_src, $optdisp($abase)[$index*S$scale] */
4669 I960_INSN_STL_INDIRECT_INDEX_DISP
, "stl-indirect-index-disp", "stl",
4670 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', 0 } },
4671 & fmt_stl_indirect_index_disp
, { 0x9a003c00 },
4672 (PTR
) & fmt_stl_indirect_index_disp_ops
[0],
4675 /* stt $st_src, $offset */
4678 I960_INSN_STT_OFFSET
, "stt-offset", "stt",
4679 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OFFSET
), 0 } },
4680 & fmt_stt_offset
, { 0xa2000000 },
4681 (PTR
) & fmt_stt_offset_ops
[0],
4684 /* stt $st_src, $offset($abase) */
4687 I960_INSN_STT_INDIRECT_OFFSET
, "stt-indirect-offset", "stt",
4688 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OFFSET
), '(', OP (ABASE
), ')', 0 } },
4689 & fmt_stt_indirect_offset
, { 0xa2002000 },
4690 (PTR
) & fmt_stt_indirect_offset_ops
[0],
4693 /* stt $st_src, ($abase) */
4696 I960_INSN_STT_INDIRECT
, "stt-indirect", "stt",
4697 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', '(', OP (ABASE
), ')', 0 } },
4698 & fmt_stt_indirect
, { 0xa2001000 },
4699 (PTR
) & fmt_stt_indirect_ops
[0],
4702 /* stt $st_src, ($abase)[$index*S$scale] */
4705 I960_INSN_STT_INDIRECT_INDEX
, "stt-indirect-index", "stt",
4706 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', 0 } },
4707 & fmt_stt_indirect_index
, { 0xa2001c00 },
4708 (PTR
) & fmt_stt_indirect_index_ops
[0],
4711 /* stt $st_src, $optdisp */
4714 I960_INSN_STT_DISP
, "stt-disp", "stt",
4715 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), 0 } },
4716 & fmt_stt_disp
, { 0xa2003000 },
4717 (PTR
) & fmt_stt_disp_ops
[0],
4720 /* stt $st_src, $optdisp($abase) */
4723 I960_INSN_STT_INDIRECT_DISP
, "stt-indirect-disp", "stt",
4724 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', 0 } },
4725 & fmt_stt_indirect_disp
, { 0xa2003400 },
4726 (PTR
) & fmt_stt_indirect_disp_ops
[0],
4729 /* stt $st_src, $optdisp[$index*S$scale */
4732 I960_INSN_STT_INDEX_DISP
, "stt-index-disp", "stt",
4733 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), '[', OP (INDEX
), '*', 'S', OP (SCALE
), 0 } },
4734 & fmt_stt_index_disp
, { 0xa2003800 },
4735 (PTR
) & fmt_stt_index_disp_ops
[0],
4738 /* stt $st_src, $optdisp($abase)[$index*S$scale] */
4741 I960_INSN_STT_INDIRECT_INDEX_DISP
, "stt-indirect-index-disp", "stt",
4742 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', 0 } },
4743 & fmt_stt_indirect_index_disp
, { 0xa2003c00 },
4744 (PTR
) & fmt_stt_indirect_index_disp_ops
[0],
4747 /* stq $st_src, $offset */
4750 I960_INSN_STQ_OFFSET
, "stq-offset", "stq",
4751 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OFFSET
), 0 } },
4752 & fmt_stq_offset
, { 0xb2000000 },
4753 (PTR
) & fmt_stq_offset_ops
[0],
4756 /* stq $st_src, $offset($abase) */
4759 I960_INSN_STQ_INDIRECT_OFFSET
, "stq-indirect-offset", "stq",
4760 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OFFSET
), '(', OP (ABASE
), ')', 0 } },
4761 & fmt_stq_indirect_offset
, { 0xb2002000 },
4762 (PTR
) & fmt_stq_indirect_offset_ops
[0],
4765 /* stq $st_src, ($abase) */
4768 I960_INSN_STQ_INDIRECT
, "stq-indirect", "stq",
4769 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', '(', OP (ABASE
), ')', 0 } },
4770 & fmt_stq_indirect
, { 0xb2001000 },
4771 (PTR
) & fmt_stq_indirect_ops
[0],
4774 /* stq $st_src, ($abase)[$index*S$scale] */
4777 I960_INSN_STQ_INDIRECT_INDEX
, "stq-indirect-index", "stq",
4778 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', 0 } },
4779 & fmt_stq_indirect_index
, { 0xb2001c00 },
4780 (PTR
) & fmt_stq_indirect_index_ops
[0],
4783 /* stq $st_src, $optdisp */
4786 I960_INSN_STQ_DISP
, "stq-disp", "stq",
4787 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), 0 } },
4788 & fmt_stq_disp
, { 0xb2003000 },
4789 (PTR
) & fmt_stq_disp_ops
[0],
4792 /* stq $st_src, $optdisp($abase) */
4795 I960_INSN_STQ_INDIRECT_DISP
, "stq-indirect-disp", "stq",
4796 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', 0 } },
4797 & fmt_stq_indirect_disp
, { 0xb2003400 },
4798 (PTR
) & fmt_stq_indirect_disp_ops
[0],
4801 /* stq $st_src, $optdisp[$index*S$scale */
4804 I960_INSN_STQ_INDEX_DISP
, "stq-index-disp", "stq",
4805 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), '[', OP (INDEX
), '*', 'S', OP (SCALE
), 0 } },
4806 & fmt_stq_index_disp
, { 0xb2003800 },
4807 (PTR
) & fmt_stq_index_disp_ops
[0],
4810 /* stq $st_src, $optdisp($abase)[$index*S$scale] */
4813 I960_INSN_STQ_INDIRECT_INDEX_DISP
, "stq-indirect-index-disp", "stq",
4814 { { MNEM
, ' ', OP (ST_SRC
), ',', ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', 0 } },
4815 & fmt_stq_indirect_index_disp
, { 0xb2003c00 },
4816 (PTR
) & fmt_stq_indirect_index_disp_ops
[0],
4819 /* cmpobe $br_src1, $br_src2, $br_disp */
4822 I960_INSN_CMPOBE_REG
, "cmpobe-reg", "cmpobe",
4823 { { MNEM
, ' ', OP (BR_SRC1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
4824 & fmt_cmpobe_reg
, { 0x32000000 },
4825 (PTR
) & fmt_cmpobe_reg_ops
[0],
4826 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
4828 /* cmpobe $br_lit1, $br_src2, $br_disp */
4831 I960_INSN_CMPOBE_LIT
, "cmpobe-lit", "cmpobe",
4832 { { MNEM
, ' ', OP (BR_LIT1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
4833 & fmt_cmpobe_lit
, { 0x32002000 },
4834 (PTR
) & fmt_cmpobe_lit_ops
[0],
4835 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
4837 /* cmpobne $br_src1, $br_src2, $br_disp */
4840 I960_INSN_CMPOBNE_REG
, "cmpobne-reg", "cmpobne",
4841 { { MNEM
, ' ', OP (BR_SRC1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
4842 & fmt_cmpobe_reg
, { 0x35000000 },
4843 (PTR
) & fmt_cmpobe_reg_ops
[0],
4844 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
4846 /* cmpobne $br_lit1, $br_src2, $br_disp */
4849 I960_INSN_CMPOBNE_LIT
, "cmpobne-lit", "cmpobne",
4850 { { MNEM
, ' ', OP (BR_LIT1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
4851 & fmt_cmpobe_lit
, { 0x35002000 },
4852 (PTR
) & fmt_cmpobe_lit_ops
[0],
4853 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
4855 /* cmpobl $br_src1, $br_src2, $br_disp */
4858 I960_INSN_CMPOBL_REG
, "cmpobl-reg", "cmpobl",
4859 { { MNEM
, ' ', OP (BR_SRC1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
4860 & fmt_cmpobl_reg
, { 0x34000000 },
4861 (PTR
) & fmt_cmpobl_reg_ops
[0],
4862 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
4864 /* cmpobl $br_lit1, $br_src2, $br_disp */
4867 I960_INSN_CMPOBL_LIT
, "cmpobl-lit", "cmpobl",
4868 { { MNEM
, ' ', OP (BR_LIT1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
4869 & fmt_cmpobl_lit
, { 0x34002000 },
4870 (PTR
) & fmt_cmpobl_lit_ops
[0],
4871 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
4873 /* cmpoble $br_src1, $br_src2, $br_disp */
4876 I960_INSN_CMPOBLE_REG
, "cmpoble-reg", "cmpoble",
4877 { { MNEM
, ' ', OP (BR_SRC1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
4878 & fmt_cmpobl_reg
, { 0x36000000 },
4879 (PTR
) & fmt_cmpobl_reg_ops
[0],
4880 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
4882 /* cmpoble $br_lit1, $br_src2, $br_disp */
4885 I960_INSN_CMPOBLE_LIT
, "cmpoble-lit", "cmpoble",
4886 { { MNEM
, ' ', OP (BR_LIT1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
4887 & fmt_cmpobl_lit
, { 0x36002000 },
4888 (PTR
) & fmt_cmpobl_lit_ops
[0],
4889 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
4891 /* cmpobg $br_src1, $br_src2, $br_disp */
4894 I960_INSN_CMPOBG_REG
, "cmpobg-reg", "cmpobg",
4895 { { MNEM
, ' ', OP (BR_SRC1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
4896 & fmt_cmpobl_reg
, { 0x31000000 },
4897 (PTR
) & fmt_cmpobl_reg_ops
[0],
4898 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
4900 /* cmpobg $br_lit1, $br_src2, $br_disp */
4903 I960_INSN_CMPOBG_LIT
, "cmpobg-lit", "cmpobg",
4904 { { MNEM
, ' ', OP (BR_LIT1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
4905 & fmt_cmpobl_lit
, { 0x31002000 },
4906 (PTR
) & fmt_cmpobl_lit_ops
[0],
4907 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
4909 /* cmpobge $br_src1, $br_src2, $br_disp */
4912 I960_INSN_CMPOBGE_REG
, "cmpobge-reg", "cmpobge",
4913 { { MNEM
, ' ', OP (BR_SRC1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
4914 & fmt_cmpobl_reg
, { 0x33000000 },
4915 (PTR
) & fmt_cmpobl_reg_ops
[0],
4916 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
4918 /* cmpobge $br_lit1, $br_src2, $br_disp */
4921 I960_INSN_CMPOBGE_LIT
, "cmpobge-lit", "cmpobge",
4922 { { MNEM
, ' ', OP (BR_LIT1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
4923 & fmt_cmpobl_lit
, { 0x33002000 },
4924 (PTR
) & fmt_cmpobl_lit_ops
[0],
4925 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
4927 /* cmpibe $br_src1, $br_src2, $br_disp */
4930 I960_INSN_CMPIBE_REG
, "cmpibe-reg", "cmpibe",
4931 { { MNEM
, ' ', OP (BR_SRC1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
4932 & fmt_cmpobe_reg
, { 0x3a000000 },
4933 (PTR
) & fmt_cmpobe_reg_ops
[0],
4934 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
4936 /* cmpibe $br_lit1, $br_src2, $br_disp */
4939 I960_INSN_CMPIBE_LIT
, "cmpibe-lit", "cmpibe",
4940 { { MNEM
, ' ', OP (BR_LIT1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
4941 & fmt_cmpobe_lit
, { 0x3a002000 },
4942 (PTR
) & fmt_cmpobe_lit_ops
[0],
4943 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
4945 /* cmpibne $br_src1, $br_src2, $br_disp */
4948 I960_INSN_CMPIBNE_REG
, "cmpibne-reg", "cmpibne",
4949 { { MNEM
, ' ', OP (BR_SRC1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
4950 & fmt_cmpobe_reg
, { 0x3d000000 },
4951 (PTR
) & fmt_cmpobe_reg_ops
[0],
4952 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
4954 /* cmpibne $br_lit1, $br_src2, $br_disp */
4957 I960_INSN_CMPIBNE_LIT
, "cmpibne-lit", "cmpibne",
4958 { { MNEM
, ' ', OP (BR_LIT1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
4959 & fmt_cmpobe_lit
, { 0x3d002000 },
4960 (PTR
) & fmt_cmpobe_lit_ops
[0],
4961 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
4963 /* cmpibl $br_src1, $br_src2, $br_disp */
4966 I960_INSN_CMPIBL_REG
, "cmpibl-reg", "cmpibl",
4967 { { MNEM
, ' ', OP (BR_SRC1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
4968 & fmt_cmpobe_reg
, { 0x3c000000 },
4969 (PTR
) & fmt_cmpobe_reg_ops
[0],
4970 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
4972 /* cmpibl $br_lit1, $br_src2, $br_disp */
4975 I960_INSN_CMPIBL_LIT
, "cmpibl-lit", "cmpibl",
4976 { { MNEM
, ' ', OP (BR_LIT1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
4977 & fmt_cmpobe_lit
, { 0x3c002000 },
4978 (PTR
) & fmt_cmpobe_lit_ops
[0],
4979 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
4981 /* cmpible $br_src1, $br_src2, $br_disp */
4984 I960_INSN_CMPIBLE_REG
, "cmpible-reg", "cmpible",
4985 { { MNEM
, ' ', OP (BR_SRC1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
4986 & fmt_cmpobe_reg
, { 0x3e000000 },
4987 (PTR
) & fmt_cmpobe_reg_ops
[0],
4988 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
4990 /* cmpible $br_lit1, $br_src2, $br_disp */
4993 I960_INSN_CMPIBLE_LIT
, "cmpible-lit", "cmpible",
4994 { { MNEM
, ' ', OP (BR_LIT1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
4995 & fmt_cmpobe_lit
, { 0x3e002000 },
4996 (PTR
) & fmt_cmpobe_lit_ops
[0],
4997 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
4999 /* cmpibg $br_src1, $br_src2, $br_disp */
5002 I960_INSN_CMPIBG_REG
, "cmpibg-reg", "cmpibg",
5003 { { MNEM
, ' ', OP (BR_SRC1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
5004 & fmt_cmpobe_reg
, { 0x39000000 },
5005 (PTR
) & fmt_cmpobe_reg_ops
[0],
5006 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
5008 /* cmpibg $br_lit1, $br_src2, $br_disp */
5011 I960_INSN_CMPIBG_LIT
, "cmpibg-lit", "cmpibg",
5012 { { MNEM
, ' ', OP (BR_LIT1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
5013 & fmt_cmpobe_lit
, { 0x39002000 },
5014 (PTR
) & fmt_cmpobe_lit_ops
[0],
5015 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
5017 /* cmpibge $br_src1, $br_src2, $br_disp */
5020 I960_INSN_CMPIBGE_REG
, "cmpibge-reg", "cmpibge",
5021 { { MNEM
, ' ', OP (BR_SRC1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
5022 & fmt_cmpobe_reg
, { 0x3b000000 },
5023 (PTR
) & fmt_cmpobe_reg_ops
[0],
5024 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
5026 /* cmpibge $br_lit1, $br_src2, $br_disp */
5029 I960_INSN_CMPIBGE_LIT
, "cmpibge-lit", "cmpibge",
5030 { { MNEM
, ' ', OP (BR_LIT1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
5031 & fmt_cmpobe_lit
, { 0x3b002000 },
5032 (PTR
) & fmt_cmpobe_lit_ops
[0],
5033 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
5035 /* bbc $br_src1, $br_src2, $br_disp */
5038 I960_INSN_BBC_REG
, "bbc-reg", "bbc",
5039 { { MNEM
, ' ', OP (BR_SRC1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
5040 & fmt_cmpobe_reg
, { 0x30000000 },
5041 (PTR
) & fmt_cmpobe_reg_ops
[0],
5042 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
5044 /* bbc $br_lit1, $br_src2, $br_disp */
5047 I960_INSN_BBC_LIT
, "bbc-lit", "bbc",
5048 { { MNEM
, ' ', OP (BR_LIT1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
5049 & fmt_bbc_lit
, { 0x30002000 },
5050 (PTR
) & fmt_bbc_lit_ops
[0],
5051 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
5053 /* bbs $br_src1, $br_src2, $br_disp */
5056 I960_INSN_BBS_REG
, "bbs-reg", "bbs",
5057 { { MNEM
, ' ', OP (BR_SRC1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
5058 & fmt_cmpobe_reg
, { 0x37000000 },
5059 (PTR
) & fmt_cmpobe_reg_ops
[0],
5060 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
5062 /* bbs $br_lit1, $br_src2, $br_disp */
5065 I960_INSN_BBS_LIT
, "bbs-lit", "bbs",
5066 { { MNEM
, ' ', OP (BR_LIT1
), ',', ' ', OP (BR_SRC2
), ',', ' ', OP (BR_DISP
), 0 } },
5067 & fmt_bbc_lit
, { 0x37002000 },
5068 (PTR
) & fmt_bbc_lit_ops
[0],
5069 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
5071 /* cmpi $src1, $src2 */
5074 I960_INSN_CMPI
, "cmpi", "cmpi",
5075 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), 0 } },
5076 & fmt_cmpi
, { 0x5a002080 },
5077 (PTR
) & fmt_cmpi_ops
[0],
5080 /* cmpi $lit1, $src2 */
5083 I960_INSN_CMPI1
, "cmpi1", "cmpi",
5084 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), 0 } },
5085 & fmt_cmpi1
, { 0x5a002880 },
5086 (PTR
) & fmt_cmpi1_ops
[0],
5089 /* cmpi $src1, $lit2 */
5092 I960_INSN_CMPI2
, "cmpi2", "cmpi",
5093 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), 0 } },
5094 & fmt_cmpi2
, { 0x5a003080 },
5095 (PTR
) & fmt_cmpi2_ops
[0],
5098 /* cmpi $lit1, $lit2 */
5101 I960_INSN_CMPI3
, "cmpi3", "cmpi",
5102 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), 0 } },
5103 & fmt_cmpi3
, { 0x5a003880 },
5104 (PTR
) & fmt_cmpi3_ops
[0],
5107 /* cmpo $src1, $src2 */
5110 I960_INSN_CMPO
, "cmpo", "cmpo",
5111 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (SRC2
), 0 } },
5112 & fmt_cmpi
, { 0x5a002000 },
5113 (PTR
) & fmt_cmpi_ops
[0],
5116 /* cmpo $lit1, $src2 */
5119 I960_INSN_CMPO1
, "cmpo1", "cmpo",
5120 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (SRC2
), 0 } },
5121 & fmt_cmpi1
, { 0x5a002800 },
5122 (PTR
) & fmt_cmpi1_ops
[0],
5125 /* cmpo $src1, $lit2 */
5128 I960_INSN_CMPO2
, "cmpo2", "cmpo",
5129 { { MNEM
, ' ', OP (SRC1
), ',', ' ', OP (LIT2
), 0 } },
5130 & fmt_cmpi2
, { 0x5a003000 },
5131 (PTR
) & fmt_cmpi2_ops
[0],
5134 /* cmpo $lit1, $lit2 */
5137 I960_INSN_CMPO3
, "cmpo3", "cmpo",
5138 { { MNEM
, ' ', OP (LIT1
), ',', ' ', OP (LIT2
), 0 } },
5139 & fmt_cmpi3
, { 0x5a003800 },
5140 (PTR
) & fmt_cmpi3_ops
[0],
5143 /* testno $br_src1 */
5146 I960_INSN_TESTNO_REG
, "testno-reg", "testno",
5147 { { MNEM
, ' ', OP (BR_SRC1
), 0 } },
5148 & fmt_testno_reg
, { 0x20000000 },
5149 (PTR
) & fmt_testno_reg_ops
[0],
5152 /* testg $br_src1 */
5155 I960_INSN_TESTG_REG
, "testg-reg", "testg",
5156 { { MNEM
, ' ', OP (BR_SRC1
), 0 } },
5157 & fmt_testno_reg
, { 0x21000000 },
5158 (PTR
) & fmt_testno_reg_ops
[0],
5161 /* teste $br_src1 */
5164 I960_INSN_TESTE_REG
, "teste-reg", "teste",
5165 { { MNEM
, ' ', OP (BR_SRC1
), 0 } },
5166 & fmt_testno_reg
, { 0x22000000 },
5167 (PTR
) & fmt_testno_reg_ops
[0],
5170 /* testge $br_src1 */
5173 I960_INSN_TESTGE_REG
, "testge-reg", "testge",
5174 { { MNEM
, ' ', OP (BR_SRC1
), 0 } },
5175 & fmt_testno_reg
, { 0x23000000 },
5176 (PTR
) & fmt_testno_reg_ops
[0],
5179 /* testl $br_src1 */
5182 I960_INSN_TESTL_REG
, "testl-reg", "testl",
5183 { { MNEM
, ' ', OP (BR_SRC1
), 0 } },
5184 & fmt_testno_reg
, { 0x24000000 },
5185 (PTR
) & fmt_testno_reg_ops
[0],
5188 /* testne $br_src1 */
5191 I960_INSN_TESTNE_REG
, "testne-reg", "testne",
5192 { { MNEM
, ' ', OP (BR_SRC1
), 0 } },
5193 & fmt_testno_reg
, { 0x25000000 },
5194 (PTR
) & fmt_testno_reg_ops
[0],
5197 /* testle $br_src1 */
5200 I960_INSN_TESTLE_REG
, "testle-reg", "testle",
5201 { { MNEM
, ' ', OP (BR_SRC1
), 0 } },
5202 & fmt_testno_reg
, { 0x26000000 },
5203 (PTR
) & fmt_testno_reg_ops
[0],
5206 /* testo $br_src1 */
5209 I960_INSN_TESTO_REG
, "testo-reg", "testo",
5210 { { MNEM
, ' ', OP (BR_SRC1
), 0 } },
5211 & fmt_testno_reg
, { 0x27000000 },
5212 (PTR
) & fmt_testno_reg_ops
[0],
5215 /* bno $ctrl_disp */
5218 I960_INSN_BNO
, "bno", "bno",
5219 { { MNEM
, ' ', OP (CTRL_DISP
), 0 } },
5220 & fmt_bno
, { 0x10000000 },
5221 (PTR
) & fmt_bno_ops
[0],
5222 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
5227 I960_INSN_BG
, "bg", "bg",
5228 { { MNEM
, ' ', OP (CTRL_DISP
), 0 } },
5229 & fmt_bno
, { 0x11000000 },
5230 (PTR
) & fmt_bno_ops
[0],
5231 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
5236 I960_INSN_BE
, "be", "be",
5237 { { MNEM
, ' ', OP (CTRL_DISP
), 0 } },
5238 & fmt_bno
, { 0x12000000 },
5239 (PTR
) & fmt_bno_ops
[0],
5240 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
5242 /* bge $ctrl_disp */
5245 I960_INSN_BGE
, "bge", "bge",
5246 { { MNEM
, ' ', OP (CTRL_DISP
), 0 } },
5247 & fmt_bno
, { 0x13000000 },
5248 (PTR
) & fmt_bno_ops
[0],
5249 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
5254 I960_INSN_BL
, "bl", "bl",
5255 { { MNEM
, ' ', OP (CTRL_DISP
), 0 } },
5256 & fmt_bno
, { 0x14000000 },
5257 (PTR
) & fmt_bno_ops
[0],
5258 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
5260 /* bne $ctrl_disp */
5263 I960_INSN_BNE
, "bne", "bne",
5264 { { MNEM
, ' ', OP (CTRL_DISP
), 0 } },
5265 & fmt_bno
, { 0x15000000 },
5266 (PTR
) & fmt_bno_ops
[0],
5267 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
5269 /* ble $ctrl_disp */
5272 I960_INSN_BLE
, "ble", "ble",
5273 { { MNEM
, ' ', OP (CTRL_DISP
), 0 } },
5274 & fmt_bno
, { 0x16000000 },
5275 (PTR
) & fmt_bno_ops
[0],
5276 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
5281 I960_INSN_BO
, "bo", "bo",
5282 { { MNEM
, ' ', OP (CTRL_DISP
), 0 } },
5283 & fmt_bno
, { 0x17000000 },
5284 (PTR
) & fmt_bno_ops
[0],
5285 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
5290 I960_INSN_B
, "b", "b",
5291 { { MNEM
, ' ', OP (CTRL_DISP
), 0 } },
5292 & fmt_b
, { 0x8000000 },
5293 (PTR
) & fmt_b_ops
[0],
5294 { 0, 0|A(UNCOND_CTI
)|A(UNCOND_CTI
), { 0 } }
5296 /* bx $offset($abase) */
5299 I960_INSN_BX_INDIRECT_OFFSET
, "bx-indirect-offset", "bx",
5300 { { MNEM
, ' ', OP (OFFSET
), '(', OP (ABASE
), ')', 0 } },
5301 & fmt_bx_indirect_offset
, { 0x84002000 },
5302 (PTR
) & fmt_bx_indirect_offset_ops
[0],
5303 { 0, 0|A(UNCOND_CTI
)|A(UNCOND_CTI
), { 0 } }
5308 I960_INSN_BX_INDIRECT
, "bx-indirect", "bx",
5309 { { MNEM
, ' ', '(', OP (ABASE
), ')', 0 } },
5310 & fmt_bx_indirect
, { 0x84001000 },
5311 (PTR
) & fmt_bx_indirect_ops
[0],
5312 { 0, 0|A(UNCOND_CTI
)|A(UNCOND_CTI
), { 0 } }
5314 /* bx ($abase)[$index*S$scale] */
5317 I960_INSN_BX_INDIRECT_INDEX
, "bx-indirect-index", "bx",
5318 { { MNEM
, ' ', '(', OP (ABASE
), ')', '[', OP (INDEX
), '*', 'S', OP (SCALE
), ']', 0 } },
5319 & fmt_bx_indirect_index
, { 0x84001c00 },
5320 (PTR
) & fmt_bx_indirect_index_ops
[0],
5321 { 0, 0|A(UNCOND_CTI
)|A(UNCOND_CTI
), { 0 } }
5326 I960_INSN_BX_DISP
, "bx-disp", "bx",
5327 { { MNEM
, ' ', OP (OPTDISP
), 0 } },
5328 & fmt_bx_disp
, { 0x84003000 },
5329 (PTR
) & fmt_bx_disp_ops
[0],
5330 { 0, 0|A(UNCOND_CTI
)|A(UNCOND_CTI
), { 0 } }
5332 /* bx $optdisp($abase) */
5335 I960_INSN_BX_INDIRECT_DISP
, "bx-indirect-disp", "bx",
5336 { { MNEM
, ' ', OP (OPTDISP
), '(', OP (ABASE
), ')', 0 } },
5337 & fmt_bx_indirect_disp
, { 0x84003400 },
5338 (PTR
) & fmt_bx_indirect_disp_ops
[0],
5339 { 0, 0|A(UNCOND_CTI
)|A(UNCOND_CTI
), { 0 } }
5341 /* callx $optdisp */
5344 I960_INSN_CALLX_DISP
, "callx-disp", "callx",
5345 { { MNEM
, ' ', OP (OPTDISP
), 0 } },
5346 & fmt_callx_disp
, { 0x86003000 },
5347 (PTR
) & fmt_callx_disp_ops
[0],
5348 { 0, 0|A(UNCOND_CTI
)|A(UNCOND_CTI
), { 0 } }
5350 /* callx ($abase) */
5353 I960_INSN_CALLX_INDIRECT
, "callx-indirect", "callx",
5354 { { MNEM
, ' ', '(', OP (ABASE
), ')', 0 } },
5355 & fmt_callx_indirect
, { 0x86001000 },
5356 (PTR
) & fmt_callx_indirect_ops
[0],
5357 { 0, 0|A(UNCOND_CTI
)|A(UNCOND_CTI
), { 0 } }
5359 /* callx $offset($abase) */
5362 I960_INSN_CALLX_INDIRECT_OFFSET
, "callx-indirect-offset", "callx",
5363 { { MNEM
, ' ', OP (OFFSET
), '(', OP (ABASE
), ')', 0 } },
5364 & fmt_callx_indirect_offset
, { 0x86002000 },
5365 (PTR
) & fmt_callx_indirect_offset_ops
[0],
5366 { 0, 0|A(UNCOND_CTI
)|A(UNCOND_CTI
), { 0 } }
5371 I960_INSN_RET
, "ret", "ret",
5373 & fmt_ret
, { 0xa000000 },
5374 (PTR
) & fmt_ret_ops
[0],
5375 { 0, 0|A(UNCOND_CTI
)|A(UNCOND_CTI
), { 0 } }
5380 I960_INSN_CALLS
, "calls", "calls",
5381 { { MNEM
, ' ', OP (SRC1
), 0 } },
5382 & fmt_calls
, { 0x66003000 },
5383 (PTR
) & fmt_calls_ops
[0],
5384 { 0, 0|A(UNCOND_CTI
)|A(UNCOND_CTI
), { 0 } }
5389 I960_INSN_FMARK
, "fmark", "fmark",
5391 & fmt_fmark
, { 0x66003e00 },
5392 (PTR
) & fmt_fmark_ops
[0],
5393 { 0, 0|A(UNCOND_CTI
)|A(UNCOND_CTI
), { 0 } }
5398 I960_INSN_FLUSHREG
, "flushreg", "flushreg",
5400 & fmt_flushreg
, { 0x66003e80 },
5401 (PTR
) & fmt_flushreg_ops
[0],
5410 static const CGEN_INSN_TABLE insn_table
=
5412 & i960_cgen_insn_table_entries
[0],
5418 /* Formats for ALIAS macro-insns. */
5420 #define F(f) & i960_cgen_ifld_table[CONCAT2 (I960_,f)]
5424 /* Each non-simple macro entry points to an array of expansion possibilities. */
5426 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
5427 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
5428 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
5430 /* The macro instruction table. */
5432 static const CGEN_INSN macro_insn_table_entries
[] =
5440 static const CGEN_INSN_TABLE macro_insn_table
=
5442 & macro_insn_table_entries
[0],
5444 (sizeof (macro_insn_table_entries
) /
5445 sizeof (macro_insn_table_entries
[0])),
5454 /* Return non-zero if INSN is to be added to the hash table.
5455 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
5458 asm_hash_insn_p (insn
)
5459 const CGEN_INSN
* insn
;
5461 return CGEN_ASM_HASH_P (insn
);
5465 dis_hash_insn_p (insn
)
5466 const CGEN_INSN
* insn
;
5468 /* If building the hash table and the NO-DIS attribute is present,
5470 if (CGEN_INSN_ATTR (insn
, CGEN_INSN_NO_DIS
))
5472 return CGEN_DIS_HASH_P (insn
);
5475 /* The result is the hash value of the insn.
5476 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
5479 asm_hash_insn (mnem
)
5482 return CGEN_ASM_HASH (mnem
);
5485 /* BUF is a pointer to the insn's bytes in target order.
5486 VALUE is an integer of the first CGEN_BASE_INSN_BITSIZE bits,
5490 dis_hash_insn (buf
, value
)
5492 CGEN_INSN_INT value
;
5494 return CGEN_DIS_HASH (buf
, value
);
5497 /* Initialize an opcode table and return a descriptor.
5498 It's much like opening a file, and must be the first function called. */
5501 i960_cgen_opcode_open (mach
, endian
)
5503 enum cgen_endian endian
;
5505 CGEN_OPCODE_TABLE
* table
= (CGEN_OPCODE_TABLE
*) xmalloc (sizeof (CGEN_OPCODE_TABLE
));
5514 memset (table
, 0, sizeof (*table
));
5516 CGEN_OPCODE_MACH (table
) = mach
;
5517 CGEN_OPCODE_ENDIAN (table
) = endian
;
5518 /* FIXME: for the sparc case we can determine insn-endianness statically.
5519 The worry here is where both data and insn endian can be independently
5520 chosen, in which case this function will need another argument.
5521 Actually, will want to allow for more arguments in the future anyway. */
5522 CGEN_OPCODE_INSN_ENDIAN (table
) = endian
;
5524 CGEN_OPCODE_HW_LIST (table
) = & i960_cgen_hw_entries
[0];
5526 CGEN_OPCODE_IFLD_TABLE (table
) = & i960_cgen_ifld_table
[0];
5528 CGEN_OPCODE_OPERAND_TABLE (table
) = & i960_cgen_operand_table
[0];
5530 * CGEN_OPCODE_INSN_TABLE (table
) = insn_table
;
5532 * CGEN_OPCODE_MACRO_INSN_TABLE (table
) = macro_insn_table
;
5534 CGEN_OPCODE_ASM_HASH_P (table
) = asm_hash_insn_p
;
5535 CGEN_OPCODE_ASM_HASH (table
) = asm_hash_insn
;
5536 CGEN_OPCODE_ASM_HASH_SIZE (table
) = CGEN_ASM_HASH_SIZE
;
5538 CGEN_OPCODE_DIS_HASH_P (table
) = dis_hash_insn_p
;
5539 CGEN_OPCODE_DIS_HASH (table
) = dis_hash_insn
;
5540 CGEN_OPCODE_DIS_HASH_SIZE (table
) = CGEN_DIS_HASH_SIZE
;
5542 return (CGEN_OPCODE_DESC
) table
;
5545 /* Close an opcode table. */
5548 i960_cgen_opcode_close (desc
)
5549 CGEN_OPCODE_DESC desc
;
5554 /* Getting values from cgen_fields is handled by a collection of functions.
5555 They are distinguished by the type of the VALUE argument they return.
5556 TODO: floating point, inlining support, remove cases where result type
5560 i960_cgen_get_int_operand (opindex
, fields
)
5562 const CGEN_FIELDS
* fields
;
5568 case I960_OPERAND_SRC1
:
5569 value
= fields
->f_src1
;
5571 case I960_OPERAND_SRC2
:
5572 value
= fields
->f_src2
;
5574 case I960_OPERAND_DST
:
5575 value
= fields
->f_srcdst
;
5577 case I960_OPERAND_LIT1
:
5578 value
= fields
->f_src1
;
5580 case I960_OPERAND_LIT2
:
5581 value
= fields
->f_src2
;
5583 case I960_OPERAND_ST_SRC
:
5584 value
= fields
->f_srcdst
;
5586 case I960_OPERAND_ABASE
:
5587 value
= fields
->f_abase
;
5589 case I960_OPERAND_OFFSET
:
5590 value
= fields
->f_offset
;
5592 case I960_OPERAND_SCALE
:
5593 value
= fields
->f_scale
;
5595 case I960_OPERAND_INDEX
:
5596 value
= fields
->f_index
;
5598 case I960_OPERAND_OPTDISP
:
5599 value
= fields
->f_optdisp
;
5601 case I960_OPERAND_BR_SRC1
:
5602 value
= fields
->f_br_src1
;
5604 case I960_OPERAND_BR_SRC2
:
5605 value
= fields
->f_br_src2
;
5607 case I960_OPERAND_BR_DISP
:
5608 value
= fields
->f_br_disp
;
5610 case I960_OPERAND_BR_LIT1
:
5611 value
= fields
->f_br_src1
;
5613 case I960_OPERAND_CTRL_DISP
:
5614 value
= fields
->f_ctrl_disp
;
5618 /* xgettext:c-format */
5619 fprintf (stderr
, _("Unrecognized field %d while getting int operand.\n"),
5628 i960_cgen_get_vma_operand (opindex
, fields
)
5630 const CGEN_FIELDS
* fields
;
5636 case I960_OPERAND_SRC1
:
5637 value
= fields
->f_src1
;
5639 case I960_OPERAND_SRC2
:
5640 value
= fields
->f_src2
;
5642 case I960_OPERAND_DST
:
5643 value
= fields
->f_srcdst
;
5645 case I960_OPERAND_LIT1
:
5646 value
= fields
->f_src1
;
5648 case I960_OPERAND_LIT2
:
5649 value
= fields
->f_src2
;
5651 case I960_OPERAND_ST_SRC
:
5652 value
= fields
->f_srcdst
;
5654 case I960_OPERAND_ABASE
:
5655 value
= fields
->f_abase
;
5657 case I960_OPERAND_OFFSET
:
5658 value
= fields
->f_offset
;
5660 case I960_OPERAND_SCALE
:
5661 value
= fields
->f_scale
;
5663 case I960_OPERAND_INDEX
:
5664 value
= fields
->f_index
;
5666 case I960_OPERAND_OPTDISP
:
5667 value
= fields
->f_optdisp
;
5669 case I960_OPERAND_BR_SRC1
:
5670 value
= fields
->f_br_src1
;
5672 case I960_OPERAND_BR_SRC2
:
5673 value
= fields
->f_br_src2
;
5675 case I960_OPERAND_BR_DISP
:
5676 value
= fields
->f_br_disp
;
5678 case I960_OPERAND_BR_LIT1
:
5679 value
= fields
->f_br_src1
;
5681 case I960_OPERAND_CTRL_DISP
:
5682 value
= fields
->f_ctrl_disp
;
5686 /* xgettext:c-format */
5687 fprintf (stderr
, _("Unrecognized field %d while getting vma operand.\n"),
5695 /* Stuffing values in cgen_fields is handled by a collection of functions.
5696 They are distinguished by the type of the VALUE argument they accept.
5697 TODO: floating point, inlining support, remove cases where argument type
5701 i960_cgen_set_int_operand (opindex
, fields
, value
)
5703 CGEN_FIELDS
* fields
;
5708 case I960_OPERAND_SRC1
:
5709 fields
->f_src1
= value
;
5711 case I960_OPERAND_SRC2
:
5712 fields
->f_src2
= value
;
5714 case I960_OPERAND_DST
:
5715 fields
->f_srcdst
= value
;
5717 case I960_OPERAND_LIT1
:
5718 fields
->f_src1
= value
;
5720 case I960_OPERAND_LIT2
:
5721 fields
->f_src2
= value
;
5723 case I960_OPERAND_ST_SRC
:
5724 fields
->f_srcdst
= value
;
5726 case I960_OPERAND_ABASE
:
5727 fields
->f_abase
= value
;
5729 case I960_OPERAND_OFFSET
:
5730 fields
->f_offset
= value
;
5732 case I960_OPERAND_SCALE
:
5733 fields
->f_scale
= value
;
5735 case I960_OPERAND_INDEX
:
5736 fields
->f_index
= value
;
5738 case I960_OPERAND_OPTDISP
:
5739 fields
->f_optdisp
= value
;
5741 case I960_OPERAND_BR_SRC1
:
5742 fields
->f_br_src1
= value
;
5744 case I960_OPERAND_BR_SRC2
:
5745 fields
->f_br_src2
= value
;
5747 case I960_OPERAND_BR_DISP
:
5748 fields
->f_br_disp
= value
;
5750 case I960_OPERAND_BR_LIT1
:
5751 fields
->f_br_src1
= value
;
5753 case I960_OPERAND_CTRL_DISP
:
5754 fields
->f_ctrl_disp
= value
;
5758 /* xgettext:c-format */
5759 fprintf (stderr
, _("Unrecognized field %d while setting int operand.\n"),
5766 i960_cgen_set_vma_operand (opindex
, fields
, value
)
5768 CGEN_FIELDS
* fields
;
5773 case I960_OPERAND_SRC1
:
5774 fields
->f_src1
= value
;
5776 case I960_OPERAND_SRC2
:
5777 fields
->f_src2
= value
;
5779 case I960_OPERAND_DST
:
5780 fields
->f_srcdst
= value
;
5782 case I960_OPERAND_LIT1
:
5783 fields
->f_src1
= value
;
5785 case I960_OPERAND_LIT2
:
5786 fields
->f_src2
= value
;
5788 case I960_OPERAND_ST_SRC
:
5789 fields
->f_srcdst
= value
;
5791 case I960_OPERAND_ABASE
:
5792 fields
->f_abase
= value
;
5794 case I960_OPERAND_OFFSET
:
5795 fields
->f_offset
= value
;
5797 case I960_OPERAND_SCALE
:
5798 fields
->f_scale
= value
;
5800 case I960_OPERAND_INDEX
:
5801 fields
->f_index
= value
;
5803 case I960_OPERAND_OPTDISP
:
5804 fields
->f_optdisp
= value
;
5806 case I960_OPERAND_BR_SRC1
:
5807 fields
->f_br_src1
= value
;
5809 case I960_OPERAND_BR_SRC2
:
5810 fields
->f_br_src2
= value
;
5812 case I960_OPERAND_BR_DISP
:
5813 fields
->f_br_disp
= value
;
5815 case I960_OPERAND_BR_LIT1
:
5816 fields
->f_br_src1
= value
;
5818 case I960_OPERAND_CTRL_DISP
:
5819 fields
->f_ctrl_disp
= value
;
5823 /* xgettext:c-format */
5824 fprintf (stderr
, _("Unrecognized field %d while setting vma operand.\n"),