ubsan: or1k: left shift of negative value
[deliverable/binutils-gdb.git] / opcodes / lm32-opc.h
1 /* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
2 /* Instruction opcode header for lm32.
3
4 THIS FILE IS MACHINE GENERATED WITH CGEN.
5
6 Copyright (C) 1996-2019 Free Software Foundation, Inc.
7
8 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
9
10 This file is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 It is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
19
20 You should have received a copy of the GNU General Public License along
21 with this program; if not, write to the Free Software Foundation, Inc.,
22 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
23
24 */
25
26 #ifndef LM32_OPC_H
27 #define LM32_OPC_H
28
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32
33 /* -- opc.h */
34
35 /* Allows reason codes to be output when assembler errors occur. */
36 #define CGEN_VERBOSE_ASSEMBLER_ERRORS
37
38 #define CGEN_DIS_HASH_SIZE 64
39 #define CGEN_DIS_HASH(buf,value) ((value >> 26) & 0x3f)
40
41 /* -- asm.c */
42 /* Enum declaration for lm32 instruction types. */
43 typedef enum cgen_insn_type {
44 LM32_INSN_INVALID, LM32_INSN_ADD, LM32_INSN_ADDI, LM32_INSN_AND
45 , LM32_INSN_ANDI, LM32_INSN_ANDHII, LM32_INSN_B, LM32_INSN_BI
46 , LM32_INSN_BE, LM32_INSN_BG, LM32_INSN_BGE, LM32_INSN_BGEU
47 , LM32_INSN_BGU, LM32_INSN_BNE, LM32_INSN_CALL, LM32_INSN_CALLI
48 , LM32_INSN_CMPE, LM32_INSN_CMPEI, LM32_INSN_CMPG, LM32_INSN_CMPGI
49 , LM32_INSN_CMPGE, LM32_INSN_CMPGEI, LM32_INSN_CMPGEU, LM32_INSN_CMPGEUI
50 , LM32_INSN_CMPGU, LM32_INSN_CMPGUI, LM32_INSN_CMPNE, LM32_INSN_CMPNEI
51 , LM32_INSN_DIVU, LM32_INSN_LB, LM32_INSN_LBU, LM32_INSN_LH
52 , LM32_INSN_LHU, LM32_INSN_LW, LM32_INSN_MODU, LM32_INSN_MUL
53 , LM32_INSN_MULI, LM32_INSN_NOR, LM32_INSN_NORI, LM32_INSN_OR
54 , LM32_INSN_ORI, LM32_INSN_ORHII, LM32_INSN_RCSR, LM32_INSN_SB
55 , LM32_INSN_SEXTB, LM32_INSN_SEXTH, LM32_INSN_SH, LM32_INSN_SL
56 , LM32_INSN_SLI, LM32_INSN_SR, LM32_INSN_SRI, LM32_INSN_SRU
57 , LM32_INSN_SRUI, LM32_INSN_SUB, LM32_INSN_SW, LM32_INSN_USER
58 , LM32_INSN_WCSR, LM32_INSN_XOR, LM32_INSN_XORI, LM32_INSN_XNOR
59 , LM32_INSN_XNORI, LM32_INSN_BREAK, LM32_INSN_SCALL, LM32_INSN_BRET
60 , LM32_INSN_ERET, LM32_INSN_RET, LM32_INSN_MV, LM32_INSN_MVI
61 , LM32_INSN_MVUI, LM32_INSN_MVHI, LM32_INSN_MVA, LM32_INSN_NOT
62 , LM32_INSN_NOP, LM32_INSN_LBGPREL, LM32_INSN_LBUGPREL, LM32_INSN_LHGPREL
63 , LM32_INSN_LHUGPREL, LM32_INSN_LWGPREL, LM32_INSN_SBGPREL, LM32_INSN_SHGPREL
64 , LM32_INSN_SWGPREL, LM32_INSN_LWGOTREL, LM32_INSN_ORHIGOTOFFI, LM32_INSN_ADDGOTOFF
65 , LM32_INSN_SWGOTOFF, LM32_INSN_LWGOTOFF, LM32_INSN_SHGOTOFF, LM32_INSN_LHGOTOFF
66 , LM32_INSN_LHUGOTOFF, LM32_INSN_SBGOTOFF, LM32_INSN_LBGOTOFF, LM32_INSN_LBUGOTOFF
67 } CGEN_INSN_TYPE;
68
69 /* Index of `invalid' insn place holder. */
70 #define CGEN_INSN_INVALID LM32_INSN_INVALID
71
72 /* Total number of insns in table. */
73 #define MAX_INSNS ((int) LM32_INSN_LBUGOTOFF + 1)
74
75 /* This struct records data prior to insertion or after extraction. */
76 struct cgen_fields
77 {
78 int length;
79 long f_nil;
80 long f_anyof;
81 long f_opcode;
82 long f_r0;
83 long f_r1;
84 long f_r2;
85 long f_resv0;
86 long f_shift;
87 long f_imm;
88 long f_uimm;
89 long f_csr;
90 long f_user;
91 long f_exception;
92 long f_branch;
93 long f_call;
94 };
95
96 #define CGEN_INIT_PARSE(od) \
97 {\
98 }
99 #define CGEN_INIT_INSERT(od) \
100 {\
101 }
102 #define CGEN_INIT_EXTRACT(od) \
103 {\
104 }
105 #define CGEN_INIT_PRINT(od) \
106 {\
107 }
108
109
110 #ifdef __cplusplus
111 }
112 #endif
113
114 #endif /* LM32_OPC_H */
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