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* m10300-opc.c (mn10300_opcodes): Fix opcode for 4 operand "mul" and
[deliverable/binutils-gdb.git] / opcodes / m10300-opc.c
1 /* Assemble Matsushita MN10300 instructions.
2 Copyright (C) 1996, 1997 Free Software Foundation, Inc.
3
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
8
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
17
18 #include "ansidecl.h"
19 #include "opcode/mn10300.h"
20
21 \f
22 const struct mn10300_operand mn10300_operands[] = {
23 #define UNUSED 0
24 {0, 0, 0},
25
26 /* dn register in the first register operand position. */
27 #define DN0 (UNUSED+1)
28 {2, 0, MN10300_OPERAND_DREG},
29
30 /* dn register in the second register operand position. */
31 #define DN1 (DN0+1)
32 {2, 2, MN10300_OPERAND_DREG},
33
34 /* dn register in the third register operand position. */
35 #define DN2 (DN1+1)
36 {2, 4, MN10300_OPERAND_DREG},
37
38 /* dm register in the first register operand position. */
39 #define DM0 (DN2+1)
40 {2, 0, MN10300_OPERAND_DREG},
41
42 /* dm register in the second register operand position. */
43 #define DM1 (DM0+1)
44 {2, 2, MN10300_OPERAND_DREG},
45
46 /* dm register in the third register operand position. */
47 #define DM2 (DM1+1)
48 {2, 4, MN10300_OPERAND_DREG},
49
50 /* an register in the first register operand position. */
51 #define AN0 (DM2+1)
52 {2, 0, MN10300_OPERAND_AREG},
53
54 /* an register in the second register operand position. */
55 #define AN1 (AN0+1)
56 {2, 2, MN10300_OPERAND_AREG},
57
58 /* an register in the third register operand position. */
59 #define AN2 (AN1+1)
60 {2, 4, MN10300_OPERAND_AREG},
61
62 /* am register in the first register operand position. */
63 #define AM0 (AN2+1)
64 {2, 0, MN10300_OPERAND_AREG},
65
66 /* am register in the second register operand position. */
67 #define AM1 (AM0+1)
68 {2, 2, MN10300_OPERAND_AREG},
69
70 /* am register in the third register operand position. */
71 #define AM2 (AM1+1)
72 {2, 4, MN10300_OPERAND_AREG},
73
74 /* 8 bit unsigned immediate which may promote to a 16bit
75 unsigned immediate. */
76 #define IMM8 (AM2+1)
77 {8, 0, MN10300_OPERAND_PROMOTE},
78
79 /* 16 bit unsigned immediate which may promote to a 32bit
80 unsigned immediate. */
81 #define IMM16 (IMM8+1)
82 {16, 0, MN10300_OPERAND_PROMOTE},
83
84 /* 16 bit pc-relative immediate which may promote to a 16bit
85 pc-relative immediate. */
86 #define IMM16_PCREL (IMM16+1)
87 {16, 0, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED},
88
89 /* 16bit unsigned dispacement in a memory operation which
90 may promote to a 32bit displacement. */
91 #define IMM16_MEM (IMM16_PCREL+1)
92 {16, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
93
94 /* 32bit immediate, high 16 bits in the main instruction
95 word, 16bits in the extension word.
96
97 The "bits" field indicates how many bits are in the
98 main instruction word for MN10300_OPERAND_SPLIT! */
99 #define IMM32 (IMM16_MEM+1)
100 {16, 0, MN10300_OPERAND_SPLIT},
101
102 /* 32bit pc-relative offset. */
103 #define IMM32_PCREL (IMM32+1)
104 {16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
105
106 /* 32bit memory offset. */
107 #define IMM32_MEM (IMM32_PCREL+1)
108 {16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR},
109
110 /* 32bit immediate, high 16 bits in the main instruction
111 word, 16bits in the extension word, low 16bits are left
112 shifted 8 places.
113
114 The "bits" field indicates how many bits are in the
115 main instruction word for MN10300_OPERAND_SPLIT! */
116 #define IMM32_LOWSHIFT8 (IMM32_MEM+1)
117 {16, 8, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR},
118
119 /* 32bit immediate, high 24 bits in the main instruction
120 word, 8 in the extension word.
121
122 The "bits" field indicates how many bits are in the
123 main instruction word for MN10300_OPERAND_SPLIT! */
124 #define IMM32_HIGH24 (IMM32_LOWSHIFT8+1)
125 {24, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
126
127 /* 32bit immediate, high 24 bits in the main instruction
128 word, 8 in the extension word, low 8 bits are left
129 shifted 16 places.
130
131 The "bits" field indicates how many bits are in the
132 main instruction word for MN10300_OPERAND_SPLIT! */
133 #define IMM32_HIGH24_LOWSHIFT16 (IMM32_HIGH24+1)
134 {24, 16, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
135
136 /* Stack pointer. */
137 #define SP (IMM32_HIGH24_LOWSHIFT16+1)
138 {8, 0, MN10300_OPERAND_SP},
139
140 /* Processor status word. */
141 #define PSW (SP+1)
142 {0, 0, MN10300_OPERAND_PSW},
143
144 /* MDR register. */
145 #define MDR (PSW+1)
146 {0, 0, MN10300_OPERAND_MDR},
147
148 /* Index register. */
149 #define DI (MDR+1)
150 {2, 2, MN10300_OPERAND_DREG},
151
152 /* 8 bit signed displacement, may promote to 16bit signed dispacement. */
153 #define SD8 (DI+1)
154 {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
155
156 /* 16 bit signed displacement, may promote to 32bit dispacement. */
157 #define SD16 (SD8+1)
158 {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
159
160 /* 8 bit signed displacement that can not promote. */
161 #define SD8N (SD16+1)
162 {8, 0, MN10300_OPERAND_SIGNED},
163
164 /* 8 bit pc-relative displacement. */
165 #define SD8N_PCREL (SD8N+1)
166 {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX},
167
168 /* 8 bit signed displacement shifted left 8 bits in the instruction. */
169 #define SD8N_SHIFT8 (SD8N_PCREL+1)
170 {8, 8, MN10300_OPERAND_SIGNED},
171
172 /* 8 bit signed immediate which may promote to 16bit signed immediate. */
173 #define SIMM8 (SD8N_SHIFT8+1)
174 {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
175
176 /* 16 bit signed immediate which may promote to 32bit immediate. */
177 #define SIMM16 (SIMM8+1)
178 {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
179
180 /* Either an open paren or close paren. */
181 #define PAREN (SIMM16+1)
182 {0, 0, MN10300_OPERAND_PAREN},
183
184 /* dn register that appears in the first and second register positions. */
185 #define DN01 (PAREN+1)
186 {2, 0, MN10300_OPERAND_DREG | MN10300_OPERAND_REPEATED},
187
188 /* an register that appears in the first and second register positions. */
189 #define AN01 (DN01+1)
190 {2, 0, MN10300_OPERAND_AREG | MN10300_OPERAND_REPEATED},
191
192 /* 16bit pc-relative displacement which may promote to 32bit pc-relative
193 displacement. */
194 #define D16_SHIFT (AN01+1)
195 {16, 8, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED},
196
197 /* 8 bit immediate found in the extension word. */
198 #define IMM8E (D16_SHIFT+1)
199 {8, 0, MN10300_OPERAND_EXTENDED},
200
201 /* Register list found in the extension word shifted 8 bits left. */
202 #define REGSE_SHIFT8 (IMM8E+1)
203 {8, 8, MN10300_OPERAND_EXTENDED | MN10300_OPERAND_REG_LIST},
204
205 /* Register list shifted 8 bits left. */
206 #define REGS_SHIFT8 (REGSE_SHIFT8 + 1)
207 {8, 8, MN10300_OPERAND_REG_LIST},
208
209 /* Reigster list. */
210 #define REGS (REGS_SHIFT8+1)
211 {8, 0, MN10300_OPERAND_REG_LIST},
212
213 /* start-sanitize-am33 */
214 /* UStack pointer. */
215 #define USP (REGS+1)
216 {0, 0, MN10300_OPERAND_USP},
217
218 /* SStack pointer. */
219 #define SSP (USP+1)
220 {0, 0, MN10300_OPERAND_SSP},
221
222 /* MStack pointer. */
223 #define MSP (SSP+1)
224 {0, 0, MN10300_OPERAND_MSP},
225
226 /* PC . */
227 #define PC (MSP+1)
228 {0, 0, MN10300_OPERAND_PC},
229
230 /* 4 bit immediate for syscall. */
231 #define IMM4 (PC+1)
232 {4, 0, 0},
233
234 /* Processor status word. */
235 #define EPSW (IMM4+1)
236 {0, 0, MN10300_OPERAND_EPSW},
237
238 /* rn register in the first register operand position. */
239 #define RN0 (EPSW+1)
240 {4, 0, MN10300_OPERAND_RREG},
241
242 /* rn register in the fourth register operand position. */
243 #define RN2 (RN0+1)
244 {4, 4, MN10300_OPERAND_RREG},
245
246 /* rm register in the first register operand position. */
247 #define RM0 (RN2+1)
248 {4, 0, MN10300_OPERAND_RREG},
249
250 /* rm register in the second register operand position. */
251 #define RM1 (RM0+1)
252 {4, 2, MN10300_OPERAND_RREG},
253
254 /* rm register in the third register operand position. */
255 #define RM2 (RM1+1)
256 {4, 4, MN10300_OPERAND_RREG},
257
258 #define RN02 (RM2+1)
259 {4, 0, MN10300_OPERAND_RREG | MN10300_OPERAND_REPEATED},
260
261 #define XRN0 (RN02+1)
262 {4, 0, MN10300_OPERAND_XRREG},
263
264 #define XRM2 (XRN0+1)
265 {4, 4, MN10300_OPERAND_XRREG},
266
267 /* + for autoincrement */
268 #define PLUS (XRM2+1)
269 {0, 0, MN10300_OPERAND_PLUS},
270
271 #define XRN02 (PLUS+1)
272 {4, 0, MN10300_OPERAND_XRREG | MN10300_OPERAND_REPEATED},
273
274 /* Ick */
275 #define RD0 (XRN02+1)
276 {4, -8, MN10300_OPERAND_RREG},
277
278 #define RD2 (RD0+1)
279 {4, -4, MN10300_OPERAND_RREG},
280
281 /* 8 unsigned dispacement in a memory operation which
282 may promote to a 32bit displacement. */
283 #define IMM8_MEM (RD2+1)
284 {8, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
285
286 /* Index register. */
287 #define RI (IMM8_MEM+1)
288 {4, 4, MN10300_OPERAND_RREG},
289
290 /* 24 bit signed displacement, may promote to 32bit dispacement. */
291 #define SD24 (RI+1)
292 {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
293
294 /* 24 bit unsigned immediate which may promote to a 32bit
295 unsigned immediate. */
296 #define IMM24 (SD24+1)
297 {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE},
298
299 /* 24 bit signed immediate which may promote to a 32bit
300 signed immediate. */
301 #define SIMM24 (IMM24+1)
302 {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_SIGNED},
303
304 /* 16bit unsigned dispacement in a memory operation which
305 may promote to a 32bit displacement. */
306 #define IMM24_MEM (SIMM24+1)
307 {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
308 /* 32bit immediate, high 24 bits in the main instruction
309 word, 8 in the extension word.
310
311 The "bits" field indicates how many bits are in the
312 main instruction word for MN10300_OPERAND_SPLIT! */
313 #define IMM32_HIGH8 (IMM24_MEM+1)
314 {8, 0, MN10300_OPERAND_SPLIT},
315
316 /* Similarly, but a memory address. */
317 #define IMM32_HIGH8_MEM (IMM32_HIGH8+1)
318 {8, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR},
319
320 /* rm register in the seventh register operand position. */
321 #define RM6 (IMM32_HIGH8_MEM+1)
322 {4, 12, MN10300_OPERAND_RREG},
323
324 /* rm register in the fifth register operand position. */
325 #define RN4 (RM6+1)
326 {4, 8, MN10300_OPERAND_RREG},
327
328 /* 4 bit immediate for dsp instructions. */
329 #define IMM4_2 (RN4+1)
330 {4, 4, 0},
331
332 /* 4 bit immediate for dsp instructions. */
333 #define SIMM4_2 (IMM4_2+1)
334 {4, 4, MN10300_OPERAND_SIGNED},
335
336 /* 4 bit immediate for dsp instructions. */
337 #define SIMM4_6 (SIMM4_2+1)
338 {4, 12, MN10300_OPERAND_SIGNED},
339 /* end-sanitize-am33 */
340
341 } ;
342
343 #define MEM(ADDR) PAREN, ADDR, PAREN
344 #define MEMINC(ADDR) PAREN, ADDR, PLUS, PAREN
345 #define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
346 \f
347 /* The opcode table.
348
349 The format of the opcode table is:
350
351 NAME OPCODE MASK { OPERANDS }
352
353 NAME is the name of the instruction.
354 OPCODE is the instruction opcode.
355 MASK is the opcode mask; this is used to tell the disassembler
356 which bits in the actual opcode must match OPCODE.
357 OPERANDS is the list of operands.
358
359 The disassembler reads the table in order and prints the first
360 instruction which matches, so this table is sorted to put more
361 specific instructions before more general instructions. It is also
362 sorted by major opcode. */
363
364 const struct mn10300_opcode mn10300_opcodes[] = {
365 { "mov", 0x8000, 0xf000, FMT_S1, 0, {SIMM8, DN01}},
366 { "mov", 0x80, 0xf0, FMT_S0, 0, {DM1, DN0}},
367 { "mov", 0xf1e0, 0xfff0, FMT_D0, 0, {DM1, AN0}},
368 { "mov", 0xf1d0, 0xfff0, FMT_D0, 0, {AM1, DN0}},
369 { "mov", 0x9000, 0xf000, FMT_S1, 0, {IMM8, AN01}},
370 { "mov", 0x90, 0xf0, FMT_S0, 0, {AM1, AN0}},
371 { "mov", 0x3c, 0xfc, FMT_S0, 0, {SP, AN0}},
372 { "mov", 0xf2f0, 0xfff3, FMT_D0, 0, {AM1, SP}},
373 { "mov", 0xf2e4, 0xfffc, FMT_D0, 0, {PSW, DN0}},
374 { "mov", 0xf2f3, 0xfff3, FMT_D0, 0, {DM1, PSW}},
375 { "mov", 0xf2e0, 0xfffc, FMT_D0, 0, {MDR, DN0}},
376 { "mov", 0xf2f2, 0xfff3, FMT_D0, 0, {DM1, MDR}},
377 { "mov", 0x70, 0xf0, FMT_S0, 0, {MEM(AM0), DN1}},
378 { "mov", 0x5800, 0xfcff, FMT_S1, 0, {MEM(SP), DN0}},
379 { "mov", 0x300000, 0xfc0000, FMT_S2, 0, {MEM(IMM16_MEM), DN0}},
380 { "mov", 0xf000, 0xfff0, FMT_D0, 0, {MEM(AM0), AN1}},
381 { "mov", 0x5c00, 0xfcff, FMT_S1, 0, {MEM(SP), AN0}},
382 { "mov", 0xfaa00000, 0xfffc0000, FMT_D2, 0, {MEM(IMM16_MEM), AN0}},
383 { "mov", 0x60, 0xf0, FMT_S0, 0, {DM1, MEM(AN0)}},
384 { "mov", 0x4200, 0xf3ff, FMT_S1, 0, {DM1, MEM(SP)}},
385 { "mov", 0x010000, 0xf30000, FMT_S2, 0, {DM1, MEM(IMM16_MEM)}},
386 { "mov", 0xf010, 0xfff0, FMT_D0, 0, {AM1, MEM(AN0)}},
387 { "mov", 0x4300, 0xf3ff, FMT_S1, 0, {AM1, MEM(SP)}},
388 { "mov", 0xfa800000, 0xfff30000, FMT_D2, 0, {AM1, MEM(IMM16_MEM)}},
389 { "mov", 0x5c00, 0xfc00, FMT_S1, 0, {MEM2(IMM8, SP), AN0}},
390 { "mov", 0xf80000, 0xfff000, FMT_D1, 0, {MEM2(SD8, AM0), DN1}},
391 { "mov", 0xfa000000, 0xfff00000, FMT_D2, 0, {MEM2(SD16, AM0), DN1}},
392 { "mov", 0x5800, 0xfc00, FMT_S1, 0, {MEM2(IMM8, SP), DN0}},
393 { "mov", 0xfab40000, 0xfffc0000, FMT_D2, 0, {MEM2(IMM16, SP), DN0}},
394 { "mov", 0xf300, 0xffc0, FMT_D0, 0, {MEM2(DI, AM0), DN2}},
395 { "mov", 0xf82000, 0xfff000, FMT_D1, 0, {MEM2(SD8,AM0), AN1}},
396 { "mov", 0xfa200000, 0xfff00000, FMT_D2, 0, {MEM2(SD16, AM0), AN1}},
397 { "mov", 0xfab00000, 0xfffc0000, FMT_D2, 0, {MEM2(IMM16, SP), AN0}},
398 { "mov", 0xf380, 0xffc0, FMT_D0, 0, {MEM2(DI, AM0), AN2}},
399 { "mov", 0x4300, 0xf300, FMT_S1, 0, {AM1, MEM2(IMM8, SP)}},
400 { "mov", 0xf81000, 0xfff000, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}},
401 { "mov", 0xfa100000, 0xfff00000, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}},
402 { "mov", 0x4200, 0xf300, FMT_S1, 0, {DM1, MEM2(IMM8, SP)}},
403 { "mov", 0xfa910000, 0xfff30000, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}},
404 { "mov", 0xf340, 0xffc0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}},
405 { "mov", 0xf83000, 0xfff000, FMT_D1, 0, {AM1, MEM2(SD8, AN0)}},
406 { "mov", 0xfa300000, 0xfff00000, FMT_D2, 0, {AM1, MEM2(SD16, AN0)}},
407 { "mov", 0xfa900000, 0xfff30000, FMT_D2, 0, {AM1, MEM2(IMM16, SP)}},
408 { "mov", 0xf3c0, 0xffc0, FMT_D0, 0, {AM2, MEM2(DI, AN0)}},
409
410 /* start-sanitize-am33 */
411 { "mov", 0xf020, 0xfffc, FMT_D0, AM33, {USP, AN0}},
412 { "mov", 0xf024, 0xfffc, FMT_D0, AM33, {SSP, AN0}},
413 { "mov", 0xf028, 0xfffc, FMT_D0, AM33, {MSP, AN0}},
414 { "mov", 0xf02c, 0xfffc, FMT_D0, AM33, {PC, AN0}},
415 { "mov", 0xf030, 0xfff3, FMT_D0, AM33, {AN1, USP}},
416 { "mov", 0xf031, 0xfff3, FMT_D0, AM33, {AN1, SSP}},
417 { "mov", 0xf032, 0xfff3, FMT_D0, AM33, {AN1, MSP}},
418 { "mov", 0xf2ec, 0xfffc, FMT_D0, AM33, {EPSW, DN0}},
419 { "mov", 0xf2f1, 0xfff3, FMT_D0, AM33, {DM1, EPSW}},
420 { "mov", 0xf500, 0xffc0, FMT_D0, AM33, {AM2, RN0}},
421 { "mov", 0xf540, 0xffc0, FMT_D0, AM33, {DM2, RN0}},
422 { "mov", 0xf580, 0xffc0, FMT_D0, AM33, {RM1, AN0}},
423 { "mov", 0xf5c0, 0xffc0, FMT_D0, AM33, {RM1, DN0}},
424 { "mov", 0xf90800, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
425 { "mov", 0xf9e800, 0xffff00, FMT_D6, AM33, {XRM2, RN0}},
426 { "mov", 0xf9f800, 0xffff00, FMT_D6, AM33, {RM2, XRN0}},
427 { "mov", 0xf90a00, 0xffff00, FMT_D6, AM33, {MEM(RM0), RN2}},
428 { "mov", 0xf98a00, 0xffff0f, FMT_D6, AM33, {MEM(SP), RN2}},
429 { "mov", 0xf96a00, 0xffff00, FMT_D6, AM33, {MEMINC(RM0), RN2}},
430 { "mov", 0xfb0e0000, 0xffff0f00, FMT_D7, AM33, {MEM(IMM8_MEM), RN2}},
431 { "mov", 0xfd0e0000, 0xffff0f00, FMT_D8, AM33, {MEM(IMM24_MEM), RN2}},
432 { "mov", 0xf91a00, 0xffff00, FMT_D6, AM33, {RM2, MEM(RN0)}},
433 { "mov", 0xf99a00, 0xffff0f, FMT_D6, AM33, {RM2, MEM(SP)}},
434 { "mov", 0xf97a00, 0xffff00, FMT_D6, AM33, {RM2, MEMINC(RN0)}},
435 { "mov", 0xfb1e0000, 0xffff0f00, FMT_D7, AM33, {RM2, MEM(IMM8_MEM)}},
436 { "mov", 0xfd1e0000, 0xffff0f00, FMT_D8, AM33, {RM2, MEM(IMM24_MEM)}},
437 { "mov", 0xfb0a0000, 0xffff0000, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}},
438 { "mov", 0xfd0a0000, 0xffff0000, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}},
439 { "mov", 0xfb8e0000, 0xffff000f, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
440 { "mov", 0xfb1a0000, 0xffff0000, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}},
441 { "mov", 0xfd1a0000, 0xffff0000, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}},
442 { "mov", 0xfb8a0000, 0xffff0f00, FMT_D7, AM33, {MEM2(SD8, SP), RN2}},
443 { "mov", 0xfd8a0000, 0xffff0f00, FMT_D8, AM33, {MEM2(SD24, SP), RN2}},
444 { "mov", 0xfb9a0000, 0xffff0f00, FMT_D7, AM33, {RM2, MEM2(SD8, SP)}},
445 { "mov", 0xfd9a0000, 0xffff0f00, FMT_D8, AM33, {RM2, MEM2(SD24, SP)}},
446 { "mov", 0xfb9e0000, 0xffff000f, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
447 /* end-sanitize-am33 */
448 /* These must come after most of the other move instructions to avoid matching
449 a symbolic name with IMMxx operands. Ugh. */
450 { "mov", 0x2c0000, 0xfc0000, FMT_S2, 0, {SIMM16, DN0}},
451 { "mov", 0xfccc0000, 0xfffc0000, FMT_D4, 0, {IMM32, DN0}},
452 { "mov", 0x240000, 0xfc0000, FMT_S2, 0, {IMM16, AN0}},
453 { "mov", 0xfcdc0000, 0xfffc0000, FMT_D4, 0, {IMM32, AN0}},
454 { "mov", 0xfca40000, 0xfffc0000, FMT_D4, 0, {MEM(IMM32_MEM), DN0}},
455 { "mov", 0xfca00000, 0xfffc0000, FMT_D4, 0, {MEM(IMM32_MEM), AN0}},
456 { "mov", 0xfc810000, 0xfff30000, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}},
457 { "mov", 0xfc800000, 0xfff30000, FMT_D4, 0, {AM1, MEM(IMM32_MEM)}},
458 { "mov", 0xfc000000, 0xfff00000, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}},
459 { "mov", 0xfcb40000, 0xfffc0000, FMT_D4, 0, {MEM2(IMM32, SP), DN0}},
460 { "mov", 0xfc200000, 0xfff00000, FMT_D4, 0, {MEM2(IMM32,AM0), AN1}},
461 { "mov", 0xfcb00000, 0xfffc0000, FMT_D4, 0, {MEM2(IMM32, SP), AN0}},
462 { "mov", 0xfc100000, 0xfff00000, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}},
463 { "mov", 0xfc910000, 0xfff30000, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}},
464 { "mov", 0xfc300000, 0xfff00000, FMT_D4, 0, {AM1, MEM2(IMM32,AN0)}},
465 { "mov", 0xfc900000, 0xfff30000, FMT_D4, 0, {AM1, MEM2(IMM32, SP)}},
466 /* These non-promoting variants need to come after all the other memory
467 moves. */
468 { "mov", 0xf8f000, 0xfffc00, FMT_D1, 0, {MEM2(SD8N, AM0), SP}},
469 { "mov", 0xf8f400, 0xfffc00, FMT_D1, 0, {SP, MEM2(SD8N, AN0)}},
470 /* start-sanitize-am33 */
471 /* These must come last so that we favor shorter move instructions for
472 loading immediates into d0-d3/a0-a3. */
473 { "mov", 0xfb080000, 0xffff0000, FMT_D7, AM33, {SIMM8, RN02}},
474 { "mov", 0xfd080000, 0xffff0000, FMT_D8, AM33, {SIMM24, RN02}},
475 { "mov", 0xfe080000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
476 { "mov", 0xfbf80000, 0xffff0000, FMT_D7, AM33, {SIMM8, XRN02}},
477 { "mov", 0xfdf80000, 0xffff0000, FMT_D8, AM33, {SIMM24, XRN02}},
478 { "mov", 0xfef80000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, XRN02}},
479 { "mov", 0xfe0e0000, 0xffff0f00, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM),
480 RN2}},
481 { "mov", 0xfe1e0000, 0xffff0f00, FMT_D9, AM33, {RM2,
482 MEM(IMM32_HIGH8_MEM)}},
483 { "mov", 0xfe0a0000, 0xffff0000, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0),
484 RN2}},
485 { "mov", 0xfe1a0000, 0xffff0000, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8,
486 RN0)}},
487 { "mov", 0xfe8a0000, 0xffff0f00, FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP),
488 RN2}},
489 { "mov", 0xfe9a0000, 0xffff0f00, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8,
490 SP)}},
491 /* end-sanitize-am33 */
492
493 /* start-sanitize-am33 */
494 { "movu", 0xfb180000, 0xffff0000, FMT_D7, AM33, {IMM8, RN02}},
495 { "movu", 0xfd180000, 0xffff0000, FMT_D8, AM33, {IMM24, RN02}},
496 { "movu", 0xfe180000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
497 /* end-sanitize-am33 */
498
499 /* start-sanitize-am33 */
500 { "mcst9", 0xf630, 0xfff0, FMT_D0, AM33, {DN01}},
501 { "mcst48", 0xf660, 0xfff0, FMT_D0, AM33, {DN01}},
502 { "swap", 0xf680, 0xfff0, FMT_D0, AM33, {DM1, DN0}},
503 { "swap", 0xf9cb00, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
504 { "swaph", 0xf690, 0xfff0, FMT_D0, AM33, {DM1, DN0}},
505 { "swaph", 0xf9db00, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
506 { "getchx", 0xf6c0, 0xfff0, FMT_D0, AM33, {DN01}},
507 { "getclx", 0xf6d0, 0xfff0, FMT_D0, AM33, {DN01}},
508 { "mac", 0xfb0f0000, 0xffff0000, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
509 { "mac", 0xf90b00, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
510 { "mac", 0xfb0b0000, 0xffff0000, FMT_D7, AM33, {SIMM8, RN02}},
511 { "mac", 0xfd0b0000, 0xffff0000, FMT_D8, AM33, {SIMM24, RN02}},
512 { "mac", 0xfe0b0000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
513 { "macu", 0xfb1f0000, 0xffff0000, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
514 { "macu", 0xf91b00, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
515 { "macu", 0xfb1b0000, 0xffff0000, FMT_D7, AM33, {IMM8, RN02}},
516 { "macu", 0xfd1b0000, 0xffff0000, FMT_D8, AM33, {IMM24, RN02}},
517 { "macu", 0xfe1b0000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
518 { "macb", 0xfb2f0000, 0xffff000f, FMT_D7, AM33, {RM2, RN0, RD2}},
519 { "macb", 0xf92b00, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
520 { "macb", 0xfb2b0000, 0xffff0000, FMT_D7, AM33, {SIMM8, RN02}},
521 { "macb", 0xfd2b0000, 0xffff0000, FMT_D8, AM33, {SIMM24, RN02}},
522 { "macb", 0xfe2b0000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
523 { "macbu", 0xfb3f0000, 0xffff000f, FMT_D7, AM33, {RM2, RN0, RD2}},
524 { "macbu", 0xf93b00, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
525 { "macbu", 0xfb3b0000, 0xffff0000, FMT_D7, AM33, {IMM8, RN02}},
526 { "macbu", 0xfd3b0000, 0xffff0000, FMT_D8, AM33, {IMM24, RN02}},
527 { "macbu", 0xfe3b0000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
528 { "mach", 0xfb4f0000, 0xffff0000, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
529 { "mach", 0xf94b00, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
530 { "mach", 0xfb4b0000, 0xffff0000, FMT_D7, AM33, {SIMM8, RN02}},
531 { "mach", 0xfd4b0000, 0xffff0000, FMT_D8, AM33, {SIMM24, RN02}},
532 { "mach", 0xfe4b0000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
533 { "machu", 0xfb5f0000, 0xffff0000, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
534 { "machu", 0xf95b00, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
535 { "machu", 0xfb5b0000, 0xffff0000, FMT_D7, AM33, {IMM8, RN02}},
536 { "machu", 0xfd5b0000, 0xffff0000, FMT_D8, AM33, {IMM24, RN02}},
537 { "machu", 0xfe5b0000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
538 { "dmach", 0xfb6f0000, 0xffff000f, FMT_D7, AM33, {RM2, RN0, RD2}},
539 { "dmach", 0xf96b00, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
540 { "dmach", 0xfe6b0000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
541 { "dmachu", 0xfb7f0000, 0xffff000f, FMT_D7, AM33, {RM2, RN0, RD2}},
542 { "dmachu", 0xf97b00, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
543 { "dmachu", 0xfe7b0000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
544 { "dmulh", 0xfb8f0000, 0xffff0000, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
545 { "dmulh", 0xf98b00, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
546 { "dmulh", 0xfe8b0000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
547 { "dmulhu", 0xfb9f0000, 0xffff0000, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
548 { "dmulhu", 0xf99b00, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
549 { "dmulhu", 0xfe9b0000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
550 { "mcste", 0xf9bb00, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
551 { "mcste", 0xfbbb0000, 0xffff0000, FMT_D7, AM33, {IMM8, RN02}},
552 { "swhw", 0xf9eb00, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
553 /* end-sanitize-am33 */
554
555 { "movbu", 0xf040, 0xfff0, FMT_D0, 0, {MEM(AM0), DN1}},
556 { "movbu", 0xf84000, 0xfff000, FMT_D1, 0, {MEM2(SD8, AM0), DN1}},
557 { "movbu", 0xfa400000, 0xfff00000, FMT_D2, 0, {MEM2(SD16, AM0), DN1}},
558 { "movbu", 0xf8b800, 0xfffcff, FMT_D1, 0, {MEM(SP), DN0}},
559 { "movbu", 0xf8b800, 0xfffc00, FMT_D1, 0, {MEM2(IMM8, SP), DN0}},
560 { "movbu", 0xfab80000, 0xfffc0000, FMT_D2, 0, {MEM2(IMM16, SP), DN0}},
561 { "movbu", 0xf400, 0xffc0, FMT_D0, 0, {MEM2(DI, AM0), DN2}},
562 { "movbu", 0x340000, 0xfc0000, FMT_S2, 0, {MEM(IMM16_MEM), DN0}},
563 { "movbu", 0xf050, 0xfff0, FMT_D0, 0, {DM1, MEM(AN0)}},
564 { "movbu", 0xf85000, 0xfff000, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}},
565 { "movbu", 0xfa500000, 0xfff00000, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}},
566 { "movbu", 0xf89200, 0xfff3ff, FMT_D1, 0, {DM1, MEM(SP)}},
567 { "movbu", 0xf89200, 0xfff300, FMT_D1, 0, {DM1, MEM2(IMM8, SP)}},
568 { "movbu", 0xfa920000, 0xfff30000, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}},
569 { "movbu", 0xf440, 0xffc0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}},
570 { "movbu", 0x020000, 0xf30000, FMT_S2, 0, {DM1, MEM(IMM16_MEM)}},
571 /* start-sanitize-am33 */
572 { "movbu", 0xf92a00, 0xffff00, FMT_D6, AM33, {MEM(RM0), RN2}},
573 { "movbu", 0xf93a00, 0xffff00, FMT_D6, AM33, {RM2, MEM(RN0)}},
574 { "movbu", 0xf9aa00, 0xffff0f, FMT_D6, AM33, {MEM(SP), RN2}},
575 { "movbu", 0xf9ba00, 0xffff0f, FMT_D6, AM33, {RM2, MEM(SP)}},
576 { "movbu", 0xfb2a0000, 0xffff0000, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}},
577 { "movbu", 0xfd2a0000, 0xffff0000, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}},
578 { "movbu", 0xfb3a0000, 0xffff0000, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}},
579 { "movbu", 0xfd3a0000, 0xffff0000, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}},
580 { "movbu", 0xfbaa0000, 0xffff0f00, FMT_D7, AM33, {MEM2(SD8, SP), RN2}},
581 { "movbu", 0xfdaa0000, 0xffff0f00, FMT_D8, AM33, {MEM2(SD24, SP), RN2}},
582 { "movbu", 0xfbba0000, 0xffff0f00, FMT_D7, AM33, {RM2, MEM2(SD8, SP)}},
583 { "movbu", 0xfdba0000, 0xffff0f00, FMT_D8, AM33, {RM2, MEM2(SD24, SP)}},
584 { "movbu", 0xfb2e0000, 0xffff0f00, FMT_D7, AM33, {MEM(IMM8_MEM), RN2}},
585 { "movbu", 0xfd2e0000, 0xffff0f00, FMT_D8, AM33, {MEM(IMM24_MEM), RN2}},
586 { "movbu", 0xfb3e0000, 0xffff0f00, FMT_D7, AM33, {RM2, MEM(IMM8_MEM)}},
587 { "movbu", 0xfd3e0000, 0xffff0f00, FMT_D8, AM33, {RM2, MEM(IMM24_MEM)}},
588 { "movbu", 0xfbae0000, 0xffff000f, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
589 { "movbu", 0xfbbe0000, 0xffff000f, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
590 /* end-sanitize-am33 */
591 { "movbu", 0xfc400000, 0xfff00000, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}},
592 { "movbu", 0xfcb80000, 0xfffc0000, FMT_D4, 0, {MEM2(IMM32, SP), DN0}},
593 { "movbu", 0xfca80000, 0xfffc0000, FMT_D4, 0, {MEM(IMM32_MEM), DN0}},
594 { "movbu", 0xfc500000, 0xfff00000, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}},
595 { "movbu", 0xfc920000, 0xfff30000, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}},
596 { "movbu", 0xfc820000, 0xfff30000, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}},
597 /* start-sanitize-am33 */
598 { "movbu", 0xfe2a0000, 0xffff0000, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0),
599 RN2}},
600 { "movbu", 0xfe3a0000, 0xffff0000, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8,
601 RN0)}},
602 { "movbu", 0xfeaa0000, 0xffff0f00, FMT_D9, AM33, {MEM2(IMM32_HIGH8,SP),
603 RN2}},
604 { "movbu", 0xfeba0000, 0xffff0f00, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8,
605 SP)}},
606 { "movbu", 0xfe2e0000, 0xffff0f00, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM),
607 RN2}},
608 { "movbu", 0xfe3e0000, 0xffff0f00, FMT_D9, AM33, {RM2,
609 MEM(IMM32_HIGH8_MEM)}},
610 /* end-sanitize-am33 */
611
612 { "movhu", 0xf060, 0xfff0, FMT_D0, 0, {MEM(AM0), DN1}},
613 { "movhu", 0xf86000, 0xfff000, FMT_D1, 0, {MEM2(SD8, AM0), DN1}},
614 { "movhu", 0xfa600000, 0xfff00000, FMT_D2, 0, {MEM2(SD16, AM0), DN1}},
615 { "movhu", 0xf8bc00, 0xfffcff, FMT_D1, 0, {MEM(SP), DN0}},
616 { "movhu", 0xf8bc00, 0xfffc00, FMT_D1, 0, {MEM2(IMM8, SP), DN0}},
617 { "movhu", 0xfabc0000, 0xfffc0000, FMT_D2, 0, {MEM2(IMM16, SP), DN0}},
618 { "movhu", 0xf480, 0xffc0, FMT_D0, 0, {MEM2(DI, AM0), DN2}},
619 { "movhu", 0x380000, 0xfc0000, FMT_S2, 0, {MEM(IMM16_MEM), DN0}},
620 { "movhu", 0xf070, 0xfff0, FMT_D0, 0, {DM1, MEM(AN0)}},
621 { "movhu", 0xf87000, 0xfff000, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}},
622 { "movhu", 0xfa700000, 0xfff00000, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}},
623 { "movhu", 0xf89300, 0xfff3ff, FMT_D1, 0, {DM1, MEM(SP)}},
624 { "movhu", 0xf89300, 0xfff300, FMT_D1, 0, {DM1, MEM2(IMM8, SP)}},
625 { "movhu", 0xfa930000, 0xfff30000, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}},
626 { "movhu", 0xf4c0, 0xffc0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}},
627 { "movhu", 0x030000, 0xf30000, FMT_S2, 0, {DM1, MEM(IMM16_MEM)}},
628 /* start-sanitize-am33 */
629 { "movhu", 0xf94a00, 0xffff00, FMT_D6, AM33, {MEM(RM0), RN2}},
630 { "movhu", 0xf95a00, 0xffff00, FMT_D6, AM33, {RM2, MEM(RN0)}},
631 { "movhu", 0xf9ca00, 0xffff0f, FMT_D6, AM33, {MEM(SP), RN2}},
632 { "movhu", 0xf9da00, 0xffff0f, FMT_D6, AM33, {RM2, MEM(SP)}},
633 { "movhu", 0xf9ea00, 0xffff00, FMT_D6, AM33, {MEMINC(RM0), RN2}},
634 { "movhu", 0xf9fa00, 0xffff00, FMT_D6, AM33, {RM2, MEMINC(RN0)}},
635 { "movhu", 0xfb4a0000, 0xffff0000, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}},
636 { "movhu", 0xfd4a0000, 0xffff0000, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}},
637 { "movhu", 0xfb5a0000, 0xffff0000, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}},
638 { "movhu", 0xfd5a0000, 0xffff0000, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}},
639 { "movhu", 0xfbca0000, 0xffff0f00, FMT_D7, AM33, {MEM2(SD8, SP), RN2}},
640 { "movhu", 0xfdca0000, 0xffff0f00, FMT_D8, AM33, {MEM2(SD24, SP), RN2}},
641 { "movhu", 0xfbda0000, 0xffff0f00, FMT_D7, AM33, {RM2, MEM2(SD8, SP)}},
642 { "movhu", 0xfdda0000, 0xffff0f00, FMT_D8, AM33, {RM2, MEM2(SD24, SP)}},
643 { "movhu", 0xfb4e0000, 0xffff0f00, FMT_D7, AM33, {MEM(IMM8_MEM), RN2}},
644 { "movhu", 0xfd4e0000, 0xffff0f00, FMT_D8, AM33, {MEM(IMM24_MEM), RN2}},
645 { "movhu", 0xfbce0000, 0xffff000f, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
646 { "movhu", 0xfbde0000, 0xffff000f, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
647 /* end-sanitize-am33 */
648 { "movhu", 0xfc600000, 0xfff00000, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}},
649 { "movhu", 0xfcbc0000, 0xfffc0000, FMT_D4, 0, {MEM2(IMM32, SP), DN0}},
650 { "movhu", 0xfcac0000, 0xfffc0000, FMT_D4, 0, {MEM(IMM32_MEM), DN0}},
651 { "movhu", 0xfc700000, 0xfff00000, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}},
652 { "movhu", 0xfc930000, 0xfff30000, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}},
653 { "movhu", 0xfc830000, 0xfff30000, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}},
654 /* start-sanitize-am33 */
655 { "movhu", 0xfe4a0000, 0xffff0000, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0),
656 RN2}},
657 { "movhu", 0xfe5a0000, 0xffff0000, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8,
658 RN0)}},
659 { "movhu", 0xfeca0000, 0xffff0f00, FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP),
660 RN2}},
661 { "movhu", 0xfeda0000, 0xffff0f00, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8,
662 SP)}},
663 { "movhu", 0xfe4e0000, 0xffff0f00, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM),
664 RN2}},
665 { "movhu", 0xfb5e0000, 0xffff0f00, FMT_D7, AM33, {RM2, MEM(IMM8_MEM)}},
666 { "movhu", 0xfd5e0000, 0xffff0f00, FMT_D8, AM33, {RM2, MEM(IMM24_MEM)}},
667 { "movhu", 0xfe5e0000, 0xffff0f00, FMT_D9, AM33, {RM2,
668 MEM(IMM32_HIGH8_MEM)}},
669 /* end-sanitize-am33 */
670
671 { "ext", 0xf2d0, 0xfffc, FMT_D0, 0, {DN0}},
672 /* start-sanitize-am33 */
673 { "ext", 0xf91800, 0xffff00, FMT_D6, AM33, {RN02}},
674 /* end-sanitize-am33 */
675
676 /* start-sanitize-am33 */
677 { "extb", 0xf92800, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
678 /* end-sanitize-am33 */
679 { "extb", 0x10, 0xfc, FMT_S0, 0, {DN0}},
680 /* start-sanitize-am33 */
681 { "extb", 0xf92800, 0xffff00, FMT_D6, AM33, {RN02}},
682 /* end-sanitize-am33 */
683
684 /* start-sanitize-am33 */
685 { "extbu", 0xf93800, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
686 /* end-sanitize-am33 */
687 { "extbu", 0x14, 0xfc, FMT_S0, 0, {DN0}},
688 /* start-sanitize-am33 */
689 { "extbu", 0xf93800, 0xffff00, FMT_D6, AM33, {RN02}},
690 /* end-sanitize-am33 */
691
692 /* start-sanitize-am33 */
693 { "exth", 0xf94800, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
694 /* end-sanitize-am33 */
695 { "exth", 0x18, 0xfc, FMT_S0, 0, {DN0}},
696 /* start-sanitize-am33 */
697 { "exth", 0xf94800, 0xffff00, FMT_D6, AM33, {RN02}},
698 /* end-sanitize-am33 */
699
700 /* start-sanitize-am33 */
701 { "exthu", 0xf95800, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
702 /* end-sanitize-am33 */
703 { "exthu", 0x1c, 0xfc, FMT_S0, 0, {DN0}},
704 /* start-sanitize-am33 */
705 { "exthu", 0xf95800, 0xffff00, FMT_D6, AM33, {RN02}},
706 /* end-sanitize-am33 */
707
708 { "movm", 0xce00, 0xff00, FMT_S1, 0, {MEM(SP), REGS}},
709 { "movm", 0xcf00, 0xff00, FMT_S1, 0, {REGS, MEM(SP)}},
710 /* start-sanitize-am33 */
711 { "movm", 0xf8ce00, 0xffff00, FMT_D1, AM33, {MEM(USP), REGS}},
712 { "movm", 0xf8cf00, 0xffff00, FMT_D1, AM33, {REGS, MEM(USP)}},
713 /* end-sanitize-am33 */
714
715 { "clr", 0x00, 0xf3, FMT_S0, 0, {DN1}},
716 /* start-sanitize-am33 */
717 { "clr", 0xf96800, 0xffff00, FMT_D6, AM33, {RN02}},
718 /* end-sanitize-am33 */
719
720 /* start-sanitize-am33 */
721 { "add", 0xfb7c0000, 0xffff000f, FMT_D7, AM33, {RM2, RN0, RD2}},
722 /* end-sanitize-am33 */
723 { "add", 0xe0, 0xf0, FMT_S0, 0, {DM1, DN0}},
724 { "add", 0xf160, 0xfff0, FMT_D0, 0, {DM1, AN0}},
725 { "add", 0xf150, 0xfff0, FMT_D0, 0, {AM1, DN0}},
726 { "add", 0xf170, 0xfff0, FMT_D0, 0, {AM1, AN0}},
727 { "add", 0x2800, 0xfc00, FMT_S1, 0, {SIMM8, DN0}},
728 { "add", 0xfac00000, 0xfffc0000, FMT_D2, 0, {SIMM16, DN0}},
729 { "add", 0x2000, 0xfc00, FMT_S1, 0, {SIMM8, AN0}},
730 { "add", 0xfad00000, 0xfffc0000, FMT_D2, 0, {SIMM16, AN0}},
731 { "add", 0xf8fe00, 0xffff00, FMT_D1, 0, {SIMM8, SP}},
732 { "add", 0xfafe0000, 0xffff0000, FMT_D2, 0, {SIMM16, SP}},
733 /* start-sanitize-am33 */
734 { "add", 0xf97800, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
735 /* end-sanitize-am33 */
736 { "add", 0xfcc00000, 0xfffc0000, FMT_D4, 0, {IMM32, DN0}},
737 { "add", 0xfcd00000, 0xfffc0000, FMT_D4, 0, {IMM32, AN0}},
738 { "add", 0xfcfe0000, 0xffff0000, FMT_D4, 0, {IMM32, SP}},
739 /* start-sanitize-am33 */
740 { "add", 0xfb780000, 0xffff0000, FMT_D7, AM33, {SIMM8, RN02}},
741 { "add", 0xfd780000, 0xffff0000, FMT_D8, AM33, {SIMM24, RN02}},
742 { "add", 0xfe780000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
743 /* end-sanitize-am33 */
744
745 /* start-sanitize-am33 */
746 { "addc", 0xfb8c0000, 0xffff000f, FMT_D7, AM33, {RM2, RN0, RD2}},
747 /* end-sanitize-am33 */
748 { "addc", 0xf140, 0xfff0, FMT_D0, 0, {DM1, DN0}},
749 /* start-sanitize-am33 */
750 { "addc", 0xf98800, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
751 { "addc", 0xfb880000, 0xffff0000, FMT_D7, AM33, {SIMM8, RN02}},
752 { "addc", 0xfd880000, 0xffff0000, FMT_D8, AM33, {SIMM24, RN02}},
753 { "addc", 0xfe880000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
754 /* end-sanitize-am33 */
755
756 /* start-sanitize-am33 */
757 { "sub", 0xfb9c0000, 0xffff000f, FMT_D7, AM33, {RM2, RN0, RD2}},
758 /* end-sanitize-am33 */
759 { "sub", 0xf100, 0xfff0, FMT_D0, 0, {DM1, DN0}},
760 { "sub", 0xf120, 0xfff0, FMT_D0, 0, {DM1, AN0}},
761 { "sub", 0xf110, 0xfff0, FMT_D0, 0, {AM1, DN0}},
762 { "sub", 0xf130, 0xfff0, FMT_D0, 0, {AM1, AN0}},
763 /* start-sanitize-am33 */
764 { "sub", 0xf99800, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
765 /* end-sanitize-am33 */
766 { "sub", 0xfcc40000, 0xfffc0000, FMT_D4, 0, {IMM32, DN0}},
767 { "sub", 0xfcd40000, 0xfffc0000, FMT_D4, 0, {IMM32, AN0}},
768 /* start-sanitize-am33 */
769 { "sub", 0xfb980000, 0xffff0000, FMT_D7, AM33, {SIMM8, RN02}},
770 { "sub", 0xfd980000, 0xffff0000, FMT_D8, AM33, {SIMM24, RN02}},
771 { "sub", 0xfe980000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
772 /* end-sanitize-am33 */
773
774 /* start-sanitize-am33 */
775 { "subc", 0xfa8c0000, 0xffff000f, FMT_D7, AM33, {RM2, RN0, RD2}},
776 /* end-sanitize-am33 */
777 { "subc", 0xf180, 0xfff0, FMT_D0, 0, {DM1, DN0}},
778 /* start-sanitize-am33 */
779 { "subc", 0xf9a800, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
780 { "subc", 0xfba80000, 0xffff0000, FMT_D7, AM33, {SIMM8, RN02}},
781 { "subc", 0xfda80000, 0xffff0000, FMT_D8, AM33, {SIMM24, RN02}},
782 { "subc", 0xfea80000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
783 /* end-sanitize-am33 */
784
785 /* start-sanitize-am33 */
786 { "mul", 0xfbad0000, 0xffff0000, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
787 /* end-sanitize-am33 */
788 { "mul", 0xf240, 0xfff0, FMT_D0, 0, {DM1, DN0}},
789 /* start-sanitize-am33 */
790 { "mul", 0xf9a900, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
791 { "mul", 0xfba90000, 0xffff0000, FMT_D7, AM33, {SIMM8, RN02}},
792 { "mul", 0xfda90000, 0xffff0000, FMT_D8, AM33, {SIMM24, RN02}},
793 { "mul", 0xfea90000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
794 /* end-sanitize-am33 */
795
796 /* start-sanitize-am33 */
797 { "mulu", 0xfbbd0000, 0xffff0000, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
798 /* end-sanitize-am33 */
799 { "mulu", 0xf250, 0xfff0, FMT_D0, 0, {DM1, DN0}},
800 /* start-sanitize-am33 */
801 { "mulu", 0xf9b900, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
802 { "mulu", 0xfbb90000, 0xffff0000, FMT_D7, AM33, {IMM8, RN02}},
803 { "mulu", 0xfdb90000, 0xffff0000, FMT_D8, AM33, {IMM24, RN02}},
804 { "mulu", 0xfeb90000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
805 /* end-sanitize-am33 */
806
807 { "div", 0xf260, 0xfff0, FMT_D0, 0, {DM1, DN0}},
808 /* start-sanitize-am33 */
809 { "div", 0xf9c900, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
810 /* end-sanitize-am33 */
811
812 { "divu", 0xf270, 0xfff0, FMT_D0, 0, {DM1, DN0}},
813 /* start-sanitize-am33 */
814 { "divu", 0xf9d900, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
815 /* end-sanitize-am33 */
816
817 { "inc", 0x40, 0xf3, FMT_S0, 0, {DN1}},
818 { "inc", 0x41, 0xf3, FMT_S0, 0, {AN1}},
819 /* start-sanitize-am33 */
820 { "inc", 0xf9b800, 0xffff00, FMT_D6, AM33, {RN02}},
821 /* end-sanitize-am33 */
822
823 { "inc4", 0x50, 0xfc, FMT_S0, 0, {AN0}},
824 /* start-sanitize-am33 */
825 { "inc4", 0xf9c800, 0xffff00, FMT_D6, AM33, {RN02}},
826 /* end-sanitize-am33 */
827
828 { "cmp", 0xa000, 0xf000, FMT_S1, 0, {SIMM8, DN01}},
829 { "cmp", 0xa0, 0xf0, FMT_S0, 0, {DM1, DN0}},
830 { "cmp", 0xf1a0, 0xfff0, FMT_D0, 0, {DM1, AN0}},
831 { "cmp", 0xf190, 0xfff0, FMT_D0, 0, {AM1, DN0}},
832 { "cmp", 0xb000, 0xf000, FMT_S1, 0, {IMM8, AN01}},
833 { "cmp", 0xb0, 0xf0, FMT_S0, 0, {AM1, AN0}},
834 { "cmp", 0xfac80000, 0xfffc0000, FMT_D2, 0, {SIMM16, DN0}},
835 { "cmp", 0xfad80000, 0xfffc0000, FMT_D2, 0, {IMM16, AN0}},
836 /* start-sanitize-am33 */
837 { "cmp", 0xf9d800, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
838 /* end-sanitize-am33 */
839 { "cmp", 0xfcc80000, 0xfffc0000, FMT_D4, 0, {IMM32, DN0}},
840 { "cmp", 0xfcd80000, 0xfffc0000, FMT_D4, 0, {IMM32, AN0}},
841 /* start-sanitize-am33 */
842 { "cmp", 0xfbd80000, 0xffff0000, FMT_D7, AM33, {SIMM8, RN02}},
843 { "cmp", 0xfdd80000, 0xffff0000, FMT_D8, AM33, {SIMM24, RN02}},
844 { "cmp", 0xfed80000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
845 /* end-sanitize-am33 */
846
847 /* start-sanitize-am33 */
848 { "and", 0xfb0d0000, 0xffff000f, FMT_D7, AM33, {RM2, RN0, RD2}},
849 /* end-sanitize-am33 */
850 { "and", 0xf200, 0xfff0, FMT_D0, 0, {DM1, DN0}},
851 { "and", 0xf8e000, 0xfffc00, FMT_D1, 0, {IMM8, DN0}},
852 { "and", 0xfae00000, 0xfffc0000, FMT_D2, 0, {IMM16, DN0}},
853 { "and", 0xfafc0000, 0xffff0000, FMT_D2, 0, {IMM16, PSW}},
854 /* start-sanitize-am33 */
855 { "and", 0xfcfc0000, 0xffff0000, FMT_D4, AM33, {IMM32, EPSW}},
856 { "and", 0xf90900, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
857 /* end-sanitize-am33 */
858 { "and", 0xfce00000, 0xfffc0000, FMT_D4, 0, {IMM32, DN0}},
859 /* start-sanitize-am33 */
860 { "and", 0xfb090000, 0xffff0000, FMT_D7, AM33, {IMM8, RN02}},
861 { "and", 0xfd090000, 0xffff0000, FMT_D8, AM33, {IMM24, RN02}},
862 { "and", 0xfe090000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
863 /* end-sanitize-am33 */
864
865 /* start-sanitize-am33 */
866 { "or", 0xfb1d0000, 0xffff000f, FMT_D7, AM33, {RM2, RN0, RD2}},
867 /* end-sanitize-am33 */
868 { "or", 0xf210, 0xfff0, FMT_D0, 0, {DM1, DN0}},
869 { "or", 0xf8e400, 0xfffc00, FMT_D1, 0, {IMM8, DN0}},
870 { "or", 0xfae40000, 0xfffc0000, FMT_D2, 0, {IMM16, DN0}},
871 { "or", 0xfafd0000, 0xffff0000, FMT_D2, 0, {IMM16, PSW}},
872 /* start-sanitize-am33 */
873 { "or", 0xfcfd0000, 0xffff0000, FMT_D4, AM33, {IMM32, EPSW}},
874 { "or", 0xf91900, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
875 /* end-sanitize-am33 */
876 { "or", 0xfce40000, 0xfffc0000, FMT_D4, 0, {IMM32, DN0}},
877 /* start-sanitize-am33 */
878 { "or", 0xfb190000, 0xffff0000, FMT_D7, AM33, {IMM8, RN02}},
879 { "or", 0xfd190000, 0xffff0000, FMT_D8, AM33, {IMM24, RN02}},
880 { "or", 0xfe190000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
881 /* end-sanitize-am33 */
882
883 /* start-sanitize-am33 */
884 { "xor", 0xfb2d0000, 0xffff000f, FMT_D7, AM33, {RM2, RN0, RD2}},
885 /* end-sanitize-am33 */
886 { "xor", 0xf220, 0xfff0, FMT_D0, 0, {DM1, DN0}},
887 { "xor", 0xfae80000, 0xfffc0000, FMT_D2, 0, {IMM16, DN0}},
888 /* start-sanitize-am33 */
889 { "xor", 0xf92900, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
890 /* end-sanitize-am33 */
891 { "xor", 0xfce80000, 0xfffc0000, FMT_D4, 0, {IMM32, DN0}},
892 /* start-sanitize-am33 */
893 { "xor", 0xfb290000, 0xffff0000, FMT_D7, AM33, {IMM8, RN02}},
894 { "xor", 0xfd290000, 0xffff0000, FMT_D8, AM33, {IMM24, RN02}},
895 { "xor", 0xfe290000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
896 /* end-sanitize-am33 */
897
898 { "not", 0xf230, 0xfffc, FMT_D0, 0, {DN0}},
899 /* start-sanitize-am33 */
900 { "not", 0xf93900, 0xffff00, FMT_D6, AM33, {RN02}},
901 /* end-sanitize-am33 */
902
903 { "btst", 0xf8ec00, 0xfffc00, FMT_D1, 0, {IMM8, DN0}},
904 { "btst", 0xfaec0000, 0xfffc0000, FMT_D2, 0, {IMM16, DN0}},
905 { "btst", 0xfcec0000, 0xfffc0000, FMT_D4, 0, {IMM32, DN0}},
906 /* start-sanitize-am33 */
907 /* Place these before the ones with IMM8E and SD8N_SHIFT8 since we want the
908 them to match last since they do not promote. */
909 { "btst", 0xfbe90000, 0xffff0000, FMT_D7, AM33, {IMM8, RN02}},
910 { "btst", 0xfde90000, 0xffff0000, FMT_D8, AM33, {IMM24, RN02}},
911 { "btst", 0xfee90000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
912 /* end-sanitize-am33 */
913 { "btst", 0xfe020000, 0xffff0000, FMT_D5, 0, {IMM8E,
914 MEM(IMM32_LOWSHIFT8)}},
915 { "btst", 0xfaf80000, 0xfffc0000, FMT_D2, 0, {IMM8, MEM2(SD8N_SHIFT8,
916 AN0)}},
917
918 { "bset", 0xf080, 0xfff0, FMT_D0, 0, {DM1, MEM(AN0)}},
919 { "bset", 0xfe000000, 0xffff0000, FMT_D5, 0, {IMM8E,
920 MEM(IMM32_LOWSHIFT8)}},
921 { "bset", 0xfaf00000, 0xfffc0000, FMT_D2, 0, {IMM8, MEM2(SD8N_SHIFT8,
922 AN0)}},
923
924 { "bclr", 0xf090, 0xfff0, FMT_D0, 0, {DM1, MEM(AN0)}},
925 { "bclr", 0xfe010000, 0xffff0000, FMT_D5, 0, {IMM8E,
926 MEM(IMM32_LOWSHIFT8)}},
927 { "bclr", 0xfaf40000, 0xfffc0000, FMT_D2, 0, {IMM8,
928 MEM2(SD8N_SHIFT8,AN0)}},
929
930 /* start-sanitize-am33 */
931 { "asr", 0xfb4d0000, 0xffff000f, FMT_D7, AM33, {RM2, RN0, RD2}},
932 /* end-sanitize-am33 */
933 { "asr", 0xf2b0, 0xfff0, FMT_D0, 0, {DM1, DN0}},
934 { "asr", 0xf8c800, 0xfffc00, FMT_D1, 0, {IMM8, DN0}},
935 /* start-sanitize-am33 */
936 { "asr", 0xf94900, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
937 { "asr", 0xfb490000, 0xffff0000, FMT_D7, AM33, {IMM8, RN02}},
938 { "asr", 0xfd490000, 0xffff0000, FMT_D8, AM33, {IMM24, RN02}},
939 { "asr", 0xfe490000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
940 /* end-sanitize-am33 */
941 { "asr", 0xf8c801, 0xfffcff, FMT_D1, 0, {DN0}},
942 /* start-sanitize-am33 */
943 { "asr", 0xfb490000, 0xffff00ff, FMT_D7, AM33, {RN02}},
944 /* end-sanitize-am33 */
945
946 /* start-sanitize-am33 */
947 { "lsr", 0xfb5d0000, 0xffff000f, FMT_D7, AM33, {RM2, RN0, RD2}},
948 /* end-sanitize-am33 */
949 { "lsr", 0xf2a0, 0xfff0, FMT_D0, 0, {DM1, DN0}},
950 { "lsr", 0xf8c400, 0xfffc00, FMT_D1, 0, {IMM8, DN0}},
951 /* start-sanitize-am33 */
952 { "lsr", 0xf95900, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
953 { "lsr", 0xfb590000, 0xffff0000, FMT_D7, AM33, {IMM8, RN02}},
954 { "lsr", 0xfd590000, 0xffff0000, FMT_D8, AM33, {IMM24, RN02}},
955 { "lsr", 0xfe590000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
956 /* end-sanitize-am33 */
957 { "lsr", 0xf8c401, 0xfffcff, FMT_D1, 0, {DN0}},
958 /* start-sanitize-am33 */
959 { "lsr", 0xfb590000, 0xffff00ff, FMT_D7, AM33, {RN02}},
960 /* end-sanitize-am33 */
961
962 /* start-sanitize-am33 */
963 { "asl", 0xfb6d0000, 0xffff000f, FMT_D7, AM33, {RM2, RN0, RD2}},
964 /* end-sanitize-am33 */
965 { "asl", 0xf290, 0xfff0, FMT_D0, 0, {DM1, DN0}},
966 { "asl", 0xf8c000, 0xfffc00, FMT_D1, 0, {IMM8, DN0}},
967 /* start-sanitize-am33 */
968 { "asl", 0xf96900, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
969 { "asl", 0xfb690000, 0xffff0000, FMT_D7, AM33, {SIMM8, RN02}},
970 { "asl", 0xfd690000, 0xffff0000, FMT_D8, AM33, {IMM24, RN02}},
971 { "asl", 0xfe690000, 0xffff0000, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
972 /* end-sanitize-am33 */
973 { "asl", 0xf8c001, 0xfffcff, FMT_D1, 0, {DN0}},
974 /* start-sanitize-am33 */
975 { "asl", 0xfb690000, 0xffff00ff, FMT_D7, AM33, {RN02}},
976 /* end-sanitize-am33 */
977
978 { "asl2", 0x54, 0xfc, FMT_S0, 0, {DN0}},
979 /* start-sanitize-am33 */
980 { "asl2", 0xf97900, 0xffff00, FMT_D6, AM33, {RN02}},
981 /* end-sanitize-am33 */
982
983 { "ror", 0xf284, 0xfffc, FMT_D0, 0, {DN0}},
984 /* start-sanitize-am33 */
985 { "ror", 0xf98900, 0xffff00, FMT_D6, AM33, {RN02}},
986 /* end-sanitize-am33 */
987
988 { "rol", 0xf280, 0xfffc, FMT_D0, 0, {DN0}},
989 /* start-sanitize-am33 */
990 { "rol", 0xf99900, 0xffff00, FMT_D6, AM33, {RN02}},
991 /* end-sanitize-am33 */
992
993 { "beq", 0xc800, 0xff00, FMT_S1, 0, {SD8N_PCREL}},
994 { "bne", 0xc900, 0xff00, FMT_S1, 0, {SD8N_PCREL}},
995 { "bgt", 0xc100, 0xff00, FMT_S1, 0, {SD8N_PCREL}},
996 { "bge", 0xc200, 0xff00, FMT_S1, 0, {SD8N_PCREL}},
997 { "ble", 0xc300, 0xff00, FMT_S1, 0, {SD8N_PCREL}},
998 { "blt", 0xc000, 0xff00, FMT_S1, 0, {SD8N_PCREL}},
999 { "bhi", 0xc500, 0xff00, FMT_S1, 0, {SD8N_PCREL}},
1000 { "bcc", 0xc600, 0xff00, FMT_S1, 0, {SD8N_PCREL}},
1001 { "bls", 0xc700, 0xff00, FMT_S1, 0, {SD8N_PCREL}},
1002 { "bcs", 0xc400, 0xff00, FMT_S1, 0, {SD8N_PCREL}},
1003 { "bvc", 0xf8e800, 0xffff00, FMT_D1, 0, {SD8N_PCREL}},
1004 { "bvs", 0xf8e900, 0xffff00, FMT_D1, 0, {SD8N_PCREL}},
1005 { "bnc", 0xf8ea00, 0xffff00, FMT_D1, 0, {SD8N_PCREL}},
1006 { "bns", 0xf8eb00, 0xffff00, FMT_D1, 0, {SD8N_PCREL}},
1007 { "bra", 0xca00, 0xff00, FMT_S1, 0, {SD8N_PCREL}},
1008
1009 { "leq", 0xd8, 0xff, FMT_S0, 0, {UNUSED}},
1010 { "lne", 0xd9, 0xff, FMT_S0, 0, {UNUSED}},
1011 { "lgt", 0xd1, 0xff, FMT_S0, 0, {UNUSED}},
1012 { "lge", 0xd2, 0xff, FMT_S0, 0, {UNUSED}},
1013 { "lle", 0xd3, 0xff, FMT_S0, 0, {UNUSED}},
1014 { "llt", 0xd0, 0xff, FMT_S0, 0, {UNUSED}},
1015 { "lhi", 0xd5, 0xff, FMT_S0, 0, {UNUSED}},
1016 { "lcc", 0xd6, 0xff, FMT_S0, 0, {UNUSED}},
1017 { "lls", 0xd7, 0xff, FMT_S0, 0, {UNUSED}},
1018 { "lcs", 0xd4, 0xff, FMT_S0, 0, {UNUSED}},
1019 { "lra", 0xda, 0xff, FMT_S0, 0, {UNUSED}},
1020 { "setlb", 0xdb, 0xff, FMT_S0, 0, {UNUSED}},
1021
1022 { "jmp", 0xf0f4, 0xfffc, FMT_D0, 0, {PAREN,AN0,PAREN}},
1023 { "jmp", 0xcc0000, 0xff0000, FMT_S2, 0, {IMM16_PCREL}},
1024 { "jmp", 0xdc000000, 0xff000000, FMT_S4, 0, {IMM32_HIGH24}},
1025 { "call", 0xcd000000, 0xff000000, FMT_S4, 0, {D16_SHIFT,REGS,IMM8E}},
1026 { "call", 0xdd000000, 0xff000000, FMT_S6, 0,
1027 {IMM32_HIGH24_LOWSHIFT16,
1028 REGSE_SHIFT8,IMM8E}},
1029 { "calls", 0xf0f0, 0xfffc, FMT_D0, 0, {PAREN,AN0,PAREN}},
1030 { "calls", 0xfaff0000, 0xffff0000, FMT_D2, 0, {IMM16_PCREL}},
1031 { "calls", 0xfcff0000, 0xffff0000, FMT_D4, 0, {IMM32_PCREL}},
1032
1033 { "ret", 0xdf0000, 0xff0000, FMT_S2, 0, {REGS_SHIFT8, IMM8}},
1034 { "retf", 0xde0000, 0xff0000, FMT_S2, 0, {REGS_SHIFT8, IMM8}},
1035 { "rets", 0xf0fc, 0xffff, FMT_D0, 0, {UNUSED}},
1036 { "rti", 0xf0fd, 0xffff, FMT_D0, 0, {UNUSED}},
1037 { "trap", 0xf0fe, 0xffff, FMT_D0, 0, {UNUSED}},
1038 { "rtm", 0xf0ff, 0xffff, FMT_D0, 0, {UNUSED}},
1039 { "nop", 0xcb, 0xff, FMT_S0, 0, {UNUSED}},
1040 /* { "udf", 0, 0, {0}}, */
1041
1042 { "putx", 0xf500, 0xfff0, FMT_D0, AM30, {DN01}},
1043 { "getx", 0xf6f0, 0xfff0, FMT_D0, AM30, {DN01}},
1044 { "mulq", 0xf600, 0xfff0, FMT_D0, AM30, {DM1, DN0}},
1045 { "mulq", 0xf90000, 0xfffc00, FMT_D1, AM30, {SIMM8, DN0}},
1046 { "mulq", 0xfb000000, 0xfffc0000, FMT_D2, AM30, {SIMM16, DN0}},
1047 { "mulq", 0xfd000000, 0xfffc0000, FMT_D4, AM30, {IMM32, DN0}},
1048 { "mulqu", 0xf610, 0xfff0, FMT_D0, AM30, {DM1, DN0}},
1049 { "mulqu", 0xf91400, 0xfffc00, FMT_D1, AM30, {SIMM8, DN0}},
1050 { "mulqu", 0xfb140000, 0xfffc0000, FMT_D2, AM30, {SIMM16, DN0}},
1051 { "mulqu", 0xfd140000, 0xfffc0000, FMT_D4, AM30, {IMM32, DN0}},
1052 { "sat16", 0xf640, 0xfff0, FMT_D0, AM30, {DM1, DN0}},
1053 /* start-sanitize-am33 */
1054 { "sat16", 0xf9ab00, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
1055 /* end-sanitize-am33 */
1056
1057 { "sat24", 0xf650, 0xfff0, FMT_D0, AM30, {DM1, DN0}},
1058 /* start-sanitize-am33 */
1059 { "sat24", 0xfbaf0000, 0xffff00ff, FMT_D7, AM33, {RM2, RN0}},
1060 /* end-sanitize-am33 */
1061
1062 /* start-sanitize-am33 */
1063 { "bsch", 0xfbff0000, 0xffff000f, FMT_D7, AM33, {RM2, RN0, RD2}},
1064 /* end-sanitize-am33 */
1065 { "bsch", 0xf670, 0xfff0, FMT_D0, AM30, {DM1, DN0}},
1066 /* start-sanitize-am33 */
1067 { "bsch", 0xf9fb00, 0xffff00, FMT_D6, AM33, {RM2, RN0}},
1068 /* end-sanitize-am33 */
1069
1070 /* Extension. We need some instruction to trigger "emulated syscalls"
1071 for our simulator. */
1072 /* start-sanitize-am33 */
1073 { "syscall", 0xf0e0, 0xfff0, FMT_D0, AM33, {IMM4}},
1074 /* end-sanitize-am33 */
1075 { "syscall", 0xf0c0, 0xffff, FMT_D0, 0, {UNUSED}},
1076
1077 /* Extension. When talking to the simulator, gdb requires some instruction
1078 that will trigger a "breakpoint" (really just an instruction that isn't
1079 otherwise used by the tools. This instruction must be the same size
1080 as the smallest instruction on the target machine. In the case of the
1081 mn10x00 the "break" instruction must be one byte. 0xff is available on
1082 both mn10x00 architectures. */
1083 { "break", 0xff, 0xff, FMT_S0, 0, {UNUSED}},
1084
1085 /* start-sanitize-am33 */
1086 { "add_add", 0xf7000000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1087 { "add_add", 0xf7100000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1088 SIMM4_2, RN0}},
1089 { "add_add", 0xf7040000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1090 RM2, RN0}},
1091 { "add_add", 0xf7140000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1092 SIMM4_2, RN0}},
1093 { "add_sub", 0xf7200000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1094 { "add_sub", 0xf7300000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1095 SIMM4_2, RN0}},
1096 { "add_sub", 0xf7240000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1097 RM2, RN0}},
1098 { "add_sub", 0xf7340000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1099 SIMM4_2, RN0}},
1100 { "add_cmp", 0xf7400000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1101 { "add_cmp", 0xf7500000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1102 SIMM4_2, RN0}},
1103 { "add_cmp", 0xf7440000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1104 RM2, RN0}},
1105 { "add_cmp", 0xf7540000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1106 SIMM4_2, RN0}},
1107 { "add_mov", 0xf7600000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1108 { "add_mov", 0xf7700000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1109 SIMM4_2, RN0}},
1110 { "add_mov", 0xf7640000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1111 RM2, RN0}},
1112 { "add_mov", 0xf7740000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1113 SIMM4_2, RN0}},
1114 { "add_asr", 0xf7800000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1115 { "add_asr", 0xf7900000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1116 IMM4_2, RN0}},
1117 { "add_asr", 0xf7840000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1118 RM2, RN0}},
1119 { "add_asr", 0xf7940000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1120 IMM4_2, RN0}},
1121 { "add_lsr", 0xf7a00000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1122 { "add_lsr", 0xf7b00000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1123 IMM4_2, RN0}},
1124 { "add_lsr", 0xf7a40000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1125 RM2, RN0}},
1126 { "add_lsr", 0xf7b40000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1127 IMM4_2, RN0}},
1128 { "add_asl", 0xf7c00000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1129 { "add_asl", 0xf7d00000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1130 IMM4_2, RN0}},
1131 { "add_asl", 0xf7c40000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1132 RM2, RN0}},
1133 { "add_asl", 0xf7d40000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1134 IMM4_2, RN0}},
1135 { "cmp_add", 0xf7010000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1136 { "cmp_add", 0xf7110000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1137 SIMM4_2, RN0}},
1138 { "cmp_add", 0xf7050000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1139 RM2, RN0}},
1140 { "cmp_add", 0xf7150000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1141 SIMM4_2, RN0}},
1142 { "cmp_sub", 0xf7210000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1143 { "cmp_sub", 0xf7310000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1144 SIMM4_2, RN0}},
1145 { "cmp_sub", 0xf7250000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1146 RM2, RN0}},
1147 { "cmp_sub", 0xf7350000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1148 SIMM4_2, RN0}},
1149 { "cmp_mov", 0xf7610000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1150 { "cmp_mov", 0xf7710000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1151 SIMM4_2, RN0}},
1152 { "cmp_mov", 0xf7650000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1153 RM2, RN0}},
1154 { "cmp_mov", 0xf7750000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1155 SIMM4_2, RN0}},
1156 { "cmp_asr", 0xf7810000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1157 { "cmp_asr", 0xf7910000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1158 IMM4_2, RN0}},
1159 { "cmp_asr", 0xf7850000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1160 RM2, RN0}},
1161 { "cmp_asr", 0xf7950000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1162 IMM4_2, RN0}},
1163 { "cmp_lsr", 0xf7a10000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1164 { "cmp_lsr", 0xf7b10000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1165 IMM4_2, RN0}},
1166 { "cmp_lsr", 0xf7a50000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1167 RM2, RN0}},
1168 { "cmp_lsr", 0xf7b50000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1169 IMM4_2, RN0}},
1170 { "cmp_asl", 0xf7c10000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1171 { "cmp_asl", 0xf7d10000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
1172 { "cmp_asl", 0xf7c50000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1173 RM2, RN0}},
1174 { "cmp_asl", 0xf7d50000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1175 IMM4_2, RN0}},
1176 { "sub_add", 0xf7020000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1177 { "sub_add", 0xf7120000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1178 SIMM4_2, RN0}},
1179 { "sub_add", 0xf7060000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1180 RM2, RN0}},
1181 { "sub_add", 0xf7160000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1182 SIMM4_2, RN0}},
1183 { "sub_sub", 0xf7220000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1184 { "sub_sub", 0xf7320000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1185 SIMM4_2, RN0}},
1186 { "sub_sub", 0xf7260000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1187 RM2, RN0}},
1188 { "sub_sub", 0xf7360000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1189 SIMM4_2, RN0}},
1190 { "sub_cmp", 0xf7420000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1191 { "sub_cmp", 0xf7520000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1192 SIMM4_2, RN0}},
1193 { "sub_cmp", 0xf7460000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1194 RM2, RN0}},
1195 { "sub_cmp", 0xf7560000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1196 SIMM4_2, RN0}},
1197 { "sub_mov", 0xf7620000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1198 { "sub_mov", 0xf7720000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1199 SIMM4_2, RN0}},
1200 { "sub_mov", 0xf7660000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1201 RM2, RN0}},
1202 { "sub_mov", 0xf7760000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1203 SIMM4_2, RN0}},
1204 { "sub_asr", 0xf7820000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1205 { "sub_asr", 0xf7920000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1206 IMM4_2, RN0}},
1207 { "sub_asr", 0xf7860000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1208 RM2, RN0}},
1209 { "sub_asr", 0xf7960000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1210 IMM4_2, RN0}},
1211 { "sub_lsr", 0xf7a20000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1212 { "sub_lsr", 0xf7b20000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1213 IMM4_2, RN0}},
1214 { "sub_lsr", 0xf7a60000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1215 RM2, RN0}},
1216 { "sub_lsr", 0xf7b60000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1217 IMM4_2, RN0}},
1218 { "sub_asl", 0xf7c20000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1219 { "sub_asl", 0xf7d20000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1220 IMM4_2, RN0}},
1221 { "sub_asl", 0xf7c60000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1222 RM2, RN0}},
1223 { "sub_asl", 0xf7d60000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1224 IMM4_2, RN0}},
1225 { "mov_add", 0xf7030000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1226 { "mov_add", 0xf7130000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1227 SIMM4_2, RN0}},
1228 { "mov_add", 0xf7070000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1229 RM2, RN0}},
1230 { "mov_add", 0xf7170000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1231 SIMM4_2, RN0}},
1232 { "mov_sub", 0xf7230000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1233 { "mov_sub", 0xf7330000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1234 SIMM4_2, RN0}},
1235 { "mov_sub", 0xf7270000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1236 RM2, RN0}},
1237 { "mov_sub", 0xf7370000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1238 SIMM4_2, RN0}},
1239 { "mov_cmp", 0xf7430000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1240 { "mov_cmp", 0xf7530000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1241 SIMM4_2, RN0}},
1242 { "mov_cmp", 0xf7470000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1243 RM2, RN0}},
1244 { "mov_cmp", 0xf7570000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1245 SIMM4_2, RN0}},
1246 { "mov_mov", 0xf7630000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1247 { "mov_mov", 0xf7730000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1248 SIMM4_2, RN0}},
1249 { "mov_mov", 0xf7670000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1250 RM2, RN0}},
1251 { "mov_mov", 0xf7770000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1252 SIMM4_2, RN0}},
1253 { "mov_asr", 0xf7830000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1254 { "mov_asr", 0xf7930000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1255 IMM4_2, RN0}},
1256 { "mov_asr", 0xf7870000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1257 RM2, RN0}},
1258 { "mov_asr", 0xf7970000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1259 IMM4_2, RN0}},
1260 { "mov_lsr", 0xf7a30000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1261 { "mov_lsr", 0xf7b30000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1262 IMM4_2, RN0}},
1263 { "mov_lsr", 0xf7a70000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1264 RM2, RN0}},
1265 { "mov_lsr", 0xf7b70000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1266 IMM4_2, RN0}},
1267 { "mov_asl", 0xf7c30000, 0xffff0000, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
1268 { "mov_asl", 0xf7d30000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1269 IMM4_2, RN0}},
1270 { "mov_asl", 0xf7c70000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1271 RM2, RN0}},
1272 { "mov_asl", 0xf7d70000, 0xffff0000, FMT_D10, AM33, {SIMM4_6, RN4,
1273 IMM4_2, RN0}},
1274 { "and_add", 0xf7080000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1275 RM2, RN0}},
1276 { "and_add", 0xf7180000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1277 SIMM4_2, RN0}},
1278 { "and_sub", 0xf7280000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1279 RM2, RN0}},
1280 { "and_sub", 0xf7380000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1281 SIMM4_2, RN0}},
1282 { "and_cmp", 0xf7480000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1283 RM2, RN0}},
1284 { "and_cmp", 0xf7580000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1285 SIMM4_2, RN0}},
1286 { "and_mov", 0xf7680000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1287 RM2, RN0}},
1288 { "and_mov", 0xf7780000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1289 SIMM4_2, RN0}},
1290 { "and_asr", 0xf7880000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1291 RM2, RN0}},
1292 { "and_asr", 0xf7980000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1293 IMM4_2, RN0}},
1294 { "and_lsr", 0xf7a80000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1295 RM2, RN0}},
1296 { "and_lsr", 0xf7b80000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1297 IMM4_2, RN0}},
1298 { "and_asl", 0xf7c80000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1299 RM2, RN0}},
1300 { "and_asl", 0xf7d80000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1301 IMM4_2, RN0}},
1302 { "dmach_add", 0xf7090000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1303 RM2, RN0}},
1304 { "dmach_add", 0xf7190000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1305 SIMM4_2, RN0}},
1306 { "dmach_sub", 0xf7290000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1307 RM2, RN0}},
1308 { "dmach_sub", 0xf7390000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1309 SIMM4_2, RN0}},
1310 { "dmach_cmp", 0xf7490000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1311 RM2, RN0}},
1312 { "dmach_cmp", 0xf7590000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1313 SIMM4_2, RN0}},
1314 { "dmach_mov", 0xf7690000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1315 RM2, RN0}},
1316 { "dmach_mov", 0xf7790000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1317 SIMM4_2, RN0}},
1318 { "dmach_asr", 0xf7890000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1319 RM2, RN0}},
1320 { "dmach_asr", 0xf7990000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1321 IMM4_2, RN0}},
1322 { "dmach_lsr", 0xf7a90000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1323 RM2, RN0}},
1324 { "dmach_lsr", 0xf7b90000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1325 IMM4_2, RN0}},
1326 { "dmach_asl", 0xf7c90000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1327 RM2, RN0}},
1328 { "dmach_asl", 0xf7d90000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1329 IMM4_2, RN0}},
1330 { "xor_add", 0xf70a0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1331 RM2, RN0}},
1332 { "xor_add", 0xf71a0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1333 SIMM4_2, RN0}},
1334 { "xor_sub", 0xf72a0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1335 RM2, RN0}},
1336 { "xor_sub", 0xf73a0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1337 SIMM4_2, RN0}},
1338 { "xor_cmp", 0xf74a0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1339 RM2, RN0}},
1340 { "xor_cmp", 0xf75a0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1341 SIMM4_2, RN0}},
1342 { "xor_mov", 0xf76a0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1343 RM2, RN0}},
1344 { "xor_mov", 0xf77a0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1345 SIMM4_2, RN0}},
1346 { "xor_asr", 0xf78a0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1347 RM2, RN0}},
1348 { "xor_asr", 0xf79a0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1349 IMM4_2, RN0}},
1350 { "xor_lsr", 0xf7aa0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1351 RM2, RN0}},
1352 { "xor_lsr", 0xf7ba0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1353 IMM4_2, RN0}},
1354 { "xor_asl", 0xf7ca0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1355 RM2, RN0}},
1356 { "xor_asl", 0xf7da0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1357 IMM4_2, RN0}},
1358 { "swhw_add", 0xf70b0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1359 RM2, RN0}},
1360 { "swhw_add", 0xf71b0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1361 SIMM4_2, RN0}},
1362 { "swhw_sub", 0xf72b0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1363 RM2, RN0}},
1364 { "swhw_sub", 0xf73b0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1365 SIMM4_2, RN0}},
1366 { "swhw_cmp", 0xf74b0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1367 RM2, RN0}},
1368 { "swhw_cmp", 0xf75b0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1369 SIMM4_2, RN0}},
1370 { "swhw_mov", 0xf76b0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1371 RM2, RN0}},
1372 { "swhw_mov", 0xf77b0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1373 SIMM4_2, RN0}},
1374 { "swhw_asr", 0xf78b0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1375 RM2, RN0}},
1376 { "swhw_asr", 0xf79b0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1377 IMM4_2, RN0}},
1378 { "swhw_lsr", 0xf7ab0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1379 RM2, RN0}},
1380 { "swhw_lsr", 0xf7bb0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1381 IMM4_2, RN0}},
1382 { "swhw_asl", 0xf7cb0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1383 RM2, RN0}},
1384 { "swhw_asl", 0xf7db0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1385 IMM4_2, RN0}},
1386 { "or_add", 0xf70c0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1387 RM2, RN0}},
1388 { "or_add", 0xf71c0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1389 SIMM4_2, RN0}},
1390 { "or_sub", 0xf72c0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1391 RM2, RN0}},
1392 { "or_sub", 0xf73c0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1393 SIMM4_2, RN0}},
1394 { "or_cmp", 0xf74c0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1395 RM2, RN0}},
1396 { "or_cmp", 0xf75c0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1397 SIMM4_2, RN0}},
1398 { "or_mov", 0xf76c0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1399 RM2, RN0}},
1400 { "or_mov", 0xf77c0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1401 SIMM4_2, RN0}},
1402 { "or_asr", 0xf78c0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1403 RM2, RN0}},
1404 { "or_asr", 0xf79c0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1405 IMM4_2, RN0}},
1406 { "or_lsr", 0xf7ac0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1407 RM2, RN0}},
1408 { "or_lsr", 0xf7bc0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1409 IMM4_2, RN0}},
1410 { "or_asl", 0xf7cc0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1411 RM2, RN0}},
1412 { "or_asl", 0xf7dc0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1413 IMM4_2, RN0}},
1414 { "sat16_add", 0xf70d0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1415 RM2, RN0}},
1416 { "sat16_add", 0xf71d0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1417 SIMM4_2, RN0}},
1418 { "sat16_sub", 0xf72d0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1419 RM2, RN0}},
1420 { "sat16_sub", 0xf73d0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1421 SIMM4_2, RN0}},
1422 { "sat16_cmp", 0xf74d0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1423 RM2, RN0}},
1424 { "sat16_cmp", 0xf75d0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1425 SIMM4_2, RN0}},
1426 { "sat16_mov", 0xf76d0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1427 RM2, RN0}},
1428 { "sat16_mov", 0xf77d0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1429 SIMM4_2, RN0}},
1430 { "sat16_asr", 0xf78d0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1431 RM2, RN0}},
1432 { "sat16_asr", 0xf79d0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1433 IMM4_2, RN0}},
1434 { "sat16_lsr", 0xf7ad0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1435 RM2, RN0}},
1436 { "sat16_lsr", 0xf7bd0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1437 IMM4_2, RN0}},
1438 { "sat16_asl", 0xf7cd0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1439 RM2, RN0}},
1440 { "sat16_asl", 0xf7dd0000, 0xffff0000, FMT_D10, AM33, {RM6, RN4,
1441 IMM4_2, RN0}},
1442 /* end-sanitize-am33 */
1443
1444 { 0, 0, 0, 0, 0, {0}},
1445
1446 } ;
1447
1448 const int mn10300_num_opcodes =
1449 sizeof (mn10300_opcodes) / sizeof (mn10300_opcodes[0]);
1450
1451 \f
GDB Binutils - Deliverables
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