opcodes/m32r-asm.in

   1 /* -- asm.c */
   2
   3 /* Handle shigh(), high().  */
   4
   5 static const char *
   6 parse_h_hi16 (strp, opindex, min, max, valuep)
   7      const char **strp;
   8      int opindex;
   9      unsigned long min, max;
  10      unsigned long *valuep;
  11 {
  12   const char *errmsg;
  13   enum cgen_parse_operand_result result_type;
  14
  15   /* FIXME: Need # in assembler syntax (means '#' is optional).  */
  16   if (**strp == '#')
  17     ++*strp;
  18
  19   if (strncmp (*strp, "high(", 5) == 0)
  20     {
  21       *strp += 5;
  22       errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_HI16_ULO,
  23                                    &result_type, valuep);
  24       if (**strp != ')')
  25         return "missing `)'";
  26       ++*strp;
  27       if (errmsg == NULL
  28           && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
  29         *valuep >>= 16;
  30       return errmsg;
  31     }
  32   else if (strncmp (*strp, "shigh(", 6) == 0)
  33     {
  34       *strp += 6;
  35       errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_HI16_SLO,
  36                                    &result_type, valuep);
  37       if (**strp != ')')
  38         return "missing `)'";
  39       ++*strp;
  40       if (errmsg == NULL
  41           && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
  42         *valuep = (*valuep >> 16) + ((*valuep) & 0x8000 ? 1 : 0);
  43       return errmsg;
  44     }
  45
  46   return cgen_parse_unsigned_integer (strp, opindex, min, max, valuep);
  47 }
  48
  49 /* Handle low() in a signed context.  Also handle sda().
  50    The signedness of the value doesn't matter to low(), but this also
  51    handles the case where low() isn't present.  */
  52
  53 static const char *
  54 parse_h_slo16 (strp, opindex, min, max, valuep)
  55      const char **strp;
  56      int opindex;
  57      long min, max;
  58      long *valuep;
  59 {
  60   const char *errmsg;
  61   enum cgen_parse_operand_result result_type;
  62
  63   /* FIXME: Need # in assembler syntax (means '#' is optional).  */
  64   if (**strp == '#')
  65     ++*strp;
  66
  67   if (strncmp (*strp, "low(", 4) == 0)
  68     {
  69       *strp += 4;
  70       errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_LO16,
  71                                    &result_type, valuep);
  72       if (**strp != ')')
  73         return "missing `)'";
  74       ++*strp;
  75       return errmsg;
  76     }
  77
  78   if (strncmp (*strp, "sda(", 4) == 0)
  79     {
  80       *strp += 4;
  81       errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_SDA16, NULL, valuep);
  82       if (**strp != ')')
  83         return "missing `)'";
  84       ++*strp;
  85       return errmsg;
  86     }
  87
  88   return cgen_parse_signed_integer (strp, opindex, min, max, valuep);
  89 }
  90
  91 /* Handle low() in an unsigned context.
  92    The signedness of the value doesn't matter to low(), but this also
  93    handles the case where low() isn't present.  */
  94
  95 static const char *
  96 parse_h_ulo16 (strp, opindex, min, max, valuep)
  97      const char **strp;
  98      int opindex;
  99      unsigned long min, max;
 100      unsigned long *valuep;
 101 {
 102   const char *errmsg;
 103   enum cgen_parse_operand_result result_type;
 104
 105   /* FIXME: Need # in assembler syntax (means '#' is optional).  */
 106   if (**strp == '#')
 107     ++*strp;
 108
 109   if (strncmp (*strp, "low(", 4) == 0)
 110     {
 111       *strp += 4;
 112       errmsg = cgen_parse_address (strp, opindex, BFD_RELOC_M32R_LO16,
 113                                    &result_type, valuep);
 114       if (**strp != ')')
 115         return "missing `)'";
 116       ++*strp;
 117       return errmsg;
 118     }
 119
 120   return cgen_parse_unsigned_integer (strp, opindex, min, max, valuep);
 121 }
 122
 123 /* -- */
 124
 125 /* Main entry point for operand parsing.
 126
 127    This function is basically just a big switch statement.  Earlier versions
 128    used tables to look up the function to use, but
 129    - if the table contains both assembler and disassembler functions then
 130      the disassembler contains much of the assembler and vice-versa,
 131    - there's a lot of inlining possibilities as things grow,
 132    - using a switch statement avoids the function call overhead.
 133
 134    This function could be moved into `parse_insn_normal', but keeping it
 135    separate makes clear the interface between `parse_insn_normal' and each of
 136    the handlers.
 137 */
 138
 139 CGEN_INLINE const char *
 140 m32r_cgen_parse_operand (opindex, strp, fields)
 141      int opindex;
 142      const char **strp;
 143      CGEN_FIELDS *fields;
 144 {
 145   const char *errmsg;
 146
 147   switch (opindex)
 148     {
 149     case M32R_OPERAND_SR :
 150       errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_gr, &fields->f_r2);
 151       break;
 152     case M32R_OPERAND_DR :
 153       errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_gr, &fields->f_r1);
 154       break;
 155     case M32R_OPERAND_SRC1 :
 156       errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_gr, &fields->f_r1);
 157       break;
 158     case M32R_OPERAND_SRC2 :
 159       errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_gr, &fields->f_r2);
 160       break;
 161     case M32R_OPERAND_SCR :
 162       errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_cr, &fields->f_r2);
 163       break;
 164     case M32R_OPERAND_DCR :
 165       errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_cr, &fields->f_r1);
 166       break;
 167     case M32R_OPERAND_SIMM8 :
 168       errmsg = cgen_parse_signed_integer (strp, 7, -128, 127, &fields->f_simm8);
 169       break;
 170     case M32R_OPERAND_SIMM16 :
 171       errmsg = cgen_parse_signed_integer (strp, 8, -32768, 32767, &fields->f_simm16);
 172       break;
 173     case M32R_OPERAND_UIMM4 :
 174       errmsg = cgen_parse_unsigned_integer (strp, 9, 0, 15, &fields->f_uimm4);
 175       break;
 176     case M32R_OPERAND_UIMM5 :
 177       errmsg = cgen_parse_unsigned_integer (strp, 10, 0, 31, &fields->f_uimm5);
 178       break;
 179     case M32R_OPERAND_UIMM16 :
 180       errmsg = cgen_parse_unsigned_integer (strp, 11, 0, 65535, &fields->f_uimm16);
 181       break;
 182     case M32R_OPERAND_ACC_S :
 183       errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_accums, &fields->f_acc_s);
 184       break;
 185     case M32R_OPERAND_ACC :
 186       errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_accums, &fields->f_acc);
 187       break;
 188     case M32R_OPERAND_HI16 :
 189       errmsg = parse_h_hi16 (strp, 14, 0, 65535, &fields->f_hi16);
 190       break;
 191     case M32R_OPERAND_SLO16 :
 192       errmsg = parse_h_slo16 (strp, 15, -32768, 32767, &fields->f_simm16);
 193       break;
 194     case M32R_OPERAND_ULO16 :
 195       errmsg = parse_h_ulo16 (strp, 16, 0, 65535, &fields->f_uimm16);
 196       break;
 197     case M32R_OPERAND_UIMM24 :
 198       errmsg = cgen_parse_address (strp, 17, 0, NULL, &fields->f_uimm24);
 199       break;
 200     case M32R_OPERAND_DISP8 :
 201       errmsg = cgen_parse_address (strp, 18, 0, NULL, &fields->f_disp8);
 202       break;
 203     case M32R_OPERAND_DISP16 :
 204       errmsg = cgen_parse_address (strp, 19, 0, NULL, &fields->f_disp16);
 205       break;
 206     case M32R_OPERAND_DISP24 :
 207       errmsg = cgen_parse_address (strp, 20, 0, NULL, &fields->f_disp24);
 208       break;
 209
 210     default :
 211       fprintf (stderr, "Unrecognized field %d while parsing.\n", opindex);
 212       abort ();
 213   }
 214
 215   return errmsg;
 216 }
 217
 218 /* Main entry point for operand insertion.
 219
 220    This function is basically just a big switch statement.  Earlier versions
 221    used tables to look up the function to use, but
 222    - if the table contains both assembler and disassembler functions then
 223      the disassembler contains much of the assembler and vice-versa,
 224    - there's a lot of inlining possibilities as things grow,
 225    - using a switch statement avoids the function call overhead.
 226
 227    This function could be moved into `parse_insn_normal', but keeping it
 228    separate makes clear the interface between `parse_insn_normal' and each of
 229    the handlers.  It's also needed by GAS to insert operands that couldn't be
 230    resolved during parsing.
 231 */
 232
 233 CGEN_INLINE void
 234 m32r_cgen_insert_operand (opindex, fields, buffer)
 235      int opindex;
 236      CGEN_FIELDS *fields;
 237      cgen_insn_t *buffer;
 238 {
 239   switch (opindex)
 240     {
 241     case M32R_OPERAND_SR :
 242       insert_normal (fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
 243       break;
 244     case M32R_OPERAND_DR :
 245       insert_normal (fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
 246       break;
 247     case M32R_OPERAND_SRC1 :
 248       insert_normal (fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
 249       break;
 250     case M32R_OPERAND_SRC2 :
 251       insert_normal (fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
 252       break;
 253     case M32R_OPERAND_SCR :
 254       insert_normal (fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
 255       break;
 256     case M32R_OPERAND_DCR :
 257       insert_normal (fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
 258       break;
 259     case M32R_OPERAND_SIMM8 :
 260       insert_normal (fields->f_simm8, 0, 8, 8, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
 261       break;
 262     case M32R_OPERAND_SIMM16 :
 263       insert_normal (fields->f_simm16, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
 264       break;
 265     case M32R_OPERAND_UIMM4 :
 266       insert_normal (fields->f_uimm4, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
 267       break;
 268     case M32R_OPERAND_UIMM5 :
 269       insert_normal (fields->f_uimm5, 0|(1<<CGEN_OPERAND_UNSIGNED), 11, 5, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
 270       break;
 271     case M32R_OPERAND_UIMM16 :
 272       insert_normal (fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
 273       break;
 274     case M32R_OPERAND_ACC_S :
 275       insert_normal (fields->f_acc_s, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 2, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
 276       break;
 277     case M32R_OPERAND_ACC :
 278       insert_normal (fields->f_acc, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 1, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
 279       break;
 280     case M32R_OPERAND_HI16 :
 281       insert_normal (fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
 282       break;
 283     case M32R_OPERAND_SLO16 :
 284       insert_normal (fields->f_simm16, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
 285       break;
 286     case M32R_OPERAND_ULO16 :
 287       insert_normal (fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
 288       break;
 289     case M32R_OPERAND_UIMM24 :
 290       insert_normal (fields->f_uimm24, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), 8, 24, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
 291       break;
 292     case M32R_OPERAND_DISP8 :
 293       insert_normal (fields->f_disp8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 8, 2, CGEN_FIELDS_BITSIZE (fields), buffer);
 294       break;
 295     case M32R_OPERAND_DISP16 :
 296       insert_normal (fields->f_disp16, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 16, 16, 2, CGEN_FIELDS_BITSIZE (fields), buffer);
 297       break;
 298     case M32R_OPERAND_DISP24 :
 299       insert_normal (fields->f_disp24, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 24, 2, CGEN_FIELDS_BITSIZE (fields), buffer);
 300       break;
 301
 302     default :
 303       fprintf (stderr, "Unrecognized field %d while building insn.\n",
 304                opindex);
 305       abort ();
 306   }
 307 }
 308
 309 /* Main entry point for operand validation.
 310
 311    This function is called from GAS when it has fully resolved an operand
 312    that couldn't be resolved during parsing.
 313
 314    The result is NULL for success or an error message (which may be
 315    computed into a static buffer).
 316 */
 317
 318 CGEN_INLINE const char *
 319 m32r_cgen_validate_operand (opindex, fields)
 320      int opindex;
 321      const CGEN_FIELDS *fields;
 322 {
 323   const char *errmsg = NULL;
 324
 325   switch (opindex)
 326     {
 327     case M32R_OPERAND_SR :
 328       /* nothing to do */
 329       break;
 330     case M32R_OPERAND_DR :
 331       /* nothing to do */
 332       break;
 333     case M32R_OPERAND_SRC1 :
 334       /* nothing to do */
 335       break;
 336     case M32R_OPERAND_SRC2 :
 337       /* nothing to do */
 338       break;
 339     case M32R_OPERAND_SCR :
 340       /* nothing to do */
 341       break;
 342     case M32R_OPERAND_DCR :
 343       /* nothing to do */
 344       break;
 345     case M32R_OPERAND_SIMM8 :
 346       errmsg = cgen_validate_signed_integer (fields->f_simm8, -128, 127);
 347       break;
 348     case M32R_OPERAND_SIMM16 :
 349       errmsg = cgen_validate_signed_integer (fields->f_simm16, -32768, 32767);
 350       break;
 351     case M32R_OPERAND_UIMM4 :
 352       errmsg = cgen_validate_unsigned_integer (fields->f_uimm4, 0, 15);
 353       break;
 354     case M32R_OPERAND_UIMM5 :
 355       errmsg = cgen_validate_unsigned_integer (fields->f_uimm5, 0, 31);
 356       break;
 357     case M32R_OPERAND_UIMM16 :
 358       errmsg = cgen_validate_unsigned_integer (fields->f_uimm16, 0, 65535);
 359       break;
 360     case M32R_OPERAND_ACC_S :
 361       /* nothing to do */
 362       break;
 363     case M32R_OPERAND_ACC :
 364       /* nothing to do */
 365       break;
 366     case M32R_OPERAND_HI16 :
 367       errmsg = cgen_validate_unsigned_integer (fields->f_hi16, 0, 65535);
 368       break;
 369     case M32R_OPERAND_SLO16 :
 370       errmsg = cgen_validate_signed_integer (fields->f_simm16, -32768, 32767);
 371       break;
 372     case M32R_OPERAND_ULO16 :
 373       errmsg = cgen_validate_unsigned_integer (fields->f_uimm16, 0, 65535);
 374       break;
 375     case M32R_OPERAND_UIMM24 :
 376       /* nothing to do */
 377       break;
 378     case M32R_OPERAND_DISP8 :
 379       /* nothing to do */
 380       break;
 381     case M32R_OPERAND_DISP16 :
 382       /* nothing to do */
 383       break;
 384     case M32R_OPERAND_DISP24 :
 385       /* nothing to do */
 386       break;
 387
 388     default :
 389       fprintf (stderr, "Unrecognized field %d while validating operand.\n",
 390                opindex);
 391       abort ();
 392   }
 393
 394   return errmsg;
 395 }
 396
 397 cgen_parse_fn *m32r_cgen_parse_handlers[] = {
 398   0, /* default */
 399   parse_insn_normal,
 400 };
 401
 402 cgen_insert_fn *m32r_cgen_insert_handlers[] = {
 403   0, /* default */
 404   insert_insn_normal,
 405 };
 406
 407 void
 408 m32r_cgen_init_asm (mach, endian)
 409      int mach;
 410      enum cgen_endian endian;
 411 {
 412   m32r_cgen_init_tables (mach);
 413   cgen_set_cpu (& m32r_cgen_opcode_data, mach, endian);
 414   cgen_asm_init ();
 415 }
 416