opcodes/m32r-desc.c

   1 /* CPU data for m32r.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #include "sysdep.h"
  26 #include <ctype.h>
  27 #include <stdio.h>
  28 #include <stdarg.h>
  29 #include "ansidecl.h"
  30 #include "bfd.h"
  31 #include "symcat.h"
  32 #include "m32r-desc.h"
  33 #include "m32r-opc.h"
  34 #include "opintl.h"
  35 #include "libiberty.h"
  36
  37 /* Attributes.  */
  38
  39 static const CGEN_ATTR_ENTRY bool_attr[] =
  40 {
  41   { "#f", 0 },
  42   { "#t", 1 },
  43   { 0, 0 }
  44 };
  45
  46 static const CGEN_ATTR_ENTRY MACH_attr[] =
  47 {
  48   { "base", MACH_BASE },
  49   { "m32r", MACH_M32R },
  50   { "m32rx", MACH_M32RX },
  51   { "max", MACH_MAX },
  52   { 0, 0 }
  53 };
  54
  55 static const CGEN_ATTR_ENTRY ISA_attr[] =
  56 {
  57   { "m32r", ISA_M32R },
  58   { "max", ISA_MAX },
  59   { 0, 0 }
  60 };
  61
  62 static const CGEN_ATTR_ENTRY PIPE_attr[] =
  63 {
  64   { "NONE", PIPE_NONE },
  65   { "O", PIPE_O },
  66   { "S", PIPE_S },
  67   { "OS", PIPE_OS },
  68   { 0, 0 }
  69 };
  70
  71 const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[] =
  72 {
  73   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  74   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  75   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  76   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  77   { "RESERVED", &bool_attr[0], &bool_attr[0] },
  78   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  79   { "SIGNED", &bool_attr[0], &bool_attr[0] },
  80   { "RELOC", &bool_attr[0], &bool_attr[0] },
  81   { 0, 0, 0 }
  82 };
  83
  84 const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[] =
  85 {
  86   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  87   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  88   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
  89   { "PC", &bool_attr[0], &bool_attr[0] },
  90   { "PROFILE", &bool_attr[0], &bool_attr[0] },
  91   { 0, 0, 0 }
  92 };
  93
  94 const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
  95 {
  96   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  97   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  98   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  99   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
 100   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
 101   { "SIGNED", &bool_attr[0], &bool_attr[0] },
 102   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
 103   { "RELAX", &bool_attr[0], &bool_attr[0] },
 104   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
 105   { "RELOC", &bool_attr[0], &bool_attr[0] },
 106   { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
 107   { 0, 0, 0 }
 108 };
 109
 110 const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
 111 {
 112   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 113   { "PIPE", & PIPE_attr[0], & PIPE_attr[0] },
 114   { "ALIAS", &bool_attr[0], &bool_attr[0] },
 115   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 116   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
 117   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
 118   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
 119   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
 120   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
 121   { "RELAX", &bool_attr[0], &bool_attr[0] },
 122   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
 123   { "PBB", &bool_attr[0], &bool_attr[0] },
 124   { "FILL-SLOT", &bool_attr[0], &bool_attr[0] },
 125   { "SPECIAL", &bool_attr[0], &bool_attr[0] },
 126   { 0, 0, 0 }
 127 };
 128
 129 /* Instruction set variants.  */
 130
 131 static const CGEN_ISA m32r_cgen_isa_table[] = {
 132   { "m32r", 32, 32, 16, 32 },
 133   { 0, 0, 0, 0, 0 }
 134 };
 135
 136 /* Machine variants.  */
 137
 138 static const CGEN_MACH m32r_cgen_mach_table[] = {
 139   { "m32r", "m32r", MACH_M32R, 0 },
 140   { "m32rx", "m32rx", MACH_M32RX, 0 },
 141   { 0, 0, 0, 0 }
 142 };
 143
 144 static CGEN_KEYWORD_ENTRY m32r_cgen_opval_gr_names_entries[] =
 145 {
 146   { "fp", 13, {0, {0}}, 0, 0 },
 147   { "lr", 14, {0, {0}}, 0, 0 },
 148   { "sp", 15, {0, {0}}, 0, 0 },
 149   { "r0", 0, {0, {0}}, 0, 0 },
 150   { "r1", 1, {0, {0}}, 0, 0 },
 151   { "r2", 2, {0, {0}}, 0, 0 },
 152   { "r3", 3, {0, {0}}, 0, 0 },
 153   { "r4", 4, {0, {0}}, 0, 0 },
 154   { "r5", 5, {0, {0}}, 0, 0 },
 155   { "r6", 6, {0, {0}}, 0, 0 },
 156   { "r7", 7, {0, {0}}, 0, 0 },
 157   { "r8", 8, {0, {0}}, 0, 0 },
 158   { "r9", 9, {0, {0}}, 0, 0 },
 159   { "r10", 10, {0, {0}}, 0, 0 },
 160   { "r11", 11, {0, {0}}, 0, 0 },
 161   { "r12", 12, {0, {0}}, 0, 0 },
 162   { "r13", 13, {0, {0}}, 0, 0 },
 163   { "r14", 14, {0, {0}}, 0, 0 },
 164   { "r15", 15, {0, {0}}, 0, 0 }
 165 };
 166
 167 CGEN_KEYWORD m32r_cgen_opval_gr_names =
 168 {
 169   & m32r_cgen_opval_gr_names_entries[0],
 170   19,
 171   0, 0, 0, 0, ""
 172 };
 173
 174 static CGEN_KEYWORD_ENTRY m32r_cgen_opval_cr_names_entries[] =
 175 {
 176   { "psw", 0, {0, {0}}, 0, 0 },
 177   { "cbr", 1, {0, {0}}, 0, 0 },
 178   { "spi", 2, {0, {0}}, 0, 0 },
 179   { "spu", 3, {0, {0}}, 0, 0 },
 180   { "bpc", 6, {0, {0}}, 0, 0 },
 181   { "bbpsw", 8, {0, {0}}, 0, 0 },
 182   { "bbpc", 14, {0, {0}}, 0, 0 },
 183   { "cr0", 0, {0, {0}}, 0, 0 },
 184   { "cr1", 1, {0, {0}}, 0, 0 },
 185   { "cr2", 2, {0, {0}}, 0, 0 },
 186   { "cr3", 3, {0, {0}}, 0, 0 },
 187   { "cr4", 4, {0, {0}}, 0, 0 },
 188   { "cr5", 5, {0, {0}}, 0, 0 },
 189   { "cr6", 6, {0, {0}}, 0, 0 },
 190   { "cr7", 7, {0, {0}}, 0, 0 },
 191   { "cr8", 8, {0, {0}}, 0, 0 },
 192   { "cr9", 9, {0, {0}}, 0, 0 },
 193   { "cr10", 10, {0, {0}}, 0, 0 },
 194   { "cr11", 11, {0, {0}}, 0, 0 },
 195   { "cr12", 12, {0, {0}}, 0, 0 },
 196   { "cr13", 13, {0, {0}}, 0, 0 },
 197   { "cr14", 14, {0, {0}}, 0, 0 },
 198   { "cr15", 15, {0, {0}}, 0, 0 }
 199 };
 200
 201 CGEN_KEYWORD m32r_cgen_opval_cr_names =
 202 {
 203   & m32r_cgen_opval_cr_names_entries[0],
 204   23,
 205   0, 0, 0, 0, ""
 206 };
 207
 208 static CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
 209 {
 210   { "a0", 0, {0, {0}}, 0, 0 },
 211   { "a1", 1, {0, {0}}, 0, 0 }
 212 };
 213
 214 CGEN_KEYWORD m32r_cgen_opval_h_accums =
 215 {
 216   & m32r_cgen_opval_h_accums_entries[0],
 217   2,
 218   0, 0, 0, 0, ""
 219 };
 220
 221
 222 /* The hardware table.  */
 223
 224 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 225 #define A(a) (1 << CGEN_HW_##a)
 226 #else
 227 #define A(a) (1 << CGEN_HW_/**/a)
 228 #endif
 229
 230 const CGEN_HW_ENTRY m32r_cgen_hw_table[] =
 231 {
 232   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 233   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 234   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 235   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 236   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 237   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
 238   { "h-hi16", HW_H_HI16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 239   { "h-slo16", HW_H_SLO16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 240   { "h-ulo16", HW_H_ULO16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 241   { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } },
 242   { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_cr_names, { 0, { (1<<MACH_BASE) } } },
 243   { "h-accum", HW_H_ACCUM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 244   { "h-accums", HW_H_ACCUMS, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { 0, { (1<<MACH_M32RX) } } },
 245   { "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 246   { "h-psw", HW_H_PSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 247   { "h-bpsw", HW_H_BPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 248   { "h-bbpsw", HW_H_BBPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 249   { "h-lock", HW_H_LOCK, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 250   { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
 251 };
 252
 253 #undef A
 254
 255
 256 /* The instruction field table.  */
 257
 258 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 259 #define A(a) (1 << CGEN_IFLD_##a)
 260 #else
 261 #define A(a) (1 << CGEN_IFLD_/**/a)
 262 #endif
 263
 264 const CGEN_IFLD m32r_cgen_ifld_table[] =
 265 {
 266   { M32R_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
 267   { M32R_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
 268   { M32R_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { (1<<MACH_BASE) } }  },
 269   { M32R_F_OP2, "f-op2", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } }  },
 270   { M32R_F_COND, "f-cond", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } }  },
 271   { M32R_F_R1, "f-r1", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } }  },
 272   { M32R_F_R2, "f-r2", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } }  },
 273   { M32R_F_SIMM8, "f-simm8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } }  },
 274   { M32R_F_SIMM16, "f-simm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } }  },
 275   { M32R_F_SHIFT_OP2, "f-shift-op2", 0, 32, 8, 3, { 0, { (1<<MACH_BASE) } }  },
 276   { M32R_F_UIMM4, "f-uimm4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } }  },
 277   { M32R_F_UIMM5, "f-uimm5", 0, 32, 11, 5, { 0, { (1<<MACH_BASE) } }  },
 278   { M32R_F_UIMM16, "f-uimm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } }  },
 279   { M32R_F_UIMM24, "f-uimm24", 0, 32, 8, 24, { 0|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
 280   { M32R_F_HI16, "f-hi16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
 281   { M32R_F_DISP8, "f-disp8", 0, 32, 8, 8, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 282   { M32R_F_DISP16, "f-disp16", 0, 32, 16, 16, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 283   { M32R_F_DISP24, "f-disp24", 0, 32, 8, 24, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 284   { M32R_F_OP23, "f-op23", 0, 32, 9, 3, { 0, { (1<<MACH_BASE) } }  },
 285   { M32R_F_OP3, "f-op3", 0, 32, 14, 2, { 0, { (1<<MACH_BASE) } }  },
 286   { M32R_F_ACC, "f-acc", 0, 32, 8, 1, { 0, { (1<<MACH_BASE) } }  },
 287   { M32R_F_ACCS, "f-accs", 0, 32, 12, 2, { 0, { (1<<MACH_BASE) } }  },
 288   { M32R_F_ACCD, "f-accd", 0, 32, 4, 2, { 0, { (1<<MACH_BASE) } }  },
 289   { M32R_F_BITS67, "f-bits67", 0, 32, 6, 2, { 0, { (1<<MACH_BASE) } }  },
 290   { M32R_F_BIT14, "f-bit14", 0, 32, 14, 1, { 0, { (1<<MACH_BASE) } }  },
 291   { M32R_F_IMM1, "f-imm1", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } }  },
 292   { 0, 0, 0, 0, 0, 0, {0, {0}} }
 293 };
 294
 295 #undef A
 296
 297
 298 /* The operand table.  */
 299
 300 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 301 #define A(a) (1 << CGEN_OPERAND_##a)
 302 #else
 303 #define A(a) (1 << CGEN_OPERAND_/**/a)
 304 #endif
 305 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 306 #define OPERAND(op) M32R_OPERAND_##op
 307 #else
 308 #define OPERAND(op) M32R_OPERAND_/**/op
 309 #endif
 310
 311 const CGEN_OPERAND m32r_cgen_operand_table[] =
 312 {
 313 /* pc: program counter */
 314   { "pc", M32R_OPERAND_PC, HW_H_PC, 0, 0,
 315     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 316 /* sr: source register */
 317   { "sr", M32R_OPERAND_SR, HW_H_GR, 12, 4,
 318     { 0, { (1<<MACH_BASE) } }  },
 319 /* dr: destination register */
 320   { "dr", M32R_OPERAND_DR, HW_H_GR, 4, 4,
 321     { 0, { (1<<MACH_BASE) } }  },
 322 /* src1: source register 1 */
 323   { "src1", M32R_OPERAND_SRC1, HW_H_GR, 4, 4,
 324     { 0, { (1<<MACH_BASE) } }  },
 325 /* src2: source register 2 */
 326   { "src2", M32R_OPERAND_SRC2, HW_H_GR, 12, 4,
 327     { 0, { (1<<MACH_BASE) } }  },
 328 /* scr: source control register */
 329   { "scr", M32R_OPERAND_SCR, HW_H_CR, 12, 4,
 330     { 0, { (1<<MACH_BASE) } }  },
 331 /* dcr: destination control register */
 332   { "dcr", M32R_OPERAND_DCR, HW_H_CR, 4, 4,
 333     { 0, { (1<<MACH_BASE) } }  },
 334 /* simm8: 8 bit signed immediate */
 335   { "simm8", M32R_OPERAND_SIMM8, HW_H_SINT, 8, 8,
 336     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 337 /* simm16: 16 bit signed immediate */
 338   { "simm16", M32R_OPERAND_SIMM16, HW_H_SINT, 16, 16,
 339     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 340 /* uimm4: 4 bit trap number */
 341   { "uimm4", M32R_OPERAND_UIMM4, HW_H_UINT, 12, 4,
 342     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 343 /* uimm5: 5 bit shift count */
 344   { "uimm5", M32R_OPERAND_UIMM5, HW_H_UINT, 11, 5,
 345     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 346 /* uimm16: 16 bit unsigned immediate */
 347   { "uimm16", M32R_OPERAND_UIMM16, HW_H_UINT, 16, 16,
 348     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 349 /* imm1: 1 bit immediate */
 350   { "imm1", M32R_OPERAND_IMM1, HW_H_UINT, 15, 1,
 351     { 0|A(HASH_PREFIX), { (1<<MACH_M32RX) } }  },
 352 /* accd: accumulator destination register */
 353   { "accd", M32R_OPERAND_ACCD, HW_H_ACCUMS, 4, 2,
 354     { 0, { (1<<MACH_M32RX) } }  },
 355 /* accs: accumulator source register */
 356   { "accs", M32R_OPERAND_ACCS, HW_H_ACCUMS, 12, 2,
 357     { 0, { (1<<MACH_M32RX) } }  },
 358 /* acc: accumulator reg (d) */
 359   { "acc", M32R_OPERAND_ACC, HW_H_ACCUMS, 8, 1,
 360     { 0, { (1<<MACH_M32RX) } }  },
 361 /* hash: # prefix */
 362   { "hash", M32R_OPERAND_HASH, HW_H_SINT, 0, 0,
 363     { 0, { (1<<MACH_BASE) } }  },
 364 /* hi16: high 16 bit immediate, sign optional */
 365   { "hi16", M32R_OPERAND_HI16, HW_H_HI16, 16, 16,
 366     { 0|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
 367 /* slo16: 16 bit signed immediate, for low() */
 368   { "slo16", M32R_OPERAND_SLO16, HW_H_SLO16, 16, 16,
 369     { 0, { (1<<MACH_BASE) } }  },
 370 /* ulo16: 16 bit unsigned immediate, for low() */
 371   { "ulo16", M32R_OPERAND_ULO16, HW_H_ULO16, 16, 16,
 372     { 0, { (1<<MACH_BASE) } }  },
 373 /* uimm24: 24 bit address */
 374   { "uimm24", M32R_OPERAND_UIMM24, HW_H_ADDR, 8, 24,
 375     { 0|A(HASH_PREFIX)|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
 376 /* disp8: 8 bit displacement */
 377   { "disp8", M32R_OPERAND_DISP8, HW_H_IADDR, 8, 8,
 378     { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 379 /* disp16: 16 bit displacement */
 380   { "disp16", M32R_OPERAND_DISP16, HW_H_IADDR, 16, 16,
 381     { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 382 /* disp24: 24 bit displacement */
 383   { "disp24", M32R_OPERAND_DISP24, HW_H_IADDR, 8, 24,
 384     { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 385 /* condbit: condition bit */
 386   { "condbit", M32R_OPERAND_CONDBIT, HW_H_COND, 0, 0,
 387     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 388 /* accum: accumulator */
 389   { "accum", M32R_OPERAND_ACCUM, HW_H_ACCUM, 0, 0,
 390     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 391   { 0, 0, 0, 0, 0, {0, {0}} }
 392 };
 393
 394 #undef A
 395
 396
 397 /* The instruction table.  */
 398
 399 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
 400 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 401 #define A(a) (1 << CGEN_INSN_##a)
 402 #else
 403 #define A(a) (1 << CGEN_INSN_/**/a)
 404 #endif
 405
 406 static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 407 {
 408   /* Special null first entry.
 409      A `num' value of zero is thus invalid.
 410      Also, the special `invalid' insn resides here.  */
 411   { 0, 0, 0, 0, {0, {0}} },
 412 /* add $dr,$sr */
 413   {
 414     M32R_INSN_ADD, "add", "add", 16,
 415     { 0, { (1<<MACH_BASE), PIPE_OS } }
 416   },
 417 /* add3 $dr,$sr,$hash$slo16 */
 418   {
 419     M32R_INSN_ADD3, "add3", "add3", 32,
 420     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 421   },
 422 /* and $dr,$sr */
 423   {
 424     M32R_INSN_AND, "and", "and", 16,
 425     { 0, { (1<<MACH_BASE), PIPE_OS } }
 426   },
 427 /* and3 $dr,$sr,$uimm16 */
 428   {
 429     M32R_INSN_AND3, "and3", "and3", 32,
 430     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 431   },
 432 /* or $dr,$sr */
 433   {
 434     M32R_INSN_OR, "or", "or", 16,
 435     { 0, { (1<<MACH_BASE), PIPE_OS } }
 436   },
 437 /* or3 $dr,$sr,$hash$ulo16 */
 438   {
 439     M32R_INSN_OR3, "or3", "or3", 32,
 440     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 441   },
 442 /* xor $dr,$sr */
 443   {
 444     M32R_INSN_XOR, "xor", "xor", 16,
 445     { 0, { (1<<MACH_BASE), PIPE_OS } }
 446   },
 447 /* xor3 $dr,$sr,$uimm16 */
 448   {
 449     M32R_INSN_XOR3, "xor3", "xor3", 32,
 450     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 451   },
 452 /* addi $dr,$simm8 */
 453   {
 454     M32R_INSN_ADDI, "addi", "addi", 16,
 455     { 0, { (1<<MACH_BASE), PIPE_OS } }
 456   },
 457 /* addv $dr,$sr */
 458   {
 459     M32R_INSN_ADDV, "addv", "addv", 16,
 460     { 0, { (1<<MACH_BASE), PIPE_OS } }
 461   },
 462 /* addv3 $dr,$sr,$simm16 */
 463   {
 464     M32R_INSN_ADDV3, "addv3", "addv3", 32,
 465     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 466   },
 467 /* addx $dr,$sr */
 468   {
 469     M32R_INSN_ADDX, "addx", "addx", 16,
 470     { 0, { (1<<MACH_BASE), PIPE_OS } }
 471   },
 472 /* bc.s $disp8 */
 473   {
 474     M32R_INSN_BC8, "bc8", "bc.s", 16,
 475     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
 476   },
 477 /* bc.l $disp24 */
 478   {
 479     M32R_INSN_BC24, "bc24", "bc.l", 32,
 480     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 481   },
 482 /* beq $src1,$src2,$disp16 */
 483   {
 484     M32R_INSN_BEQ, "beq", "beq", 32,
 485     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 486   },
 487 /* beqz $src2,$disp16 */
 488   {
 489     M32R_INSN_BEQZ, "beqz", "beqz", 32,
 490     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 491   },
 492 /* bgez $src2,$disp16 */
 493   {
 494     M32R_INSN_BGEZ, "bgez", "bgez", 32,
 495     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 496   },
 497 /* bgtz $src2,$disp16 */
 498   {
 499     M32R_INSN_BGTZ, "bgtz", "bgtz", 32,
 500     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 501   },
 502 /* blez $src2,$disp16 */
 503   {
 504     M32R_INSN_BLEZ, "blez", "blez", 32,
 505     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 506   },
 507 /* bltz $src2,$disp16 */
 508   {
 509     M32R_INSN_BLTZ, "bltz", "bltz", 32,
 510     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 511   },
 512 /* bnez $src2,$disp16 */
 513   {
 514     M32R_INSN_BNEZ, "bnez", "bnez", 32,
 515     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 516   },
 517 /* bl.s $disp8 */
 518   {
 519     M32R_INSN_BL8, "bl8", "bl.s", 16,
 520     { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
 521   },
 522 /* bl.l $disp24 */
 523   {
 524     M32R_INSN_BL24, "bl24", "bl.l", 32,
 525     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 526   },
 527 /* bcl.s $disp8 */
 528   {
 529     M32R_INSN_BCL8, "bcl8", "bcl.s", 16,
 530     { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
 531   },
 532 /* bcl.l $disp24 */
 533   {
 534     M32R_INSN_BCL24, "bcl24", "bcl.l", 32,
 535     { 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
 536   },
 537 /* bnc.s $disp8 */
 538   {
 539     M32R_INSN_BNC8, "bnc8", "bnc.s", 16,
 540     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
 541   },
 542 /* bnc.l $disp24 */
 543   {
 544     M32R_INSN_BNC24, "bnc24", "bnc.l", 32,
 545     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 546   },
 547 /* bne $src1,$src2,$disp16 */
 548   {
 549     M32R_INSN_BNE, "bne", "bne", 32,
 550     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 551   },
 552 /* bra.s $disp8 */
 553   {
 554     M32R_INSN_BRA8, "bra8", "bra.s", 16,
 555     { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
 556   },
 557 /* bra.l $disp24 */
 558   {
 559     M32R_INSN_BRA24, "bra24", "bra.l", 32,
 560     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 561   },
 562 /* bncl.s $disp8 */
 563   {
 564     M32R_INSN_BNCL8, "bncl8", "bncl.s", 16,
 565     { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
 566   },
 567 /* bncl.l $disp24 */
 568   {
 569     M32R_INSN_BNCL24, "bncl24", "bncl.l", 32,
 570     { 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
 571   },
 572 /* cmp $src1,$src2 */
 573   {
 574     M32R_INSN_CMP, "cmp", "cmp", 16,
 575     { 0, { (1<<MACH_BASE), PIPE_OS } }
 576   },
 577 /* cmpi $src2,$simm16 */
 578   {
 579     M32R_INSN_CMPI, "cmpi", "cmpi", 32,
 580     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 581   },
 582 /* cmpu $src1,$src2 */
 583   {
 584     M32R_INSN_CMPU, "cmpu", "cmpu", 16,
 585     { 0, { (1<<MACH_BASE), PIPE_OS } }
 586   },
 587 /* cmpui $src2,$simm16 */
 588   {
 589     M32R_INSN_CMPUI, "cmpui", "cmpui", 32,
 590     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 591   },
 592 /* cmpeq $src1,$src2 */
 593   {
 594     M32R_INSN_CMPEQ, "cmpeq", "cmpeq", 16,
 595     { 0, { (1<<MACH_M32RX), PIPE_OS } }
 596   },
 597 /* cmpz $src2 */
 598   {
 599     M32R_INSN_CMPZ, "cmpz", "cmpz", 16,
 600     { 0, { (1<<MACH_M32RX), PIPE_OS } }
 601   },
 602 /* div $dr,$sr */
 603   {
 604     M32R_INSN_DIV, "div", "div", 32,
 605     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 606   },
 607 /* divu $dr,$sr */
 608   {
 609     M32R_INSN_DIVU, "divu", "divu", 32,
 610     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 611   },
 612 /* rem $dr,$sr */
 613   {
 614     M32R_INSN_REM, "rem", "rem", 32,
 615     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 616   },
 617 /* remu $dr,$sr */
 618   {
 619     M32R_INSN_REMU, "remu", "remu", 32,
 620     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 621   },
 622 /* divh $dr,$sr */
 623   {
 624     M32R_INSN_DIVH, "divh", "divh", 32,
 625     { 0, { (1<<MACH_M32RX), PIPE_NONE } }
 626   },
 627 /* jc $sr */
 628   {
 629     M32R_INSN_JC, "jc", "jc", 16,
 630     { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
 631   },
 632 /* jnc $sr */
 633   {
 634     M32R_INSN_JNC, "jnc", "jnc", 16,
 635     { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
 636   },
 637 /* jl $sr */
 638   {
 639     M32R_INSN_JL, "jl", "jl", 16,
 640     { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
 641   },
 642 /* jmp $sr */
 643   {
 644     M32R_INSN_JMP, "jmp", "jmp", 16,
 645     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
 646   },
 647 /* ld $dr,@$sr */
 648   {
 649     M32R_INSN_LD, "ld", "ld", 16,
 650     { 0, { (1<<MACH_BASE), PIPE_O } }
 651   },
 652 /* ld $dr,@($slo16,$sr) */
 653   {
 654     M32R_INSN_LD_D, "ld-d", "ld", 32,
 655     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 656   },
 657 /* ldb $dr,@$sr */
 658   {
 659     M32R_INSN_LDB, "ldb", "ldb", 16,
 660     { 0, { (1<<MACH_BASE), PIPE_O } }
 661   },
 662 /* ldb $dr,@($slo16,$sr) */
 663   {
 664     M32R_INSN_LDB_D, "ldb-d", "ldb", 32,
 665     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 666   },
 667 /* ldh $dr,@$sr */
 668   {
 669     M32R_INSN_LDH, "ldh", "ldh", 16,
 670     { 0, { (1<<MACH_BASE), PIPE_O } }
 671   },
 672 /* ldh $dr,@($slo16,$sr) */
 673   {
 674     M32R_INSN_LDH_D, "ldh-d", "ldh", 32,
 675     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 676   },
 677 /* ldub $dr,@$sr */
 678   {
 679     M32R_INSN_LDUB, "ldub", "ldub", 16,
 680     { 0, { (1<<MACH_BASE), PIPE_O } }
 681   },
 682 /* ldub $dr,@($slo16,$sr) */
 683   {
 684     M32R_INSN_LDUB_D, "ldub-d", "ldub", 32,
 685     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 686   },
 687 /* lduh $dr,@$sr */
 688   {
 689     M32R_INSN_LDUH, "lduh", "lduh", 16,
 690     { 0, { (1<<MACH_BASE), PIPE_O } }
 691   },
 692 /* lduh $dr,@($slo16,$sr) */
 693   {
 694     M32R_INSN_LDUH_D, "lduh-d", "lduh", 32,
 695     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 696   },
 697 /* ld $dr,@$sr+ */
 698   {
 699     M32R_INSN_LD_PLUS, "ld-plus", "ld", 16,
 700     { 0, { (1<<MACH_BASE), PIPE_O } }
 701   },
 702 /* ld24 $dr,$uimm24 */
 703   {
 704     M32R_INSN_LD24, "ld24", "ld24", 32,
 705     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 706   },
 707 /* ldi8 $dr,$simm8 */
 708   {
 709     M32R_INSN_LDI8, "ldi8", "ldi8", 16,
 710     { 0, { (1<<MACH_BASE), PIPE_OS } }
 711   },
 712 /* ldi16 $dr,$hash$slo16 */
 713   {
 714     M32R_INSN_LDI16, "ldi16", "ldi16", 32,
 715     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 716   },
 717 /* lock $dr,@$sr */
 718   {
 719     M32R_INSN_LOCK, "lock", "lock", 16,
 720     { 0, { (1<<MACH_BASE), PIPE_O } }
 721   },
 722 /* machi $src1,$src2 */
 723   {
 724     M32R_INSN_MACHI, "machi", "machi", 16,
 725     { 0, { (1<<MACH_M32R), PIPE_S } }
 726   },
 727 /* machi $src1,$src2,$acc */
 728   {
 729     M32R_INSN_MACHI_A, "machi-a", "machi", 16,
 730     { 0, { (1<<MACH_M32RX), PIPE_S } }
 731   },
 732 /* maclo $src1,$src2 */
 733   {
 734     M32R_INSN_MACLO, "maclo", "maclo", 16,
 735     { 0, { (1<<MACH_M32R), PIPE_S } }
 736   },
 737 /* maclo $src1,$src2,$acc */
 738   {
 739     M32R_INSN_MACLO_A, "maclo-a", "maclo", 16,
 740     { 0, { (1<<MACH_M32RX), PIPE_S } }
 741   },
 742 /* macwhi $src1,$src2 */
 743   {
 744     M32R_INSN_MACWHI, "macwhi", "macwhi", 16,
 745     { 0, { (1<<MACH_M32R), PIPE_S } }
 746   },
 747 /* macwhi $src1,$src2,$acc */
 748   {
 749     M32R_INSN_MACWHI_A, "macwhi-a", "macwhi", 16,
 750     { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
 751   },
 752 /* macwlo $src1,$src2 */
 753   {
 754     M32R_INSN_MACWLO, "macwlo", "macwlo", 16,
 755     { 0, { (1<<MACH_M32R), PIPE_S } }
 756   },
 757 /* macwlo $src1,$src2,$acc */
 758   {
 759     M32R_INSN_MACWLO_A, "macwlo-a", "macwlo", 16,
 760     { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
 761   },
 762 /* mul $dr,$sr */
 763   {
 764     M32R_INSN_MUL, "mul", "mul", 16,
 765     { 0, { (1<<MACH_BASE), PIPE_S } }
 766   },
 767 /* mulhi $src1,$src2 */
 768   {
 769     M32R_INSN_MULHI, "mulhi", "mulhi", 16,
 770     { 0, { (1<<MACH_M32R), PIPE_S } }
 771   },
 772 /* mulhi $src1,$src2,$acc */
 773   {
 774     M32R_INSN_MULHI_A, "mulhi-a", "mulhi", 16,
 775     { 0, { (1<<MACH_M32RX), PIPE_S } }
 776   },
 777 /* mullo $src1,$src2 */
 778   {
 779     M32R_INSN_MULLO, "mullo", "mullo", 16,
 780     { 0, { (1<<MACH_M32R), PIPE_S } }
 781   },
 782 /* mullo $src1,$src2,$acc */
 783   {
 784     M32R_INSN_MULLO_A, "mullo-a", "mullo", 16,
 785     { 0, { (1<<MACH_M32RX), PIPE_S } }
 786   },
 787 /* mulwhi $src1,$src2 */
 788   {
 789     M32R_INSN_MULWHI, "mulwhi", "mulwhi", 16,
 790     { 0, { (1<<MACH_M32R), PIPE_S } }
 791   },
 792 /* mulwhi $src1,$src2,$acc */
 793   {
 794     M32R_INSN_MULWHI_A, "mulwhi-a", "mulwhi", 16,
 795     { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
 796   },
 797 /* mulwlo $src1,$src2 */
 798   {
 799     M32R_INSN_MULWLO, "mulwlo", "mulwlo", 16,
 800     { 0, { (1<<MACH_M32R), PIPE_S } }
 801   },
 802 /* mulwlo $src1,$src2,$acc */
 803   {
 804     M32R_INSN_MULWLO_A, "mulwlo-a", "mulwlo", 16,
 805     { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
 806   },
 807 /* mv $dr,$sr */
 808   {
 809     M32R_INSN_MV, "mv", "mv", 16,
 810     { 0, { (1<<MACH_BASE), PIPE_OS } }
 811   },
 812 /* mvfachi $dr */
 813   {
 814     M32R_INSN_MVFACHI, "mvfachi", "mvfachi", 16,
 815     { 0, { (1<<MACH_M32R), PIPE_S } }
 816   },
 817 /* mvfachi $dr,$accs */
 818   {
 819     M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi", 16,
 820     { 0, { (1<<MACH_M32RX), PIPE_S } }
 821   },
 822 /* mvfaclo $dr */
 823   {
 824     M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo", 16,
 825     { 0, { (1<<MACH_M32R), PIPE_S } }
 826   },
 827 /* mvfaclo $dr,$accs */
 828   {
 829     M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo", 16,
 830     { 0, { (1<<MACH_M32RX), PIPE_S } }
 831   },
 832 /* mvfacmi $dr */
 833   {
 834     M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi", 16,
 835     { 0, { (1<<MACH_M32R), PIPE_S } }
 836   },
 837 /* mvfacmi $dr,$accs */
 838   {
 839     M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi", 16,
 840     { 0, { (1<<MACH_M32RX), PIPE_S } }
 841   },
 842 /* mvfc $dr,$scr */
 843   {
 844     M32R_INSN_MVFC, "mvfc", "mvfc", 16,
 845     { 0, { (1<<MACH_BASE), PIPE_O } }
 846   },
 847 /* mvtachi $src1 */
 848   {
 849     M32R_INSN_MVTACHI, "mvtachi", "mvtachi", 16,
 850     { 0, { (1<<MACH_M32R), PIPE_S } }
 851   },
 852 /* mvtachi $src1,$accs */
 853   {
 854     M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi", 16,
 855     { 0, { (1<<MACH_M32RX), PIPE_S } }
 856   },
 857 /* mvtaclo $src1 */
 858   {
 859     M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo", 16,
 860     { 0, { (1<<MACH_M32R), PIPE_S } }
 861   },
 862 /* mvtaclo $src1,$accs */
 863   {
 864     M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo", 16,
 865     { 0, { (1<<MACH_M32RX), PIPE_S } }
 866   },
 867 /* mvtc $sr,$dcr */
 868   {
 869     M32R_INSN_MVTC, "mvtc", "mvtc", 16,
 870     { 0, { (1<<MACH_BASE), PIPE_O } }
 871   },
 872 /* neg $dr,$sr */
 873   {
 874     M32R_INSN_NEG, "neg", "neg", 16,
 875     { 0, { (1<<MACH_BASE), PIPE_OS } }
 876   },
 877 /* nop */
 878   {
 879     M32R_INSN_NOP, "nop", "nop", 16,
 880     { 0, { (1<<MACH_BASE), PIPE_OS } }
 881   },
 882 /* not $dr,$sr */
 883   {
 884     M32R_INSN_NOT, "not", "not", 16,
 885     { 0, { (1<<MACH_BASE), PIPE_OS } }
 886   },
 887 /* rac */
 888   {
 889     M32R_INSN_RAC, "rac", "rac", 16,
 890     { 0, { (1<<MACH_M32R), PIPE_S } }
 891   },
 892 /* rac $accd,$accs,$imm1 */
 893   {
 894     M32R_INSN_RAC_DSI, "rac-dsi", "rac", 16,
 895     { 0, { (1<<MACH_M32RX), PIPE_S } }
 896   },
 897 /* rach */
 898   {
 899     M32R_INSN_RACH, "rach", "rach", 16,
 900     { 0, { (1<<MACH_M32R), PIPE_S } }
 901   },
 902 /* rach $accd,$accs,$imm1 */
 903   {
 904     M32R_INSN_RACH_DSI, "rach-dsi", "rach", 16,
 905     { 0, { (1<<MACH_M32RX), PIPE_S } }
 906   },
 907 /* rte */
 908   {
 909     M32R_INSN_RTE, "rte", "rte", 16,
 910     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
 911   },
 912 /* seth $dr,$hash$hi16 */
 913   {
 914     M32R_INSN_SETH, "seth", "seth", 32,
 915     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 916   },
 917 /* sll $dr,$sr */
 918   {
 919     M32R_INSN_SLL, "sll", "sll", 16,
 920     { 0, { (1<<MACH_BASE), PIPE_O } }
 921   },
 922 /* sll3 $dr,$sr,$simm16 */
 923   {
 924     M32R_INSN_SLL3, "sll3", "sll3", 32,
 925     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 926   },
 927 /* slli $dr,$uimm5 */
 928   {
 929     M32R_INSN_SLLI, "slli", "slli", 16,
 930     { 0, { (1<<MACH_BASE), PIPE_O } }
 931   },
 932 /* sra $dr,$sr */
 933   {
 934     M32R_INSN_SRA, "sra", "sra", 16,
 935     { 0, { (1<<MACH_BASE), PIPE_O } }
 936   },
 937 /* sra3 $dr,$sr,$simm16 */
 938   {
 939     M32R_INSN_SRA3, "sra3", "sra3", 32,
 940     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 941   },
 942 /* srai $dr,$uimm5 */
 943   {
 944     M32R_INSN_SRAI, "srai", "srai", 16,
 945     { 0, { (1<<MACH_BASE), PIPE_O } }
 946   },
 947 /* srl $dr,$sr */
 948   {
 949     M32R_INSN_SRL, "srl", "srl", 16,
 950     { 0, { (1<<MACH_BASE), PIPE_O } }
 951   },
 952 /* srl3 $dr,$sr,$simm16 */
 953   {
 954     M32R_INSN_SRL3, "srl3", "srl3", 32,
 955     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 956   },
 957 /* srli $dr,$uimm5 */
 958   {
 959     M32R_INSN_SRLI, "srli", "srli", 16,
 960     { 0, { (1<<MACH_BASE), PIPE_O } }
 961   },
 962 /* st $src1,@$src2 */
 963   {
 964     M32R_INSN_ST, "st", "st", 16,
 965     { 0, { (1<<MACH_BASE), PIPE_O } }
 966   },
 967 /* st $src1,@($slo16,$src2) */
 968   {
 969     M32R_INSN_ST_D, "st-d", "st", 32,
 970     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 971   },
 972 /* stb $src1,@$src2 */
 973   {
 974     M32R_INSN_STB, "stb", "stb", 16,
 975     { 0, { (1<<MACH_BASE), PIPE_O } }
 976   },
 977 /* stb $src1,@($slo16,$src2) */
 978   {
 979     M32R_INSN_STB_D, "stb-d", "stb", 32,
 980     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 981   },
 982 /* sth $src1,@$src2 */
 983   {
 984     M32R_INSN_STH, "sth", "sth", 16,
 985     { 0, { (1<<MACH_BASE), PIPE_O } }
 986   },
 987 /* sth $src1,@($slo16,$src2) */
 988   {
 989     M32R_INSN_STH_D, "sth-d", "sth", 32,
 990     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 991   },
 992 /* st $src1,@+$src2 */
 993   {
 994     M32R_INSN_ST_PLUS, "st-plus", "st", 16,
 995     { 0, { (1<<MACH_BASE), PIPE_O } }
 996   },
 997 /* st $src1,@-$src2 */
 998   {
 999     M32R_INSN_ST_MINUS, "st-minus", "st", 16,
1000     { 0, { (1<<MACH_BASE), PIPE_O } }
1001   },
1002 /* sub $dr,$sr */
1003   {
1004     M32R_INSN_SUB, "sub", "sub", 16,
1005     { 0, { (1<<MACH_BASE), PIPE_OS } }
1006   },
1007 /* subv $dr,$sr */
1008   {
1009     M32R_INSN_SUBV, "subv", "subv", 16,
1010     { 0, { (1<<MACH_BASE), PIPE_OS } }
1011   },
1012 /* subx $dr,$sr */
1013   {
1014     M32R_INSN_SUBX, "subx", "subx", 16,
1015     { 0, { (1<<MACH_BASE), PIPE_OS } }
1016   },
1017 /* trap $uimm4 */
1018   {
1019     M32R_INSN_TRAP, "trap", "trap", 16,
1020     { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
1021   },
1022 /* unlock $src1,@$src2 */
1023   {
1024     M32R_INSN_UNLOCK, "unlock", "unlock", 16,
1025     { 0, { (1<<MACH_BASE), PIPE_O } }
1026   },
1027 /* satb $dr,$sr */
1028   {
1029     M32R_INSN_SATB, "satb", "satb", 32,
1030     { 0, { (1<<MACH_M32RX), PIPE_NONE } }
1031   },
1032 /* sath $dr,$sr */
1033   {
1034     M32R_INSN_SATH, "sath", "sath", 32,
1035     { 0, { (1<<MACH_M32RX), PIPE_NONE } }
1036   },
1037 /* sat $dr,$sr */
1038   {
1039     M32R_INSN_SAT, "sat", "sat", 32,
1040     { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_NONE } }
1041   },
1042 /* pcmpbz $src2 */
1043   {
1044     M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz", 16,
1045     { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_OS } }
1046   },
1047 /* sadd */
1048   {
1049     M32R_INSN_SADD, "sadd", "sadd", 16,
1050     { 0, { (1<<MACH_M32RX), PIPE_S } }
1051   },
1052 /* macwu1 $src1,$src2 */
1053   {
1054     M32R_INSN_MACWU1, "macwu1", "macwu1", 16,
1055     { 0, { (1<<MACH_M32RX), PIPE_S } }
1056   },
1057 /* msblo $src1,$src2 */
1058   {
1059     M32R_INSN_MSBLO, "msblo", "msblo", 16,
1060     { 0, { (1<<MACH_M32RX), PIPE_S } }
1061   },
1062 /* mulwu1 $src1,$src2 */
1063   {
1064     M32R_INSN_MULWU1, "mulwu1", "mulwu1", 16,
1065     { 0, { (1<<MACH_M32RX), PIPE_S } }
1066   },
1067 /* maclh1 $src1,$src2 */
1068   {
1069     M32R_INSN_MACLH1, "maclh1", "maclh1", 16,
1070     { 0, { (1<<MACH_M32RX), PIPE_S } }
1071   },
1072 /* sc */
1073   {
1074     M32R_INSN_SC, "sc", "sc", 16,
1075     { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
1076   },
1077 /* snc */
1078   {
1079     M32R_INSN_SNC, "snc", "snc", 16,
1080     { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
1081   },
1082 };
1083
1084 #undef OP
1085 #undef A
1086
1087 /* Initialize anything needed to be done once, before any cpu_open call.  */
1088 static void init_tables PARAMS ((void));
1089
1090 static void
1091 init_tables ()
1092 {
1093 }
1094
1095 static const CGEN_MACH * lookup_mach_via_bfd_name
1096   PARAMS ((const CGEN_MACH *, const char *));
1097 static void build_hw_table  PARAMS ((CGEN_CPU_TABLE *));
1098 static void build_ifield_table  PARAMS ((CGEN_CPU_TABLE *));
1099 static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
1100 static void build_insn_table    PARAMS ((CGEN_CPU_TABLE *));
1101 static void m32r_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
1102
1103 /* Subroutine of m32r_cgen_cpu_open to look up a mach via its bfd name.  */
1104
1105 static const CGEN_MACH *
1106 lookup_mach_via_bfd_name (table, name)
1107      const CGEN_MACH *table;
1108      const char *name;
1109 {
1110   while (table->name)
1111     {
1112       if (strcmp (name, table->bfd_name) == 0)
1113         return table;
1114       ++table;
1115     }
1116   abort ();
1117 }
1118
1119 /* Subroutine of m32r_cgen_cpu_open to build the hardware table.  */
1120
1121 static void
1122 build_hw_table (cd)
1123      CGEN_CPU_TABLE *cd;
1124 {
1125   int i;
1126   int machs = cd->machs;
1127   const CGEN_HW_ENTRY *init = & m32r_cgen_hw_table[0];
1128   /* MAX_HW is only an upper bound on the number of selected entries.
1129      However each entry is indexed by it's enum so there can be holes in
1130      the table.  */
1131   const CGEN_HW_ENTRY **selected =
1132     (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1133
1134   cd->hw_table.init_entries = init;
1135   cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1136   memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1137   /* ??? For now we just use machs to determine which ones we want.  */
1138   for (i = 0; init[i].name != NULL; ++i)
1139     if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1140         & machs)
1141       selected[init[i].type] = &init[i];
1142   cd->hw_table.entries = selected;
1143   cd->hw_table.num_entries = MAX_HW;
1144 }
1145
1146 /* Subroutine of m32r_cgen_cpu_open to build the hardware table.  */
1147
1148 static void
1149 build_ifield_table (cd)
1150      CGEN_CPU_TABLE *cd;
1151 {
1152   cd->ifld_table = & m32r_cgen_ifld_table[0];
1153 }
1154
1155 /* Subroutine of m32r_cgen_cpu_open to build the hardware table.  */
1156
1157 static void
1158 build_operand_table (cd)
1159      CGEN_CPU_TABLE *cd;
1160 {
1161   int i;
1162   int machs = cd->machs;
1163   const CGEN_OPERAND *init = & m32r_cgen_operand_table[0];
1164   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
1165      However each entry is indexed by it's enum so there can be holes in
1166      the table.  */
1167   const CGEN_OPERAND **selected =
1168     (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1169
1170   cd->operand_table.init_entries = init;
1171   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
1172   memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1173   /* ??? For now we just use mach to determine which ones we want.  */
1174   for (i = 0; init[i].name != NULL; ++i)
1175     if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
1176         & machs)
1177       selected[init[i].type] = &init[i];
1178   cd->operand_table.entries = selected;
1179   cd->operand_table.num_entries = MAX_OPERANDS;
1180 }
1181
1182 /* Subroutine of m32r_cgen_cpu_open to build the hardware table.
1183    ??? This could leave out insns not supported by the specified mach/isa,
1184    but that would cause errors like "foo only supported by bar" to become
1185    "unknown insn", so for now we include all insns and require the app to
1186    do the checking later.
1187    ??? On the other hand, parsing of such insns may require their hardware or
1188    operand elements to be in the table [which they mightn't be].  */
1189
1190 static void
1191 build_insn_table (cd)
1192      CGEN_CPU_TABLE *cd;
1193 {
1194   int i;
1195   const CGEN_IBASE *ib = & m32r_cgen_insn_table[0];
1196   CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
1197
1198   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
1199   for (i = 0; i < MAX_INSNS; ++i)
1200     insns[i].base = &ib[i];
1201   cd->insn_table.init_entries = insns;
1202   cd->insn_table.entry_size = sizeof (CGEN_IBASE);
1203   cd->insn_table.num_init_entries = MAX_INSNS;
1204 }
1205
1206 /* Subroutine of m32r_cgen_cpu_open to rebuild the tables.  */
1207
1208 static void
1209 m32r_cgen_rebuild_tables (cd)
1210      CGEN_CPU_TABLE *cd;
1211 {
1212   int i;
1213   unsigned int isas = cd->isas;
1214   unsigned int machs = cd->machs;
1215
1216   cd->int_insn_p = CGEN_INT_INSN_P;
1217
1218   /* Data derived from the isa spec.  */
1219 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
1220   cd->default_insn_bitsize = UNSET;
1221   cd->base_insn_bitsize = UNSET;
1222   cd->min_insn_bitsize = 65535; /* some ridiculously big number */
1223   cd->max_insn_bitsize = 0;
1224   for (i = 0; i < MAX_ISAS; ++i)
1225     if (((1 << i) & isas) != 0)
1226       {
1227         const CGEN_ISA *isa = & m32r_cgen_isa_table[i];
1228
1229         /* Default insn sizes of all selected isas must be equal or we set
1230            the result to 0, meaning "unknown".  */
1231         if (cd->default_insn_bitsize == UNSET)
1232           cd->default_insn_bitsize = isa->default_insn_bitsize;
1233         else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
1234           ; /* this is ok */
1235         else
1236           cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
1237
1238         /* Base insn sizes of all selected isas must be equal or we set
1239            the result to 0, meaning "unknown".  */
1240         if (cd->base_insn_bitsize == UNSET)
1241           cd->base_insn_bitsize = isa->base_insn_bitsize;
1242         else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
1243           ; /* this is ok */
1244         else
1245           cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
1246
1247         /* Set min,max insn sizes.  */
1248         if (isa->min_insn_bitsize < cd->min_insn_bitsize)
1249           cd->min_insn_bitsize = isa->min_insn_bitsize;
1250         if (isa->max_insn_bitsize > cd->max_insn_bitsize)
1251           cd->max_insn_bitsize = isa->max_insn_bitsize;
1252       }
1253
1254   /* Data derived from the mach spec.  */
1255   for (i = 0; i < MAX_MACHS; ++i)
1256     if (((1 << i) & machs) != 0)
1257       {
1258         const CGEN_MACH *mach = & m32r_cgen_mach_table[i];
1259
1260         if (mach->insn_chunk_bitsize != 0)
1261         {
1262           if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
1263             {
1264               fprintf (stderr, "m32r_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
1265                        cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
1266               abort ();
1267             }
1268
1269           cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
1270         }
1271       }
1272
1273   /* Determine which hw elements are used by MACH.  */
1274   build_hw_table (cd);
1275
1276   /* Build the ifield table.  */
1277   build_ifield_table (cd);
1278
1279   /* Determine which operands are used by MACH/ISA.  */
1280   build_operand_table (cd);
1281
1282   /* Build the instruction table.  */
1283   build_insn_table (cd);
1284 }
1285
1286 /* Initialize a cpu table and return a descriptor.
1287    It's much like opening a file, and must be the first function called.
1288    The arguments are a set of (type/value) pairs, terminated with
1289    CGEN_CPU_OPEN_END.
1290
1291    Currently supported values:
1292    CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
1293    CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
1294    CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
1295    CGEN_CPU_OPEN_ENDIAN:  specify endian choice
1296    CGEN_CPU_OPEN_END:     terminates arguments
1297
1298    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
1299    precluded.
1300
1301    ??? We only support ISO C stdargs here, not K&R.
1302    Laziness, plus experiment to see if anything requires K&R - eventually
1303    K&R will no longer be supported - e.g. GDB is currently trying this.  */
1304
1305 CGEN_CPU_DESC
1306 m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
1307 {
1308   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
1309   static int init_p;
1310   unsigned int isas = 0;  /* 0 = "unspecified" */
1311   unsigned int machs = 0; /* 0 = "unspecified" */
1312   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
1313   va_list ap;
1314
1315   if (! init_p)
1316     {
1317       init_tables ();
1318       init_p = 1;
1319     }
1320
1321   memset (cd, 0, sizeof (*cd));
1322
1323   va_start (ap, arg_type);
1324   while (arg_type != CGEN_CPU_OPEN_END)
1325     {
1326       switch (arg_type)
1327         {
1328         case CGEN_CPU_OPEN_ISAS :
1329           isas = va_arg (ap, unsigned int);
1330           break;
1331         case CGEN_CPU_OPEN_MACHS :
1332           machs = va_arg (ap, unsigned int);
1333           break;
1334         case CGEN_CPU_OPEN_BFDMACH :
1335           {
1336             const char *name = va_arg (ap, const char *);
1337             const CGEN_MACH *mach =
1338               lookup_mach_via_bfd_name (m32r_cgen_mach_table, name);
1339
1340             machs |= 1 << mach->num;
1341             break;
1342           }
1343         case CGEN_CPU_OPEN_ENDIAN :
1344           endian = va_arg (ap, enum cgen_endian);
1345           break;
1346         default :
1347           fprintf (stderr, "m32r_cgen_cpu_open: unsupported argument `%d'\n",
1348                    arg_type);
1349           abort (); /* ??? return NULL? */
1350         }
1351       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
1352     }
1353   va_end (ap);
1354
1355   /* mach unspecified means "all" */
1356   if (machs == 0)
1357     machs = (1 << MAX_MACHS) - 1;
1358   /* base mach is always selected */
1359   machs |= 1;
1360   /* isa unspecified means "all" */
1361   if (isas == 0)
1362     isas = (1 << MAX_ISAS) - 1;
1363   if (endian == CGEN_ENDIAN_UNKNOWN)
1364     {
1365       /* ??? If target has only one, could have a default.  */
1366       fprintf (stderr, "m32r_cgen_cpu_open: no endianness specified\n");
1367       abort ();
1368     }
1369
1370   cd->isas = isas;
1371   cd->machs = machs;
1372   cd->endian = endian;
1373   /* FIXME: for the sparc case we can determine insn-endianness statically.
1374      The worry here is where both data and insn endian can be independently
1375      chosen, in which case this function will need another argument.
1376      Actually, will want to allow for more arguments in the future anyway.  */
1377   cd->insn_endian = endian;
1378
1379   /* Table (re)builder.  */
1380   cd->rebuild_tables = m32r_cgen_rebuild_tables;
1381   m32r_cgen_rebuild_tables (cd);
1382
1383   /* Default to not allowing signed overflow.  */
1384   cd->signed_overflow_ok_p = 0;
1385
1386   return (CGEN_CPU_DESC) cd;
1387 }
1388
1389 /* Cover fn to m32r_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
1390    MACH_NAME is the bfd name of the mach.  */
1391
1392 CGEN_CPU_DESC
1393 m32r_cgen_cpu_open_1 (mach_name, endian)
1394      const char *mach_name;
1395      enum cgen_endian endian;
1396 {
1397   return m32r_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
1398                                CGEN_CPU_OPEN_ENDIAN, endian,
1399                                CGEN_CPU_OPEN_END);
1400 }
1401
1402 /* Close a cpu table.
1403    ??? This can live in a machine independent file, but there's currently
1404    no place to put this file (there's no libcgen).  libopcodes is the wrong
1405    place as some simulator ports use this but they don't use libopcodes.  */
1406
1407 void
1408 m32r_cgen_cpu_close (cd)
1409      CGEN_CPU_DESC cd;
1410 {
1411   if (cd->insn_table.init_entries)
1412     free ((CGEN_INSN *) cd->insn_table.init_entries);
1413   if (cd->hw_table.entries)
1414     free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
1415   free (cd);
1416 }
1417