1 /* CPU data header for m32r.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
28 #define CGEN_ARCH m32r
30 /* Given symbol S, return m32r_cgen_<S>. */
31 #define CGEN_SYM(s) CONCAT3 (m32r,_cgen_,s)
33 /* Selected cpu families. */
34 #define HAVE_CPU_M32RBF
35 #define HAVE_CPU_M32RXF
37 #define CGEN_INSN_LSB0_P 0
39 /* Minimum size of any insn (in bytes). */
40 #define CGEN_MIN_INSN_SIZE 2
42 /* Maximum size of any insn (in bytes). */
43 #define CGEN_MAX_INSN_SIZE 4
45 #define CGEN_INT_INSN_P 1
47 /* Maximum number of syntax bytes in an instruction. */
48 #define CGEN_ACTUAL_MAX_SYNTAX_BYTES 15
50 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
51 e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
52 we can't hash on everything up to the space. */
53 #define CGEN_MNEMONIC_OPERANDS
55 /* Maximum number of fields in an instruction. */
56 #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 7
60 /* Enum declaration for insn format enums. */
61 typedef enum insn_op1
{
62 OP1_0
, OP1_1
, OP1_2
, OP1_3
63 , OP1_4
, OP1_5
, OP1_6
, OP1_7
64 , OP1_8
, OP1_9
, OP1_10
, OP1_11
65 , OP1_12
, OP1_13
, OP1_14
, OP1_15
68 /* Enum declaration for op2 enums. */
69 typedef enum insn_op2
{
70 OP2_0
, OP2_1
, OP2_2
, OP2_3
71 , OP2_4
, OP2_5
, OP2_6
, OP2_7
72 , OP2_8
, OP2_9
, OP2_10
, OP2_11
73 , OP2_12
, OP2_13
, OP2_14
, OP2_15
76 /* Enum declaration for . */
77 typedef enum gr_names
{
78 H_GR_FP
= 13, H_GR_LR
= 14, H_GR_SP
= 15, H_GR_R0
= 0
79 , H_GR_R1
= 1, H_GR_R2
= 2, H_GR_R3
= 3, H_GR_R4
= 4
80 , H_GR_R5
= 5, H_GR_R6
= 6, H_GR_R7
= 7, H_GR_R8
= 8
81 , H_GR_R9
= 9, H_GR_R10
= 10, H_GR_R11
= 11, H_GR_R12
= 12
82 , H_GR_R13
= 13, H_GR_R14
= 14, H_GR_R15
= 15
85 /* Enum declaration for . */
86 typedef enum cr_names
{
87 H_CR_PSW
= 0, H_CR_CBR
= 1, H_CR_SPI
= 2, H_CR_SPU
= 3
88 , H_CR_BPC
= 6, H_CR_BBPSW
= 8, H_CR_BBPC
= 14, H_CR_CR0
= 0
89 , H_CR_CR1
= 1, H_CR_CR2
= 2, H_CR_CR3
= 3, H_CR_CR4
= 4
90 , H_CR_CR5
= 5, H_CR_CR6
= 6, H_CR_CR7
= 7, H_CR_CR8
= 8
91 , H_CR_CR9
= 9, H_CR_CR10
= 10, H_CR_CR11
= 11, H_CR_CR12
= 12
92 , H_CR_CR13
= 13, H_CR_CR14
= 14, H_CR_CR15
= 15
97 /* Enum declaration for machine type selection. */
98 typedef enum mach_attr
{
99 MACH_BASE
, MACH_M32R
, MACH_M32RX
, MACH_MAX
102 /* Enum declaration for instruction set selection. */
103 typedef enum isa_attr
{
107 /* Enum declaration for parallel execution pipeline selection. */
108 typedef enum pipe_attr
{
109 PIPE_NONE
, PIPE_O
, PIPE_S
, PIPE_OS
112 /* Number of architecture variants. */
114 #define MAX_MACHS ((int) MACH_MAX)
116 /* Ifield support. */
118 extern const struct cgen_ifld m32r_cgen_ifld_table
[];
120 /* Ifield attribute indices. */
122 /* Enum declaration for cgen_ifld attrs. */
123 typedef enum cgen_ifld_attr
{
124 CGEN_IFLD_VIRTUAL
, CGEN_IFLD_PCREL_ADDR
, CGEN_IFLD_ABS_ADDR
, CGEN_IFLD_RESERVED
125 , CGEN_IFLD_SIGN_OPT
, CGEN_IFLD_SIGNED
, CGEN_IFLD_RELOC
, CGEN_IFLD_END_BOOLS
126 , CGEN_IFLD_START_NBOOLS
= 31, CGEN_IFLD_MACH
, CGEN_IFLD_END_NBOOLS
129 /* Number of non-boolean elements in cgen_ifld_attr. */
130 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
132 /* Enum declaration for m32r ifield types. */
133 typedef enum ifield_type
{
134 M32R_F_NIL
, M32R_F_ANYOF
, M32R_F_OP1
, M32R_F_OP2
135 , M32R_F_COND
, M32R_F_R1
, M32R_F_R2
, M32R_F_SIMM8
136 , M32R_F_SIMM16
, M32R_F_SHIFT_OP2
, M32R_F_UIMM4
, M32R_F_UIMM5
137 , M32R_F_UIMM16
, M32R_F_UIMM24
, M32R_F_HI16
, M32R_F_DISP8
138 , M32R_F_DISP16
, M32R_F_DISP24
, M32R_F_OP23
, M32R_F_OP3
139 , M32R_F_ACC
, M32R_F_ACCS
, M32R_F_ACCD
, M32R_F_BITS67
140 , M32R_F_BIT14
, M32R_F_IMM1
, M32R_F_MAX
143 #define MAX_IFLD ((int) M32R_F_MAX)
145 /* Hardware attribute indices. */
147 /* Enum declaration for cgen_hw attrs. */
148 typedef enum cgen_hw_attr
{
149 CGEN_HW_VIRTUAL
, CGEN_HW_CACHE_ADDR
, CGEN_HW_PC
, CGEN_HW_PROFILE
150 , CGEN_HW_END_BOOLS
, CGEN_HW_START_NBOOLS
= 31, CGEN_HW_MACH
, CGEN_HW_END_NBOOLS
153 /* Number of non-boolean elements in cgen_hw_attr. */
154 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
156 /* Enum declaration for m32r hardware types. */
157 typedef enum cgen_hw_type
{
158 HW_H_MEMORY
, HW_H_SINT
, HW_H_UINT
, HW_H_ADDR
159 , HW_H_IADDR
, HW_H_PC
, HW_H_HI16
, HW_H_SLO16
160 , HW_H_ULO16
, HW_H_GR
, HW_H_CR
, HW_H_ACCUM
161 , HW_H_ACCUMS
, HW_H_COND
, HW_H_PSW
, HW_H_BPSW
162 , HW_H_BBPSW
, HW_H_LOCK
, HW_MAX
165 #define MAX_HW ((int) HW_MAX)
167 /* Operand attribute indices. */
169 /* Enum declaration for cgen_operand attrs. */
170 typedef enum cgen_operand_attr
{
171 CGEN_OPERAND_VIRTUAL
, CGEN_OPERAND_PCREL_ADDR
, CGEN_OPERAND_ABS_ADDR
, CGEN_OPERAND_SIGN_OPT
172 , CGEN_OPERAND_SIGNED
, CGEN_OPERAND_NEGATIVE
, CGEN_OPERAND_RELAX
, CGEN_OPERAND_SEM_ONLY
173 , CGEN_OPERAND_RELOC
, CGEN_OPERAND_HASH_PREFIX
, CGEN_OPERAND_END_BOOLS
, CGEN_OPERAND_START_NBOOLS
= 31
174 , CGEN_OPERAND_MACH
, CGEN_OPERAND_END_NBOOLS
177 /* Number of non-boolean elements in cgen_operand_attr. */
178 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
180 /* Enum declaration for m32r operand types. */
181 typedef enum cgen_operand_type
{
182 M32R_OPERAND_PC
, M32R_OPERAND_SR
, M32R_OPERAND_DR
, M32R_OPERAND_SRC1
183 , M32R_OPERAND_SRC2
, M32R_OPERAND_SCR
, M32R_OPERAND_DCR
, M32R_OPERAND_SIMM8
184 , M32R_OPERAND_SIMM16
, M32R_OPERAND_UIMM4
, M32R_OPERAND_UIMM5
, M32R_OPERAND_UIMM16
185 , M32R_OPERAND_IMM1
, M32R_OPERAND_ACCD
, M32R_OPERAND_ACCS
, M32R_OPERAND_ACC
186 , M32R_OPERAND_HASH
, M32R_OPERAND_HI16
, M32R_OPERAND_SLO16
, M32R_OPERAND_ULO16
187 , M32R_OPERAND_UIMM24
, M32R_OPERAND_DISP8
, M32R_OPERAND_DISP16
, M32R_OPERAND_DISP24
188 , M32R_OPERAND_CONDBIT
, M32R_OPERAND_ACCUM
, M32R_OPERAND_MAX
191 /* Number of operands types. */
192 #define MAX_OPERANDS ((int) M32R_OPERAND_MAX)
194 /* Maximum number of operands referenced by any insn. */
195 #define MAX_OPERAND_INSTANCES 11
197 /* Insn attribute indices. */
199 /* Enum declaration for cgen_insn attrs. */
200 typedef enum cgen_insn_attr
{
201 CGEN_INSN_ALIAS
, CGEN_INSN_VIRTUAL
, CGEN_INSN_UNCOND_CTI
, CGEN_INSN_COND_CTI
202 , CGEN_INSN_SKIP_CTI
, CGEN_INSN_DELAY_SLOT
, CGEN_INSN_RELAXABLE
, CGEN_INSN_RELAX
203 , CGEN_INSN_NO_DIS
, CGEN_INSN_PBB
, CGEN_INSN_FILL_SLOT
, CGEN_INSN_SPECIAL
204 , CGEN_INSN_END_BOOLS
, CGEN_INSN_START_NBOOLS
= 31, CGEN_INSN_MACH
, CGEN_INSN_PIPE
205 , CGEN_INSN_END_NBOOLS
208 /* Number of non-boolean elements in cgen_insn_attr. */
209 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
211 /* cgen.h uses things we just defined. */
212 #include "opcode/cgen.h"
215 extern const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table
[];
216 extern const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table
[];
217 extern const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table
[];
218 extern const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table
[];
220 /* Hardware decls. */
222 extern CGEN_KEYWORD m32r_cgen_opval_gr_names
;
223 extern CGEN_KEYWORD m32r_cgen_opval_cr_names
;
224 extern CGEN_KEYWORD m32r_cgen_opval_h_accums
;
229 #endif /* M32R_CPU_H */