opcodes/m32r-dis.c

   1 /* Disassembler interface for targets using CGEN. -*- C -*-
   2    CGEN: Cpu tools GENerator
   3
   4 THIS FILE IS MACHINE GENERATED WITH CGEN.
   5 - the resultant file is machine generated, cgen-dis.in isn't
   6
   7 Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
   8
   9 This file is part of the GNU Binutils and GDB, the GNU debugger.
  10
  11 This program is free software; you can redistribute it and/or modify
  12 it under the terms of the GNU General Public License as published by
  13 the Free Software Foundation; either version 2, or (at your option)
  14 any later version.
  15
  16 This program is distributed in the hope that it will be useful,
  17 but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 GNU General Public License for more details.
  20
  21 You should have received a copy of the GNU General Public License
  22 along with this program; if not, write to the Free Software Foundation, Inc.,
  23 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  24
  25 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
  26    Keep that in mind.  */
  27
  28 #include "sysdep.h"
  29 #include <stdio.h>
  30 #include "ansidecl.h"
  31 #include "dis-asm.h"
  32 #include "bfd.h"
  33 #include "symcat.h"
  34 #include "m32r-desc.h"
  35 #include "m32r-opc.h"
  36 #include "opintl.h"
  37
  38 /* Default text to print if an instruction isn't recognized.  */
  39 #define UNKNOWN_INSN_MSG _("*unknown*")
  40
  41 static void print_normal
  42      PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int));
  43 static void print_address
  44      PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int));
  45 static void print_keyword
  46      PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int));
  47 static void print_insn_normal
  48      PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
  49               bfd_vma, int));
  50 static int print_insn
  51      PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int));
  52 static void print_hash
  53      PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
  54 static int my_print_insn
  55      PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
  56 void m32r_cgen_print_operand
  57      PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int));
  58 static int read_insn
  59      PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int,
  60               CGEN_EXTRACT_INFO *, unsigned long *));
  61 \f
  62 /* -- disassembler routines inserted here */
  63
  64 /* -- dis.c */
  65
  66 /* Immediate values are prefixed with '#'.  */
  67
  68 #define CGEN_PRINT_NORMAL(cd, info, value, attrs, pc, length) \
  69 do { \
  70   if (CGEN_BOOL_ATTR ((attrs), CGEN_OPERAND_HASH_PREFIX)) \
  71     (*info->fprintf_func) (info->stream, "#"); \
  72 } while (0)
  73
  74 /* Handle '#' prefixes as operands.  */
  75
  76 static void
  77 print_hash (cd, dis_info, value, attrs, pc, length)
  78      CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
  79      PTR dis_info;
  80      long value ATTRIBUTE_UNUSED;
  81      unsigned int attrs ATTRIBUTE_UNUSED;
  82      bfd_vma pc ATTRIBUTE_UNUSED;
  83      int length ATTRIBUTE_UNUSED;
  84 {
  85   disassemble_info *info = (disassemble_info *) dis_info;
  86   (*info->fprintf_func) (info->stream, "#");
  87 }
  88
  89 #undef CGEN_PRINT_INSN
  90 #define CGEN_PRINT_INSN my_print_insn
  91
  92 static int
  93 my_print_insn (cd, pc, info)
  94      CGEN_CPU_DESC cd;
  95      bfd_vma pc;
  96      disassemble_info *info;
  97 {
  98   char buffer[CGEN_MAX_INSN_SIZE];
  99   char *buf = buffer;
 100   int status;
 101   int buflen = (pc & 3) == 0 ? 4 : 2;
 102
 103   /* Read the base part of the insn.  */
 104
 105   status = (*info->read_memory_func) (pc, buf, buflen, info);
 106   if (status != 0)
 107     {
 108       (*info->memory_error_func) (status, pc, info);
 109       return -1;
 110     }
 111
 112   /* 32 bit insn?  */
 113   if ((pc & 3) == 0 && (buf[0] & 0x80) != 0)
 114     return print_insn (cd, pc, info, buf, buflen);
 115
 116   /* Print the first insn.  */
 117   if ((pc & 3) == 0)
 118     {
 119       if (print_insn (cd, pc, info, buf, 2) == 0)
 120         (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
 121       buf += 2;
 122     }
 123
 124   if (buf[0] & 0x80)
 125     {
 126       /* Parallel.  */
 127       (*info->fprintf_func) (info->stream, " || ");
 128       buf[0] &= 0x7f;
 129     }
 130   else
 131     (*info->fprintf_func) (info->stream, " -> ");
 132
 133   /* The "& 3" is to pass a consistent address.
 134      Parallel insns arguably both begin on the word boundary.
 135      Also, branch insns are calculated relative to the word boundary.  */
 136   if (print_insn (cd, pc & ~ (bfd_vma) 3, info, buf, 2) == 0)
 137     (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
 138
 139   return (pc & 3) ? 2 : 4;
 140 }
 141
 142 /* -- */
 143
 144 /* Main entry point for printing operands.
 145    XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
 146    of dis-asm.h on cgen.h.
 147
 148    This function is basically just a big switch statement.  Earlier versions
 149    used tables to look up the function to use, but
 150    - if the table contains both assembler and disassembler functions then
 151      the disassembler contains much of the assembler and vice-versa,
 152    - there's a lot of inlining possibilities as things grow,
 153    - using a switch statement avoids the function call overhead.
 154
 155    This function could be moved into `print_insn_normal', but keeping it
 156    separate makes clear the interface between `print_insn_normal' and each of
 157    the handlers.
 158 */
 159
 160 void
 161 m32r_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
 162      CGEN_CPU_DESC cd;
 163      int opindex;
 164      PTR xinfo;
 165      CGEN_FIELDS *fields;
 166      void const *attrs ATTRIBUTE_UNUSED;
 167      bfd_vma pc;
 168      int length;
 169 {
 170  disassemble_info *info = (disassemble_info *) xinfo;
 171
 172   switch (opindex)
 173     {
 174     case M32R_OPERAND_ACC :
 175       print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_acc, 0);
 176       break;
 177     case M32R_OPERAND_ACCD :
 178       print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_accd, 0);
 179       break;
 180     case M32R_OPERAND_ACCS :
 181       print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_accs, 0);
 182       break;
 183     case M32R_OPERAND_DCR :
 184       print_keyword (cd, info, & m32r_cgen_opval_cr_names, fields->f_r1, 0);
 185       break;
 186     case M32R_OPERAND_DISP16 :
 187       print_address (cd, info, fields->f_disp16, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
 188       break;
 189     case M32R_OPERAND_DISP24 :
 190       print_address (cd, info, fields->f_disp24, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
 191       break;
 192     case M32R_OPERAND_DISP8 :
 193       print_address (cd, info, fields->f_disp8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
 194       break;
 195     case M32R_OPERAND_DR :
 196       print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r1, 0);
 197       break;
 198     case M32R_OPERAND_HASH :
 199       print_hash (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
 200       break;
 201     case M32R_OPERAND_HI16 :
 202       print_normal (cd, info, fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
 203       break;
 204     case M32R_OPERAND_IMM1 :
 205       print_normal (cd, info, fields->f_imm1, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 206       break;
 207     case M32R_OPERAND_SCR :
 208       print_keyword (cd, info, & m32r_cgen_opval_cr_names, fields->f_r2, 0);
 209       break;
 210     case M32R_OPERAND_SIMM16 :
 211       print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 212       break;
 213     case M32R_OPERAND_SIMM8 :
 214       print_normal (cd, info, fields->f_simm8, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 215       break;
 216     case M32R_OPERAND_SLO16 :
 217       print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
 218       break;
 219     case M32R_OPERAND_SR :
 220       print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r2, 0);
 221       break;
 222     case M32R_OPERAND_SRC1 :
 223       print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r1, 0);
 224       break;
 225     case M32R_OPERAND_SRC2 :
 226       print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r2, 0);
 227       break;
 228     case M32R_OPERAND_UIMM16 :
 229       print_normal (cd, info, fields->f_uimm16, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 230       break;
 231     case M32R_OPERAND_UIMM24 :
 232       print_address (cd, info, fields->f_uimm24, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
 233       break;
 234     case M32R_OPERAND_UIMM4 :
 235       print_normal (cd, info, fields->f_uimm4, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 236       break;
 237     case M32R_OPERAND_UIMM5 :
 238       print_normal (cd, info, fields->f_uimm5, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 239       break;
 240     case M32R_OPERAND_ULO16 :
 241       print_normal (cd, info, fields->f_uimm16, 0, pc, length);
 242       break;
 243
 244     default :
 245       /* xgettext:c-format */
 246       fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
 247                opindex);
 248     abort ();
 249   }
 250 }
 251
 252 cgen_print_fn * const m32r_cgen_print_handlers[] =
 253 {
 254   print_insn_normal,
 255 };
 256
 257
 258 void
 259 m32r_cgen_init_dis (cd)
 260      CGEN_CPU_DESC cd;
 261 {
 262   m32r_cgen_init_opcode_table (cd);
 263   m32r_cgen_init_ibld_table (cd);
 264   cd->print_handlers = & m32r_cgen_print_handlers[0];
 265   cd->print_operand = m32r_cgen_print_operand;
 266 }
 267
 268 \f
 269 /* Default print handler.  */
 270
 271 static void
 272 print_normal (cd, dis_info, value, attrs, pc, length)
 273 #ifdef CGEN_PRINT_NORMAL
 274      CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
 275 #else
 276      CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
 277 #endif
 278      PTR dis_info;
 279      long value;
 280      unsigned int attrs;
 281 #ifdef CGEN_PRINT_NORMAL
 282      bfd_vma pc ATTRIBUTE_UNUSED;
 283      int length ATTRIBUTE_UNUSED;
 284 #else
 285      bfd_vma pc ATTRIBUTE_UNUSED;
 286      int length ATTRIBUTE_UNUSED;
 287 #endif
 288 {
 289   disassemble_info *info = (disassemble_info *) dis_info;
 290
 291 #ifdef CGEN_PRINT_NORMAL
 292   CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
 293 #endif
 294
 295   /* Print the operand as directed by the attributes.  */
 296   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
 297     ; /* nothing to do */
 298   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
 299     (*info->fprintf_func) (info->stream, "%ld", value);
 300   else
 301     (*info->fprintf_func) (info->stream, "0x%lx", value);
 302 }
 303
 304 /* Default address handler.  */
 305
 306 static void
 307 print_address (cd, dis_info, value, attrs, pc, length)
 308 #ifdef CGEN_PRINT_NORMAL
 309      CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
 310 #else
 311      CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
 312 #endif
 313      PTR dis_info;
 314      bfd_vma value;
 315      unsigned int attrs;
 316 #ifdef CGEN_PRINT_NORMAL
 317      bfd_vma pc ATTRIBUTE_UNUSED;
 318      int length ATTRIBUTE_UNUSED;
 319 #else
 320      bfd_vma pc ATTRIBUTE_UNUSED;
 321      int length ATTRIBUTE_UNUSED;
 322 #endif
 323 {
 324   disassemble_info *info = (disassemble_info *) dis_info;
 325
 326 #ifdef CGEN_PRINT_ADDRESS
 327   CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
 328 #endif
 329
 330   /* Print the operand as directed by the attributes.  */
 331   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
 332     ; /* nothing to do */
 333   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
 334     (*info->print_address_func) (value, info);
 335   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
 336     (*info->print_address_func) (value, info);
 337   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
 338     (*info->fprintf_func) (info->stream, "%ld", (long) value);
 339   else
 340     (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
 341 }
 342
 343 /* Keyword print handler.  */
 344
 345 static void
 346 print_keyword (cd, dis_info, keyword_table, value, attrs)
 347      CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
 348      PTR dis_info;
 349      CGEN_KEYWORD *keyword_table;
 350      long value;
 351      unsigned int attrs ATTRIBUTE_UNUSED;
 352 {
 353   disassemble_info *info = (disassemble_info *) dis_info;
 354   const CGEN_KEYWORD_ENTRY *ke;
 355
 356   ke = cgen_keyword_lookup_value (keyword_table, value);
 357   if (ke != NULL)
 358     (*info->fprintf_func) (info->stream, "%s", ke->name);
 359   else
 360     (*info->fprintf_func) (info->stream, "???");
 361 }
 362 \f
 363 /* Default insn printer.
 364
 365    DIS_INFO is defined as `PTR' so the disassembler needn't know anything
 366    about disassemble_info.  */
 367
 368 static void
 369 print_insn_normal (cd, dis_info, insn, fields, pc, length)
 370      CGEN_CPU_DESC cd;
 371      PTR dis_info;
 372      const CGEN_INSN *insn;
 373      CGEN_FIELDS *fields;
 374      bfd_vma pc;
 375      int length;
 376 {
 377   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
 378   disassemble_info *info = (disassemble_info *) dis_info;
 379   const CGEN_SYNTAX_CHAR_TYPE *syn;
 380
 381   CGEN_INIT_PRINT (cd);
 382
 383   for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
 384     {
 385       if (CGEN_SYNTAX_MNEMONIC_P (*syn))
 386         {
 387           (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
 388           continue;
 389         }
 390       if (CGEN_SYNTAX_CHAR_P (*syn))
 391         {
 392           (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
 393           continue;
 394         }
 395
 396       /* We have an operand.  */
 397       m32r_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
 398                                  fields, CGEN_INSN_ATTRS (insn), pc, length);
 399     }
 400 }
 401 \f
 402 /* Subroutine of print_insn. Reads an insn into the given buffers and updates
 403    the extract info.
 404    Returns 0 if all is well, non-zero otherwise.  */
 405 static int
 406 read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
 407      CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
 408      bfd_vma pc;
 409      disassemble_info *info;
 410      char *buf;
 411      int buflen;
 412      CGEN_EXTRACT_INFO *ex_info;
 413      unsigned long *insn_value;
 414 {
 415   int status = (*info->read_memory_func) (pc, buf, buflen, info);
 416   if (status != 0)
 417     {
 418       (*info->memory_error_func) (status, pc, info);
 419       return -1;
 420     }
 421
 422   ex_info->dis_info = info;
 423   ex_info->valid = (1 << buflen) - 1;
 424   ex_info->insn_bytes = buf;
 425
 426   *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
 427   return 0;
 428 }
 429
 430 /* Utility to print an insn.
 431    BUF is the base part of the insn, target byte order, BUFLEN bytes long.
 432    The result is the size of the insn in bytes or zero for an unknown insn
 433    or -1 if an error occurs fetching data (memory_error_func will have
 434    been called).  */
 435
 436 static int
 437 print_insn (cd, pc, info, buf, buflen)
 438      CGEN_CPU_DESC cd;
 439      bfd_vma pc;
 440      disassemble_info *info;
 441      char *buf;
 442      int buflen;
 443 {
 444   CGEN_INSN_INT insn_value;
 445   const CGEN_INSN_LIST *insn_list;
 446   CGEN_EXTRACT_INFO ex_info;
 447
 448   /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
 449   insn_value = cgen_get_insn_value (cd, buf, buflen * 8);
 450
 451   /* Fill in ex_info fields like read_insn would.  Don't actually call
 452      read_insn, since the incoming buffer is already read (and possibly
 453      modified a la m32r).  */
 454   ex_info.valid = (1 << buflen) - 1;
 455   ex_info.dis_info = info;
 456   ex_info.insn_bytes = buf;
 457
 458   /* The instructions are stored in hash lists.
 459      Pick the first one and keep trying until we find the right one.  */
 460
 461   insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value);
 462   while (insn_list != NULL)
 463     {
 464       const CGEN_INSN *insn = insn_list->insn;
 465       CGEN_FIELDS fields;
 466       int length;
 467       unsigned long insn_value_cropped;
 468
 469 #ifdef CGEN_VALIDATE_INSN_SUPPORTED
 470       /* not needed as insn shouldn't be in hash lists if not supported */
 471       /* Supported by this cpu?  */
 472       if (! m32r_cgen_insn_supported (cd, insn))
 473         {
 474           insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 475           continue;
 476         }
 477 #endif
 478
 479       /* Basic bit mask must be correct.  */
 480       /* ??? May wish to allow target to defer this check until the extract
 481          handler.  */
 482
 483       /* Base size may exceed this instruction's size.  Extract the
 484          relevant part from the buffer. */
 485       if ((CGEN_INSN_BITSIZE (insn) / 8) < buflen
 486           && (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
 487         insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
 488                                            info->endian == BFD_ENDIAN_BIG);
 489       else
 490         insn_value_cropped = insn_value;
 491
 492       if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
 493           == CGEN_INSN_BASE_VALUE (insn))
 494         {
 495           /* Printing is handled in two passes.  The first pass parses the
 496              machine insn and extracts the fields.  The second pass prints
 497              them.  */
 498
 499           /* Make sure the entire insn is loaded into insn_value, if it
 500              can fit.  */
 501           if ((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize
 502               && ((unsigned) CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
 503             {
 504               unsigned long full_insn_value;
 505               int rc = read_insn (cd, pc, info, buf,
 506                                   CGEN_INSN_BITSIZE (insn) / 8,
 507                                   & ex_info, & full_insn_value);
 508               if (rc != 0)
 509                 return rc;
 510               length = CGEN_EXTRACT_FN (cd, insn)
 511                 (cd, insn, &ex_info, full_insn_value, &fields, pc);
 512             }
 513           else
 514             length = CGEN_EXTRACT_FN (cd, insn)
 515               (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
 516
 517           /* length < 0 -> error */
 518           if (length < 0)
 519             return length;
 520           if (length > 0)
 521             {
 522               CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
 523               /* length is in bits, result is in bytes */
 524               return length / 8;
 525             }
 526         }
 527
 528       insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 529     }
 530
 531   return 0;
 532 }
 533
 534 /* Default value for CGEN_PRINT_INSN.
 535    The result is the size of the insn in bytes or zero for an unknown insn
 536    or -1 if an error occured fetching bytes.  */
 537
 538 #ifndef CGEN_PRINT_INSN
 539 #define CGEN_PRINT_INSN default_print_insn
 540
 541 static int default_print_insn
 542      PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
 543
 544 static int
 545 default_print_insn (cd, pc, info)
 546      CGEN_CPU_DESC cd;
 547      bfd_vma pc;
 548      disassemble_info *info;
 549 {
 550   char buf[CGEN_MAX_INSN_SIZE];
 551   int buflen;
 552   int status;
 553
 554   /* Attempt to read the base part of the insn.  */
 555   buflen = cd->base_insn_bitsize / 8;
 556   status = (*info->read_memory_func) (pc, buf, buflen, info);
 557
 558   /* Try again with the minimum part, if min < base.  */
 559   if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
 560     {
 561       buflen = cd->min_insn_bitsize / 8;
 562       status = (*info->read_memory_func) (pc, buf, buflen, info);
 563     }
 564
 565   if (status != 0)
 566     {
 567       (*info->memory_error_func) (status, pc, info);
 568       return -1;
 569     }
 570
 571   return print_insn (cd, pc, info, buf, buflen);
 572 }
 573 #endif
 574
 575 /* Main entry point.
 576    Print one instruction from PC on INFO->STREAM.
 577    Return the size of the instruction (in bytes).  */
 578
 579 int
 580 print_insn_m32r (pc, info)
 581      bfd_vma pc;
 582      disassemble_info *info;
 583 {
 584   static CGEN_CPU_DESC cd = 0;
 585   static int prev_isa;
 586   static int prev_mach;
 587   static int prev_endian;
 588   int length;
 589   int isa,mach;
 590   int endian = (info->endian == BFD_ENDIAN_BIG
 591                 ? CGEN_ENDIAN_BIG
 592                 : CGEN_ENDIAN_LITTLE);
 593   enum bfd_architecture arch;
 594
 595   /* ??? gdb will set mach but leave the architecture as "unknown" */
 596 #ifndef CGEN_BFD_ARCH
 597 #define CGEN_BFD_ARCH bfd_arch_m32r
 598 #endif
 599   arch = info->arch;
 600   if (arch == bfd_arch_unknown)
 601     arch = CGEN_BFD_ARCH;
 602
 603   /* There's no standard way to compute the machine or isa number
 604      so we leave it to the target.  */
 605 #ifdef CGEN_COMPUTE_MACH
 606   mach = CGEN_COMPUTE_MACH (info);
 607 #else
 608   mach = info->mach;
 609 #endif
 610
 611 #ifdef CGEN_COMPUTE_ISA
 612   isa = CGEN_COMPUTE_ISA (info);
 613 #else
 614   isa = 0;
 615 #endif
 616
 617   /* If we've switched cpu's, close the current table and open a new one.  */
 618   if (cd
 619       && (isa != prev_isa
 620           || mach != prev_mach
 621           || endian != prev_endian))
 622     {
 623       m32r_cgen_cpu_close (cd);
 624       cd = 0;
 625     }
 626
 627   /* If we haven't initialized yet, initialize the opcode table.  */
 628   if (! cd)
 629     {
 630       const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
 631       const char *mach_name;
 632
 633       if (!arch_type)
 634         abort ();
 635       mach_name = arch_type->printable_name;
 636
 637       prev_isa = isa;
 638       prev_mach = mach;
 639       prev_endian = endian;
 640       cd = m32r_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
 641                                  CGEN_CPU_OPEN_BFDMACH, mach_name,
 642                                  CGEN_CPU_OPEN_ENDIAN, prev_endian,
 643                                  CGEN_CPU_OPEN_END);
 644       if (!cd)
 645         abort ();
 646       m32r_cgen_init_dis (cd);
 647     }
 648
 649   /* We try to have as much common code as possible.
 650      But at this point some targets need to take over.  */
 651   /* ??? Some targets may need a hook elsewhere.  Try to avoid this,
 652      but if not possible try to move this hook elsewhere rather than
 653      have two hooks.  */
 654   length = CGEN_PRINT_INSN (cd, pc, info);
 655   if (length > 0)
 656     return length;
 657   if (length < 0)
 658     return -1;
 659
 660   (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
 661   return cd->default_insn_bitsize / 8;
 662 }