opcodes/m32r-dis.c

   1 /* Disassembler interface for targets using CGEN. -*- C -*-
   2    CGEN: Cpu tools GENerator
   3
   4 THIS FILE IS MACHINE GENERATED WITH CGEN.
   5 - the resultant file is machine generated, cgen-dis.in isn't
   6
   7 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002
   8 Free Software Foundation, Inc.
   9
  10 This file is part of the GNU Binutils and GDB, the GNU debugger.
  11
  12 This program is free software; you can redistribute it and/or modify
  13 it under the terms of the GNU General Public License as published by
  14 the Free Software Foundation; either version 2, or (at your option)
  15 any later version.
  16
  17 This program is distributed in the hope that it will be useful,
  18 but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20 GNU General Public License for more details.
  21
  22 You should have received a copy of the GNU General Public License
  23 along with this program; if not, write to the Free Software Foundation, Inc.,
  24 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  25
  26 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
  27    Keep that in mind.  */
  28
  29 #include "sysdep.h"
  30 #include <stdio.h>
  31 #include "ansidecl.h"
  32 #include "dis-asm.h"
  33 #include "bfd.h"
  34 #include "symcat.h"
  35 #include "libiberty.h"
  36 #include "m32r-desc.h"
  37 #include "m32r-opc.h"
  38 #include "opintl.h"
  39
  40 /* Default text to print if an instruction isn't recognized.  */
  41 #define UNKNOWN_INSN_MSG _("*unknown*")
  42
  43 static void print_normal
  44   (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
  45 static void print_address
  46   (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int);
  47 static void print_keyword
  48   (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int);
  49 static void print_insn_normal
  50   (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
  51 static int print_insn
  52   (CGEN_CPU_DESC, bfd_vma,  disassemble_info *, char *, unsigned);
  53 static int default_print_insn
  54   (CGEN_CPU_DESC, bfd_vma, disassemble_info *);
  55 static int read_insn
  56   (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, CGEN_EXTRACT_INFO *,
  57    unsigned long *);
  58 \f
  59 /* -- disassembler routines inserted here */
  60
  61 /* -- dis.c */
  62 static void print_hash PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
  63 static int my_print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
  64
  65 /* Immediate values are prefixed with '#'.  */
  66
  67 #define CGEN_PRINT_NORMAL(cd, info, value, attrs, pc, length)   \
  68   do                                                            \
  69     {                                                           \
  70       if (CGEN_BOOL_ATTR ((attrs), CGEN_OPERAND_HASH_PREFIX))   \
  71         (*info->fprintf_func) (info->stream, "#");              \
  72     }                                                           \
  73   while (0)
  74
  75 /* Handle '#' prefixes as operands.  */
  76
  77 static void
  78 print_hash (cd, dis_info, value, attrs, pc, length)
  79      CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
  80      PTR dis_info;
  81      long value ATTRIBUTE_UNUSED;
  82      unsigned int attrs ATTRIBUTE_UNUSED;
  83      bfd_vma pc ATTRIBUTE_UNUSED;
  84      int length ATTRIBUTE_UNUSED;
  85 {
  86   disassemble_info *info = (disassemble_info *) dis_info;
  87   (*info->fprintf_func) (info->stream, "#");
  88 }
  89
  90 #undef  CGEN_PRINT_INSN
  91 #define CGEN_PRINT_INSN my_print_insn
  92
  93 static int
  94 my_print_insn (cd, pc, info)
  95      CGEN_CPU_DESC cd;
  96      bfd_vma pc;
  97      disassemble_info *info;
  98 {
  99   char buffer[CGEN_MAX_INSN_SIZE];
 100   char *buf = buffer;
 101   int status;
 102   int buflen = (pc & 3) == 0 ? 4 : 2;
 103
 104   /* Read the base part of the insn.  */
 105
 106   status = (*info->read_memory_func) (pc, buf, buflen, info);
 107   if (status != 0)
 108     {
 109       (*info->memory_error_func) (status, pc, info);
 110       return -1;
 111     }
 112
 113   /* 32 bit insn?  */
 114   if ((pc & 3) == 0 && (buf[0] & 0x80) != 0)
 115     return print_insn (cd, pc, info, buf, buflen);
 116
 117   /* Print the first insn.  */
 118   if ((pc & 3) == 0)
 119     {
 120       if (print_insn (cd, pc, info, buf, 2) == 0)
 121         (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
 122       buf += 2;
 123     }
 124
 125   if (buf[0] & 0x80)
 126     {
 127       /* Parallel.  */
 128       (*info->fprintf_func) (info->stream, " || ");
 129       buf[0] &= 0x7f;
 130     }
 131   else
 132     (*info->fprintf_func) (info->stream, " -> ");
 133
 134   /* The "& 3" is to pass a consistent address.
 135      Parallel insns arguably both begin on the word boundary.
 136      Also, branch insns are calculated relative to the word boundary.  */
 137   if (print_insn (cd, pc & ~ (bfd_vma) 3, info, buf, 2) == 0)
 138     (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
 139
 140   return (pc & 3) ? 2 : 4;
 141 }
 142
 143 /* -- */
 144
 145 void m32r_cgen_print_operand
 146   PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
 147            void const *, bfd_vma, int));
 148
 149 /* Main entry point for printing operands.
 150    XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
 151    of dis-asm.h on cgen.h.
 152
 153    This function is basically just a big switch statement.  Earlier versions
 154    used tables to look up the function to use, but
 155    - if the table contains both assembler and disassembler functions then
 156      the disassembler contains much of the assembler and vice-versa,
 157    - there's a lot of inlining possibilities as things grow,
 158    - using a switch statement avoids the function call overhead.
 159
 160    This function could be moved into `print_insn_normal', but keeping it
 161    separate makes clear the interface between `print_insn_normal' and each of
 162    the handlers.  */
 163
 164 void
 165 m32r_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
 166      CGEN_CPU_DESC cd;
 167      int opindex;
 168      PTR xinfo;
 169      CGEN_FIELDS *fields;
 170      void const *attrs ATTRIBUTE_UNUSED;
 171      bfd_vma pc;
 172      int length;
 173 {
 174  disassemble_info *info = (disassemble_info *) xinfo;
 175
 176   switch (opindex)
 177     {
 178     case M32R_OPERAND_ACC :
 179       print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_acc, 0);
 180       break;
 181     case M32R_OPERAND_ACCD :
 182       print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_accd, 0);
 183       break;
 184     case M32R_OPERAND_ACCS :
 185       print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_accs, 0);
 186       break;
 187     case M32R_OPERAND_DCR :
 188       print_keyword (cd, info, & m32r_cgen_opval_cr_names, fields->f_r1, 0);
 189       break;
 190     case M32R_OPERAND_DISP16 :
 191       print_address (cd, info, fields->f_disp16, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
 192       break;
 193     case M32R_OPERAND_DISP24 :
 194       print_address (cd, info, fields->f_disp24, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
 195       break;
 196     case M32R_OPERAND_DISP8 :
 197       print_address (cd, info, fields->f_disp8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
 198       break;
 199     case M32R_OPERAND_DR :
 200       print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r1, 0);
 201       break;
 202     case M32R_OPERAND_HASH :
 203       print_hash (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
 204       break;
 205     case M32R_OPERAND_HI16 :
 206       print_normal (cd, info, fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
 207       break;
 208     case M32R_OPERAND_IMM1 :
 209       print_normal (cd, info, fields->f_imm1, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 210       break;
 211     case M32R_OPERAND_SCR :
 212       print_keyword (cd, info, & m32r_cgen_opval_cr_names, fields->f_r2, 0);
 213       break;
 214     case M32R_OPERAND_SIMM16 :
 215       print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 216       break;
 217     case M32R_OPERAND_SIMM8 :
 218       print_normal (cd, info, fields->f_simm8, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 219       break;
 220     case M32R_OPERAND_SLO16 :
 221       print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
 222       break;
 223     case M32R_OPERAND_SR :
 224       print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r2, 0);
 225       break;
 226     case M32R_OPERAND_SRC1 :
 227       print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r1, 0);
 228       break;
 229     case M32R_OPERAND_SRC2 :
 230       print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r2, 0);
 231       break;
 232     case M32R_OPERAND_UIMM16 :
 233       print_normal (cd, info, fields->f_uimm16, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 234       break;
 235     case M32R_OPERAND_UIMM24 :
 236       print_address (cd, info, fields->f_uimm24, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
 237       break;
 238     case M32R_OPERAND_UIMM4 :
 239       print_normal (cd, info, fields->f_uimm4, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 240       break;
 241     case M32R_OPERAND_UIMM5 :
 242       print_normal (cd, info, fields->f_uimm5, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
 243       break;
 244     case M32R_OPERAND_ULO16 :
 245       print_normal (cd, info, fields->f_uimm16, 0, pc, length);
 246       break;
 247
 248     default :
 249       /* xgettext:c-format */
 250       fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
 251                opindex);
 252     abort ();
 253   }
 254 }
 255
 256 cgen_print_fn * const m32r_cgen_print_handlers[] =
 257 {
 258   print_insn_normal,
 259 };
 260
 261
 262 void
 263 m32r_cgen_init_dis (cd)
 264      CGEN_CPU_DESC cd;
 265 {
 266   m32r_cgen_init_opcode_table (cd);
 267   m32r_cgen_init_ibld_table (cd);
 268   cd->print_handlers = & m32r_cgen_print_handlers[0];
 269   cd->print_operand = m32r_cgen_print_operand;
 270 }
 271
 272 \f
 273 /* Default print handler.  */
 274
 275 static void
 276 print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 277               void *dis_info,
 278               long value,
 279               unsigned int attrs,
 280               bfd_vma pc ATTRIBUTE_UNUSED,
 281               int length ATTRIBUTE_UNUSED)
 282 {
 283   disassemble_info *info = (disassemble_info *) dis_info;
 284
 285 #ifdef CGEN_PRINT_NORMAL
 286   CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
 287 #endif
 288
 289   /* Print the operand as directed by the attributes.  */
 290   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
 291     ; /* nothing to do */
 292   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
 293     (*info->fprintf_func) (info->stream, "%ld", value);
 294   else
 295     (*info->fprintf_func) (info->stream, "0x%lx", value);
 296 }
 297
 298 /* Default address handler.  */
 299
 300 static void
 301 print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 302                void *dis_info,
 303                bfd_vma value,
 304                unsigned int attrs,
 305                bfd_vma pc ATTRIBUTE_UNUSED,
 306                int length ATTRIBUTE_UNUSED)
 307 {
 308   disassemble_info *info = (disassemble_info *) dis_info;
 309
 310 #ifdef CGEN_PRINT_ADDRESS
 311   CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
 312 #endif
 313
 314   /* Print the operand as directed by the attributes.  */
 315   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
 316     ; /* nothing to do */
 317   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
 318     (*info->print_address_func) (value, info);
 319   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
 320     (*info->print_address_func) (value, info);
 321   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
 322     (*info->fprintf_func) (info->stream, "%ld", (long) value);
 323   else
 324     (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
 325 }
 326
 327 /* Keyword print handler.  */
 328
 329 static void
 330 print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 331                void *dis_info,
 332                CGEN_KEYWORD *keyword_table,
 333                long value,
 334                unsigned int attrs ATTRIBUTE_UNUSED)
 335 {
 336   disassemble_info *info = (disassemble_info *) dis_info;
 337   const CGEN_KEYWORD_ENTRY *ke;
 338
 339   ke = cgen_keyword_lookup_value (keyword_table, value);
 340   if (ke != NULL)
 341     (*info->fprintf_func) (info->stream, "%s", ke->name);
 342   else
 343     (*info->fprintf_func) (info->stream, "???");
 344 }
 345 \f
 346 /* Default insn printer.
 347
 348    DIS_INFO is defined as `void *' so the disassembler needn't know anything
 349    about disassemble_info.  */
 350
 351 static void
 352 print_insn_normal (CGEN_CPU_DESC cd,
 353                    void *dis_info,
 354                    const CGEN_INSN *insn,
 355                    CGEN_FIELDS *fields,
 356                    bfd_vma pc,
 357                    int length)
 358 {
 359   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
 360   disassemble_info *info = (disassemble_info *) dis_info;
 361   const CGEN_SYNTAX_CHAR_TYPE *syn;
 362
 363   CGEN_INIT_PRINT (cd);
 364
 365   for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
 366     {
 367       if (CGEN_SYNTAX_MNEMONIC_P (*syn))
 368         {
 369           (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
 370           continue;
 371         }
 372       if (CGEN_SYNTAX_CHAR_P (*syn))
 373         {
 374           (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
 375           continue;
 376         }
 377
 378       /* We have an operand.  */
 379       m32r_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
 380                                  fields, CGEN_INSN_ATTRS (insn), pc, length);
 381     }
 382 }
 383 \f
 384 /* Subroutine of print_insn. Reads an insn into the given buffers and updates
 385    the extract info.
 386    Returns 0 if all is well, non-zero otherwise.  */
 387
 388 static int
 389 read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 390            bfd_vma pc,
 391            disassemble_info *info,
 392            char *buf,
 393            int buflen,
 394            CGEN_EXTRACT_INFO *ex_info,
 395            unsigned long *insn_value)
 396 {
 397   int status = (*info->read_memory_func) (pc, buf, buflen, info);
 398   if (status != 0)
 399     {
 400       (*info->memory_error_func) (status, pc, info);
 401       return -1;
 402     }
 403
 404   ex_info->dis_info = info;
 405   ex_info->valid = (1 << buflen) - 1;
 406   ex_info->insn_bytes = buf;
 407
 408   *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
 409   return 0;
 410 }
 411
 412 /* Utility to print an insn.
 413    BUF is the base part of the insn, target byte order, BUFLEN bytes long.
 414    The result is the size of the insn in bytes or zero for an unknown insn
 415    or -1 if an error occurs fetching data (memory_error_func will have
 416    been called).  */
 417
 418 static int
 419 print_insn (CGEN_CPU_DESC cd,
 420             bfd_vma pc,
 421             disassemble_info *info,
 422             char *buf,
 423             unsigned int buflen)
 424 {
 425   CGEN_INSN_INT insn_value;
 426   const CGEN_INSN_LIST *insn_list;
 427   CGEN_EXTRACT_INFO ex_info;
 428   int basesize;
 429
 430   /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
 431   basesize = cd->base_insn_bitsize < buflen * 8 ?
 432                                      cd->base_insn_bitsize : buflen * 8;
 433   insn_value = cgen_get_insn_value (cd, buf, basesize);
 434
 435
 436   /* Fill in ex_info fields like read_insn would.  Don't actually call
 437      read_insn, since the incoming buffer is already read (and possibly
 438      modified a la m32r).  */
 439   ex_info.valid = (1 << buflen) - 1;
 440   ex_info.dis_info = info;
 441   ex_info.insn_bytes = buf;
 442
 443   /* The instructions are stored in hash lists.
 444      Pick the first one and keep trying until we find the right one.  */
 445
 446   insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value);
 447   while (insn_list != NULL)
 448     {
 449       const CGEN_INSN *insn = insn_list->insn;
 450       CGEN_FIELDS fields;
 451       int length;
 452       unsigned long insn_value_cropped;
 453
 454 #ifdef CGEN_VALIDATE_INSN_SUPPORTED
 455       /* Not needed as insn shouldn't be in hash lists if not supported.  */
 456       /* Supported by this cpu?  */
 457       if (! m32r_cgen_insn_supported (cd, insn))
 458         {
 459           insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 460           continue;
 461         }
 462 #endif
 463
 464       /* Basic bit mask must be correct.  */
 465       /* ??? May wish to allow target to defer this check until the extract
 466          handler.  */
 467
 468       /* Base size may exceed this instruction's size.  Extract the
 469          relevant part from the buffer. */
 470       if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
 471           (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
 472         insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
 473                                            info->endian == BFD_ENDIAN_BIG);
 474       else
 475         insn_value_cropped = insn_value;
 476
 477       if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
 478           == CGEN_INSN_BASE_VALUE (insn))
 479         {
 480           /* Printing is handled in two passes.  The first pass parses the
 481              machine insn and extracts the fields.  The second pass prints
 482              them.  */
 483
 484           /* Make sure the entire insn is loaded into insn_value, if it
 485              can fit.  */
 486           if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
 487               (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
 488             {
 489               unsigned long full_insn_value;
 490               int rc = read_insn (cd, pc, info, buf,
 491                                   CGEN_INSN_BITSIZE (insn) / 8,
 492                                   & ex_info, & full_insn_value);
 493               if (rc != 0)
 494                 return rc;
 495               length = CGEN_EXTRACT_FN (cd, insn)
 496                 (cd, insn, &ex_info, full_insn_value, &fields, pc);
 497             }
 498           else
 499             length = CGEN_EXTRACT_FN (cd, insn)
 500               (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
 501
 502           /* length < 0 -> error */
 503           if (length < 0)
 504             return length;
 505           if (length > 0)
 506             {
 507               CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
 508               /* length is in bits, result is in bytes */
 509               return length / 8;
 510             }
 511         }
 512
 513       insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 514     }
 515
 516   return 0;
 517 }
 518
 519 /* Default value for CGEN_PRINT_INSN.
 520    The result is the size of the insn in bytes or zero for an unknown insn
 521    or -1 if an error occured fetching bytes.  */
 522
 523 #ifndef CGEN_PRINT_INSN
 524 #define CGEN_PRINT_INSN default_print_insn
 525 #endif
 526
 527 static int
 528 default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
 529 {
 530   char buf[CGEN_MAX_INSN_SIZE];
 531   int buflen;
 532   int status;
 533
 534   /* Attempt to read the base part of the insn.  */
 535   buflen = cd->base_insn_bitsize / 8;
 536   status = (*info->read_memory_func) (pc, buf, buflen, info);
 537
 538   /* Try again with the minimum part, if min < base.  */
 539   if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
 540     {
 541       buflen = cd->min_insn_bitsize / 8;
 542       status = (*info->read_memory_func) (pc, buf, buflen, info);
 543     }
 544
 545   if (status != 0)
 546     {
 547       (*info->memory_error_func) (status, pc, info);
 548       return -1;
 549     }
 550
 551   return print_insn (cd, pc, info, buf, buflen);
 552 }
 553
 554 /* Main entry point.
 555    Print one instruction from PC on INFO->STREAM.
 556    Return the size of the instruction (in bytes).  */
 557
 558 typedef struct cpu_desc_list {
 559   struct cpu_desc_list *next;
 560   int isa;
 561   int mach;
 562   int endian;
 563   CGEN_CPU_DESC cd;
 564 } cpu_desc_list;
 565
 566 int
 567 print_insn_m32r (bfd_vma pc, disassemble_info *info)
 568 {
 569   static cpu_desc_list *cd_list = 0;
 570   cpu_desc_list *cl = 0;
 571   static CGEN_CPU_DESC cd = 0;
 572   static int prev_isa;
 573   static int prev_mach;
 574   static int prev_endian;
 575   int length;
 576   int isa,mach;
 577   int endian = (info->endian == BFD_ENDIAN_BIG
 578                 ? CGEN_ENDIAN_BIG
 579                 : CGEN_ENDIAN_LITTLE);
 580   enum bfd_architecture arch;
 581
 582   /* ??? gdb will set mach but leave the architecture as "unknown" */
 583 #ifndef CGEN_BFD_ARCH
 584 #define CGEN_BFD_ARCH bfd_arch_m32r
 585 #endif
 586   arch = info->arch;
 587   if (arch == bfd_arch_unknown)
 588     arch = CGEN_BFD_ARCH;
 589
 590   /* There's no standard way to compute the machine or isa number
 591      so we leave it to the target.  */
 592 #ifdef CGEN_COMPUTE_MACH
 593   mach = CGEN_COMPUTE_MACH (info);
 594 #else
 595   mach = info->mach;
 596 #endif
 597
 598 #ifdef CGEN_COMPUTE_ISA
 599   isa = CGEN_COMPUTE_ISA (info);
 600 #else
 601   isa = info->insn_sets;
 602 #endif
 603
 604   /* If we've switched cpu's, try to find a handle we've used before */
 605   if (cd
 606       && (isa != prev_isa
 607           || mach != prev_mach
 608           || endian != prev_endian))
 609     {
 610       cd = 0;
 611       for (cl = cd_list; cl; cl = cl->next)
 612         {
 613           if (cl->isa == isa &&
 614               cl->mach == mach &&
 615               cl->endian == endian)
 616             {
 617               cd = cl->cd;
 618               break;
 619             }
 620         }
 621     }
 622
 623   /* If we haven't initialized yet, initialize the opcode table.  */
 624   if (! cd)
 625     {
 626       const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
 627       const char *mach_name;
 628
 629       if (!arch_type)
 630         abort ();
 631       mach_name = arch_type->printable_name;
 632
 633       prev_isa = isa;
 634       prev_mach = mach;
 635       prev_endian = endian;
 636       cd = m32r_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
 637                                  CGEN_CPU_OPEN_BFDMACH, mach_name,
 638                                  CGEN_CPU_OPEN_ENDIAN, prev_endian,
 639                                  CGEN_CPU_OPEN_END);
 640       if (!cd)
 641         abort ();
 642
 643       /* save this away for future reference */
 644       cl = xmalloc (sizeof (struct cpu_desc_list));
 645       cl->cd = cd;
 646       cl->isa = isa;
 647       cl->mach = mach;
 648       cl->endian = endian;
 649       cl->next = cd_list;
 650       cd_list = cl;
 651
 652       m32r_cgen_init_dis (cd);
 653     }
 654
 655   /* We try to have as much common code as possible.
 656      But at this point some targets need to take over.  */
 657   /* ??? Some targets may need a hook elsewhere.  Try to avoid this,
 658      but if not possible try to move this hook elsewhere rather than
 659      have two hooks.  */
 660   length = CGEN_PRINT_INSN (cd, pc, info);
 661   if (length > 0)
 662     return length;
 663   if (length < 0)
 664     return -1;
 665
 666   (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
 667   return cd->default_insn_bitsize / 8;
 668 }