1 /* Instruction building/extraction support for m32r. -*- C -*-
3 THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
4 - the resultant file is machine generated, cgen-ibld.in isn't
6 Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
8 This file is part of the GNU Binutils and GDB, the GNU debugger.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software Foundation, Inc.,
22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
34 #include "m32r-desc.h"
39 #define min(a,b) ((a) < (b) ? (a) : (b))
41 #define max(a,b) ((a) > (b) ? (a) : (b))
43 /* Used by the ifield rtx function. */
44 #define FLD(f) (fields->f)
46 static const char * insert_normal
47 PARAMS ((CGEN_CPU_DESC
, long, unsigned int, unsigned int, unsigned int,
48 unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR
));
49 static const char * insert_insn_normal
50 PARAMS ((CGEN_CPU_DESC
, const CGEN_INSN
*,
51 CGEN_FIELDS
*, CGEN_INSN_BYTES_PTR
, bfd_vma
));
53 static int extract_normal
54 PARAMS ((CGEN_CPU_DESC
, CGEN_EXTRACT_INFO
*, CGEN_INSN_INT
,
55 unsigned int, unsigned int, unsigned int, unsigned int,
56 unsigned int, unsigned int, bfd_vma
, long *));
57 static int extract_insn_normal
58 PARAMS ((CGEN_CPU_DESC
, const CGEN_INSN
*, CGEN_EXTRACT_INFO
*,
59 CGEN_INSN_INT
, CGEN_FIELDS
*, bfd_vma
));
60 static void put_insn_int_value
61 PARAMS ((CGEN_CPU_DESC
, CGEN_INSN_BYTES_PTR
, int, int, CGEN_INSN_INT
));
64 /* Operand insertion. */
68 /* Subroutine of insert_normal. */
70 static CGEN_INLINE
void
71 insert_1 (cd
, value
, start
, length
, word_length
, bufp
)
74 int start
,length
,word_length
;
79 int big_p
= CGEN_CPU_INSN_ENDIAN (cd
) == CGEN_ENDIAN_BIG
;
81 x
= bfd_get_bits (bufp
, word_length
, big_p
);
83 /* Written this way to avoid undefined behaviour. */
84 mask
= (((1L << (length
- 1)) - 1) << 1) | 1;
86 shift
= (start
+ 1) - length
;
88 shift
= (word_length
- (start
+ length
));
89 x
= (x
& ~(mask
<< shift
)) | ((value
& mask
) << shift
);
91 bfd_put_bits ((bfd_vma
) x
, bufp
, word_length
, big_p
);
94 #endif /* ! CGEN_INT_INSN_P */
96 /* Default insertion routine.
98 ATTRS is a mask of the boolean attributes.
99 WORD_OFFSET is the offset in bits from the start of the insn of the value.
100 WORD_LENGTH is the length of the word in bits in which the value resides.
101 START is the starting bit number in the word, architecture origin.
102 LENGTH is the length of VALUE in bits.
103 TOTAL_LENGTH is the total length of the insn in bits.
105 The result is an error message or NULL if success. */
107 /* ??? This duplicates functionality with bfd's howto table and
108 bfd_install_relocation. */
109 /* ??? This doesn't handle bfd_vma's. Create another function when
113 insert_normal (cd
, value
, attrs
, word_offset
, start
, length
, word_length
,
114 total_length
, buffer
)
118 unsigned int word_offset
, start
, length
, word_length
, total_length
;
119 CGEN_INSN_BYTES_PTR buffer
;
121 static char errbuf
[100];
122 /* Written this way to avoid undefined behaviour. */
123 unsigned long mask
= (((1L << (length
- 1)) - 1) << 1) | 1;
125 /* If LENGTH is zero, this operand doesn't contribute to the value. */
135 if (word_length
> 32)
138 /* For architectures with insns smaller than the base-insn-bitsize,
139 word_length may be too big. */
140 if (cd
->min_insn_bitsize
< cd
->base_insn_bitsize
)
143 && word_length
> total_length
)
144 word_length
= total_length
;
147 /* Ensure VALUE will fit. */
148 if (CGEN_BOOL_ATTR (attrs
, CGEN_IFLD_SIGN_OPT
))
150 long minval
= - (1L << (length
- 1));
151 unsigned long maxval
= mask
;
153 if ((value
> 0 && (unsigned long) value
> maxval
)
156 /* xgettext:c-format */
158 _("operand out of range (%ld not between %ld and %lu)"),
159 value
, minval
, maxval
);
163 else if (! CGEN_BOOL_ATTR (attrs
, CGEN_IFLD_SIGNED
))
165 unsigned long maxval
= mask
;
167 if ((unsigned long) value
> maxval
)
169 /* xgettext:c-format */
171 _("operand out of range (%lu not between 0 and %lu)"),
178 if (! cgen_signed_overflow_ok_p (cd
))
180 long minval
= - (1L << (length
- 1));
181 long maxval
= (1L << (length
- 1)) - 1;
183 if (value
< minval
|| value
> maxval
)
186 /* xgettext:c-format */
187 (errbuf
, _("operand out of range (%ld not between %ld and %ld)"),
188 value
, minval
, maxval
);
199 if (CGEN_INSN_LSB0_P
)
200 shift
= (word_offset
+ start
+ 1) - length
;
202 shift
= total_length
- (word_offset
+ start
+ length
);
203 *buffer
= (*buffer
& ~(mask
<< shift
)) | ((value
& mask
) << shift
);
206 #else /* ! CGEN_INT_INSN_P */
209 unsigned char *bufp
= (unsigned char *) buffer
+ word_offset
/ 8;
211 insert_1 (cd
, value
, start
, length
, word_length
, bufp
);
214 #endif /* ! CGEN_INT_INSN_P */
219 /* Default insn builder (insert handler).
220 The instruction is recorded in CGEN_INT_INSN_P byte order (meaning
221 that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is
222 recorded in host byte order, otherwise BUFFER is an array of bytes
223 and the value is recorded in target byte order).
224 The result is an error message or NULL if success. */
227 insert_insn_normal (cd
, insn
, fields
, buffer
, pc
)
229 const CGEN_INSN
* insn
;
230 CGEN_FIELDS
* fields
;
231 CGEN_INSN_BYTES_PTR buffer
;
234 const CGEN_SYNTAX
*syntax
= CGEN_INSN_SYNTAX (insn
);
236 const CGEN_SYNTAX_CHAR_TYPE
* syn
;
238 CGEN_INIT_INSERT (cd
);
239 value
= CGEN_INSN_BASE_VALUE (insn
);
241 /* If we're recording insns as numbers (rather than a string of bytes),
242 target byte order handling is deferred until later. */
246 put_insn_int_value (cd
, buffer
, cd
->base_insn_bitsize
,
247 CGEN_FIELDS_BITSIZE (fields
), value
);
251 cgen_put_insn_value (cd
, buffer
, min (cd
->base_insn_bitsize
,
252 CGEN_FIELDS_BITSIZE (fields
)),
255 #endif /* ! CGEN_INT_INSN_P */
257 /* ??? It would be better to scan the format's fields.
258 Still need to be able to insert a value based on the operand though;
259 e.g. storing a branch displacement that got resolved later.
260 Needs more thought first. */
262 for (syn
= CGEN_SYNTAX_STRING (syntax
); * syn
; ++ syn
)
266 if (CGEN_SYNTAX_CHAR_P (* syn
))
269 errmsg
= (* cd
->insert_operand
) (cd
, CGEN_SYNTAX_FIELD (*syn
),
278 /* Cover function to store an insn value into an integral insn. Must go here
279 because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
282 put_insn_int_value (cd
, buf
, length
, insn_length
, value
)
283 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED
;
284 CGEN_INSN_BYTES_PTR buf
;
289 /* For architectures with insns smaller than the base-insn-bitsize,
290 length may be too big. */
291 if (length
> insn_length
)
295 int shift
= insn_length
- length
;
296 /* Written this way to avoid undefined behaviour. */
297 CGEN_INSN_INT mask
= (((1L << (length
- 1)) - 1) << 1) | 1;
298 *buf
= (*buf
& ~(mask
<< shift
)) | ((value
& mask
) << shift
);
302 /* Operand extraction. */
304 #if ! CGEN_INT_INSN_P
306 /* Subroutine of extract_normal.
307 Ensure sufficient bytes are cached in EX_INFO.
308 OFFSET is the offset in bytes from the start of the insn of the value.
309 BYTES is the length of the needed value.
310 Returns 1 for success, 0 for failure. */
312 static CGEN_INLINE
int
313 fill_cache (cd
, ex_info
, offset
, bytes
, pc
)
315 CGEN_EXTRACT_INFO
*ex_info
;
319 /* It's doubtful that the middle part has already been fetched so
320 we don't optimize that case. kiss. */
322 disassemble_info
*info
= (disassemble_info
*) ex_info
->dis_info
;
324 /* First do a quick check. */
325 mask
= (1 << bytes
) - 1;
326 if (((ex_info
->valid
>> offset
) & mask
) == mask
)
329 /* Search for the first byte we need to read. */
330 for (mask
= 1 << offset
; bytes
> 0; --bytes
, ++offset
, mask
<<= 1)
331 if (! (mask
& ex_info
->valid
))
339 status
= (*info
->read_memory_func
)
340 (pc
, ex_info
->insn_bytes
+ offset
, bytes
, info
);
344 (*info
->memory_error_func
) (status
, pc
, info
);
348 ex_info
->valid
|= ((1 << bytes
) - 1) << offset
;
354 /* Subroutine of extract_normal. */
356 static CGEN_INLINE
long
357 extract_1 (cd
, ex_info
, start
, length
, word_length
, bufp
, pc
)
359 CGEN_EXTRACT_INFO
*ex_info
;
360 int start
,length
,word_length
;
366 int big_p
= CGEN_CPU_INSN_ENDIAN (cd
) == CGEN_ENDIAN_BIG
;
368 x
= bfd_get_bits (bufp
, word_length
, big_p
);
370 if (CGEN_INSN_LSB0_P
)
371 shift
= (start
+ 1) - length
;
373 shift
= (word_length
- (start
+ length
));
377 #endif /* ! CGEN_INT_INSN_P */
379 /* Default extraction routine.
381 INSN_VALUE is the first base_insn_bitsize bits of the insn in host order,
382 or sometimes less for cases like the m32r where the base insn size is 32
383 but some insns are 16 bits.
384 ATTRS is a mask of the boolean attributes. We only need `SIGNED',
385 but for generality we take a bitmask of all of them.
386 WORD_OFFSET is the offset in bits from the start of the insn of the value.
387 WORD_LENGTH is the length of the word in bits in which the value resides.
388 START is the starting bit number in the word, architecture origin.
389 LENGTH is the length of VALUE in bits.
390 TOTAL_LENGTH is the total length of the insn in bits.
392 Returns 1 for success, 0 for failure. */
394 /* ??? The return code isn't properly used. wip. */
396 /* ??? This doesn't handle bfd_vma's. Create another function when
400 extract_normal (cd
, ex_info
, insn_value
, attrs
, word_offset
, start
, length
,
401 word_length
, total_length
, pc
, valuep
)
403 #if ! CGEN_INT_INSN_P
404 CGEN_EXTRACT_INFO
*ex_info
;
406 CGEN_EXTRACT_INFO
*ex_info ATTRIBUTE_UNUSED
;
408 CGEN_INSN_INT insn_value
;
410 unsigned int word_offset
, start
, length
, word_length
, total_length
;
411 #if ! CGEN_INT_INSN_P
414 bfd_vma pc ATTRIBUTE_UNUSED
;
420 /* If LENGTH is zero, this operand doesn't contribute to the value
421 so give it a standard value of zero. */
434 if (word_length
> 32)
437 /* For architectures with insns smaller than the insn-base-bitsize,
438 word_length may be too big. */
439 if (cd
->min_insn_bitsize
< cd
->base_insn_bitsize
)
442 && word_length
> total_length
)
443 word_length
= total_length
;
446 /* Does the value reside in INSN_VALUE, and at the right alignment? */
448 if (CGEN_INT_INSN_P
|| (word_offset
== 0 && word_length
== total_length
))
450 if (CGEN_INSN_LSB0_P
)
451 value
= insn_value
>> ((word_offset
+ start
+ 1) - length
);
453 value
= insn_value
>> (total_length
- ( word_offset
+ start
+ length
));
456 #if ! CGEN_INT_INSN_P
460 unsigned char *bufp
= ex_info
->insn_bytes
+ word_offset
/ 8;
462 if (word_length
> 32)
465 if (fill_cache (cd
, ex_info
, word_offset
/ 8, word_length
/ 8, pc
) == 0)
468 value
= extract_1 (cd
, ex_info
, start
, length
, word_length
, bufp
, pc
);
471 #endif /* ! CGEN_INT_INSN_P */
473 /* Written this way to avoid undefined behaviour. */
474 mask
= (((1L << (length
- 1)) - 1) << 1) | 1;
478 if (CGEN_BOOL_ATTR (attrs
, CGEN_IFLD_SIGNED
)
479 && (value
& (1L << (length
- 1))))
487 /* Default insn extractor.
489 INSN_VALUE is the first base_insn_bitsize bits, translated to host order.
490 The extracted fields are stored in FIELDS.
491 EX_INFO is used to handle reading variable length insns.
492 Return the length of the insn in bits, or 0 if no match,
493 or -1 if an error occurs fetching data (memory_error_func will have
497 extract_insn_normal (cd
, insn
, ex_info
, insn_value
, fields
, pc
)
499 const CGEN_INSN
*insn
;
500 CGEN_EXTRACT_INFO
*ex_info
;
501 CGEN_INSN_INT insn_value
;
505 const CGEN_SYNTAX
*syntax
= CGEN_INSN_SYNTAX (insn
);
506 const CGEN_SYNTAX_CHAR_TYPE
*syn
;
508 CGEN_FIELDS_BITSIZE (fields
) = CGEN_INSN_BITSIZE (insn
);
510 CGEN_INIT_EXTRACT (cd
);
512 for (syn
= CGEN_SYNTAX_STRING (syntax
); *syn
; ++syn
)
516 if (CGEN_SYNTAX_CHAR_P (*syn
))
519 length
= (* cd
->extract_operand
) (cd
, CGEN_SYNTAX_FIELD (*syn
),
520 ex_info
, insn_value
, fields
, pc
);
525 /* We recognized and successfully extracted this insn. */
526 return CGEN_INSN_BITSIZE (insn
);
529 /* machine generated code added here */
531 /* Main entry point for operand insertion.
533 This function is basically just a big switch statement. Earlier versions
534 used tables to look up the function to use, but
535 - if the table contains both assembler and disassembler functions then
536 the disassembler contains much of the assembler and vice-versa,
537 - there's a lot of inlining possibilities as things grow,
538 - using a switch statement avoids the function call overhead.
540 This function could be moved into `parse_insn_normal', but keeping it
541 separate makes clear the interface between `parse_insn_normal' and each of
542 the handlers. It's also needed by GAS to insert operands that couldn't be
543 resolved during parsing.
547 m32r_cgen_insert_operand (cd
, opindex
, fields
, buffer
, pc
)
550 CGEN_FIELDS
* fields
;
551 CGEN_INSN_BYTES_PTR buffer
;
554 const char * errmsg
= NULL
;
555 unsigned int total_length
= CGEN_FIELDS_BITSIZE (fields
);
559 case M32R_OPERAND_ACC
:
560 errmsg
= insert_normal (cd
, fields
->f_acc
, 0, 0, 8, 1, 32, total_length
, buffer
);
562 case M32R_OPERAND_ACCD
:
563 errmsg
= insert_normal (cd
, fields
->f_accd
, 0, 0, 4, 2, 32, total_length
, buffer
);
565 case M32R_OPERAND_ACCS
:
566 errmsg
= insert_normal (cd
, fields
->f_accs
, 0, 0, 12, 2, 32, total_length
, buffer
);
568 case M32R_OPERAND_DCR
:
569 errmsg
= insert_normal (cd
, fields
->f_r1
, 0, 0, 4, 4, 32, total_length
, buffer
);
571 case M32R_OPERAND_DISP16
:
573 long value
= fields
->f_disp16
;
574 value
= ((int) (((value
) - (pc
))) >> (2));
575 errmsg
= insert_normal (cd
, value
, 0|(1<<CGEN_IFLD_SIGNED
)|(1<<CGEN_IFLD_RELOC
)|(1<<CGEN_IFLD_PCREL_ADDR
), 0, 16, 16, 32, total_length
, buffer
);
578 case M32R_OPERAND_DISP24
:
580 long value
= fields
->f_disp24
;
581 value
= ((int) (((value
) - (pc
))) >> (2));
582 errmsg
= insert_normal (cd
, value
, 0|(1<<CGEN_IFLD_SIGNED
)|(1<<CGEN_IFLD_RELOC
)|(1<<CGEN_IFLD_PCREL_ADDR
), 0, 8, 24, 32, total_length
, buffer
);
585 case M32R_OPERAND_DISP8
:
587 long value
= fields
->f_disp8
;
588 value
= ((int) (((value
) - (((pc
) & (-4))))) >> (2));
589 errmsg
= insert_normal (cd
, value
, 0|(1<<CGEN_IFLD_SIGNED
)|(1<<CGEN_IFLD_RELOC
)|(1<<CGEN_IFLD_PCREL_ADDR
), 0, 8, 8, 32, total_length
, buffer
);
592 case M32R_OPERAND_DR
:
593 errmsg
= insert_normal (cd
, fields
->f_r1
, 0, 0, 4, 4, 32, total_length
, buffer
);
595 case M32R_OPERAND_HASH
:
597 case M32R_OPERAND_HI16
:
598 errmsg
= insert_normal (cd
, fields
->f_hi16
, 0|(1<<CGEN_IFLD_SIGN_OPT
), 0, 16, 16, 32, total_length
, buffer
);
600 case M32R_OPERAND_IMM1
:
602 long value
= fields
->f_imm1
;
603 value
= ((value
) - (1));
604 errmsg
= insert_normal (cd
, value
, 0, 0, 15, 1, 32, total_length
, buffer
);
607 case M32R_OPERAND_SCR
:
608 errmsg
= insert_normal (cd
, fields
->f_r2
, 0, 0, 12, 4, 32, total_length
, buffer
);
610 case M32R_OPERAND_SIMM16
:
611 errmsg
= insert_normal (cd
, fields
->f_simm16
, 0|(1<<CGEN_IFLD_SIGNED
), 0, 16, 16, 32, total_length
, buffer
);
613 case M32R_OPERAND_SIMM8
:
614 errmsg
= insert_normal (cd
, fields
->f_simm8
, 0|(1<<CGEN_IFLD_SIGNED
), 0, 8, 8, 32, total_length
, buffer
);
616 case M32R_OPERAND_SLO16
:
617 errmsg
= insert_normal (cd
, fields
->f_simm16
, 0|(1<<CGEN_IFLD_SIGNED
), 0, 16, 16, 32, total_length
, buffer
);
619 case M32R_OPERAND_SR
:
620 errmsg
= insert_normal (cd
, fields
->f_r2
, 0, 0, 12, 4, 32, total_length
, buffer
);
622 case M32R_OPERAND_SRC1
:
623 errmsg
= insert_normal (cd
, fields
->f_r1
, 0, 0, 4, 4, 32, total_length
, buffer
);
625 case M32R_OPERAND_SRC2
:
626 errmsg
= insert_normal (cd
, fields
->f_r2
, 0, 0, 12, 4, 32, total_length
, buffer
);
628 case M32R_OPERAND_UIMM16
:
629 errmsg
= insert_normal (cd
, fields
->f_uimm16
, 0, 0, 16, 16, 32, total_length
, buffer
);
631 case M32R_OPERAND_UIMM24
:
632 errmsg
= insert_normal (cd
, fields
->f_uimm24
, 0|(1<<CGEN_IFLD_RELOC
)|(1<<CGEN_IFLD_ABS_ADDR
), 0, 8, 24, 32, total_length
, buffer
);
634 case M32R_OPERAND_UIMM4
:
635 errmsg
= insert_normal (cd
, fields
->f_uimm4
, 0, 0, 12, 4, 32, total_length
, buffer
);
637 case M32R_OPERAND_UIMM5
:
638 errmsg
= insert_normal (cd
, fields
->f_uimm5
, 0, 0, 11, 5, 32, total_length
, buffer
);
640 case M32R_OPERAND_ULO16
:
641 errmsg
= insert_normal (cd
, fields
->f_uimm16
, 0, 0, 16, 16, 32, total_length
, buffer
);
645 /* xgettext:c-format */
646 fprintf (stderr
, _("Unrecognized field %d while building insn.\n"),
654 /* Main entry point for operand extraction.
655 The result is <= 0 for error, >0 for success.
656 ??? Actual values aren't well defined right now.
658 This function is basically just a big switch statement. Earlier versions
659 used tables to look up the function to use, but
660 - if the table contains both assembler and disassembler functions then
661 the disassembler contains much of the assembler and vice-versa,
662 - there's a lot of inlining possibilities as things grow,
663 - using a switch statement avoids the function call overhead.
665 This function could be moved into `print_insn_normal', but keeping it
666 separate makes clear the interface between `print_insn_normal' and each of
671 m32r_cgen_extract_operand (cd
, opindex
, ex_info
, insn_value
, fields
, pc
)
674 CGEN_EXTRACT_INFO
*ex_info
;
675 CGEN_INSN_INT insn_value
;
676 CGEN_FIELDS
* fields
;
679 /* Assume success (for those operands that are nops). */
681 unsigned int total_length
= CGEN_FIELDS_BITSIZE (fields
);
685 case M32R_OPERAND_ACC
:
686 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 8, 1, 32, total_length
, pc
, & fields
->f_acc
);
688 case M32R_OPERAND_ACCD
:
689 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 4, 2, 32, total_length
, pc
, & fields
->f_accd
);
691 case M32R_OPERAND_ACCS
:
692 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 12, 2, 32, total_length
, pc
, & fields
->f_accs
);
694 case M32R_OPERAND_DCR
:
695 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 4, 4, 32, total_length
, pc
, & fields
->f_r1
);
697 case M32R_OPERAND_DISP16
:
700 length
= extract_normal (cd
, ex_info
, insn_value
, 0|(1<<CGEN_IFLD_SIGNED
)|(1<<CGEN_IFLD_RELOC
)|(1<<CGEN_IFLD_PCREL_ADDR
), 0, 16, 16, 32, total_length
, pc
, & value
);
701 value
= ((((value
) << (2))) + (pc
));
702 fields
->f_disp16
= value
;
705 case M32R_OPERAND_DISP24
:
708 length
= extract_normal (cd
, ex_info
, insn_value
, 0|(1<<CGEN_IFLD_SIGNED
)|(1<<CGEN_IFLD_RELOC
)|(1<<CGEN_IFLD_PCREL_ADDR
), 0, 8, 24, 32, total_length
, pc
, & value
);
709 value
= ((((value
) << (2))) + (pc
));
710 fields
->f_disp24
= value
;
713 case M32R_OPERAND_DISP8
:
716 length
= extract_normal (cd
, ex_info
, insn_value
, 0|(1<<CGEN_IFLD_SIGNED
)|(1<<CGEN_IFLD_RELOC
)|(1<<CGEN_IFLD_PCREL_ADDR
), 0, 8, 8, 32, total_length
, pc
, & value
);
717 value
= ((((value
) << (2))) + (((pc
) & (-4))));
718 fields
->f_disp8
= value
;
721 case M32R_OPERAND_DR
:
722 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 4, 4, 32, total_length
, pc
, & fields
->f_r1
);
724 case M32R_OPERAND_HASH
:
726 case M32R_OPERAND_HI16
:
727 length
= extract_normal (cd
, ex_info
, insn_value
, 0|(1<<CGEN_IFLD_SIGN_OPT
), 0, 16, 16, 32, total_length
, pc
, & fields
->f_hi16
);
729 case M32R_OPERAND_IMM1
:
732 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 15, 1, 32, total_length
, pc
, & value
);
733 value
= ((value
) + (1));
734 fields
->f_imm1
= value
;
737 case M32R_OPERAND_SCR
:
738 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 12, 4, 32, total_length
, pc
, & fields
->f_r2
);
740 case M32R_OPERAND_SIMM16
:
741 length
= extract_normal (cd
, ex_info
, insn_value
, 0|(1<<CGEN_IFLD_SIGNED
), 0, 16, 16, 32, total_length
, pc
, & fields
->f_simm16
);
743 case M32R_OPERAND_SIMM8
:
744 length
= extract_normal (cd
, ex_info
, insn_value
, 0|(1<<CGEN_IFLD_SIGNED
), 0, 8, 8, 32, total_length
, pc
, & fields
->f_simm8
);
746 case M32R_OPERAND_SLO16
:
747 length
= extract_normal (cd
, ex_info
, insn_value
, 0|(1<<CGEN_IFLD_SIGNED
), 0, 16, 16, 32, total_length
, pc
, & fields
->f_simm16
);
749 case M32R_OPERAND_SR
:
750 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 12, 4, 32, total_length
, pc
, & fields
->f_r2
);
752 case M32R_OPERAND_SRC1
:
753 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 4, 4, 32, total_length
, pc
, & fields
->f_r1
);
755 case M32R_OPERAND_SRC2
:
756 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 12, 4, 32, total_length
, pc
, & fields
->f_r2
);
758 case M32R_OPERAND_UIMM16
:
759 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 16, 16, 32, total_length
, pc
, & fields
->f_uimm16
);
761 case M32R_OPERAND_UIMM24
:
762 length
= extract_normal (cd
, ex_info
, insn_value
, 0|(1<<CGEN_IFLD_RELOC
)|(1<<CGEN_IFLD_ABS_ADDR
), 0, 8, 24, 32, total_length
, pc
, & fields
->f_uimm24
);
764 case M32R_OPERAND_UIMM4
:
765 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 12, 4, 32, total_length
, pc
, & fields
->f_uimm4
);
767 case M32R_OPERAND_UIMM5
:
768 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 11, 5, 32, total_length
, pc
, & fields
->f_uimm5
);
770 case M32R_OPERAND_ULO16
:
771 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 16, 16, 32, total_length
, pc
, & fields
->f_uimm16
);
775 /* xgettext:c-format */
776 fprintf (stderr
, _("Unrecognized field %d while decoding insn.\n"),
784 cgen_insert_fn
* const m32r_cgen_insert_handlers
[] =
789 cgen_extract_fn
* const m32r_cgen_extract_handlers
[] =
794 /* Getting values from cgen_fields is handled by a collection of functions.
795 They are distinguished by the type of the VALUE argument they return.
796 TODO: floating point, inlining support, remove cases where result type
800 m32r_cgen_get_int_operand (cd
, opindex
, fields
)
803 const CGEN_FIELDS
* fields
;
809 case M32R_OPERAND_ACC
:
810 value
= fields
->f_acc
;
812 case M32R_OPERAND_ACCD
:
813 value
= fields
->f_accd
;
815 case M32R_OPERAND_ACCS
:
816 value
= fields
->f_accs
;
818 case M32R_OPERAND_DCR
:
819 value
= fields
->f_r1
;
821 case M32R_OPERAND_DISP16
:
822 value
= fields
->f_disp16
;
824 case M32R_OPERAND_DISP24
:
825 value
= fields
->f_disp24
;
827 case M32R_OPERAND_DISP8
:
828 value
= fields
->f_disp8
;
830 case M32R_OPERAND_DR
:
831 value
= fields
->f_r1
;
833 case M32R_OPERAND_HASH
:
836 case M32R_OPERAND_HI16
:
837 value
= fields
->f_hi16
;
839 case M32R_OPERAND_IMM1
:
840 value
= fields
->f_imm1
;
842 case M32R_OPERAND_SCR
:
843 value
= fields
->f_r2
;
845 case M32R_OPERAND_SIMM16
:
846 value
= fields
->f_simm16
;
848 case M32R_OPERAND_SIMM8
:
849 value
= fields
->f_simm8
;
851 case M32R_OPERAND_SLO16
:
852 value
= fields
->f_simm16
;
854 case M32R_OPERAND_SR
:
855 value
= fields
->f_r2
;
857 case M32R_OPERAND_SRC1
:
858 value
= fields
->f_r1
;
860 case M32R_OPERAND_SRC2
:
861 value
= fields
->f_r2
;
863 case M32R_OPERAND_UIMM16
:
864 value
= fields
->f_uimm16
;
866 case M32R_OPERAND_UIMM24
:
867 value
= fields
->f_uimm24
;
869 case M32R_OPERAND_UIMM4
:
870 value
= fields
->f_uimm4
;
872 case M32R_OPERAND_UIMM5
:
873 value
= fields
->f_uimm5
;
875 case M32R_OPERAND_ULO16
:
876 value
= fields
->f_uimm16
;
880 /* xgettext:c-format */
881 fprintf (stderr
, _("Unrecognized field %d while getting int operand.\n"),
890 m32r_cgen_get_vma_operand (cd
, opindex
, fields
)
893 const CGEN_FIELDS
* fields
;
899 case M32R_OPERAND_ACC
:
900 value
= fields
->f_acc
;
902 case M32R_OPERAND_ACCD
:
903 value
= fields
->f_accd
;
905 case M32R_OPERAND_ACCS
:
906 value
= fields
->f_accs
;
908 case M32R_OPERAND_DCR
:
909 value
= fields
->f_r1
;
911 case M32R_OPERAND_DISP16
:
912 value
= fields
->f_disp16
;
914 case M32R_OPERAND_DISP24
:
915 value
= fields
->f_disp24
;
917 case M32R_OPERAND_DISP8
:
918 value
= fields
->f_disp8
;
920 case M32R_OPERAND_DR
:
921 value
= fields
->f_r1
;
923 case M32R_OPERAND_HASH
:
926 case M32R_OPERAND_HI16
:
927 value
= fields
->f_hi16
;
929 case M32R_OPERAND_IMM1
:
930 value
= fields
->f_imm1
;
932 case M32R_OPERAND_SCR
:
933 value
= fields
->f_r2
;
935 case M32R_OPERAND_SIMM16
:
936 value
= fields
->f_simm16
;
938 case M32R_OPERAND_SIMM8
:
939 value
= fields
->f_simm8
;
941 case M32R_OPERAND_SLO16
:
942 value
= fields
->f_simm16
;
944 case M32R_OPERAND_SR
:
945 value
= fields
->f_r2
;
947 case M32R_OPERAND_SRC1
:
948 value
= fields
->f_r1
;
950 case M32R_OPERAND_SRC2
:
951 value
= fields
->f_r2
;
953 case M32R_OPERAND_UIMM16
:
954 value
= fields
->f_uimm16
;
956 case M32R_OPERAND_UIMM24
:
957 value
= fields
->f_uimm24
;
959 case M32R_OPERAND_UIMM4
:
960 value
= fields
->f_uimm4
;
962 case M32R_OPERAND_UIMM5
:
963 value
= fields
->f_uimm5
;
965 case M32R_OPERAND_ULO16
:
966 value
= fields
->f_uimm16
;
970 /* xgettext:c-format */
971 fprintf (stderr
, _("Unrecognized field %d while getting vma operand.\n"),
979 /* Stuffing values in cgen_fields is handled by a collection of functions.
980 They are distinguished by the type of the VALUE argument they accept.
981 TODO: floating point, inlining support, remove cases where argument type
985 m32r_cgen_set_int_operand (cd
, opindex
, fields
, value
)
988 CGEN_FIELDS
* fields
;
993 case M32R_OPERAND_ACC
:
994 fields
->f_acc
= value
;
996 case M32R_OPERAND_ACCD
:
997 fields
->f_accd
= value
;
999 case M32R_OPERAND_ACCS
:
1000 fields
->f_accs
= value
;
1002 case M32R_OPERAND_DCR
:
1003 fields
->f_r1
= value
;
1005 case M32R_OPERAND_DISP16
:
1006 fields
->f_disp16
= value
;
1008 case M32R_OPERAND_DISP24
:
1009 fields
->f_disp24
= value
;
1011 case M32R_OPERAND_DISP8
:
1012 fields
->f_disp8
= value
;
1014 case M32R_OPERAND_DR
:
1015 fields
->f_r1
= value
;
1017 case M32R_OPERAND_HASH
:
1019 case M32R_OPERAND_HI16
:
1020 fields
->f_hi16
= value
;
1022 case M32R_OPERAND_IMM1
:
1023 fields
->f_imm1
= value
;
1025 case M32R_OPERAND_SCR
:
1026 fields
->f_r2
= value
;
1028 case M32R_OPERAND_SIMM16
:
1029 fields
->f_simm16
= value
;
1031 case M32R_OPERAND_SIMM8
:
1032 fields
->f_simm8
= value
;
1034 case M32R_OPERAND_SLO16
:
1035 fields
->f_simm16
= value
;
1037 case M32R_OPERAND_SR
:
1038 fields
->f_r2
= value
;
1040 case M32R_OPERAND_SRC1
:
1041 fields
->f_r1
= value
;
1043 case M32R_OPERAND_SRC2
:
1044 fields
->f_r2
= value
;
1046 case M32R_OPERAND_UIMM16
:
1047 fields
->f_uimm16
= value
;
1049 case M32R_OPERAND_UIMM24
:
1050 fields
->f_uimm24
= value
;
1052 case M32R_OPERAND_UIMM4
:
1053 fields
->f_uimm4
= value
;
1055 case M32R_OPERAND_UIMM5
:
1056 fields
->f_uimm5
= value
;
1058 case M32R_OPERAND_ULO16
:
1059 fields
->f_uimm16
= value
;
1063 /* xgettext:c-format */
1064 fprintf (stderr
, _("Unrecognized field %d while setting int operand.\n"),
1071 m32r_cgen_set_vma_operand (cd
, opindex
, fields
, value
)
1074 CGEN_FIELDS
* fields
;
1079 case M32R_OPERAND_ACC
:
1080 fields
->f_acc
= value
;
1082 case M32R_OPERAND_ACCD
:
1083 fields
->f_accd
= value
;
1085 case M32R_OPERAND_ACCS
:
1086 fields
->f_accs
= value
;
1088 case M32R_OPERAND_DCR
:
1089 fields
->f_r1
= value
;
1091 case M32R_OPERAND_DISP16
:
1092 fields
->f_disp16
= value
;
1094 case M32R_OPERAND_DISP24
:
1095 fields
->f_disp24
= value
;
1097 case M32R_OPERAND_DISP8
:
1098 fields
->f_disp8
= value
;
1100 case M32R_OPERAND_DR
:
1101 fields
->f_r1
= value
;
1103 case M32R_OPERAND_HASH
:
1105 case M32R_OPERAND_HI16
:
1106 fields
->f_hi16
= value
;
1108 case M32R_OPERAND_IMM1
:
1109 fields
->f_imm1
= value
;
1111 case M32R_OPERAND_SCR
:
1112 fields
->f_r2
= value
;
1114 case M32R_OPERAND_SIMM16
:
1115 fields
->f_simm16
= value
;
1117 case M32R_OPERAND_SIMM8
:
1118 fields
->f_simm8
= value
;
1120 case M32R_OPERAND_SLO16
:
1121 fields
->f_simm16
= value
;
1123 case M32R_OPERAND_SR
:
1124 fields
->f_r2
= value
;
1126 case M32R_OPERAND_SRC1
:
1127 fields
->f_r1
= value
;
1129 case M32R_OPERAND_SRC2
:
1130 fields
->f_r2
= value
;
1132 case M32R_OPERAND_UIMM16
:
1133 fields
->f_uimm16
= value
;
1135 case M32R_OPERAND_UIMM24
:
1136 fields
->f_uimm24
= value
;
1138 case M32R_OPERAND_UIMM4
:
1139 fields
->f_uimm4
= value
;
1141 case M32R_OPERAND_UIMM5
:
1142 fields
->f_uimm5
= value
;
1144 case M32R_OPERAND_ULO16
:
1145 fields
->f_uimm16
= value
;
1149 /* xgettext:c-format */
1150 fprintf (stderr
, _("Unrecognized field %d while setting vma operand.\n"),
1156 /* Function to call before using the instruction builder tables. */
1159 m32r_cgen_init_ibld_table (cd
)
1162 cd
->insert_handlers
= & m32r_cgen_insert_handlers
[0];
1163 cd
->extract_handlers
= & m32r_cgen_extract_handlers
[0];
1165 cd
->insert_operand
= m32r_cgen_insert_operand
;
1166 cd
->extract_operand
= m32r_cgen_extract_operand
;
1168 cd
->get_int_operand
= m32r_cgen_get_int_operand
;
1169 cd
->set_int_operand
= m32r_cgen_set_int_operand
;
1170 cd
->get_vma_operand
= m32r_cgen_get_vma_operand
;
1171 cd
->set_vma_operand
= m32r_cgen_set_vma_operand
;