1 /* CGEN opcode support for m32r.
3 This file is machine generated.
5 Copyright (C) 1996, 1997 Free Software Foundation, Inc.
7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 #include "libiberty.h"
35 static const CGEN_ATTR_ENTRY MACH_attr
[] = {
36 { "m32r", MACH_M32R
},
37 { "m32rx", MACH_M32RX
},
41 static const CGEN_ATTR_ENTRY PIPE_attr
[] = {
42 { "NONE", PIPE_NONE
},
49 const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table
[] = {
54 { "PCREL-ADDR", NULL
},
62 const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table
[] = {
63 { "MACH", & MACH_attr
[0] },
64 { "PIPE", & PIPE_attr
[0] },
67 { "FILL-SLOT", NULL
},
71 { "RELAX-BCL", NULL
},
73 { "RELAX-BNC", NULL
},
74 { "RELAX-BNCL", NULL
},
75 { "RELAX-BRA", NULL
},
76 { "RELAXABLE", NULL
},
77 { "UNCOND-CTI", NULL
},
81 CGEN_KEYWORD_ENTRY m32r_cgen_opval_mach_entries
[] = {
82 { "m32r", MACH_M32R
},
83 { "m32rx", MACH_M32RX
}
86 CGEN_KEYWORD m32r_cgen_opval_mach
= {
87 & m32r_cgen_opval_mach_entries
[0],
91 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_gr_entries
[] = {
113 CGEN_KEYWORD m32r_cgen_opval_h_gr
= {
114 & m32r_cgen_opval_h_gr_entries
[0],
118 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_cr_entries
[] = {
133 CGEN_KEYWORD m32r_cgen_opval_h_cr
= {
134 & m32r_cgen_opval_h_cr_entries
[0],
138 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries
[] = {
143 CGEN_KEYWORD m32r_cgen_opval_h_accums
= {
144 & m32r_cgen_opval_h_accums_entries
[0],
149 static CGEN_HW_ENTRY m32r_cgen_hw_entries
[] = {
150 { & m32r_cgen_hw_entries
[1], "h-pc", CGEN_ASM_KEYWORD
/*FIXME*/, 0 },
151 { & m32r_cgen_hw_entries
[2], "h-memory", CGEN_ASM_KEYWORD
/*FIXME*/, 0 },
152 { & m32r_cgen_hw_entries
[3], "h-sint", CGEN_ASM_KEYWORD
/*FIXME*/, 0 },
153 { & m32r_cgen_hw_entries
[4], "h-uint", CGEN_ASM_KEYWORD
/*FIXME*/, 0 },
154 { & m32r_cgen_hw_entries
[5], "h-addr", CGEN_ASM_KEYWORD
/*FIXME*/, 0 },
155 { & m32r_cgen_hw_entries
[6], "h-iaddr", CGEN_ASM_KEYWORD
/*FIXME*/, 0 },
156 { & m32r_cgen_hw_entries
[7], "h-hi16", CGEN_ASM_KEYWORD
/*FIXME*/, 0 },
157 { & m32r_cgen_hw_entries
[8], "h-slo16", CGEN_ASM_KEYWORD
/*FIXME*/, 0 },
158 { & m32r_cgen_hw_entries
[9], "h-ulo16", CGEN_ASM_KEYWORD
/*FIXME*/, 0 },
159 { & m32r_cgen_hw_entries
[10], "h-gr", CGEN_ASM_KEYWORD
/*FIXME*/, & m32r_cgen_opval_h_gr
},
160 { & m32r_cgen_hw_entries
[11], "h-cr", CGEN_ASM_KEYWORD
/*FIXME*/, & m32r_cgen_opval_h_cr
},
161 { & m32r_cgen_hw_entries
[12], "h-accum", CGEN_ASM_KEYWORD
/*FIXME*/, 0 },
162 { & m32r_cgen_hw_entries
[13], "h-accums", CGEN_ASM_KEYWORD
/*FIXME*/, & m32r_cgen_opval_h_accums
},
163 { & m32r_cgen_hw_entries
[14], "h-abort", CGEN_ASM_KEYWORD
/*FIXME*/, 0 },
164 { & m32r_cgen_hw_entries
[15], "h-cond", CGEN_ASM_KEYWORD
/*FIXME*/, 0 },
165 { & m32r_cgen_hw_entries
[16], "h-sm", CGEN_ASM_KEYWORD
/*FIXME*/, 0 },
166 { & m32r_cgen_hw_entries
[17], "h-bsm", CGEN_ASM_KEYWORD
/*FIXME*/, 0 },
167 { & m32r_cgen_hw_entries
[18], "h-ie", CGEN_ASM_KEYWORD
/*FIXME*/, 0 },
168 { & m32r_cgen_hw_entries
[19], "h-bie", CGEN_ASM_KEYWORD
/*FIXME*/, 0 },
169 { & m32r_cgen_hw_entries
[20], "h-bcond", CGEN_ASM_KEYWORD
/*FIXME*/, 0 },
170 { NULL
, "h-bpc", CGEN_ASM_KEYWORD
/*FIXME*/, 0 }
174 const CGEN_OPERAND m32r_cgen_operand_table
[CGEN_NUM_OPERANDS
] =
176 /* pc: program counter */
177 { "pc", 0, 0, { 0, 0|(1<<CGEN_OPERAND_FAKE
)|(1<<CGEN_OPERAND_PC
), { 0 } } },
178 /* sr: source register */
179 { "sr", 12, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
180 /* dr: destination register */
181 { "dr", 4, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
182 /* src1: source register 1 */
183 { "src1", 4, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
184 /* src2: source register 2 */
185 { "src2", 12, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
186 /* scr: source control register */
187 { "scr", 12, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
188 /* dcr: destination control register */
189 { "dcr", 4, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
190 /* simm8: 8 bit signed immediate */
191 { "simm8", 8, 8, { 0, 0, { 0 } } },
192 /* simm16: 16 bit signed immediate */
193 { "simm16", 16, 16, { 0, 0, { 0 } } },
194 /* uimm4: 4 bit trap number */
195 { "uimm4", 12, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
196 /* uimm5: 5 bit shift count */
197 { "uimm5", 11, 5, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
198 /* uimm16: 16 bit unsigned immediate */
199 { "uimm16", 16, 16, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
200 /* acc-s: accumulator register */
201 { "acc-s", 12, 2, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
202 /* acc: accumulator reg (d) */
203 { "acc", 8, 1, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
204 /* hi16: high 16 bit immediate, sign optional */
205 { "hi16", 16, 16, { 0, 0|(1<<CGEN_OPERAND_SIGN_OPT
)|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
206 /* slo16: 16 bit signed immediate, for low() */
207 { "slo16", 16, 16, { 0, 0, { 0 } } },
208 /* ulo16: 16 bit unsigned immediate, for low() */
209 { "ulo16", 16, 16, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
210 /* uimm24: 24 bit address */
211 { "uimm24", 8, 24, { 0, 0|(1<<CGEN_OPERAND_RELOC
)|(1<<CGEN_OPERAND_ABS_ADDR
)|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
212 /* disp8: 8 bit displacement */
213 { "disp8", 8, 8, { 0, 0|(1<<CGEN_OPERAND_RELAX
)|(1<<CGEN_OPERAND_RELOC
)|(1<<CGEN_OPERAND_PCREL_ADDR
), { 0 } } },
214 /* disp16: 16 bit displacement */
215 { "disp16", 16, 16, { 0, 0|(1<<CGEN_OPERAND_RELOC
)|(1<<CGEN_OPERAND_PCREL_ADDR
), { 0 } } },
216 /* disp24: 24 bit displacement */
217 { "disp24", 8, 24, { 0, 0|(1<<CGEN_OPERAND_RELAX
)|(1<<CGEN_OPERAND_RELOC
)|(1<<CGEN_OPERAND_PCREL_ADDR
), { 0 } } },
218 /* condbit: condition bit */
219 { "condbit", 0, 0, { 0, 0|(1<<CGEN_OPERAND_FAKE
), { 0 } } },
220 /* accum: accumulator */
221 { "accum", 0, 0, { 0, 0|(1<<CGEN_OPERAND_FAKE
), { 0 } } },
222 /* abort-parallel-execution: abort parallel execution */
223 { "abort-parallel-execution", 0, 0, { 0, 0|(1<<CGEN_OPERAND_FAKE
), { 0 } } },
226 #define OP 1 /* syntax value for mnemonic */
228 static const CGEN_SYNTAX syntax_table
[] = {
230 /* 0 */ { OP
, ' ', 130, ',', 129, 0 },
231 /* <op> $dr,$sr,$slo16 */
232 /* 1 */ { OP
, ' ', 130, ',', 129, ',', 143, 0 },
233 /* <op> $dr,$sr,$uimm16 */
234 /* 2 */ { OP
, ' ', 130, ',', 129, ',', 139, 0 },
235 /* <op> $dr,$sr,$ulo16 */
236 /* 3 */ { OP
, ' ', 130, ',', 129, ',', 144, 0 },
237 /* <op> $dr,$simm8 */
238 /* 4 */ { OP
, ' ', 130, ',', 135, 0 },
239 /* <op> $dr,$sr,$simm16 */
240 /* 5 */ { OP
, ' ', 130, ',', 129, ',', 136, 0 },
242 /* 6 */ { OP
, ' ', 146, 0 },
244 /* 7 */ { OP
, ' ', 148, 0 },
245 /* <op> $src1,$src2,$disp16 */
246 /* 8 */ { OP
, ' ', 131, ',', 132, ',', 147, 0 },
247 /* <op> $src2,$disp16 */
248 /* 9 */ { OP
, ' ', 132, ',', 147, 0 },
249 /* <op> $src1,$src2 */
250 /* 10 */ { OP
, ' ', 131, ',', 132, 0 },
251 /* <op> $src2,$simm16 */
252 /* 11 */ { OP
, ' ', 132, ',', 136, 0 },
253 /* <op> $src2,$uimm16 */
254 /* 12 */ { OP
, ' ', 132, ',', 139, 0 },
256 /* 13 */ { OP
, ' ', 132, 0 },
258 /* 14 */ { OP
, ' ', 129, 0 },
260 /* 15 */ { OP
, ' ', 130, ',', '@', 129, 0 },
261 /* <op> $dr,@($sr) */
262 /* 16 */ { OP
, ' ', 130, ',', '@', '(', 129, ')', 0 },
263 /* <op> $dr,@($slo16,$sr) */
264 /* 17 */ { OP
, ' ', 130, ',', '@', '(', 143, ',', 129, ')', 0 },
265 /* <op> $dr,@($sr,$slo16) */
266 /* 18 */ { OP
, ' ', 130, ',', '@', '(', 129, ',', 143, ')', 0 },
268 /* 19 */ { OP
, ' ', 130, ',', '@', 129, '+', 0 },
269 /* <op> $dr,$uimm24 */
270 /* 20 */ { OP
, ' ', 130, ',', 145, 0 },
271 /* <op> $dr,$slo16 */
272 /* 21 */ { OP
, ' ', 130, ',', 143, 0 },
273 /* <op> $src1,$src2,$acc */
274 /* 22 */ { OP
, ' ', 131, ',', 132, ',', 141, 0 },
276 /* 23 */ { OP
, ' ', 130, 0 },
278 /* 24 */ { OP
, ' ', 130, ',', 141, 0 },
280 /* 25 */ { OP
, ' ', 130, ',', 133, 0 },
282 /* 26 */ { OP
, ' ', 131, 0 },
283 /* <op> $src1,$accs */
284 /* 27 */ { OP
, ' ', 131, ',', 141, 0 },
286 /* 28 */ { OP
, ' ', 129, ',', 134, 0 },
290 /* 30 */ { OP
, ' ', 141, 0 },
292 /* 31 */ { OP
, ' ', 130, ',', 142, 0 },
293 /* <op> $dr,$uimm5 */
294 /* 32 */ { OP
, ' ', 130, ',', 138, 0 },
295 /* <op> $src1,@$src2 */
296 /* 33 */ { OP
, ' ', 131, ',', '@', 132, 0 },
297 /* <op> $src1,@($src2) */
298 /* 34 */ { OP
, ' ', 131, ',', '@', '(', 132, ')', 0 },
299 /* <op> $src1,@($slo16,$src2) */
300 /* 35 */ { OP
, ' ', 131, ',', '@', '(', 143, ',', 132, ')', 0 },
301 /* <op> $src1,@($src2,$slo16) */
302 /* 36 */ { OP
, ' ', 131, ',', '@', '(', 132, ',', 143, ')', 0 },
303 /* <op> $src1,@+$src2 */
304 /* 37 */ { OP
, ' ', 131, ',', '@', '+', 132, 0 },
305 /* <op> $src1,@-$src2 */
306 /* 38 */ { OP
, ' ', 131, ',', '@', '-', 132, 0 },
308 /* 39 */ { OP
, ' ', 137, 0 },
310 /* 40 */ { OP
, ' ', 130, ',', 132, 0 },
315 static const CGEN_FORMAT format_table
[] = {
316 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr. */
317 /* 0 */ { 16, 16, 0xf0f0 },
318 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.slo16. */
319 /* 1 */ { 32, 32, 0xf0f00000 },
320 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-uimm16.uimm16. */
321 /* 2 */ { 32, 32, 0xf0f00000 },
322 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-uimm16.ulo16. */
323 /* 3 */ { 32, 32, 0xf0f00000 },
324 /* f-op1.number.f-r1.dr.f-simm8.simm8. */
325 /* 4 */ { 16, 16, 0xf000 },
326 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.simm16. */
327 /* 5 */ { 32, 32, 0xf0f00000 },
328 /* f-op1.number.f-r1.number.f-disp8.disp8. */
329 /* 6 */ { 16, 16, 0xff00 },
330 /* f-op1.number.f-r1.number.f-disp24.disp24. */
331 /* 7 */ { 32, 32, 0xff000000 },
332 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2.f-disp16.disp16. */
333 /* 8 */ { 32, 32, 0xf0f00000 },
334 /* f-op1.number.f-r1.number.f-op2.number.f-r2.src2.f-disp16.disp16. */
335 /* 9 */ { 32, 32, 0xfff00000 },
336 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2. */
337 /* 10 */ { 16, 16, 0xf0f0 },
338 /* f-op1.number.f-r1.number.f-op2.number.f-r2.src2.f-simm16.simm16. */
339 /* 11 */ { 32, 32, 0xfff00000 },
340 /* f-op1.number.f-r1.number.f-op2.number.f-r2.src2.f-uimm16.uimm16. */
341 /* 12 */ { 32, 32, 0xfff00000 },
342 /* f-op1.number.f-r1.number.f-op2.number.f-r2.src2. */
343 /* 13 */ { 16, 16, 0xfff0 },
344 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.number. */
345 /* 14 */ { 32, 32, 0xf0f0ffff },
346 /* f-op1.number.f-r1.number.f-op2.number.f-r2.sr. */
347 /* 15 */ { 16, 16, 0xfff0 },
348 /* f-op1.number.f-r1.dr.f-uimm24.uimm24. */
349 /* 16 */ { 32, 32, 0xf0000000 },
350 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.number.f-simm16.slo16. */
351 /* 17 */ { 32, 32, 0xf0ff0000 },
352 /* f-op1.number.f-r1.src1.f-acc.acc.f-op23.number.f-r2.src2. */
353 /* 18 */ { 16, 16, 0xf070 },
354 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.number. */
355 /* 19 */ { 16, 16, 0xf0ff },
356 /* f-op1.number.f-r1.dr.f-op2.number.f-acc-s.acc-s.f-op3.number. */
357 /* 20 */ { 16, 16, 0xf0f3 },
358 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.scr. */
359 /* 21 */ { 16, 16, 0xf0f0 },
360 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.number. */
361 /* 22 */ { 16, 16, 0xf0ff },
362 /* f-op1.number.f-r1.src1.f-op2.number.f-acc-s.acc-s.f-op3.number. */
363 /* 23 */ { 16, 16, 0xf0f3 },
364 /* f-op1.number.f-r1.dcr.f-op2.number.f-r2.sr. */
365 /* 24 */ { 16, 16, 0xf0f0 },
366 /* f-op1.number.f-r1.number.f-op2.number.f-r2.number. */
367 /* 25 */ { 16, 16, 0xffff },
368 /* f-op1.number.f-r1.number.f-op2.number.f-acc-s.acc-s.f-op3.number. */
369 /* 26 */ { 16, 16, 0xfff3 },
370 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.number.f-hi16.hi16. */
371 /* 27 */ { 32, 32, 0xf0ff0000 },
372 /* f-op1.number.f-r1.dr.f-shift-op2.number.f-uimm5.uimm5. */
373 /* 28 */ { 16, 16, 0xf0e0 },
374 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2.f-simm16.slo16. */
375 /* 29 */ { 32, 32, 0xf0f00000 },
376 /* f-op1.number.f-r1.number.f-op2.number.f-uimm4.uimm4. */
377 /* 30 */ { 16, 16, 0xfff0 },
378 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.src2.f-uimm16.number. */
379 /* 31 */ { 32, 32, 0xf0f0ffff },
382 #define A(a) (1 << CGEN_CAT3 (CGEN_INSN,_,a))
383 #define SYN(n) (& syntax_table[n])
384 #define FMT(n) (& format_table[n])
386 const CGEN_INSN m32r_cgen_insn_table_entries
[CGEN_NUM_INSNS
] = {
387 /* null first entry, end of all hash chains */
392 "add", "add", SYN (0), FMT (0), 0xa0,
393 { 2, 0|A(PARALLEL
), { [CGEN_INSN_PIPE
] = PIPE_OS
} }
395 /* add3 $dr,$sr,$slo16 */
398 "add3", "add3", SYN (1), FMT (1), 0x80a00000,
404 "and", "and", SYN (0), FMT (0), 0xc0,
405 { 2, 0|A(PARALLEL
), { [CGEN_INSN_PIPE
] = PIPE_OS
} }
407 /* and3 $dr,$sr,$uimm16 */
410 "and3", "and3", SYN (2), FMT (2), 0x80c00000,
416 "or", "or", SYN (0), FMT (0), 0xe0,
417 { 2, 0|A(PARALLEL
), { [CGEN_INSN_PIPE
] = PIPE_OS
} }
419 /* or3 $dr,$sr,$ulo16 */
422 "or3", "or3", SYN (3), FMT (3), 0x80e00000,
428 "xor", "xor", SYN (0), FMT (0), 0xd0,
429 { 2, 0|A(PARALLEL
), { [CGEN_INSN_PIPE
] = PIPE_OS
} }
431 /* xor3 $dr,$sr,$uimm16 */
434 "xor3", "xor3", SYN (2), FMT (2), 0x80d00000,
437 /* addi $dr,$simm8 */
440 "addi", "addi", SYN (4), FMT (4), 0x4000,
441 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_OS
} }
446 "addv", "addv", SYN (0), FMT (0), 0x80,
447 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_OS
} }
449 /* addv3 $dr,$sr,$simm16 */
452 "addv3", "addv3", SYN (5), FMT (5), 0x80800000,
458 "addx", "addx", SYN (0), FMT (0), 0x90,
459 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_OS
} }
464 "bc8", "bc", SYN (6), FMT (6), 0x7c00,
465 { 2, 0|A(RELAX_BC
)|A(RELAXABLE
)|A(COND_CTI
), { [CGEN_INSN_PIPE
] = PIPE_O
} }
470 "bc8.s", "bc.s", SYN (6), FMT (6), 0x7c00,
471 { 2, 0|A(ALIAS
)|A(COND_CTI
), { [CGEN_INSN_PIPE
] = PIPE_O
} }
476 "bc24", "bc", SYN (7), FMT (7), 0xfc000000,
477 { 2, 0|A(RELAX_BC
)|A(RELAX
)|A(COND_CTI
), { 0 } }
482 "bc24.l", "bc.l", SYN (7), FMT (7), 0xfc000000,
483 { 2, 0|A(ALIAS
)|A(COND_CTI
), { 0 } }
485 /* beq $src1,$src2,$disp16 */
488 "beq", "beq", SYN (8), FMT (8), 0xb0000000,
489 { 2, 0|A(COND_CTI
), { 0 } }
491 /* beqz $src2,$disp16 */
494 "beqz", "beqz", SYN (9), FMT (9), 0xb0800000,
495 { 2, 0|A(COND_CTI
), { 0 } }
497 /* bgez $src2,$disp16 */
500 "bgez", "bgez", SYN (9), FMT (9), 0xb0b00000,
501 { 2, 0|A(COND_CTI
), { 0 } }
503 /* bgtz $src2,$disp16 */
506 "bgtz", "bgtz", SYN (9), FMT (9), 0xb0d00000,
507 { 2, 0|A(COND_CTI
), { 0 } }
509 /* blez $src2,$disp16 */
512 "blez", "blez", SYN (9), FMT (9), 0xb0c00000,
513 { 2, 0|A(COND_CTI
), { 0 } }
515 /* bltz $src2,$disp16 */
518 "bltz", "bltz", SYN (9), FMT (9), 0xb0a00000,
519 { 2, 0|A(COND_CTI
), { 0 } }
521 /* bnez $src2,$disp16 */
524 "bnez", "bnez", SYN (9), FMT (9), 0xb0900000,
525 { 2, 0|A(COND_CTI
), { 0 } }
530 "bl8", "bl", SYN (6), FMT (6), 0x7e00,
531 { 2, 0|A(FILL_SLOT
)|A(RELAX_BL
)|A(RELAXABLE
)|A(UNCOND_CTI
), { [CGEN_INSN_PIPE
] = PIPE_O
} }
536 "bl8.s", "bl.s", SYN (6), FMT (6), 0x7e00,
537 { 2, 0|A(FILL_SLOT
)|A(ALIAS
)|A(UNCOND_CTI
), { [CGEN_INSN_PIPE
] = PIPE_O
} }
542 "bl24", "bl", SYN (7), FMT (7), 0xfe000000,
543 { 2, 0|A(RELAX_BL
)|A(RELAX
)|A(UNCOND_CTI
), { 0 } }
548 "bl24.l", "bl.l", SYN (7), FMT (7), 0xfe000000,
549 { 2, 0|A(ALIAS
)|A(UNCOND_CTI
), { 0 } }
554 "bcl8", "bcl", SYN (6), FMT (6), 0x7800,
555 { 2, 0|A(RELAX_BCL
)|A(RELAXABLE
)|A(COND_CTI
), { [CGEN_INSN_PIPE
] = PIPE_O
, [CGEN_INSN_MACH
] = 1 << MACH_M32RX
} }
560 "bcl8.s", "bcl.s", SYN (6), FMT (6), 0x7800,
561 { 2, 0|A(ALIAS
)|A(COND_CTI
), { [CGEN_INSN_PIPE
] = PIPE_O
, [CGEN_INSN_MACH
] = 1 << MACH_M32RX
} }
566 "bcl24", "bcl", SYN (7), FMT (7), 0xf8000000,
567 { 2, 0|A(RELAX_BCL
)|A(RELAX
)|A(COND_CTI
), { [CGEN_INSN_MACH
] = 1 << MACH_M32RX
} }
572 "bcl24.l", "bcl.l", SYN (7), FMT (7), 0xf8000000,
573 { 2, 0|A(ALIAS
)|A(COND_CTI
), { [CGEN_INSN_MACH
] = 1 << MACH_M32RX
} }
578 "bnc8", "bnc", SYN (6), FMT (6), 0x7d00,
579 { 2, 0|A(RELAX_BNC
)|A(RELAXABLE
)|A(COND_CTI
), { [CGEN_INSN_PIPE
] = PIPE_O
} }
584 "bnc8.s", "bnc.s", SYN (6), FMT (6), 0x7d00,
585 { 2, 0|A(ALIAS
)|A(COND_CTI
), { [CGEN_INSN_PIPE
] = PIPE_O
} }
590 "bnc24", "bnc", SYN (7), FMT (7), 0xfd000000,
591 { 2, 0|A(RELAX_BNC
)|A(RELAX
)|A(COND_CTI
), { 0 } }
596 "bnc24.l", "bnc.l", SYN (7), FMT (7), 0xfd000000,
597 { 2, 0|A(ALIAS
)|A(COND_CTI
), { 0 } }
599 /* bne $src1,$src2,$disp16 */
602 "bne", "bne", SYN (8), FMT (8), 0xb0100000,
603 { 2, 0|A(COND_CTI
), { 0 } }
608 "bra8", "bra", SYN (6), FMT (6), 0x7f00,
609 { 2, 0|A(FILL_SLOT
)|A(RELAX_BRA
)|A(RELAXABLE
)|A(UNCOND_CTI
), { [CGEN_INSN_PIPE
] = PIPE_O
} }
614 "bra8.s", "bra.s", SYN (6), FMT (6), 0x7f00,
615 { 2, 0|A(ALIAS
)|A(UNCOND_CTI
), { [CGEN_INSN_PIPE
] = PIPE_O
} }
620 "bra24", "bra", SYN (7), FMT (7), 0xff000000,
621 { 2, 0|A(RELAX_BRA
)|A(RELAX
)|A(UNCOND_CTI
), { 0 } }
626 "bra24.l", "bra.l", SYN (7), FMT (7), 0xff000000,
627 { 2, 0|A(ALIAS
)|A(UNCOND_CTI
), { 0 } }
632 "bncl8", "bncl", SYN (6), FMT (6), 0x7900,
633 { 2, 0|A(RELAX_BNCL
)|A(RELAXABLE
)|A(COND_CTI
), { [CGEN_INSN_PIPE
] = PIPE_O
, [CGEN_INSN_MACH
] = 1 << MACH_M32RX
} }
638 "bncl8.s", "bncl.s", SYN (6), FMT (6), 0x7900,
639 { 2, 0|A(ALIAS
)|A(COND_CTI
), { [CGEN_INSN_MACH
] = 1 << MACH_M32RX
} }
644 "bncl24", "bncl", SYN (7), FMT (7), 0xf9000000,
645 { 2, 0|A(RELAX_BNC
)|A(RELAX
)|A(COND_CTI
), { [CGEN_INSN_MACH
] = 1 << MACH_M32RX
} }
650 "bncl24.l", "bncl.l", SYN (7), FMT (7), 0xf9000000,
651 { 2, 0|A(ALIAS
)|A(COND_CTI
), { [CGEN_INSN_MACH
] = 1 << MACH_M32RX
} }
653 /* cmp $src1,$src2 */
656 "cmp", "cmp", SYN (10), FMT (10), 0x40,
657 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_OS
} }
659 /* cmpi $src2,$simm16 */
662 "cmpi", "cmpi", SYN (11), FMT (11), 0x80400000,
665 /* cmpu $src1,$src2 */
668 "cmpu", "cmpu", SYN (10), FMT (10), 0x50,
669 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_OS
} }
671 /* cmpui $src2,$uimm16 */
674 "cmpui", "cmpui", SYN (12), FMT (12), 0x80500000,
675 { 2, 0, { [CGEN_INSN_MACH
] = (1 << MACH_M32R
) | (1 << MACH_M32RX
) } }
677 /* cmpeq $src1,$src2 */
680 "cmpeq", "cmpeq", SYN (10), FMT (10), 0x60,
681 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_OS
, [CGEN_INSN_MACH
] = 1 << MACH_M32RX
} }
686 "cmpz", "cmpz", SYN (13), FMT (13), 0x70,
687 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_OS
, [CGEN_INSN_MACH
] = 1 << MACH_M32RX
} }
692 "div", "div", SYN (0), FMT (14), 0x90000000,
698 "divu", "divu", SYN (0), FMT (14), 0x90100000,
704 "rem", "rem", SYN (0), FMT (14), 0x90200000,
710 "remu", "remu", SYN (0), FMT (14), 0x90300000,
716 "jc", "jc", SYN (14), FMT (15), 0x1cc0,
717 { 2, 0|A(COND_CTI
), { [CGEN_INSN_PIPE
] = PIPE_O
, [CGEN_INSN_MACH
] = 1 << MACH_M32RX
} }
722 "jnc", "jnc", SYN (14), FMT (15), 0x1cc0,
723 { 2, 0|A(COND_CTI
), { [CGEN_INSN_PIPE
] = PIPE_O
, [CGEN_INSN_MACH
] = 1 << MACH_M32RX
} }
728 "jl", "jl", SYN (14), FMT (15), 0x1ec0,
729 { 2, 0|A(FILL_SLOT
)|A(UNCOND_CTI
), { [CGEN_INSN_PIPE
] = PIPE_O
} }
734 "jmp", "jmp", SYN (14), FMT (15), 0x1fc0,
735 { 2, 0|A(UNCOND_CTI
), { [CGEN_INSN_PIPE
] = PIPE_O
} }
740 "ld", "ld", SYN (15), FMT (0), 0x20c0,
741 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_O
} }
746 "ld-2", "ld", SYN (16), FMT (0), 0x20c0,
747 { 2, 0|A(ALIAS
), { [CGEN_INSN_PIPE
] = PIPE_O
} }
749 /* ld $dr,@($slo16,$sr) */
752 "ld-d", "ld", SYN (17), FMT (1), 0xa0c00000,
755 /* ld $dr,@($sr,$slo16) */
758 "ld-d2", "ld", SYN (18), FMT (1), 0xa0c00000,
759 { 2, 0|A(ALIAS
), { 0 } }
764 "ldb", "ldb", SYN (15), FMT (0), 0x2080,
765 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_O
} }
770 "ldb-2", "ldb", SYN (16), FMT (0), 0x2080,
771 { 2, 0|A(ALIAS
), { [CGEN_INSN_PIPE
] = PIPE_O
} }
773 /* ldb $dr,@($slo16,$sr) */
776 "ldb-d", "ldb", SYN (17), FMT (1), 0xa0800000,
779 /* ldb $dr,@($sr,$slo16) */
782 "ldb-d2", "ldb", SYN (18), FMT (1), 0xa0800000,
783 { 2, 0|A(ALIAS
), { 0 } }
788 "ldh", "ldh", SYN (15), FMT (0), 0x20a0,
789 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_O
} }
794 "ldh-2", "ldh", SYN (16), FMT (0), 0x20a0,
795 { 2, 0|A(ALIAS
), { [CGEN_INSN_PIPE
] = PIPE_O
} }
797 /* ldh $dr,@($slo16,$sr) */
800 "ldh-d", "ldh", SYN (17), FMT (1), 0xa0a00000,
803 /* ldh $dr,@($sr,$slo16) */
806 "ldh-d2", "ldh", SYN (18), FMT (1), 0xa0a00000,
807 { 2, 0|A(ALIAS
), { 0 } }
812 "ldub", "ldub", SYN (15), FMT (0), 0x2090,
813 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_O
} }
815 /* ldub $dr,@($sr) */
818 "ldub-2", "ldub", SYN (16), FMT (0), 0x2090,
819 { 2, 0|A(ALIAS
), { [CGEN_INSN_PIPE
] = PIPE_O
} }
821 /* ldub $dr,@($slo16,$sr) */
824 "ldub-d", "ldub", SYN (17), FMT (1), 0xa0900000,
827 /* ldub $dr,@($sr,$slo16) */
830 "ldub-d2", "ldub", SYN (18), FMT (1), 0xa0900000,
831 { 2, 0|A(ALIAS
), { 0 } }
836 "lduh", "lduh", SYN (15), FMT (0), 0x20b0,
837 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_O
} }
839 /* lduh $dr,@($sr) */
842 "lduh-2", "lduh", SYN (16), FMT (0), 0x20b0,
843 { 2, 0|A(ALIAS
), { [CGEN_INSN_PIPE
] = PIPE_O
} }
845 /* lduh $dr,@($slo16,$sr) */
848 "lduh-d", "lduh", SYN (17), FMT (1), 0xa0b00000,
851 /* lduh $dr,@($sr,$slo16) */
854 "lduh-d2", "lduh", SYN (18), FMT (1), 0xa0b00000,
855 { 2, 0|A(ALIAS
), { 0 } }
860 "ld-plus", "ld", SYN (19), FMT (0), 0x20e0,
861 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_O
} }
863 /* ld24 $dr,$uimm24 */
866 "ld24", "ld24", SYN (20), FMT (16), 0xe0000000,
872 "ldi8", "ldi", SYN (4), FMT (4), 0x6000,
873 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_OS
} }
875 /* ldi8 $dr,$simm8 */
878 "ldi8a", "ldi8", SYN (4), FMT (4), 0x6000,
879 { 2, 0|A(ALIAS
), { [CGEN_INSN_PIPE
] = PIPE_OS
} }
884 "ldi16", "ldi", SYN (21), FMT (17), 0x90f00000,
887 /* ldi16 $dr,$slo16 */
890 "ldi16a", "ldi16", SYN (21), FMT (17), 0x90f00000,
891 { 2, 0|A(ALIAS
), { 0 } }
896 "lock", "lock", SYN (15), FMT (0), 0x20d0,
897 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_O
} }
899 /* machi $src1,$src2 */
902 "machi", "machi", SYN (10), FMT (10), 0x3040,
903 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_S
} }
905 /* machi $src1,$src2,$acc */
908 "machi-a", "machi", SYN (22), FMT (18), 0x3040,
909 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_S
, [CGEN_INSN_MACH
] = 1 << MACH_M32RX
} }
911 /* maclo $src1,$src2 */
914 "maclo", "maclo", SYN (10), FMT (10), 0x3050,
915 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_S
} }
917 /* maclo $src1,$src2,$acc */
920 "maclo-a", "maclo", SYN (22), FMT (18), 0x3050,
921 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_S
, [CGEN_INSN_MACH
] = 1 << MACH_M32RX
} }
923 /* macwhi $src1,$src2 */
926 "macwhi", "macwhi", SYN (10), FMT (10), 0x3060,
927 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_S
} }
929 /* macwhi $src1,$src2,$acc */
932 "macwhi-a", "macwhi", SYN (22), FMT (18), 0x3060,
933 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_S
, [CGEN_INSN_MACH
] = 1 << MACH_M32RX
} }
935 /* macwlo $src1,$src2 */
938 "macwlo", "macwlo", SYN (10), FMT (10), 0x3070,
939 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_S
} }
941 /* macwlo $src1,$src2,$acc */
944 "macwlo-a", "macwlo", SYN (22), FMT (18), 0x3070,
945 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_S
, [CGEN_INSN_MACH
] = 1 << MACH_M32RX
} }
950 "mul", "mul", SYN (0), FMT (0), 0x1060,
951 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_S
} }
953 /* mulhi $src1,$src2 */
956 "mulhi", "mulhi", SYN (10), FMT (10), 0x3000,
957 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_S
} }
959 /* mulhi $src1,$src2,$acc */
962 "mulhi-a", "mulhi", SYN (22), FMT (18), 0x3000,
963 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_S
, [CGEN_INSN_MACH
] = 1 << MACH_M32RX
} }
965 /* mullo $src1,$src2 */
968 "mullo", "mullo", SYN (10), FMT (10), 0x3010,
969 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_S
} }
971 /* mullo $src1,$src2,$acc */
974 "mullo-a", "mullo", SYN (22), FMT (18), 0x3010,
975 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_S
, [CGEN_INSN_MACH
] = 1 << MACH_M32RX
} }
977 /* mulwhi $src1,$src2 */
980 "mulwhi", "mulwhi", SYN (10), FMT (10), 0x3020,
981 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_S
} }
983 /* mulwhi $src1,$src2,$acc */
986 "mulwhi-a", "mulwhi", SYN (22), FMT (18), 0x3020,
987 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_S
, [CGEN_INSN_MACH
] = 1 << MACH_M32RX
} }
989 /* mulwlo $src1,$src2 */
992 "mulwlo", "mulwlo", SYN (10), FMT (10), 0x3030,
993 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_S
} }
995 /* mulwlo $src1,$src2,$acc */
998 "mulwlo-a", "mulwlo", SYN (22), FMT (18), 0x3030,
999 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_S
, [CGEN_INSN_MACH
] = 1 << MACH_M32RX
} }
1004 "mv", "mv", SYN (0), FMT (0), 0x1080,
1005 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_OS
} }
1010 "mvfachi", "mvfachi", SYN (23), FMT (19), 0x50f0,
1011 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_S
} }
1013 /* mvfachi $dr,$accs */
1016 "mvfachi-a", "mvfachi", SYN (24), FMT (20), 0x50f0,
1017 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_S
, [CGEN_INSN_MACH
] = 1 << MACH_M32RX
} }
1022 "mvfaclo", "mvfaclo", SYN (23), FMT (19), 0x50f1,
1023 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_S
} }
1025 /* mvfaclo $dr,$acc-s */
1028 "mvfaclo-a", "mvfaclo", SYN (24), FMT (20), 0x50f1,
1029 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_S
, [CGEN_INSN_MACH
] = 1 << MACH_M32RX
} }
1034 "mvfacmi", "mvfacmi", SYN (23), FMT (19), 0x50f2,
1035 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_S
} }
1037 /* mvfacmi $dr,$acc-s */
1040 "mvfacmi-a", "mvfacmi", SYN (24), FMT (20), 0x50f2,
1041 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_S
, [CGEN_INSN_MACH
] = 1 << MACH_M32RX
} }
1046 "mvfc", "mvfc", SYN (25), FMT (21), 0x1090,
1047 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_O
} }
1052 "mvtachi", "mvtachi", SYN (26), FMT (22), 0x5070,
1053 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_S
} }
1055 /* mvtachi $src1,$acc-s */
1058 "mvtachi-a", "mvtachi", SYN (27), FMT (23), 0x5070,
1059 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_S
, [CGEN_INSN_MACH
] = 1 << MACH_M32RX
} }
1064 "mvtaclo", "mvtaclo", SYN (26), FMT (22), 0x5071,
1065 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_S
} }
1067 /* mvtaclo $src1,$acc-s */
1070 "mvtaclo-a", "mvtaclo", SYN (27), FMT (23), 0x5071,
1071 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_S
, [CGEN_INSN_MACH
] = 1 << MACH_M32RX
} }
1076 "mvtc", "mvtc", SYN (28), FMT (24), 0x10a0,
1077 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_O
} }
1082 "neg", "neg", SYN (0), FMT (0), 0x30,
1083 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_OS
} }
1088 "nop", "nop", SYN (29), FMT (25), 0x7000,
1089 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_OS
} }
1094 "not", "not", SYN (0), FMT (0), 0xb0,
1095 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_OS
} }
1100 "rac", "rac", SYN (29), FMT (25), 0x5090,
1101 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_S
} }
1106 "rac-a", "rac", SYN (30), FMT (26), 0x5090,
1107 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_S
, [CGEN_INSN_MACH
] = 1 << MACH_M32RX
} }
1112 "rach", "rach", SYN (29), FMT (25), 0x5080,
1113 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_S
} }
1118 "rach-a", "rach", SYN (30), FMT (26), 0x5080,
1119 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_S
, [CGEN_INSN_MACH
] = 1 << MACH_M32RX
} }
1124 "rte", "rte", SYN (29), FMT (25), 0x10d6,
1125 { 2, 0|A(UNCOND_CTI
), { [CGEN_INSN_PIPE
] = PIPE_O
} }
1127 /* seth $dr,$hi16 */
1130 "seth", "seth", SYN (31), FMT (27), 0xd0c00000,
1136 "sll", "sll", SYN (0), FMT (0), 0x1040,
1137 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_O
} }
1139 /* sll3 $dr,$sr,$simm16 */
1142 "sll3", "sll3", SYN (5), FMT (5), 0x90c00000,
1145 /* slli $dr,$uimm5 */
1148 "slli", "slli", SYN (32), FMT (28), 0x5040,
1149 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_O
} }
1154 "sra", "sra", SYN (0), FMT (0), 0x1020,
1155 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_O
} }
1157 /* sra3 $dr,$sr,$simm16 */
1160 "sra3", "sra3", SYN (5), FMT (5), 0x90a00000,
1163 /* srai $dr,$uimm5 */
1166 "srai", "srai", SYN (32), FMT (28), 0x5020,
1167 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_O
} }
1172 "srl", "srl", SYN (0), FMT (0), 0x1000,
1173 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_O
} }
1175 /* srl3 $dr,$sr,$simm16 */
1178 "srl3", "srl3", SYN (5), FMT (5), 0x90800000,
1181 /* srli $dr,$uimm5 */
1184 "srli", "srli", SYN (32), FMT (28), 0x5000,
1185 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_O
} }
1187 /* st $src1,@$src2 */
1190 "st", "st", SYN (33), FMT (10), 0x2040,
1191 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_O
} }
1193 /* st $src1,@($src2) */
1196 "st-2", "st", SYN (34), FMT (10), 0x2040,
1197 { 2, 0|A(ALIAS
), { [CGEN_INSN_PIPE
] = PIPE_O
} }
1199 /* st $src1,@($slo16,$src2) */
1202 "st-d", "st", SYN (35), FMT (29), 0xa0400000,
1205 /* st $src1,@($src2,$slo16) */
1208 "st-d2", "st", SYN (36), FMT (29), 0xa0400000,
1209 { 2, 0|A(ALIAS
), { 0 } }
1211 /* stb $src1,@$src2 */
1214 "stb", "stb", SYN (33), FMT (10), 0x2000,
1215 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_O
} }
1217 /* stb $src1,@($src2) */
1220 "stb-2", "stb", SYN (34), FMT (10), 0x2000,
1221 { 2, 0|A(ALIAS
), { [CGEN_INSN_PIPE
] = PIPE_O
} }
1223 /* stb $src1,@($slo16,$src2) */
1226 "stb-d", "stb", SYN (35), FMT (29), 0xa0000000,
1229 /* stb $src1,@($src2,$slo16) */
1232 "stb-d2", "stb", SYN (36), FMT (29), 0xa0000000,
1233 { 2, 0|A(ALIAS
), { 0 } }
1235 /* sth $src1,@$src2 */
1238 "sth", "sth", SYN (33), FMT (10), 0x2020,
1239 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_O
} }
1241 /* sth $src1,@($src2) */
1244 "sth-2", "sth", SYN (34), FMT (10), 0x2020,
1245 { 2, 0|A(ALIAS
), { [CGEN_INSN_PIPE
] = PIPE_O
} }
1247 /* sth $src1,@($slo16,$src2) */
1250 "sth-d", "sth", SYN (35), FMT (29), 0xa0200000,
1253 /* sth $src1,@($src2,$slo16) */
1256 "sth-d2", "sth", SYN (36), FMT (29), 0xa0200000,
1257 { 2, 0|A(ALIAS
), { 0 } }
1259 /* st $src1,@+$src2 */
1262 "st-plus", "st", SYN (37), FMT (10), 0x2060,
1263 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_O
} }
1265 /* st $src1,@-$src2 */
1268 "st-minus", "st", SYN (38), FMT (10), 0x2070,
1269 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_O
} }
1274 "sub", "sub", SYN (0), FMT (0), 0x20,
1275 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_OS
} }
1280 "subv", "subv", SYN (0), FMT (0), 0x0,
1281 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_OS
} }
1286 "subx", "subx", SYN (0), FMT (0), 0x10,
1287 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_OS
} }
1292 "trap", "trap", SYN (39), FMT (30), 0x10f0,
1293 { 2, 0|A(FILL_SLOT
)|A(UNCOND_CTI
), { [CGEN_INSN_PIPE
] = PIPE_O
} }
1295 /* unlock $src1,@$src2 */
1298 "unlock", "unlock", SYN (33), FMT (10), 0x2050,
1299 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_O
} }
1304 "push", "push", SYN (26), FMT (22), 0x207f,
1305 { 2, 0|A(ALIAS
), { 0 } }
1310 "pop", "pop", SYN (23), FMT (19), 0x20ef,
1311 { 2, 0|A(ALIAS
), { 0 } }
1313 /* satb $dr,$src2 */
1316 "satb", "satb", SYN (40), FMT (31), 0x80000100,
1317 { 2, 0, { [CGEN_INSN_MACH
] = 1 << MACH_M32RX
} }
1319 /* sath $dr,$src2 */
1322 "sath", "sath", SYN (40), FMT (31), 0x80000200,
1323 { 2, 0, { [CGEN_INSN_MACH
] = 1 << MACH_M32RX
} }
1328 "sat", "sat", SYN (40), FMT (31), 0x80000000,
1329 { 2, 0, { [CGEN_INSN_MACH
] = 1 << MACH_M32RX
} }
1334 "pcmpbz", "pcmpbz", SYN (13), FMT (13), 0x370,
1335 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_OS
, [CGEN_INSN_MACH
] = 1 << MACH_M32RX
} }
1340 "sadd", "sadd", SYN (29), FMT (25), 0x50e4,
1341 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_S
, [CGEN_INSN_MACH
] = 1 << MACH_M32RX
} }
1343 /* macwu1 $src1,$src2 */
1346 "macwu1", "macwu1", SYN (10), FMT (10), 0x50b0,
1347 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_S
, [CGEN_INSN_MACH
] = 1 << MACH_M32RX
} }
1349 /* msblo $src1,$src2 */
1352 "msblo", "msblo", SYN (10), FMT (10), 0x50d0,
1353 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_S
, [CGEN_INSN_MACH
] = 1 << MACH_M32RX
} }
1355 /* mulwu1 $src1,$src2 */
1358 "mulwu1", "mulwu1", SYN (10), FMT (10), 0x50a0,
1359 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_S
, [CGEN_INSN_MACH
] = 1 << MACH_M32RX
} }
1361 /* machl1 $src1,$src2 */
1364 "machl1", "machl1", SYN (10), FMT (10), 0x50c0,
1365 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_S
, [CGEN_INSN_MACH
] = 1 << MACH_M32RX
} }
1370 "sc", "sc", SYN (29), FMT (25), 0x7401,
1371 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_O
, [CGEN_INSN_MACH
] = 1 << MACH_M32RX
} }
1376 "snc", "snc", SYN (29), FMT (25), 0x7501,
1377 { 2, 0, { [CGEN_INSN_PIPE
] = PIPE_O
, [CGEN_INSN_MACH
] = 1 << MACH_M32RX
} }
1385 CGEN_INSN_TABLE m32r_cgen_insn_table
= {
1386 & m32r_cgen_insn_table_entries
[0],
1390 m32r_cgen_asm_hash_insn
, CGEN_ASM_HASH_SIZE
,
1391 m32r_cgen_dis_hash_insn
, CGEN_DIS_HASH_SIZE
1394 /* The hash functions are recorded here to help keep assembler code out of
1395 the disassembler and vice versa. */
1398 m32r_cgen_asm_hash_insn (insn
)
1401 return CGEN_ASM_HASH (insn
);
1405 m32r_cgen_dis_hash_insn (buf
, value
)
1407 unsigned long value
;
1409 return CGEN_DIS_HASH (buf
, value
);
1412 CGEN_OPCODE_DATA m32r_cgen_opcode_data
= {
1413 & m32r_cgen_hw_entries
[0],
1414 & m32r_cgen_insn_table
,
1418 m32r_cgen_init_tables (mach
)
1423 /* Main entry point for stuffing values in cgen_fields. */
1426 m32r_cgen_set_operand (opindex
, valuep
, fields
)
1429 CGEN_FIELDS
*fields
;
1433 case M32R_OPERAND_SR
:
1434 fields
->f_r2
= *valuep
;
1436 case M32R_OPERAND_DR
:
1437 fields
->f_r1
= *valuep
;
1439 case M32R_OPERAND_SRC1
:
1440 fields
->f_r1
= *valuep
;
1442 case M32R_OPERAND_SRC2
:
1443 fields
->f_r2
= *valuep
;
1445 case M32R_OPERAND_SCR
:
1446 fields
->f_r2
= *valuep
;
1448 case M32R_OPERAND_DCR
:
1449 fields
->f_r1
= *valuep
;
1451 case M32R_OPERAND_SIMM8
:
1452 fields
->f_simm8
= *valuep
;
1454 case M32R_OPERAND_SIMM16
:
1455 fields
->f_simm16
= *valuep
;
1457 case M32R_OPERAND_UIMM4
:
1458 fields
->f_uimm4
= *valuep
;
1460 case M32R_OPERAND_UIMM5
:
1461 fields
->f_uimm5
= *valuep
;
1463 case M32R_OPERAND_UIMM16
:
1464 fields
->f_uimm16
= *valuep
;
1466 case M32R_OPERAND_ACC_S
:
1467 fields
->f_acc_s
= *valuep
;
1469 case M32R_OPERAND_ACC
:
1470 fields
->f_acc
= *valuep
;
1472 case M32R_OPERAND_HI16
:
1473 fields
->f_hi16
= *valuep
;
1475 case M32R_OPERAND_SLO16
:
1476 fields
->f_simm16
= *valuep
;
1478 case M32R_OPERAND_ULO16
:
1479 fields
->f_uimm16
= *valuep
;
1481 case M32R_OPERAND_UIMM24
:
1482 fields
->f_uimm24
= *valuep
;
1484 case M32R_OPERAND_DISP8
:
1485 fields
->f_disp8
= *valuep
;
1487 case M32R_OPERAND_DISP16
:
1488 fields
->f_disp16
= *valuep
;
1490 case M32R_OPERAND_DISP24
:
1491 fields
->f_disp24
= *valuep
;
1495 fprintf (stderr
, "Unrecognized field %d while setting operand.\n",
1501 /* Main entry point for getting values from cgen_fields. */
1504 m32r_cgen_get_operand (opindex
, fields
)
1506 const CGEN_FIELDS
*fields
;
1512 case M32R_OPERAND_SR
:
1513 value
= fields
->f_r2
;
1515 case M32R_OPERAND_DR
:
1516 value
= fields
->f_r1
;
1518 case M32R_OPERAND_SRC1
:
1519 value
= fields
->f_r1
;
1521 case M32R_OPERAND_SRC2
:
1522 value
= fields
->f_r2
;
1524 case M32R_OPERAND_SCR
:
1525 value
= fields
->f_r2
;
1527 case M32R_OPERAND_DCR
:
1528 value
= fields
->f_r1
;
1530 case M32R_OPERAND_SIMM8
:
1531 value
= fields
->f_simm8
;
1533 case M32R_OPERAND_SIMM16
:
1534 value
= fields
->f_simm16
;
1536 case M32R_OPERAND_UIMM4
:
1537 value
= fields
->f_uimm4
;
1539 case M32R_OPERAND_UIMM5
:
1540 value
= fields
->f_uimm5
;
1542 case M32R_OPERAND_UIMM16
:
1543 value
= fields
->f_uimm16
;
1545 case M32R_OPERAND_ACC_S
:
1546 value
= fields
->f_acc_s
;
1548 case M32R_OPERAND_ACC
:
1549 value
= fields
->f_acc
;
1551 case M32R_OPERAND_HI16
:
1552 value
= fields
->f_hi16
;
1554 case M32R_OPERAND_SLO16
:
1555 value
= fields
->f_simm16
;
1557 case M32R_OPERAND_ULO16
:
1558 value
= fields
->f_uimm16
;
1560 case M32R_OPERAND_UIMM24
:
1561 value
= fields
->f_uimm24
;
1563 case M32R_OPERAND_DISP8
:
1564 value
= fields
->f_disp8
;
1566 case M32R_OPERAND_DISP16
:
1567 value
= fields
->f_disp16
;
1569 case M32R_OPERAND_DISP24
:
1570 value
= fields
->f_disp24
;
1574 fprintf (stderr
, "Unrecognized field %d while getting operand.\n",