opcodes/m32r-opc.c

   1 /* Generic opcode table support for targets using CGEN. -*- C -*-
   2    CGEN: Cpu tools GENerator
   3
   4 THIS FILE IS USED TO GENERATE m32r-opc.c.
   5
   6 Copyright (C) 1998 Free Software Foundation, Inc.
   7
   8 This file is part of the GNU Binutils and GDB, the GNU debugger.
   9
  10 This program is free software; you can redistribute it and/or modify
  11 it under the terms of the GNU General Public License as published by
  12 the Free Software Foundation; either version 2, or (at your option)
  13 any later version.
  14
  15 This program is distributed in the hope that it will be useful,
  16 but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 GNU General Public License for more details.
  19
  20 You should have received a copy of the GNU General Public License
  21 along with this program; if not, write to the Free Software Foundation, Inc.,
  22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  23
  24 #include "sysdep.h"
  25 #include <stdio.h>
  26 #include "ansidecl.h"
  27 #include "libiberty.h"
  28 #include "bfd.h"
  29 #include "symcat.h"
  30 #include "m32r-opc.h"
  31 #include "opintl.h"
  32
  33 /* The hash functions are recorded here to help keep assembler code out of
  34    the disassembler and vice versa.  */
  35
  36 static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
  37 static unsigned int asm_hash_insn PARAMS ((const char *));
  38 static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
  39 static unsigned int dis_hash_insn PARAMS ((const char *, unsigned long));
  40
  41 /* Look up instruction INSN_VALUE and extract its fields.
  42    INSN, if non-null, is the insn table entry.
  43    Otherwise INSN_VALUE is examined to compute it.
  44    LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
  45    0 is only valid if `insn == NULL && ! defined (CGEN_INT_INSN)'.
  46    If INSN != NULL, LENGTH must be valid.
  47    ALIAS_P is non-zero if alias insns are to be included in the search.
  48
  49    The result a pointer to the insn table entry, or NULL if the instruction
  50    wasn't recognized.  */
  51
  52 const CGEN_INSN *
  53 m32r_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p)
  54      CGEN_OPCODE_DESC od;
  55      const CGEN_INSN *insn;
  56      cgen_insn_t insn_value;
  57      int length;
  58      CGEN_FIELDS *fields;
  59      int alias_p;
  60 {
  61   char buf[16];
  62
  63   if (!insn)
  64     {
  65       const CGEN_INSN_LIST *insn_list;
  66
  67 #ifdef CGEN_INT_INSN
  68       switch (length)
  69         {
  70         case 8:
  71           buf[0] = insn_value;
  72           break;
  73         case 16:
  74           if (CGEN_OPCODE_ENDIAN (od) == CGEN_ENDIAN_BIG)
  75             bfd_putb16 (insn_value, buf);
  76           else
  77             bfd_putl16 (insn_value, buf);
  78           break;
  79         case 32:
  80           if (CGEN_OPCODE_ENDIAN (od) == CGEN_ENDIAN_BIG)
  81             bfd_putb32 (insn_value, buf);
  82           else
  83             bfd_putl32 (insn_value, buf);
  84           break;
  85         default:
  86           abort ();
  87         }
  88 #else
  89       abort (); /* FIXME: unfinished */
  90 #endif
  91
  92       /* The instructions are stored in hash lists.
  93          Pick the first one and keep trying until we find the right one.  */
  94
  95       insn_list = CGEN_DIS_LOOKUP_INSN (od, buf, insn_value);
  96       while (insn_list != NULL)
  97         {
  98           insn = insn_list->insn;
  99
 100           if (alias_p
 101               || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
 102             {
 103               /* Basic bit mask must be correct.  */
 104               /* ??? May wish to allow target to defer this check until the
 105                  extract handler.  */
 106               if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
 107                 {
 108                   /* ??? 0 is passed for `pc' */
 109                   int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, NULL,
 110                                                            insn_value, fields,
 111                                                            (bfd_vma) 0);
 112                   if (elength > 0)
 113                     {
 114                       /* sanity check */
 115                       if (length != 0 && length != elength)
 116                         abort ();
 117                       return insn;
 118                     }
 119                 }
 120             }
 121
 122           insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 123         }
 124     }
 125   else
 126     {
 127       /* Sanity check: can't pass an alias insn if ! alias_p.  */
 128       if (! alias_p
 129           && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
 130         abort ();
 131       /* Sanity check: length must be correct.  */
 132       if (length != CGEN_INSN_BITSIZE (insn))
 133         abort ();
 134
 135       /* ??? 0 is passed for `pc' */
 136       length = (*CGEN_EXTRACT_FN (insn)) (od, insn, NULL, insn_value, fields,
 137                                           (bfd_vma) 0);
 138       /* Sanity check: must succeed.
 139          Could relax this later if it ever proves useful.  */
 140       if (length == 0)
 141         abort ();
 142       return insn;
 143     }
 144
 145   return NULL;
 146 }
 147
 148 /* Fill in the operand instances used by INSN whose operands are FIELDS.
 149    INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
 150    in.  */
 151
 152 void
 153 m32r_cgen_get_insn_operands (od, insn, fields, indices)
 154      CGEN_OPCODE_DESC od;
 155      const CGEN_INSN * insn;
 156      const CGEN_FIELDS * fields;
 157      int *indices;
 158 {
 159   const CGEN_OPERAND_INSTANCE *opinst;
 160   int i;
 161
 162   for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
 163        opinst != NULL
 164          && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
 165        ++i, ++opinst)
 166     {
 167       const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
 168       if (op == NULL)
 169         indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
 170       else
 171         indices[i] = m32r_cgen_get_int_operand (CGEN_OPERAND_INDEX (op),
 172                                                   fields);
 173     }
 174 }
 175
 176 /* Cover function to m32r_cgen_get_insn_operands when either INSN or FIELDS
 177    isn't known.
 178    The INSN, INSN_VALUE, and LENGTH arguments are passed to
 179    m32r_cgen_lookup_insn unchanged.
 180
 181    The result is the insn table entry or NULL if the instruction wasn't
 182    recognized.  */
 183
 184 const CGEN_INSN *
 185 m32r_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices)
 186      CGEN_OPCODE_DESC od;
 187      const CGEN_INSN *insn;
 188      cgen_insn_t insn_value;
 189      int length;
 190      int *indices;
 191 {
 192   CGEN_FIELDS fields;
 193
 194   /* Pass non-zero for ALIAS_P only if INSN != NULL.
 195      If INSN == NULL, we want a real insn.  */
 196   insn = m32r_cgen_lookup_insn (od, insn, insn_value, length, &fields,
 197                                   insn != NULL);
 198   if (! insn)
 199     return NULL;
 200
 201   m32r_cgen_get_insn_operands (od, insn, &fields, indices);
 202   return insn;
 203 }
 204 /* Attributes.  */
 205
 206 static const CGEN_ATTR_ENTRY MACH_attr[] =
 207 {
 208   { "m32r", MACH_M32R },
 209 /* start-sanitize-m32rx */
 210   { "m32rx", MACH_M32RX },
 211 /* end-sanitize-m32rx */
 212   { "max", MACH_MAX },
 213   { 0, 0 }
 214 };
 215
 216 /* start-sanitize-m32rx */
 217 static const CGEN_ATTR_ENTRY PIPE_attr[] =
 218 {
 219   { "NONE", PIPE_NONE },
 220   { "O", PIPE_O },
 221   { "S", PIPE_S },
 222   { "OS", PIPE_OS },
 223   { 0, 0 }
 224 };
 225
 226 /* end-sanitize-m32rx */
 227 const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
 228 {
 229   { "ABS-ADDR", NULL },
 230   { "FAKE", NULL },
 231   { "HASH-PREFIX", NULL },
 232   { "NEGATIVE", NULL },
 233   { "PCREL-ADDR", NULL },
 234   { "RELAX", NULL },
 235   { "RELOC", NULL },
 236   { "SIGN-OPT", NULL },
 237   { "UNSIGNED", NULL },
 238   { 0, 0 }
 239 };
 240
 241 const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
 242 {
 243   { "MACH", & MACH_attr[0] },
 244 /* start-sanitize-m32rx */
 245   { "PIPE", & PIPE_attr[0] },
 246 /* end-sanitize-m32rx */
 247   { "ALIAS", NULL },
 248   { "COND-CTI", NULL },
 249   { "FILL-SLOT", NULL },
 250   { "NO-DIS", NULL },
 251   { "PARALLEL", NULL },
 252   { "RELAX", NULL },
 253   { "RELAXABLE", NULL },
 254   { "SPECIAL", NULL },
 255   { "UNCOND-CTI", NULL },
 256   { 0, 0 }
 257 };
 258
 259 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_gr_entries[] =
 260 {
 261   { "fp", 13 },
 262   { "lr", 14 },
 263   { "sp", 15 },
 264   { "r0", 0 },
 265   { "r1", 1 },
 266   { "r2", 2 },
 267   { "r3", 3 },
 268   { "r4", 4 },
 269   { "r5", 5 },
 270   { "r6", 6 },
 271   { "r7", 7 },
 272   { "r8", 8 },
 273   { "r9", 9 },
 274   { "r10", 10 },
 275   { "r11", 11 },
 276   { "r12", 12 },
 277   { "r13", 13 },
 278   { "r14", 14 },
 279   { "r15", 15 }
 280 };
 281
 282 CGEN_KEYWORD m32r_cgen_opval_h_gr =
 283 {
 284   & m32r_cgen_opval_h_gr_entries[0],
 285   19
 286 };
 287
 288 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_cr_entries[] =
 289 {
 290   { "psw", 0 },
 291   { "cbr", 1 },
 292   { "spi", 2 },
 293   { "spu", 3 },
 294   { "bpc", 6 },
 295   { "cr0", 0 },
 296   { "cr1", 1 },
 297   { "cr2", 2 },
 298   { "cr3", 3 },
 299   { "cr4", 4 },
 300   { "cr5", 5 },
 301   { "cr6", 6 },
 302   { "cr7", 7 },
 303   { "cr8", 8 },
 304   { "cr9", 9 },
 305   { "cr10", 10 },
 306   { "cr11", 11 },
 307   { "cr12", 12 },
 308   { "cr13", 13 },
 309   { "cr14", 14 },
 310   { "cr15", 15 }
 311 };
 312
 313 CGEN_KEYWORD m32r_cgen_opval_h_cr =
 314 {
 315   & m32r_cgen_opval_h_cr_entries[0],
 316   21
 317 };
 318
 319 /* start-sanitize-m32rx */
 320 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
 321 {
 322   { "a0", 0 },
 323   { "a1", 1 }
 324 };
 325
 326 CGEN_KEYWORD m32r_cgen_opval_h_accums =
 327 {
 328   & m32r_cgen_opval_h_accums_entries[0],
 329   2
 330 };
 331
 332 /* end-sanitize-m32rx */
 333
 334 /* The hardware table.  */
 335
 336 #define HW_ENT(n) m32r_cgen_hw_entries[n]
 337 static const CGEN_HW_ENTRY m32r_cgen_hw_entries[] =
 338 {
 339   { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0 },
 340   { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0 },
 341   { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0 },
 342   { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0 },
 343   { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0 },
 344   { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0 },
 345   { HW_H_HI16, & HW_ENT (HW_H_HI16 + 1), "h-hi16", CGEN_ASM_KEYWORD, (PTR) 0 },
 346   { HW_H_SLO16, & HW_ENT (HW_H_SLO16 + 1), "h-slo16", CGEN_ASM_KEYWORD, (PTR) 0 },
 347   { HW_H_ULO16, & HW_ENT (HW_H_ULO16 + 1), "h-ulo16", CGEN_ASM_KEYWORD, (PTR) 0 },
 348   { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_gr },
 349   { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_cr },
 350   { HW_H_ACCUM, & HW_ENT (HW_H_ACCUM + 1), "h-accum", CGEN_ASM_KEYWORD, (PTR) 0 },
 351 /* start-sanitize-m32rx */
 352   { HW_H_ACCUMS, & HW_ENT (HW_H_ACCUMS + 1), "h-accums", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums },
 353 /* end-sanitize-m32rx */
 354   { HW_H_COND, & HW_ENT (HW_H_COND + 1), "h-cond", CGEN_ASM_KEYWORD, (PTR) 0 },
 355   { HW_H_SM, & HW_ENT (HW_H_SM + 1), "h-sm", CGEN_ASM_KEYWORD, (PTR) 0 },
 356   { HW_H_BSM, & HW_ENT (HW_H_BSM + 1), "h-bsm", CGEN_ASM_KEYWORD, (PTR) 0 },
 357   { HW_H_IE, & HW_ENT (HW_H_IE + 1), "h-ie", CGEN_ASM_KEYWORD, (PTR) 0 },
 358   { HW_H_BIE, & HW_ENT (HW_H_BIE + 1), "h-bie", CGEN_ASM_KEYWORD, (PTR) 0 },
 359   { HW_H_BCOND, & HW_ENT (HW_H_BCOND + 1), "h-bcond", CGEN_ASM_KEYWORD, (PTR) 0 },
 360   { HW_H_BPC, & HW_ENT (HW_H_BPC + 1), "h-bpc", CGEN_ASM_KEYWORD, (PTR) 0 },
 361   { HW_H_LOCK, & HW_ENT (HW_H_LOCK + 1), "h-lock", CGEN_ASM_KEYWORD, (PTR) 0 },
 362   { 0 }
 363 };
 364
 365 /* The operand table.  */
 366
 367 #define OPERAND(op) CONCAT2 (M32R_OPERAND_,op)
 368 #define OP_ENT(op) m32r_cgen_operand_table[OPERAND (op)]
 369
 370 const CGEN_OPERAND m32r_cgen_operand_table[MAX_OPERANDS] =
 371 {
 372 /* pc: program counter */
 373   { "pc", & HW_ENT (HW_H_PC), 0, 0,
 374     { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } }  },
 375 /* sr: source register */
 376   { "sr", & HW_ENT (HW_H_GR), 12, 4,
 377     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 378 /* dr: destination register */
 379   { "dr", & HW_ENT (HW_H_GR), 4, 4,
 380     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 381 /* src1: source register 1 */
 382   { "src1", & HW_ENT (HW_H_GR), 4, 4,
 383     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 384 /* src2: source register 2 */
 385   { "src2", & HW_ENT (HW_H_GR), 12, 4,
 386     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 387 /* scr: source control register */
 388   { "scr", & HW_ENT (HW_H_CR), 12, 4,
 389     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 390 /* dcr: destination control register */
 391   { "dcr", & HW_ENT (HW_H_CR), 4, 4,
 392     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 393 /* simm8: 8 bit signed immediate */
 394   { "simm8", & HW_ENT (HW_H_SINT), 8, 8,
 395     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { 0 } }  },
 396 /* simm16: 16 bit signed immediate */
 397   { "simm16", & HW_ENT (HW_H_SINT), 16, 16,
 398     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { 0 } }  },
 399 /* uimm4: 4 bit trap number */
 400   { "uimm4", & HW_ENT (HW_H_UINT), 12, 4,
 401     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 402 /* uimm5: 5 bit shift count */
 403   { "uimm5", & HW_ENT (HW_H_UINT), 11, 5,
 404     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 405 /* uimm16: 16 bit unsigned immediate */
 406   { "uimm16", & HW_ENT (HW_H_UINT), 16, 16,
 407     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 408 /* start-sanitize-m32rx */
 409 /* imm1: 1 bit immediate */
 410   { "imm1", & HW_ENT (HW_H_UINT), 15, 1,
 411     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 412 /* end-sanitize-m32rx */
 413 /* start-sanitize-m32rx */
 414 /* accd: accumulator destination register */
 415   { "accd", & HW_ENT (HW_H_ACCUMS), 4, 2,
 416     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 417 /* end-sanitize-m32rx */
 418 /* start-sanitize-m32rx */
 419 /* accs: accumulator source register */
 420   { "accs", & HW_ENT (HW_H_ACCUMS), 12, 2,
 421     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 422 /* end-sanitize-m32rx */
 423 /* start-sanitize-m32rx */
 424 /* acc: accumulator reg (d) */
 425   { "acc", & HW_ENT (HW_H_ACCUMS), 8, 1,
 426     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 427 /* end-sanitize-m32rx */
 428 /* hash: # prefix */
 429   { "hash", & HW_ENT (HW_H_SINT), 0, 0,
 430     { 0, 0, { 0 } }  },
 431 /* hi16: high 16 bit immediate, sign optional */
 432   { "hi16", & HW_ENT (HW_H_HI16), 16, 16,
 433     { 0, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 434 /* slo16: 16 bit signed immediate, for low() */
 435   { "slo16", & HW_ENT (HW_H_SLO16), 16, 16,
 436     { 0, 0, { 0 } }  },
 437 /* ulo16: 16 bit unsigned immediate, for low() */
 438   { "ulo16", & HW_ENT (HW_H_ULO16), 16, 16,
 439     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 440 /* uimm24: 24 bit address */
 441   { "uimm24", & HW_ENT (HW_H_ADDR), 8, 24,
 442     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 443 /* disp8: 8 bit displacement */
 444   { "disp8", & HW_ENT (HW_H_IADDR), 8, 8,
 445     { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
 446 /* disp16: 16 bit displacement */
 447   { "disp16", & HW_ENT (HW_H_IADDR), 16, 16,
 448     { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
 449 /* disp24: 24 bit displacement */
 450   { "disp24", & HW_ENT (HW_H_IADDR), 8, 24,
 451     { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
 452 /* condbit: condition bit */
 453   { "condbit", & HW_ENT (HW_H_COND), 0, 0,
 454     { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } }  },
 455 /* accum: accumulator */
 456   { "accum", & HW_ENT (HW_H_ACCUM), 0, 0,
 457     { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } }  },
 458 };
 459
 460 /* Operand references.  */
 461
 462 #define INPUT CGEN_OPERAND_INSTANCE_INPUT
 463 #define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
 464
 465 static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = {
 466   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 467   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 468   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 469   { 0 }
 470 };
 471
 472 static const CGEN_OPERAND_INSTANCE fmt_add3_ops[] = {
 473   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 474   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 475   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 476   { 0 }
 477 };
 478
 479 static const CGEN_OPERAND_INSTANCE fmt_and3_ops[] = {
 480   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 481   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0 },
 482   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 483   { 0 }
 484 };
 485
 486 static const CGEN_OPERAND_INSTANCE fmt_or3_ops[] = {
 487   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 488   { INPUT, & HW_ENT (HW_H_ULO16), CGEN_MODE_UHI, & OP_ENT (ULO16), 0 },
 489   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 490   { 0 }
 491 };
 492
 493 static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = {
 494   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 495   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
 496   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 497   { 0 }
 498 };
 499
 500 static const CGEN_OPERAND_INSTANCE fmt_addv_ops[] = {
 501   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 502   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 503   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 504   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 505   { 0 }
 506 };
 507
 508 static const CGEN_OPERAND_INSTANCE fmt_addv3_ops[] = {
 509   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 510   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
 511   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 512   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 513   { 0 }
 514 };
 515
 516 static const CGEN_OPERAND_INSTANCE fmt_addx_ops[] = {
 517   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 518   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 519   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 520   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 521   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 522   { 0 }
 523 };
 524
 525 static const CGEN_OPERAND_INSTANCE fmt_bc8_ops[] = {
 526   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 527   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
 528   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 529   { 0 }
 530 };
 531
 532 static const CGEN_OPERAND_INSTANCE fmt_bc24_ops[] = {
 533   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 534   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
 535   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 536   { 0 }
 537 };
 538
 539 static const CGEN_OPERAND_INSTANCE fmt_beq_ops[] = {
 540   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 541   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 542   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0 },
 543   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 544   { 0 }
 545 };
 546
 547 static const CGEN_OPERAND_INSTANCE fmt_beqz_ops[] = {
 548   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 549   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0 },
 550   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 551   { 0 }
 552 };
 553
 554 static const CGEN_OPERAND_INSTANCE fmt_bl8_ops[] = {
 555   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 556   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
 557   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 558   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 559   { 0 }
 560 };
 561
 562 static const CGEN_OPERAND_INSTANCE fmt_bl24_ops[] = {
 563   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 564   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
 565   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 566   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 567   { 0 }
 568 };
 569
 570 /* start-sanitize-m32rx */
 571 static const CGEN_OPERAND_INSTANCE fmt_bcl8_ops[] = {
 572   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 573   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 574   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
 575   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 576   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 577   { 0 }
 578 };
 579
 580 /* end-sanitize-m32rx */
 581 /* start-sanitize-m32rx */
 582 static const CGEN_OPERAND_INSTANCE fmt_bcl24_ops[] = {
 583   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 584   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 585   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
 586   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 587   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 588   { 0 }
 589 };
 590
 591 /* end-sanitize-m32rx */
 592 static const CGEN_OPERAND_INSTANCE fmt_bra8_ops[] = {
 593   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
 594   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 595   { 0 }
 596 };
 597
 598 static const CGEN_OPERAND_INSTANCE fmt_bra24_ops[] = {
 599   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
 600   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 601   { 0 }
 602 };
 603
 604 static const CGEN_OPERAND_INSTANCE fmt_cmp_ops[] = {
 605   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 606   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 607   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 608   { 0 }
 609 };
 610
 611 static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
 612   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 613   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
 614   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 615   { 0 }
 616 };
 617
 618 /* start-sanitize-m32rx */
 619 static const CGEN_OPERAND_INSTANCE fmt_cmpz_ops[] = {
 620   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 621   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 622   { 0 }
 623 };
 624
 625 /* end-sanitize-m32rx */
 626 static const CGEN_OPERAND_INSTANCE fmt_div_ops[] = {
 627   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 628   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 629   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 630   { 0 }
 631 };
 632
 633 /* start-sanitize-m32rx */
 634 static const CGEN_OPERAND_INSTANCE fmt_jc_ops[] = {
 635   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 636   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 637   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 638   { 0 }
 639 };
 640
 641 /* end-sanitize-m32rx */
 642 static const CGEN_OPERAND_INSTANCE fmt_jl_ops[] = {
 643   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 644   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 645   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 646   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 647   { 0 }
 648 };
 649
 650 static const CGEN_OPERAND_INSTANCE fmt_jmp_ops[] = {
 651   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 652   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 653   { 0 }
 654 };
 655
 656 static const CGEN_OPERAND_INSTANCE fmt_ld_ops[] = {
 657   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 658   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
 659   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 660   { 0 }
 661 };
 662
 663 static const CGEN_OPERAND_INSTANCE fmt_ld_d_ops[] = {
 664   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 665   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 666   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 667   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 668   { 0 }
 669 };
 670
 671 static const CGEN_OPERAND_INSTANCE fmt_ldb_ops[] = {
 672   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 673   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
 674   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 675   { 0 }
 676 };
 677
 678 static const CGEN_OPERAND_INSTANCE fmt_ldb_d_ops[] = {
 679   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 680   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 681   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 682   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 683   { 0 }
 684 };
 685
 686 static const CGEN_OPERAND_INSTANCE fmt_ldh_ops[] = {
 687   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 688   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
 689   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 690   { 0 }
 691 };
 692
 693 static const CGEN_OPERAND_INSTANCE fmt_ldh_d_ops[] = {
 694   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 695   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 696   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 697   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 698   { 0 }
 699 };
 700
 701 static const CGEN_OPERAND_INSTANCE fmt_ld_plus_ops[] = {
 702   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 703   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 704   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 705   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 706   { 0 }
 707 };
 708
 709 static const CGEN_OPERAND_INSTANCE fmt_ld24_ops[] = {
 710   { INPUT, & HW_ENT (HW_H_ADDR), CGEN_MODE_USI, & OP_ENT (UIMM24), 0 },
 711   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 712   { 0 }
 713 };
 714
 715 static const CGEN_OPERAND_INSTANCE fmt_ldi8_ops[] = {
 716   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
 717   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 718   { 0 }
 719 };
 720
 721 static const CGEN_OPERAND_INSTANCE fmt_ldi16_ops[] = {
 722   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 723   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 724   { 0 }
 725 };
 726
 727 static const CGEN_OPERAND_INSTANCE fmt_lock_ops[] = {
 728   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 729   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
 730   { OUTPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
 731   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 732   { 0 }
 733 };
 734
 735 static const CGEN_OPERAND_INSTANCE fmt_machi_ops[] = {
 736   { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 737   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 738   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 739   { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 740   { 0 }
 741 };
 742
 743 /* start-sanitize-m32rx */
 744 static const CGEN_OPERAND_INSTANCE fmt_machi_a_ops[] = {
 745   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
 746   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 747   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 748   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
 749   { 0 }
 750 };
 751
 752 /* end-sanitize-m32rx */
 753 static const CGEN_OPERAND_INSTANCE fmt_mulhi_ops[] = {
 754   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 755   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 756   { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 757   { 0 }
 758 };
 759
 760 /* start-sanitize-m32rx */
 761 static const CGEN_OPERAND_INSTANCE fmt_mulhi_a_ops[] = {
 762   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 763   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 764   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
 765   { 0 }
 766 };
 767
 768 /* end-sanitize-m32rx */
 769 static const CGEN_OPERAND_INSTANCE fmt_mv_ops[] = {
 770   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 771   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 772   { 0 }
 773 };
 774
 775 static const CGEN_OPERAND_INSTANCE fmt_mvfachi_ops[] = {
 776   { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 777   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 778   { 0 }
 779 };
 780
 781 /* start-sanitize-m32rx */
 782 static const CGEN_OPERAND_INSTANCE fmt_mvfachi_a_ops[] = {
 783   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 784   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 785   { 0 }
 786 };
 787
 788 /* end-sanitize-m32rx */
 789 static const CGEN_OPERAND_INSTANCE fmt_mvfc_ops[] = {
 790   { INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (SCR), 0 },
 791   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 792   { 0 }
 793 };
 794
 795 static const CGEN_OPERAND_INSTANCE fmt_mvtachi_ops[] = {
 796   { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 797   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 798   { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 799   { 0 }
 800 };
 801
 802 /* start-sanitize-m32rx */
 803 static const CGEN_OPERAND_INSTANCE fmt_mvtachi_a_ops[] = {
 804   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 805   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 806   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 807   { 0 }
 808 };
 809
 810 /* end-sanitize-m32rx */
 811 static const CGEN_OPERAND_INSTANCE fmt_mvtc_ops[] = {
 812   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 813   { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (DCR), 0 },
 814   { 0 }
 815 };
 816
 817 static const CGEN_OPERAND_INSTANCE fmt_rac_ops[] = {
 818   { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 819   { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 820   { 0 }
 821 };
 822
 823 /* start-sanitize-m32rx */
 824 static const CGEN_OPERAND_INSTANCE fmt_rac_dsi_ops[] = {
 825   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 826   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (IMM1), 0 },
 827   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0 },
 828   { 0 }
 829 };
 830
 831 /* end-sanitize-m32rx */
 832 static const CGEN_OPERAND_INSTANCE fmt_rte_ops[] = {
 833   { INPUT, & HW_ENT (HW_H_BSM), CGEN_MODE_UBI, 0, 0 },
 834   { INPUT, & HW_ENT (HW_H_BIE), CGEN_MODE_UBI, 0, 0 },
 835   { INPUT, & HW_ENT (HW_H_BCOND), CGEN_MODE_UBI, 0, 0 },
 836   { INPUT, & HW_ENT (HW_H_BPC), CGEN_MODE_SI, 0, 0 },
 837   { OUTPUT, & HW_ENT (HW_H_SM), CGEN_MODE_UBI, 0, 0 },
 838   { OUTPUT, & HW_ENT (HW_H_IE), CGEN_MODE_UBI, 0, 0 },
 839   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 840   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 841   { 0 }
 842 };
 843
 844 static const CGEN_OPERAND_INSTANCE fmt_seth_ops[] = {
 845   { INPUT, & HW_ENT (HW_H_HI16), CGEN_MODE_SI, & OP_ENT (HI16), 0 },
 846   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 847   { 0 }
 848 };
 849
 850 static const CGEN_OPERAND_INSTANCE fmt_sll3_ops[] = {
 851   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 852   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
 853   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 854   { 0 }
 855 };
 856
 857 static const CGEN_OPERAND_INSTANCE fmt_slli_ops[] = {
 858   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 859   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM5), 0 },
 860   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 861   { 0 }
 862 };
 863
 864 static const CGEN_OPERAND_INSTANCE fmt_st_ops[] = {
 865   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
 866   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 867   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 868   { 0 }
 869 };
 870
 871 static const CGEN_OPERAND_INSTANCE fmt_st_d_ops[] = {
 872   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 873   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 874   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 875   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 876   { 0 }
 877 };
 878
 879 static const CGEN_OPERAND_INSTANCE fmt_stb_ops[] = {
 880   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
 881   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (SRC1), 0 },
 882   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 883   { 0 }
 884 };
 885
 886 static const CGEN_OPERAND_INSTANCE fmt_stb_d_ops[] = {
 887   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 888   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 889   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (SRC1), 0 },
 890   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 891   { 0 }
 892 };
 893
 894 static const CGEN_OPERAND_INSTANCE fmt_sth_ops[] = {
 895   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
 896   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (SRC1), 0 },
 897   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 898   { 0 }
 899 };
 900
 901 static const CGEN_OPERAND_INSTANCE fmt_sth_d_ops[] = {
 902   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 903   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 904   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (SRC1), 0 },
 905   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 906   { 0 }
 907 };
 908
 909 static const CGEN_OPERAND_INSTANCE fmt_st_plus_ops[] = {
 910   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 911   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 912   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 913   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 914   { 0 }
 915 };
 916
 917 static const CGEN_OPERAND_INSTANCE fmt_trap_ops[] = {
 918   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 919   { INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 0 },
 920   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (UIMM4), 0 },
 921   { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6 },
 922   { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 0 },
 923   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0 },
 924   { 0 }
 925 };
 926
 927 static const CGEN_OPERAND_INSTANCE fmt_unlock_ops[] = {
 928   { INPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
 929   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
 930   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 931   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 932   { OUTPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
 933   { 0 }
 934 };
 935
 936 /* start-sanitize-m32rx */
 937 static const CGEN_OPERAND_INSTANCE fmt_satb_ops[] = {
 938   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 939   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 940   { 0 }
 941 };
 942
 943 /* end-sanitize-m32rx */
 944 /* start-sanitize-m32rx */
 945 static const CGEN_OPERAND_INSTANCE fmt_sat_ops[] = {
 946   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 947   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 948   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 949   { 0 }
 950 };
 951
 952 /* end-sanitize-m32rx */
 953 /* start-sanitize-m32rx */
 954 static const CGEN_OPERAND_INSTANCE fmt_sadd_ops[] = {
 955   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
 956   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
 957   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
 958   { 0 }
 959 };
 960
 961 /* end-sanitize-m32rx */
 962 /* start-sanitize-m32rx */
 963 static const CGEN_OPERAND_INSTANCE fmt_macwu1_ops[] = {
 964   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
 965   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 966   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 967   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
 968   { 0 }
 969 };
 970
 971 /* end-sanitize-m32rx */
 972 /* start-sanitize-m32rx */
 973 static const CGEN_OPERAND_INSTANCE fmt_mulwu1_ops[] = {
 974   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 975   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 976   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
 977   { 0 }
 978 };
 979
 980 /* end-sanitize-m32rx */
 981 /* start-sanitize-m32rx */
 982 static const CGEN_OPERAND_INSTANCE fmt_sc_ops[] = {
 983   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 984   { 0 }
 985 };
 986
 987 /* end-sanitize-m32rx */
 988 #undef INPUT
 989 #undef OUTPUT
 990
 991 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
 992 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
 993 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
 994
 995 /* The instruction table.
 996    This is currently non-static because the simulator accesses it
 997    directly.  */
 998
 999 const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
1000 {
1001   /* Special null first entry.
1002      A `num' value of zero is thus illegal.
1003      Also, the special `illegal' insn resides here.  */
1004   { { 0 }, 0 },
1005 /* add $dr,$sr */
1006   {
1007     { 1, 1, 1, 1 },
1008     M32R_INSN_ADD, "add", "add",
1009     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1010     { 16, 16, 0xf0f0 }, 0xa0,
1011     "(set dr (add dr sr))",
1012     (PTR) & fmt_add_ops[0],
1013     { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
1014   },
1015 /* add3 $dr,$sr,$hash$slo16 */
1016   {
1017     { 1, 1, 1, 1 },
1018     M32R_INSN_ADD3, "add3", "add3",
1019     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (SLO16), 0 } },
1020     { 32, 32, 0xf0f00000 }, 0x80a00000,
1021     "(set dr (add sr slo16))",
1022     (PTR) & fmt_add3_ops[0],
1023     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1024   },
1025 /* and $dr,$sr */
1026   {
1027     { 1, 1, 1, 1 },
1028     M32R_INSN_AND, "and", "and",
1029     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1030     { 16, 16, 0xf0f0 }, 0xc0,
1031     "(set dr (and dr sr))",
1032     (PTR) & fmt_add_ops[0],
1033     { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
1034   },
1035 /* and3 $dr,$sr,$uimm16 */
1036   {
1037     { 1, 1, 1, 1 },
1038     M32R_INSN_AND3, "and3", "and3",
1039     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
1040     { 32, 32, 0xf0f00000 }, 0x80c00000,
1041     "(set dr (and sr uimm16))",
1042     (PTR) & fmt_and3_ops[0],
1043     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1044   },
1045 /* or $dr,$sr */
1046   {
1047     { 1, 1, 1, 1 },
1048     M32R_INSN_OR, "or", "or",
1049     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1050     { 16, 16, 0xf0f0 }, 0xe0,
1051     "(set dr (or dr sr))",
1052     (PTR) & fmt_add_ops[0],
1053     { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
1054   },
1055 /* or3 $dr,$sr,$hash$ulo16 */
1056   {
1057     { 1, 1, 1, 1 },
1058     M32R_INSN_OR3, "or3", "or3",
1059     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (ULO16), 0 } },
1060     { 32, 32, 0xf0f00000 }, 0x80e00000,
1061     "(set dr (or sr ulo16))",
1062     (PTR) & fmt_or3_ops[0],
1063     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1064   },
1065 /* xor $dr,$sr */
1066   {
1067     { 1, 1, 1, 1 },
1068     M32R_INSN_XOR, "xor", "xor",
1069     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1070     { 16, 16, 0xf0f0 }, 0xd0,
1071     "(set dr (xor dr sr))",
1072     (PTR) & fmt_add_ops[0],
1073     { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
1074   },
1075 /* xor3 $dr,$sr,$uimm16 */
1076   {
1077     { 1, 1, 1, 1 },
1078     M32R_INSN_XOR3, "xor3", "xor3",
1079     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
1080     { 32, 32, 0xf0f00000 }, 0x80d00000,
1081     "(set dr (xor sr uimm16))",
1082     (PTR) & fmt_and3_ops[0],
1083     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1084   },
1085 /* addi $dr,$simm8 */
1086   {
1087     { 1, 1, 1, 1 },
1088     M32R_INSN_ADDI, "addi", "addi",
1089     { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
1090     { 16, 16, 0xf000 }, 0x4000,
1091     "(set dr (add dr simm8))",
1092     (PTR) & fmt_addi_ops[0],
1093     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1094   },
1095 /* addv $dr,$sr */
1096   {
1097     { 1, 1, 1, 1 },
1098     M32R_INSN_ADDV, "addv", "addv",
1099     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1100     { 16, 16, 0xf0f0 }, 0x80,
1101     "(parallel () (set dr (add dr sr)) (set condbit (add-oflag dr sr (const 0))))",
1102     (PTR) & fmt_addv_ops[0],
1103     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1104   },
1105 /* addv3 $dr,$sr,$simm16 */
1106   {
1107     { 1, 1, 1, 1 },
1108     M32R_INSN_ADDV3, "addv3", "addv3",
1109     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
1110     { 32, 32, 0xf0f00000 }, 0x80800000,
1111     "(parallel () (set dr (add sr simm16)) (set condbit (add-oflag sr simm16 (const 0))))",
1112     (PTR) & fmt_addv3_ops[0],
1113     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1114   },
1115 /* addx $dr,$sr */
1116   {
1117     { 1, 1, 1, 1 },
1118     M32R_INSN_ADDX, "addx", "addx",
1119     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1120     { 16, 16, 0xf0f0 }, 0x90,
1121     "(parallel () (set dr (addc dr sr condbit)) (set condbit (add-cflag dr sr condbit)))",
1122     (PTR) & fmt_addx_ops[0],
1123     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1124   },
1125 /* bc.s $disp8 */
1126   {
1127     { 1, 1, 1, 1 },
1128     M32R_INSN_BC8, "bc8", "bc.s",
1129     { { MNEM, ' ', OP (DISP8), 0 } },
1130     { 16, 16, 0xff00 }, 0x7c00,
1131     "(if condbit (set pc disp8))",
1132     (PTR) & fmt_bc8_ops[0],
1133     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
1134   },
1135 /* bc.l $disp24 */
1136   {
1137     { 1, 1, 1, 1 },
1138     M32R_INSN_BC24, "bc24", "bc.l",
1139     { { MNEM, ' ', OP (DISP24), 0 } },
1140     { 32, 32, 0xff000000 }, 0xfc000000,
1141     "(if condbit (set pc disp24))",
1142     (PTR) & fmt_bc24_ops[0],
1143     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1144   },
1145 /* beq $src1,$src2,$disp16 */
1146   {
1147     { 1, 1, 1, 1 },
1148     M32R_INSN_BEQ, "beq", "beq",
1149     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
1150     { 32, 32, 0xf0f00000 }, 0xb0000000,
1151     "(if (eq src1 src2) (set pc disp16))",
1152     (PTR) & fmt_beq_ops[0],
1153     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1154   },
1155 /* beqz $src2,$disp16 */
1156   {
1157     { 1, 1, 1, 1 },
1158     M32R_INSN_BEQZ, "beqz", "beqz",
1159     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
1160     { 32, 32, 0xfff00000 }, 0xb0800000,
1161     "(if (eq src2 (const: WI 0)) (set pc disp16))",
1162     (PTR) & fmt_beqz_ops[0],
1163     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1164   },
1165 /* bgez $src2,$disp16 */
1166   {
1167     { 1, 1, 1, 1 },
1168     M32R_INSN_BGEZ, "bgez", "bgez",
1169     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
1170     { 32, 32, 0xfff00000 }, 0xb0b00000,
1171     "(if (ge src2 (const: WI 0)) (set pc disp16))",
1172     (PTR) & fmt_beqz_ops[0],
1173     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1174   },
1175 /* bgtz $src2,$disp16 */
1176   {
1177     { 1, 1, 1, 1 },
1178     M32R_INSN_BGTZ, "bgtz", "bgtz",
1179     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
1180     { 32, 32, 0xfff00000 }, 0xb0d00000,
1181     "(if (gt src2 (const: WI 0)) (set pc disp16))",
1182     (PTR) & fmt_beqz_ops[0],
1183     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1184   },
1185 /* blez $src2,$disp16 */
1186   {
1187     { 1, 1, 1, 1 },
1188     M32R_INSN_BLEZ, "blez", "blez",
1189     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
1190     { 32, 32, 0xfff00000 }, 0xb0c00000,
1191     "(if (le src2 (const: WI 0)) (set pc disp16))",
1192     (PTR) & fmt_beqz_ops[0],
1193     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1194   },
1195 /* bltz $src2,$disp16 */
1196   {
1197     { 1, 1, 1, 1 },
1198     M32R_INSN_BLTZ, "bltz", "bltz",
1199     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
1200     { 32, 32, 0xfff00000 }, 0xb0a00000,
1201     "(if (lt src2 (const: WI 0)) (set pc disp16))",
1202     (PTR) & fmt_beqz_ops[0],
1203     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1204   },
1205 /* bnez $src2,$disp16 */
1206   {
1207     { 1, 1, 1, 1 },
1208     M32R_INSN_BNEZ, "bnez", "bnez",
1209     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
1210     { 32, 32, 0xfff00000 }, 0xb0900000,
1211     "(if (ne src2 (const: WI 0)) (set pc disp16))",
1212     (PTR) & fmt_beqz_ops[0],
1213     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1214   },
1215 /* bl.s $disp8 */
1216   {
1217     { 1, 1, 1, 1 },
1218     M32R_INSN_BL8, "bl8", "bl.s",
1219     { { MNEM, ' ', OP (DISP8), 0 } },
1220     { 16, 16, 0xff00 }, 0x7e00,
1221     "(sequence () (set (reg h-gr 14) (add (and pc (const -4)) (const 4))) (set pc disp8))",
1222     (PTR) & fmt_bl8_ops[0],
1223     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1224   },
1225 /* bl.l $disp24 */
1226   {
1227     { 1, 1, 1, 1 },
1228     M32R_INSN_BL24, "bl24", "bl.l",
1229     { { MNEM, ' ', OP (DISP24), 0 } },
1230     { 32, 32, 0xff000000 }, 0xfe000000,
1231     "(sequence () (set (reg h-gr 14) (add pc (const 4))) (set pc disp24))",
1232     (PTR) & fmt_bl24_ops[0],
1233     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1234   },
1235 /* start-sanitize-m32rx */
1236 /* bcl.s $disp8 */
1237   {
1238     { 1, 1, 1, 1 },
1239     M32R_INSN_BCL8, "bcl8", "bcl.s",
1240     { { MNEM, ' ', OP (DISP8), 0 } },
1241     { 16, 16, 0xff00 }, 0x7800,
1242     "(if condbit (sequence () (set (reg h-gr 14) (add (and pc (const -4)) (const 4))) (set pc disp8)))",
1243     (PTR) & fmt_bcl8_ops[0],
1244     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1245   },
1246 /* end-sanitize-m32rx */
1247 /* start-sanitize-m32rx */
1248 /* bcl.l $disp24 */
1249   {
1250     { 1, 1, 1, 1 },
1251     M32R_INSN_BCL24, "bcl24", "bcl.l",
1252     { { MNEM, ' ', OP (DISP24), 0 } },
1253     { 32, 32, 0xff000000 }, 0xf8000000,
1254     "(if condbit (sequence () (set (reg h-gr 14) (add pc (const 4))) (set pc disp24)))",
1255     (PTR) & fmt_bcl24_ops[0],
1256     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1257   },
1258 /* end-sanitize-m32rx */
1259 /* bnc.s $disp8 */
1260   {
1261     { 1, 1, 1, 1 },
1262     M32R_INSN_BNC8, "bnc8", "bnc.s",
1263     { { MNEM, ' ', OP (DISP8), 0 } },
1264     { 16, 16, 0xff00 }, 0x7d00,
1265     "(if (not condbit) (set pc disp8))",
1266     (PTR) & fmt_bc8_ops[0],
1267     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
1268   },
1269 /* bnc.l $disp24 */
1270   {
1271     { 1, 1, 1, 1 },
1272     M32R_INSN_BNC24, "bnc24", "bnc.l",
1273     { { MNEM, ' ', OP (DISP24), 0 } },
1274     { 32, 32, 0xff000000 }, 0xfd000000,
1275     "(if (not condbit) (set pc disp24))",
1276     (PTR) & fmt_bc24_ops[0],
1277     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1278   },
1279 /* bne $src1,$src2,$disp16 */
1280   {
1281     { 1, 1, 1, 1 },
1282     M32R_INSN_BNE, "bne", "bne",
1283     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
1284     { 32, 32, 0xf0f00000 }, 0xb0100000,
1285     "(if (ne src1 src2) (set pc disp16))",
1286     (PTR) & fmt_beq_ops[0],
1287     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1288   },
1289 /* bra.s $disp8 */
1290   {
1291     { 1, 1, 1, 1 },
1292     M32R_INSN_BRA8, "bra8", "bra.s",
1293     { { MNEM, ' ', OP (DISP8), 0 } },
1294     { 16, 16, 0xff00 }, 0x7f00,
1295     "(set pc disp8)",
1296     (PTR) & fmt_bra8_ops[0],
1297     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1298   },
1299 /* bra.l $disp24 */
1300   {
1301     { 1, 1, 1, 1 },
1302     M32R_INSN_BRA24, "bra24", "bra.l",
1303     { { MNEM, ' ', OP (DISP24), 0 } },
1304     { 32, 32, 0xff000000 }, 0xff000000,
1305     "(set pc disp24)",
1306     (PTR) & fmt_bra24_ops[0],
1307     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1308   },
1309 /* start-sanitize-m32rx */
1310 /* bncl.s $disp8 */
1311   {
1312     { 1, 1, 1, 1 },
1313     M32R_INSN_BNCL8, "bncl8", "bncl.s",
1314     { { MNEM, ' ', OP (DISP8), 0 } },
1315     { 16, 16, 0xff00 }, 0x7900,
1316     "(if (not condbit) (sequence () (set (reg h-gr 14) (add (and pc (const -4)) (const 4))) (set pc disp8)))",
1317     (PTR) & fmt_bcl8_ops[0],
1318     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1319   },
1320 /* end-sanitize-m32rx */
1321 /* start-sanitize-m32rx */
1322 /* bncl.l $disp24 */
1323   {
1324     { 1, 1, 1, 1 },
1325     M32R_INSN_BNCL24, "bncl24", "bncl.l",
1326     { { MNEM, ' ', OP (DISP24), 0 } },
1327     { 32, 32, 0xff000000 }, 0xf9000000,
1328     "(if (not condbit) (sequence () (set (reg h-gr 14) (add pc (const 4))) (set pc disp24)))",
1329     (PTR) & fmt_bcl24_ops[0],
1330     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1331   },
1332 /* end-sanitize-m32rx */
1333 /* cmp $src1,$src2 */
1334   {
1335     { 1, 1, 1, 1 },
1336     M32R_INSN_CMP, "cmp", "cmp",
1337     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1338     { 16, 16, 0xf0f0 }, 0x40,
1339     "(set condbit (lt src1 src2))",
1340     (PTR) & fmt_cmp_ops[0],
1341     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1342   },
1343 /* cmpi $src2,$simm16 */
1344   {
1345     { 1, 1, 1, 1 },
1346     M32R_INSN_CMPI, "cmpi", "cmpi",
1347     { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
1348     { 32, 32, 0xfff00000 }, 0x80400000,
1349     "(set condbit (lt src2 simm16))",
1350     (PTR) & fmt_cmpi_ops[0],
1351     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1352   },
1353 /* cmpu $src1,$src2 */
1354   {
1355     { 1, 1, 1, 1 },
1356     M32R_INSN_CMPU, "cmpu", "cmpu",
1357     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1358     { 16, 16, 0xf0f0 }, 0x50,
1359     "(set condbit (ltu src1 src2))",
1360     (PTR) & fmt_cmp_ops[0],
1361     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1362   },
1363 /* cmpui $src2,$simm16 */
1364   {
1365     { 1, 1, 1, 1 },
1366     M32R_INSN_CMPUI, "cmpui", "cmpui",
1367     { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
1368     { 32, 32, 0xfff00000 }, 0x80500000,
1369     "(set condbit (ltu src2 simm16))",
1370     (PTR) & fmt_cmpi_ops[0],
1371     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1372   },
1373 /* start-sanitize-m32rx */
1374 /* cmpeq $src1,$src2 */
1375   {
1376     { 1, 1, 1, 1 },
1377     M32R_INSN_CMPEQ, "cmpeq", "cmpeq",
1378     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1379     { 16, 16, 0xf0f0 }, 0x60,
1380     "(set condbit (eq src1 src2))",
1381     (PTR) & fmt_cmp_ops[0],
1382     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
1383   },
1384 /* end-sanitize-m32rx */
1385 /* start-sanitize-m32rx */
1386 /* cmpz $src2 */
1387   {
1388     { 1, 1, 1, 1 },
1389     M32R_INSN_CMPZ, "cmpz", "cmpz",
1390     { { MNEM, ' ', OP (SRC2), 0 } },
1391     { 16, 16, 0xfff0 }, 0x70,
1392     "(set condbit (eq src2 (const 0)))",
1393     (PTR) & fmt_cmpz_ops[0],
1394     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
1395   },
1396 /* end-sanitize-m32rx */
1397 /* div $dr,$sr */
1398   {
1399     { 1, 1, 1, 1 },
1400     M32R_INSN_DIV, "div", "div",
1401     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1402     { 32, 32, 0xf0f0ffff }, 0x90000000,
1403     "(if (ne sr (const 0)) (set dr (div dr sr)))",
1404     (PTR) & fmt_div_ops[0],
1405     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1406   },
1407 /* divu $dr,$sr */
1408   {
1409     { 1, 1, 1, 1 },
1410     M32R_INSN_DIVU, "divu", "divu",
1411     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1412     { 32, 32, 0xf0f0ffff }, 0x90100000,
1413     "(if (ne sr (const 0)) (set dr (udiv dr sr)))",
1414     (PTR) & fmt_div_ops[0],
1415     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1416   },
1417 /* rem $dr,$sr */
1418   {
1419     { 1, 1, 1, 1 },
1420     M32R_INSN_REM, "rem", "rem",
1421     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1422     { 32, 32, 0xf0f0ffff }, 0x90200000,
1423     "(if (ne sr (const 0)) (set dr (mod dr sr)))",
1424     (PTR) & fmt_div_ops[0],
1425     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1426   },
1427 /* remu $dr,$sr */
1428   {
1429     { 1, 1, 1, 1 },
1430     M32R_INSN_REMU, "remu", "remu",
1431     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1432     { 32, 32, 0xf0f0ffff }, 0x90300000,
1433     "(if (ne sr (const 0)) (set dr (umod dr sr)))",
1434     (PTR) & fmt_div_ops[0],
1435     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1436   },
1437 /* start-sanitize-m32rx */
1438 /* divh $dr,$sr */
1439   {
1440     { 1, 1, 1, 1 },
1441     M32R_INSN_DIVH, "divh", "divh",
1442     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1443     { 32, 32, 0xf0f0ffff }, 0x90000010,
1444     "(if (ne sr (const 0)) (set dr (div (ext: WI (trunc: HI dr)) sr)))",
1445     (PTR) & fmt_div_ops[0],
1446     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
1447   },
1448 /* end-sanitize-m32rx */
1449 /* start-sanitize-m32rx */
1450 /* jc $sr */
1451   {
1452     { 1, 1, 1, 1 },
1453     M32R_INSN_JC, "jc", "jc",
1454     { { MNEM, ' ', OP (SR), 0 } },
1455     { 16, 16, 0xfff0 }, 0x1cc0,
1456     "(if condbit (set pc (and sr (const -4))))",
1457     (PTR) & fmt_jc_ops[0],
1458     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1459   },
1460 /* end-sanitize-m32rx */
1461 /* start-sanitize-m32rx */
1462 /* jnc $sr */
1463   {
1464     { 1, 1, 1, 1 },
1465     M32R_INSN_JNC, "jnc", "jnc",
1466     { { MNEM, ' ', OP (SR), 0 } },
1467     { 16, 16, 0xfff0 }, 0x1dc0,
1468     "(if (not condbit) (set pc (and sr (const -4))))",
1469     (PTR) & fmt_jc_ops[0],
1470     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1471   },
1472 /* end-sanitize-m32rx */
1473 /* jl $sr */
1474   {
1475     { 1, 1, 1, 1 },
1476     M32R_INSN_JL, "jl", "jl",
1477     { { MNEM, ' ', OP (SR), 0 } },
1478     { 16, 16, 0xfff0 }, 0x1ec0,
1479     "(parallel () (set (reg h-gr 14) (add (and pc (const -4)) (const 4))) (set pc (and sr (const -4))))",
1480     (PTR) & fmt_jl_ops[0],
1481     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1482   },
1483 /* jmp $sr */
1484   {
1485     { 1, 1, 1, 1 },
1486     M32R_INSN_JMP, "jmp", "jmp",
1487     { { MNEM, ' ', OP (SR), 0 } },
1488     { 16, 16, 0xfff0 }, 0x1fc0,
1489     "(set pc (and sr (const -4)))",
1490     (PTR) & fmt_jmp_ops[0],
1491     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1492   },
1493 /* ld $dr,@$sr */
1494   {
1495     { 1, 1, 1, 1 },
1496     M32R_INSN_LD, "ld", "ld",
1497     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
1498     { 16, 16, 0xf0f0 }, 0x20c0,
1499     "(set dr (mem: WI sr))",
1500     (PTR) & fmt_ld_ops[0],
1501     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1502   },
1503 /* ld $dr,@($slo16,$sr) */
1504   {
1505     { 1, 1, 1, 1 },
1506     M32R_INSN_LD_D, "ld-d", "ld",
1507     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
1508     { 32, 32, 0xf0f00000 }, 0xa0c00000,
1509     "(set dr (mem: WI (add sr slo16)))",
1510     (PTR) & fmt_ld_d_ops[0],
1511     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1512   },
1513 /* ldb $dr,@$sr */
1514   {
1515     { 1, 1, 1, 1 },
1516     M32R_INSN_LDB, "ldb", "ldb",
1517     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
1518     { 16, 16, 0xf0f0 }, 0x2080,
1519     "(set dr (ext: WI (mem: QI sr)))",
1520     (PTR) & fmt_ldb_ops[0],
1521     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1522   },
1523 /* ldb $dr,@($slo16,$sr) */
1524   {
1525     { 1, 1, 1, 1 },
1526     M32R_INSN_LDB_D, "ldb-d", "ldb",
1527     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
1528     { 32, 32, 0xf0f00000 }, 0xa0800000,
1529     "(set dr (ext: WI (mem: QI (add sr slo16))))",
1530     (PTR) & fmt_ldb_d_ops[0],
1531     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1532   },
1533 /* ldh $dr,@$sr */
1534   {
1535     { 1, 1, 1, 1 },
1536     M32R_INSN_LDH, "ldh", "ldh",
1537     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
1538     { 16, 16, 0xf0f0 }, 0x20a0,
1539     "(set dr (ext: WI (mem: HI sr)))",
1540     (PTR) & fmt_ldh_ops[0],
1541     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1542   },
1543 /* ldh $dr,@($slo16,$sr) */
1544   {
1545     { 1, 1, 1, 1 },
1546     M32R_INSN_LDH_D, "ldh-d", "ldh",
1547     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
1548     { 32, 32, 0xf0f00000 }, 0xa0a00000,
1549     "(set dr (ext: WI (mem: HI (add sr slo16))))",
1550     (PTR) & fmt_ldh_d_ops[0],
1551     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1552   },
1553 /* ldub $dr,@$sr */
1554   {
1555     { 1, 1, 1, 1 },
1556     M32R_INSN_LDUB, "ldub", "ldub",
1557     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
1558     { 16, 16, 0xf0f0 }, 0x2090,
1559     "(set dr (zext: WI (mem: QI sr)))",
1560     (PTR) & fmt_ldb_ops[0],
1561     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1562   },
1563 /* ldub $dr,@($slo16,$sr) */
1564   {
1565     { 1, 1, 1, 1 },
1566     M32R_INSN_LDUB_D, "ldub-d", "ldub",
1567     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
1568     { 32, 32, 0xf0f00000 }, 0xa0900000,
1569     "(set dr (zext: WI (mem: QI (add sr slo16))))",
1570     (PTR) & fmt_ldb_d_ops[0],
1571     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1572   },
1573 /* lduh $dr,@$sr */
1574   {
1575     { 1, 1, 1, 1 },
1576     M32R_INSN_LDUH, "lduh", "lduh",
1577     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
1578     { 16, 16, 0xf0f0 }, 0x20b0,
1579     "(set dr (zext: WI (mem: HI sr)))",
1580     (PTR) & fmt_ldh_ops[0],
1581     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1582   },
1583 /* lduh $dr,@($slo16,$sr) */
1584   {
1585     { 1, 1, 1, 1 },
1586     M32R_INSN_LDUH_D, "lduh-d", "lduh",
1587     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
1588     { 32, 32, 0xf0f00000 }, 0xa0b00000,
1589     "(set dr (zext: WI (mem: HI (add sr slo16))))",
1590     (PTR) & fmt_ldh_d_ops[0],
1591     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1592   },
1593 /* ld $dr,@$sr+ */
1594   {
1595     { 1, 1, 1, 1 },
1596     M32R_INSN_LD_PLUS, "ld-plus", "ld",
1597     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 } },
1598     { 16, 16, 0xf0f0 }, 0x20e0,
1599     "(parallel () (set dr (mem: WI sr)) (set sr (add sr (const 4))))",
1600     (PTR) & fmt_ld_plus_ops[0],
1601     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1602   },
1603 /* ld24 $dr,$uimm24 */
1604   {
1605     { 1, 1, 1, 1 },
1606     M32R_INSN_LD24, "ld24", "ld24",
1607     { { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 } },
1608     { 32, 32, 0xf0000000 }, 0xe0000000,
1609     "(set dr uimm24)",
1610     (PTR) & fmt_ld24_ops[0],
1611     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1612   },
1613 /* ldi8 $dr,$simm8 */
1614   {
1615     { 1, 1, 1, 1 },
1616     M32R_INSN_LDI8, "ldi8", "ldi8",
1617     { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
1618     { 16, 16, 0xf000 }, 0x6000,
1619     "(set dr simm8)",
1620     (PTR) & fmt_ldi8_ops[0],
1621     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1622   },
1623 /* ldi16 $dr,$hash$slo16 */
1624   {
1625     { 1, 1, 1, 1 },
1626     M32R_INSN_LDI16, "ldi16", "ldi16",
1627     { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
1628     { 32, 32, 0xf0ff0000 }, 0x90f00000,
1629     "(set dr slo16)",
1630     (PTR) & fmt_ldi16_ops[0],
1631     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1632   },
1633 /* lock $dr,@$sr */
1634   {
1635     { 1, 1, 1, 1 },
1636     M32R_INSN_LOCK, "lock", "lock",
1637     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
1638     { 16, 16, 0xf0f0 }, 0x20d0,
1639     "(sequence () (set (reg h-lock) (const: UBI 1)) (set dr (mem: WI sr)))",
1640     (PTR) & fmt_lock_ops[0],
1641     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1642   },
1643 /* machi $src1,$src2 */
1644   {
1645     { 1, 1, 1, 1 },
1646     M32R_INSN_MACHI, "machi", "machi",
1647     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1648     { 16, 16, 0xf0f0 }, 0x3040,
1649     "(set accum (sra: DI (sll: DI (add: DI accum (mul: DI (ext: DI (and: WI src1 (const 4294901760))) (ext: DI (trunc: HI (sra: WI src2 (const 16)))))) (const 8)) (const 8)))",
1650     (PTR) & fmt_machi_ops[0],
1651     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1652   },
1653 /* start-sanitize-m32rx */
1654 /* machi $src1,$src2,$acc */
1655   {
1656     { 1, 1, 1, 1 },
1657     M32R_INSN_MACHI_A, "machi-a", "machi",
1658     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
1659     { 16, 16, 0xf070 }, 0x3040,
1660     "(set acc (sra: DI (sll: DI (add: DI acc (mul: DI (ext: DI (and: WI src1 (const 4294901760))) (ext: DI (trunc: HI (sra: WI src2 (const 16)))))) (const 8)) (const 8)))",
1661     (PTR) & fmt_machi_a_ops[0],
1662     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1663   },
1664 /* end-sanitize-m32rx */
1665 /* maclo $src1,$src2 */
1666   {
1667     { 1, 1, 1, 1 },
1668     M32R_INSN_MACLO, "maclo", "maclo",
1669     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1670     { 16, 16, 0xf0f0 }, 0x3050,
1671     "(set accum (sra: DI (sll: DI (add: DI accum (mul: DI (ext: DI (sll: WI src1 (const 16))) (ext: DI (trunc: HI src2)))) (const 8)) (const 8)))",
1672     (PTR) & fmt_machi_ops[0],
1673     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1674   },
1675 /* start-sanitize-m32rx */
1676 /* maclo $src1,$src2,$acc */
1677   {
1678     { 1, 1, 1, 1 },
1679     M32R_INSN_MACLO_A, "maclo-a", "maclo",
1680     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
1681     { 16, 16, 0xf070 }, 0x3050,
1682     "(set acc (sra: DI (sll: DI (add: DI acc (mul: DI (ext: DI (sll: WI src1 (const 16))) (ext: DI (trunc: HI src2)))) (const 8)) (const 8)))",
1683     (PTR) & fmt_machi_a_ops[0],
1684     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1685   },
1686 /* end-sanitize-m32rx */
1687 /* macwhi $src1,$src2 */
1688   {
1689     { 1, 1, 1, 1 },
1690     M32R_INSN_MACWHI, "macwhi", "macwhi",
1691     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1692     { 16, 16, 0xf0f0 }, 0x3060,
1693     "(set accum (sra: DI (sll: DI (add: DI accum (mul: DI (ext: DI src1) (ext: DI (trunc: HI (sra: WI src2 (const 16)))))) (const 8)) (const 8)))",
1694     (PTR) & fmt_machi_ops[0],
1695     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1696   },
1697 /* start-sanitize-m32rx */
1698 /* macwhi $src1,$src2,$acc */
1699   {
1700     { 1, 1, 1, 1 },
1701     M32R_INSN_MACWHI_A, "macwhi-a", "macwhi",
1702     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
1703     { 16, 16, 0xf070 }, 0x3060,
1704     "(set acc (add acc (mul (ext: DI src1) (ext: DI (trunc: HI (sra src2 (const 16)))))))",
1705     (PTR) & fmt_machi_a_ops[0],
1706     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
1707   },
1708 /* end-sanitize-m32rx */
1709 /* macwlo $src1,$src2 */
1710   {
1711     { 1, 1, 1, 1 },
1712     M32R_INSN_MACWLO, "macwlo", "macwlo",
1713     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1714     { 16, 16, 0xf0f0 }, 0x3070,
1715     "(set accum (sra: DI (sll: DI (add: DI accum (mul: DI (ext: DI src1) (ext: DI (trunc: HI src2)))) (const 8)) (const 8)))",
1716     (PTR) & fmt_machi_ops[0],
1717     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1718   },
1719 /* start-sanitize-m32rx */
1720 /* macwlo $src1,$src2,$acc */
1721   {
1722     { 1, 1, 1, 1 },
1723     M32R_INSN_MACWLO_A, "macwlo-a", "macwlo",
1724     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
1725     { 16, 16, 0xf070 }, 0x3070,
1726     "(set acc (add acc (mul (ext: DI src1) (ext: DI (trunc: HI src2)))))",
1727     (PTR) & fmt_machi_a_ops[0],
1728     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
1729   },
1730 /* end-sanitize-m32rx */
1731 /* mul $dr,$sr */
1732   {
1733     { 1, 1, 1, 1 },
1734     M32R_INSN_MUL, "mul", "mul",
1735     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1736     { 16, 16, 0xf0f0 }, 0x1060,
1737     "(set dr (mul dr sr))",
1738     (PTR) & fmt_add_ops[0],
1739     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1740   },
1741 /* mulhi $src1,$src2 */
1742   {
1743     { 1, 1, 1, 1 },
1744     M32R_INSN_MULHI, "mulhi", "mulhi",
1745     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1746     { 16, 16, 0xf0f0 }, 0x3000,
1747     "(set accum (sra: DI (sll: DI (mul: DI (ext: DI (and: WI src1 (const 4294901760))) (ext: DI (trunc: HI (sra: WI src2 (const 16))))) (const 16)) (const 16)))",
1748     (PTR) & fmt_mulhi_ops[0],
1749     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1750   },
1751 /* start-sanitize-m32rx */
1752 /* mulhi $src1,$src2,$acc */
1753   {
1754     { 1, 1, 1, 1 },
1755     M32R_INSN_MULHI_A, "mulhi-a", "mulhi",
1756     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
1757     { 16, 16, 0xf070 }, 0x3000,
1758     "(set acc (sra: DI (sll: DI (mul: DI (ext: DI (and: WI src1 (const 4294901760))) (ext: DI (trunc: HI (sra: WI src2 (const 16))))) (const 16)) (const 16)))",
1759     (PTR) & fmt_mulhi_a_ops[0],
1760     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1761   },
1762 /* end-sanitize-m32rx */
1763 /* mullo $src1,$src2 */
1764   {
1765     { 1, 1, 1, 1 },
1766     M32R_INSN_MULLO, "mullo", "mullo",
1767     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1768     { 16, 16, 0xf0f0 }, 0x3010,
1769     "(set accum (sra: DI (sll: DI (mul: DI (ext: DI (sll: WI src1 (const 16))) (ext: DI (trunc: HI src2))) (const 16)) (const 16)))",
1770     (PTR) & fmt_mulhi_ops[0],
1771     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1772   },
1773 /* start-sanitize-m32rx */
1774 /* mullo $src1,$src2,$acc */
1775   {
1776     { 1, 1, 1, 1 },
1777     M32R_INSN_MULLO_A, "mullo-a", "mullo",
1778     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
1779     { 16, 16, 0xf070 }, 0x3010,
1780     "(set acc (sra: DI (sll: DI (mul: DI (ext: DI (sll: WI src1 (const 16))) (ext: DI (trunc: HI src2))) (const 16)) (const 16)))",
1781     (PTR) & fmt_mulhi_a_ops[0],
1782     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1783   },
1784 /* end-sanitize-m32rx */
1785 /* mulwhi $src1,$src2 */
1786   {
1787     { 1, 1, 1, 1 },
1788     M32R_INSN_MULWHI, "mulwhi", "mulwhi",
1789     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1790     { 16, 16, 0xf0f0 }, 0x3020,
1791     "(set accum (sra: DI (sll: DI (mul: DI (ext: DI src1) (ext: DI (trunc: HI (sra: WI src2 (const 16))))) (const 8)) (const 8)))",
1792     (PTR) & fmt_mulhi_ops[0],
1793     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1794   },
1795 /* start-sanitize-m32rx */
1796 /* mulwhi $src1,$src2,$acc */
1797   {
1798     { 1, 1, 1, 1 },
1799     M32R_INSN_MULWHI_A, "mulwhi-a", "mulwhi",
1800     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
1801     { 16, 16, 0xf070 }, 0x3020,
1802     "(set acc (mul (ext: DI src1) (ext: DI (trunc: HI (sra src2 (const 16))))))",
1803     (PTR) & fmt_mulhi_a_ops[0],
1804     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
1805   },
1806 /* end-sanitize-m32rx */
1807 /* mulwlo $src1,$src2 */
1808   {
1809     { 1, 1, 1, 1 },
1810     M32R_INSN_MULWLO, "mulwlo", "mulwlo",
1811     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1812     { 16, 16, 0xf0f0 }, 0x3030,
1813     "(set accum (sra: DI (sll: DI (mul: DI (ext: DI src1) (ext: DI (trunc: HI src2))) (const 8)) (const 8)))",
1814     (PTR) & fmt_mulhi_ops[0],
1815     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1816   },
1817 /* start-sanitize-m32rx */
1818 /* mulwlo $src1,$src2,$acc */
1819   {
1820     { 1, 1, 1, 1 },
1821     M32R_INSN_MULWLO_A, "mulwlo-a", "mulwlo",
1822     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
1823     { 16, 16, 0xf070 }, 0x3030,
1824     "(set acc (mul (ext: DI src1) (ext: DI (trunc: HI src2))))",
1825     (PTR) & fmt_mulhi_a_ops[0],
1826     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
1827   },
1828 /* end-sanitize-m32rx */
1829 /* mv $dr,$sr */
1830   {
1831     { 1, 1, 1, 1 },
1832     M32R_INSN_MV, "mv", "mv",
1833     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1834     { 16, 16, 0xf0f0 }, 0x1080,
1835     "(set dr sr)",
1836     (PTR) & fmt_mv_ops[0],
1837     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1838   },
1839 /* mvfachi $dr */
1840   {
1841     { 1, 1, 1, 1 },
1842     M32R_INSN_MVFACHI, "mvfachi", "mvfachi",
1843     { { MNEM, ' ', OP (DR), 0 } },
1844     { 16, 16, 0xf0ff }, 0x50f0,
1845     "(set dr (trunc: WI (sra: DI accum (const 32))))",
1846     (PTR) & fmt_mvfachi_ops[0],
1847     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1848   },
1849 /* start-sanitize-m32rx */
1850 /* mvfachi $dr,$accs */
1851   {
1852     { 1, 1, 1, 1 },
1853     M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi",
1854     { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
1855     { 16, 16, 0xf0f3 }, 0x50f0,
1856     "(set dr (trunc: WI (sra: DI accs (const 32))))",
1857     (PTR) & fmt_mvfachi_a_ops[0],
1858     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1859   },
1860 /* end-sanitize-m32rx */
1861 /* mvfaclo $dr */
1862   {
1863     { 1, 1, 1, 1 },
1864     M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo",
1865     { { MNEM, ' ', OP (DR), 0 } },
1866     { 16, 16, 0xf0ff }, 0x50f1,
1867     "(set dr (trunc: WI accum))",
1868     (PTR) & fmt_mvfachi_ops[0],
1869     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1870   },
1871 /* start-sanitize-m32rx */
1872 /* mvfaclo $dr,$accs */
1873   {
1874     { 1, 1, 1, 1 },
1875     M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo",
1876     { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
1877     { 16, 16, 0xf0f3 }, 0x50f1,
1878     "(set dr (trunc: WI accs))",
1879     (PTR) & fmt_mvfachi_a_ops[0],
1880     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1881   },
1882 /* end-sanitize-m32rx */
1883 /* mvfacmi $dr */
1884   {
1885     { 1, 1, 1, 1 },
1886     M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi",
1887     { { MNEM, ' ', OP (DR), 0 } },
1888     { 16, 16, 0xf0ff }, 0x50f2,
1889     "(set dr (trunc: WI (sra: DI accum (const 16))))",
1890     (PTR) & fmt_mvfachi_ops[0],
1891     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1892   },
1893 /* start-sanitize-m32rx */
1894 /* mvfacmi $dr,$accs */
1895   {
1896     { 1, 1, 1, 1 },
1897     M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi",
1898     { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
1899     { 16, 16, 0xf0f3 }, 0x50f2,
1900     "(set dr (trunc: WI (sra: DI accs (const 16))))",
1901     (PTR) & fmt_mvfachi_a_ops[0],
1902     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1903   },
1904 /* end-sanitize-m32rx */
1905 /* mvfc $dr,$scr */
1906   {
1907     { 1, 1, 1, 1 },
1908     M32R_INSN_MVFC, "mvfc", "mvfc",
1909     { { MNEM, ' ', OP (DR), ',', OP (SCR), 0 } },
1910     { 16, 16, 0xf0f0 }, 0x1090,
1911     "(set dr scr)",
1912     (PTR) & fmt_mvfc_ops[0],
1913     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1914   },
1915 /* mvtachi $src1 */
1916   {
1917     { 1, 1, 1, 1 },
1918     M32R_INSN_MVTACHI, "mvtachi", "mvtachi",
1919     { { MNEM, ' ', OP (SRC1), 0 } },
1920     { 16, 16, 0xf0ff }, 0x5070,
1921     "(set accum (or: DI (and: DI accum (const: DI 4294967295)) (sll: DI (ext: DI src1) (const 32))))",
1922     (PTR) & fmt_mvtachi_ops[0],
1923     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1924   },
1925 /* start-sanitize-m32rx */
1926 /* mvtachi $src1,$accs */
1927   {
1928     { 1, 1, 1, 1 },
1929     M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi",
1930     { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
1931     { 16, 16, 0xf0f3 }, 0x5070,
1932     "(set accs (or: DI (and: DI accs (const: DI 4294967295)) (sll: DI (ext: DI src1) (const 32))))",
1933     (PTR) & fmt_mvtachi_a_ops[0],
1934     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1935   },
1936 /* end-sanitize-m32rx */
1937 /* mvtaclo $src1 */
1938   {
1939     { 1, 1, 1, 1 },
1940     M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo",
1941     { { MNEM, ' ', OP (SRC1), 0 } },
1942     { 16, 16, 0xf0ff }, 0x5071,
1943     "(set accum (or: DI (and: DI accum (const: DI 18446744069414584320)) (zext: DI src1)))",
1944     (PTR) & fmt_mvtachi_ops[0],
1945     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1946   },
1947 /* start-sanitize-m32rx */
1948 /* mvtaclo $src1,$accs */
1949   {
1950     { 1, 1, 1, 1 },
1951     M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo",
1952     { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
1953     { 16, 16, 0xf0f3 }, 0x5071,
1954     "(set accs (or: DI (and: DI accs (const: DI 18446744069414584320)) (zext: DI src1)))",
1955     (PTR) & fmt_mvtachi_a_ops[0],
1956     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1957   },
1958 /* end-sanitize-m32rx */
1959 /* mvtc $sr,$dcr */
1960   {
1961     { 1, 1, 1, 1 },
1962     M32R_INSN_MVTC, "mvtc", "mvtc",
1963     { { MNEM, ' ', OP (SR), ',', OP (DCR), 0 } },
1964     { 16, 16, 0xf0f0 }, 0x10a0,
1965     "(set dcr sr)",
1966     (PTR) & fmt_mvtc_ops[0],
1967     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1968   },
1969 /* neg $dr,$sr */
1970   {
1971     { 1, 1, 1, 1 },
1972     M32R_INSN_NEG, "neg", "neg",
1973     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1974     { 16, 16, 0xf0f0 }, 0x30,
1975     "(set dr (neg sr))",
1976     (PTR) & fmt_mv_ops[0],
1977     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1978   },
1979 /* nop */
1980   {
1981     { 1, 1, 1, 1 },
1982     M32R_INSN_NOP, "nop", "nop",
1983     { { MNEM, 0 } },
1984     { 16, 16, 0xffff }, 0x7000,
1985     "(c-code: VM PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
1986 )",
1987     (PTR) 0,
1988     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1989   },
1990 /* not $dr,$sr */
1991   {
1992     { 1, 1, 1, 1 },
1993     M32R_INSN_NOT, "not", "not",
1994     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1995     { 16, 16, 0xf0f0 }, 0xb0,
1996     "(set dr (inv sr))",
1997     (PTR) & fmt_mv_ops[0],
1998     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1999   },
2000 /* rac */
2001   {
2002     { 1, 1, 1, 1 },
2003     M32R_INSN_RAC, "rac", "rac",
2004     { { MNEM, 0 } },
2005     { 16, 16, 0xffff }, 0x5090,
2006     "(sequence ((DI tmp1)) (set tmp1 (sll: DI accum (const 1))) (set tmp1 (add: DI tmp1 (const: DI 32768))) (set accum (cond: DI ((gt tmp1 (const: DI 140737488289792)) (const: DI 140737488289792)) ((lt tmp1 (const: DI 18446603336221196288)) (const: DI 18446603336221196288)) (else (and tmp1 (const: DI 18446744073709486080))))))",
2007     (PTR) & fmt_rac_ops[0],
2008     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
2009   },
2010 /* start-sanitize-m32rx */
2011 /* rac $accd,$accs,$imm1 */
2012   {
2013     { 1, 1, 1, 1 },
2014     M32R_INSN_RAC_DSI, "rac-dsi", "rac",
2015     { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
2016     { 16, 16, 0xf3f2 }, 0x5090,
2017     "(sequence ((DI tmp1)) (set tmp1 (sll accs imm1)) (set tmp1 (add tmp1 (const: DI 32768))) (set accd (cond: DI ((gt tmp1 (const: DI 140737488289792)) (const: DI 140737488289792)) ((lt tmp1 (const: DI 18446603336221196288)) (const: DI 18446603336221196288)) (else (and tmp1 (const: DI 18446744073709486080))))))",
2018     (PTR) & fmt_rac_dsi_ops[0],
2019     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2020   },
2021 /* end-sanitize-m32rx */
2022 /* rach */
2023   {
2024     { 1, 1, 1, 1 },
2025     M32R_INSN_RACH, "rach", "rach",
2026     { { MNEM, 0 } },
2027     { 16, 16, 0xffff }, 0x5080,
2028     "(sequence ((DI tmp1)) (set tmp1 (and accum (const: DI 72057594037927935))) (if (andif: WI (ge tmp1 (const: DI 70366596694016)) (le tmp1 (const: DI 36028797018963967))) (set tmp1 (const: DI 70366596694016)) (if (andif: WI (ge tmp1 (const: DI 36028797018963968)) (le tmp1 (const: DI 71987225293750272))) (set tmp1 (const: DI 71987225293750272)) (set tmp1 (and (add accum (const: DI 1073741824)) (const: DI 18446744071562067968))))) (set tmp1 (sll tmp1 (const 1))) (set accum (sra: DI (sll: DI tmp1 (const 7)) (const 7))))",
2029     (PTR) & fmt_rac_ops[0],
2030     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
2031   },
2032 /* start-sanitize-m32rx */
2033 /* rach $accd,$accs,$imm1 */
2034   {
2035     { 1, 1, 1, 1 },
2036     M32R_INSN_RACH_DSI, "rach-dsi", "rach",
2037     { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
2038     { 16, 16, 0xf3f2 }, 0x5080,
2039     "(sequence ((DI tmp1)) (set tmp1 (sll accs imm1)) (set tmp1 (add tmp1 (const: DI 2147483648))) (set accd (cond: DI ((gt tmp1 (const: DI 140733193388032)) (const: DI 140733193388032)) ((lt tmp1 (const: DI 18446603336221196288)) (const: DI 18446603336221196288)) (else (and tmp1 (const: DI 18446744069414584320))))))",
2040     (PTR) & fmt_rac_dsi_ops[0],
2041     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2042   },
2043 /* end-sanitize-m32rx */
2044 /* rte */
2045   {
2046     { 1, 1, 1, 1 },
2047     M32R_INSN_RTE, "rte", "rte",
2048     { { MNEM, 0 } },
2049     { 16, 16, 0xffff }, 0x10d6,
2050     "(sequence () (set (reg h-sm) (reg h-bsm)) (set (reg h-ie) (reg h-bie)) (set condbit (reg h-bcond)) (set pc (and (reg h-bpc) (const -4))))",
2051     (PTR) & fmt_rte_ops[0],
2052     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
2053   },
2054 /* seth $dr,$hash$hi16 */
2055   {
2056     { 1, 1, 1, 1 },
2057     M32R_INSN_SETH, "seth", "seth",
2058     { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (HI16), 0 } },
2059     { 32, 32, 0xf0ff0000 }, 0xd0c00000,
2060     "(set dr (sll: WI hi16 (const 16)))",
2061     (PTR) & fmt_seth_ops[0],
2062     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2063   },
2064 /* sll $dr,$sr */
2065   {
2066     { 1, 1, 1, 1 },
2067     M32R_INSN_SLL, "sll", "sll",
2068     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
2069     { 16, 16, 0xf0f0 }, 0x1040,
2070     "(set dr (sll dr (and sr (const 31))))",
2071     (PTR) & fmt_add_ops[0],
2072     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2073   },
2074 /* sll3 $dr,$sr,$simm16 */
2075   {
2076     { 1, 1, 1, 1 },
2077     M32R_INSN_SLL3, "sll3", "sll3",
2078     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
2079     { 32, 32, 0xf0f00000 }, 0x90c00000,
2080     "(set dr (sll sr (and: WI simm16 (const 31))))",
2081     (PTR) & fmt_sll3_ops[0],
2082     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2083   },
2084 /* slli $dr,$uimm5 */
2085   {
2086     { 1, 1, 1, 1 },
2087     M32R_INSN_SLLI, "slli", "slli",
2088     { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
2089     { 16, 16, 0xf0e0 }, 0x5040,
2090     "(set dr (sll dr uimm5))",
2091     (PTR) & fmt_slli_ops[0],
2092     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2093   },
2094 /* sra $dr,$sr */
2095   {
2096     { 1, 1, 1, 1 },
2097     M32R_INSN_SRA, "sra", "sra",
2098     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
2099     { 16, 16, 0xf0f0 }, 0x1020,
2100     "(set dr (sra dr (and sr (const 31))))",
2101     (PTR) & fmt_add_ops[0],
2102     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2103   },
2104 /* sra3 $dr,$sr,$simm16 */
2105   {
2106     { 1, 1, 1, 1 },
2107     M32R_INSN_SRA3, "sra3", "sra3",
2108     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
2109     { 32, 32, 0xf0f00000 }, 0x90a00000,
2110     "(set dr (sra sr (and: WI simm16 (const 31))))",
2111     (PTR) & fmt_sll3_ops[0],
2112     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2113   },
2114 /* srai $dr,$uimm5 */
2115   {
2116     { 1, 1, 1, 1 },
2117     M32R_INSN_SRAI, "srai", "srai",
2118     { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
2119     { 16, 16, 0xf0e0 }, 0x5020,
2120     "(set dr (sra dr uimm5))",
2121     (PTR) & fmt_slli_ops[0],
2122     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2123   },
2124 /* srl $dr,$sr */
2125   {
2126     { 1, 1, 1, 1 },
2127     M32R_INSN_SRL, "srl", "srl",
2128     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
2129     { 16, 16, 0xf0f0 }, 0x1000,
2130     "(set dr (srl dr (and sr (const 31))))",
2131     (PTR) & fmt_add_ops[0],
2132     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2133   },
2134 /* srl3 $dr,$sr,$simm16 */
2135   {
2136     { 1, 1, 1, 1 },
2137     M32R_INSN_SRL3, "srl3", "srl3",
2138     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
2139     { 32, 32, 0xf0f00000 }, 0x90800000,
2140     "(set dr (srl sr (and: WI simm16 (const 31))))",
2141     (PTR) & fmt_sll3_ops[0],
2142     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2143   },
2144 /* srli $dr,$uimm5 */
2145   {
2146     { 1, 1, 1, 1 },
2147     M32R_INSN_SRLI, "srli", "srli",
2148     { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
2149     { 16, 16, 0xf0e0 }, 0x5000,
2150     "(set dr (srl dr uimm5))",
2151     (PTR) & fmt_slli_ops[0],
2152     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2153   },
2154 /* st $src1,@$src2 */
2155   {
2156     { 1, 1, 1, 1 },
2157     M32R_INSN_ST, "st", "st",
2158     { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
2159     { 16, 16, 0xf0f0 }, 0x2040,
2160     "(set: WI (mem: WI src2) src1)",
2161     (PTR) & fmt_st_ops[0],
2162     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2163   },
2164 /* st $src1,@($slo16,$src2) */
2165   {
2166     { 1, 1, 1, 1 },
2167     M32R_INSN_ST_D, "st-d", "st",
2168     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
2169     { 32, 32, 0xf0f00000 }, 0xa0400000,
2170     "(set: WI (mem: WI (add src2 slo16)) src1)",
2171     (PTR) & fmt_st_d_ops[0],
2172     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2173   },
2174 /* stb $src1,@$src2 */
2175   {
2176     { 1, 1, 1, 1 },
2177     M32R_INSN_STB, "stb", "stb",
2178     { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
2179     { 16, 16, 0xf0f0 }, 0x2000,
2180     "(set: QI (mem: QI src2) src1)",
2181     (PTR) & fmt_stb_ops[0],
2182     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2183   },
2184 /* stb $src1,@($slo16,$src2) */
2185   {
2186     { 1, 1, 1, 1 },
2187     M32R_INSN_STB_D, "stb-d", "stb",
2188     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
2189     { 32, 32, 0xf0f00000 }, 0xa0000000,
2190     "(set: QI (mem: QI (add src2 slo16)) src1)",
2191     (PTR) & fmt_stb_d_ops[0],
2192     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2193   },
2194 /* sth $src1,@$src2 */
2195   {
2196     { 1, 1, 1, 1 },
2197     M32R_INSN_STH, "sth", "sth",
2198     { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
2199     { 16, 16, 0xf0f0 }, 0x2020,
2200     "(set: HI (mem: HI src2) src1)",
2201     (PTR) & fmt_sth_ops[0],
2202     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2203   },
2204 /* sth $src1,@($slo16,$src2) */
2205   {
2206     { 1, 1, 1, 1 },
2207     M32R_INSN_STH_D, "sth-d", "sth",
2208     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
2209     { 32, 32, 0xf0f00000 }, 0xa0200000,
2210     "(set: HI (mem: HI (add src2 slo16)) src1)",
2211     (PTR) & fmt_sth_d_ops[0],
2212     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2213   },
2214 /* st $src1,@+$src2 */
2215   {
2216     { 1, 1, 1, 1 },
2217     M32R_INSN_ST_PLUS, "st-plus", "st",
2218     { { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 } },
2219     { 16, 16, 0xf0f0 }, 0x2060,
2220     "(sequence ((WI new-src2)) (set new-src2 (add: WI src2 (const: WI 4))) (set (mem: WI new-src2) src1) (set src2 new-src2))",
2221     (PTR) & fmt_st_plus_ops[0],
2222     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2223   },
2224 /* st $src1,@-$src2 */
2225   {
2226     { 1, 1, 1, 1 },
2227     M32R_INSN_ST_MINUS, "st-minus", "st",
2228     { { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 } },
2229     { 16, 16, 0xf0f0 }, 0x2070,
2230     "(sequence ((WI new-src2)) (set new-src2 (sub src2 (const 4))) (set (mem: WI new-src2) src1) (set src2 new-src2))",
2231     (PTR) & fmt_st_plus_ops[0],
2232     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2233   },
2234 /* sub $dr,$sr */
2235   {
2236     { 1, 1, 1, 1 },
2237     M32R_INSN_SUB, "sub", "sub",
2238     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
2239     { 16, 16, 0xf0f0 }, 0x20,
2240     "(set dr (sub dr sr))",
2241     (PTR) & fmt_add_ops[0],
2242     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2243   },
2244 /* subv $dr,$sr */
2245   {
2246     { 1, 1, 1, 1 },
2247     M32R_INSN_SUBV, "subv", "subv",
2248     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
2249     { 16, 16, 0xf0f0 }, 0x0,
2250     "(parallel () (set dr (sub dr sr)) (set condbit (sub-oflag dr sr (const 0))))",
2251     (PTR) & fmt_addv_ops[0],
2252     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2253   },
2254 /* subx $dr,$sr */
2255   {
2256     { 1, 1, 1, 1 },
2257     M32R_INSN_SUBX, "subx", "subx",
2258     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
2259     { 16, 16, 0xf0f0 }, 0x10,
2260     "(parallel () (set dr (subc dr sr condbit)) (set condbit (sub-cflag dr sr condbit)))",
2261     (PTR) & fmt_addx_ops[0],
2262     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2263   },
2264 /* trap $uimm4 */
2265   {
2266     { 1, 1, 1, 1 },
2267     M32R_INSN_TRAP, "trap", "trap",
2268     { { MNEM, ' ', OP (UIMM4), 0 } },
2269     { 16, 16, 0xfff0 }, 0x10f0,
2270     "(sequence () (set (reg h-cr 6) (add pc (const 4))) (set (reg h-cr 0) (and (sll (reg h-cr 0) (const 8)) (const 65408))) (set: WI pc (c-call: WI m32r_trap uimm4)))",
2271     (PTR) & fmt_trap_ops[0],
2272     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
2273   },
2274 /* unlock $src1,@$src2 */
2275   {
2276     { 1, 1, 1, 1 },
2277     M32R_INSN_UNLOCK, "unlock", "unlock",
2278     { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
2279     { 16, 16, 0xf0f0 }, 0x2050,
2280     "(sequence () (if (reg h-lock) (set (mem: WI src2) src1)) (set (reg h-lock) (const: UBI 0)))",
2281     (PTR) & fmt_unlock_ops[0],
2282     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2283   },
2284 /* start-sanitize-m32rx */
2285 /* satb $dr,$sr */
2286   {
2287     { 1, 1, 1, 1 },
2288     M32R_INSN_SATB, "satb", "satb",
2289     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
2290     { 32, 32, 0xf0f0ffff }, 0x80600300,
2291     "(set dr (cond: WI ((ge sr (const 127)) (const 127)) ((le sr (const -128)) (const -128)) (else sr)))",
2292     (PTR) & fmt_satb_ops[0],
2293     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
2294   },
2295 /* end-sanitize-m32rx */
2296 /* start-sanitize-m32rx */
2297 /* sath $dr,$sr */
2298   {
2299     { 1, 1, 1, 1 },
2300     M32R_INSN_SATH, "sath", "sath",
2301     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
2302     { 32, 32, 0xf0f0ffff }, 0x80600200,
2303     "(set dr (cond: WI ((ge sr (const 32767)) (const 32767)) ((le sr (const -32768)) (const -32768)) (else sr)))",
2304     (PTR) & fmt_satb_ops[0],
2305     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
2306   },
2307 /* end-sanitize-m32rx */
2308 /* start-sanitize-m32rx */
2309 /* sat $dr,$sr */
2310   {
2311     { 1, 1, 1, 1 },
2312     M32R_INSN_SAT, "sat", "sat",
2313     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
2314     { 32, 32, 0xf0f0ffff }, 0x80600000,
2315     "(set dr (if: WI condbit (if: WI (lt sr (const 0)) (const 2147483647) (const 2147483648)) sr))",
2316     (PTR) & fmt_sat_ops[0],
2317     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_NONE } }
2318   },
2319 /* end-sanitize-m32rx */
2320 /* start-sanitize-m32rx */
2321 /* pcmpbz $src2 */
2322   {
2323     { 1, 1, 1, 1 },
2324     M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz",
2325     { { MNEM, ' ', OP (SRC2), 0 } },
2326     { 16, 16, 0xfff0 }, 0x370,
2327     "(set condbit (cond: BI ((eq (and src2 (const 255)) (const 0)) (const: BI 1)) ((eq (and src2 (const 65280)) (const 0)) (const: BI 1)) ((eq (and src2 (const 16711680)) (const 0)) (const: BI 1)) ((eq (and src2 (const 4278190080)) (const 0)) (const: BI 1)) (else (const: BI 0))))",
2328     (PTR) & fmt_cmpz_ops[0],
2329     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
2330   },
2331 /* end-sanitize-m32rx */
2332 /* start-sanitize-m32rx */
2333 /* sadd */
2334   {
2335     { 1, 1, 1, 1 },
2336     M32R_INSN_SADD, "sadd", "sadd",
2337     { { MNEM, 0 } },
2338     { 16, 16, 0xffff }, 0x50e4,
2339     "(set (reg h-accums 0) (add (sra (reg h-accums 1) (const 16)) (reg h-accums 0)))",
2340     (PTR) & fmt_sadd_ops[0],
2341     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2342   },
2343 /* end-sanitize-m32rx */
2344 /* start-sanitize-m32rx */
2345 /* macwu1 $src1,$src2 */
2346   {
2347     { 1, 1, 1, 1 },
2348     M32R_INSN_MACWU1, "macwu1", "macwu1",
2349     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
2350     { 16, 16, 0xf0f0 }, 0x50b0,
2351     "(set (reg h-accums 1) (sra: DI (sll: DI (add: DI (reg h-accums 1) (mul: DI (ext: DI src1) (ext: DI (and src2 (const 65535))))) (const 8)) (const 8)))",
2352     (PTR) & fmt_macwu1_ops[0],
2353     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2354   },
2355 /* end-sanitize-m32rx */
2356 /* start-sanitize-m32rx */
2357 /* msblo $src1,$src2 */
2358   {
2359     { 1, 1, 1, 1 },
2360     M32R_INSN_MSBLO, "msblo", "msblo",
2361     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
2362     { 16, 16, 0xf0f0 }, 0x50d0,
2363     "(set accum (sra: DI (sll: DI (sub accum (sra: DI (sll: DI (mul: DI (ext: DI (trunc: HI src1)) (ext: DI (trunc: HI src2))) (const 32)) (const 16))) (const 8)) (const 8)))",
2364     (PTR) & fmt_machi_ops[0],
2365     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2366   },
2367 /* end-sanitize-m32rx */
2368 /* start-sanitize-m32rx */
2369 /* mulwu1 $src1,$src2 */
2370   {
2371     { 1, 1, 1, 1 },
2372     M32R_INSN_MULWU1, "mulwu1", "mulwu1",
2373     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
2374     { 16, 16, 0xf0f0 }, 0x50a0,
2375     "(set (reg h-accums 1) (sra: DI (sll: DI (mul: DI (ext: DI src1) (ext: DI (and src2 (const 65535)))) (const 16)) (const 16)))",
2376     (PTR) & fmt_mulwu1_ops[0],
2377     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2378   },
2379 /* end-sanitize-m32rx */
2380 /* start-sanitize-m32rx */
2381 /* maclh1 $src1,$src2 */
2382   {
2383     { 1, 1, 1, 1 },
2384     M32R_INSN_MACLH1, "maclh1", "maclh1",
2385     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
2386     { 16, 16, 0xf0f0 }, 0x50c0,
2387     "(set (reg h-accums 1) (sra: DI (sll: DI (add: DI (reg h-accums 1) (sll: DI (ext: DI (mul: SI (ext: SI (trunc: HI src1)) (sra: SI src2 (const: SI 16)))) (const 16))) (const 8)) (const 8)))",
2388     (PTR) & fmt_macwu1_ops[0],
2389     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2390   },
2391 /* end-sanitize-m32rx */
2392 /* start-sanitize-m32rx */
2393 /* sc */
2394   {
2395     { 1, 1, 1, 1 },
2396     M32R_INSN_SC, "sc", "sc",
2397     { { MNEM, 0 } },
2398     { 16, 16, 0xffff }, 0x7401,
2399     "(if condbit (c-code: VM BRANCH_NEW_PC (new_pc, NEW_PC_SKIP);
2400 ))",
2401     (PTR) & fmt_sc_ops[0],
2402     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_O } }
2403   },
2404 /* end-sanitize-m32rx */
2405 /* start-sanitize-m32rx */
2406 /* snc */
2407   {
2408     { 1, 1, 1, 1 },
2409     M32R_INSN_SNC, "snc", "snc",
2410     { { MNEM, 0 } },
2411     { 16, 16, 0xffff }, 0x7501,
2412     "(if (not condbit) (c-code: VM BRANCH_NEW_PC (new_pc, NEW_PC_SKIP);
2413 ))",
2414     (PTR) & fmt_sc_ops[0],
2415     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_O } }
2416   },
2417 /* end-sanitize-m32rx */
2418 };
2419
2420 #undef A
2421 #undef MNEM
2422 #undef OP
2423
2424 static const CGEN_INSN_TABLE insn_table =
2425 {
2426   & m32r_cgen_insn_table_entries[0],
2427   sizeof (CGEN_INSN),
2428   MAX_INSNS,
2429   NULL
2430 };
2431
2432 /* Each non-simple macro entry points to an array of expansion possibilities.  */
2433
2434 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
2435 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
2436 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
2437
2438 /* The macro instruction table.  */
2439
2440 static const CGEN_INSN macro_insn_table_entries[] =
2441 {
2442 /* bc $disp8 */
2443   {
2444     { 1, 1, 1, 1 },
2445     -1, "bc8r", "bc",
2446     { { MNEM, ' ', OP (DISP8), 0 } },
2447     { 16, 16, 0xff00 }, 0x7c00,
2448     0,
2449     (PTR) 0,
2450     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2451   },
2452 /* bc $disp24 */
2453   {
2454     { 1, 1, 1, 1 },
2455     -1, "bc24r", "bc",
2456     { { MNEM, ' ', OP (DISP24), 0 } },
2457     { 32, 32, 0xff000000 }, 0xfc000000,
2458     0,
2459     (PTR) 0,
2460     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2461   },
2462 /* bl $disp8 */
2463   {
2464     { 1, 1, 1, 1 },
2465     -1, "bl8r", "bl",
2466     { { MNEM, ' ', OP (DISP8), 0 } },
2467     { 16, 16, 0xff00 }, 0x7e00,
2468     0,
2469     (PTR) 0,
2470     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2471   },
2472 /* bl $disp24 */
2473   {
2474     { 1, 1, 1, 1 },
2475     -1, "bl24r", "bl",
2476     { { MNEM, ' ', OP (DISP24), 0 } },
2477     { 32, 32, 0xff000000 }, 0xfe000000,
2478     0,
2479     (PTR) 0,
2480     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2481   },
2482 /* bcl $disp8 */
2483   {
2484     { 1, 1, 1, 1 },
2485     -1, "bcl8r", "bcl",
2486     { { MNEM, ' ', OP (DISP8), 0 } },
2487     { 16, 16, 0xff00 }, 0x7800,
2488     0,
2489     (PTR) 0,
2490     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
2491   },
2492 /* bcl $disp24 */
2493   {
2494     { 1, 1, 1, 1 },
2495     -1, "bcl24r", "bcl",
2496     { { MNEM, ' ', OP (DISP24), 0 } },
2497     { 32, 32, 0xff000000 }, 0xf8000000,
2498     0,
2499     (PTR) 0,
2500     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
2501   },
2502 /* bnc $disp8 */
2503   {
2504     { 1, 1, 1, 1 },
2505     -1, "bnc8r", "bnc",
2506     { { MNEM, ' ', OP (DISP8), 0 } },
2507     { 16, 16, 0xff00 }, 0x7d00,
2508     0,
2509     (PTR) 0,
2510     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2511   },
2512 /* bnc $disp24 */
2513   {
2514     { 1, 1, 1, 1 },
2515     -1, "bnc24r", "bnc",
2516     { { MNEM, ' ', OP (DISP24), 0 } },
2517     { 32, 32, 0xff000000 }, 0xfd000000,
2518     0,
2519     (PTR) 0,
2520     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2521   },
2522 /* bra $disp8 */
2523   {
2524     { 1, 1, 1, 1 },
2525     -1, "bra8r", "bra",
2526     { { MNEM, ' ', OP (DISP8), 0 } },
2527     { 16, 16, 0xff00 }, 0x7f00,
2528     0,
2529     (PTR) 0,
2530     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2531   },
2532 /* bra $disp24 */
2533   {
2534     { 1, 1, 1, 1 },
2535     -1, "bra24r", "bra",
2536     { { MNEM, ' ', OP (DISP24), 0 } },
2537     { 32, 32, 0xff000000 }, 0xff000000,
2538     0,
2539     (PTR) 0,
2540     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2541   },
2542 /* bncl $disp8 */
2543   {
2544     { 1, 1, 1, 1 },
2545     -1, "bncl8r", "bncl",
2546     { { MNEM, ' ', OP (DISP8), 0 } },
2547     { 16, 16, 0xff00 }, 0x7900,
2548     0,
2549     (PTR) 0,
2550     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
2551   },
2552 /* bncl $disp24 */
2553   {
2554     { 1, 1, 1, 1 },
2555     -1, "bncl24r", "bncl",
2556     { { MNEM, ' ', OP (DISP24), 0 } },
2557     { 32, 32, 0xff000000 }, 0xf9000000,
2558     0,
2559     (PTR) 0,
2560     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
2561   },
2562 /* ld $dr,@($sr) */
2563   {
2564     { 1, 1, 1, 1 },
2565     -1, "ld-2", "ld",
2566     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
2567     { 16, 16, 0xf0f0 }, 0x20c0,
2568     0,
2569     (PTR) 0,
2570     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2571   },
2572 /* ld $dr,@($sr,$slo16) */
2573   {
2574     { 1, 1, 1, 1 },
2575     -1, "ld-d2", "ld",
2576     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
2577     { 32, 32, 0xf0f00000 }, 0xa0c00000,
2578     0,
2579     (PTR) 0,
2580     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2581   },
2582 /* ldb $dr,@($sr) */
2583   {
2584     { 1, 1, 1, 1 },
2585     -1, "ldb-2", "ldb",
2586     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
2587     { 16, 16, 0xf0f0 }, 0x2080,
2588     0,
2589     (PTR) 0,
2590     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2591   },
2592 /* ldb $dr,@($sr,$slo16) */
2593   {
2594     { 1, 1, 1, 1 },
2595     -1, "ldb-d2", "ldb",
2596     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
2597     { 32, 32, 0xf0f00000 }, 0xa0800000,
2598     0,
2599     (PTR) 0,
2600     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2601   },
2602 /* ldh $dr,@($sr) */
2603   {
2604     { 1, 1, 1, 1 },
2605     -1, "ldh-2", "ldh",
2606     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
2607     { 16, 16, 0xf0f0 }, 0x20a0,
2608     0,
2609     (PTR) 0,
2610     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2611   },
2612 /* ldh $dr,@($sr,$slo16) */
2613   {
2614     { 1, 1, 1, 1 },
2615     -1, "ldh-d2", "ldh",
2616     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
2617     { 32, 32, 0xf0f00000 }, 0xa0a00000,
2618     0,
2619     (PTR) 0,
2620     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2621   },
2622 /* ldub $dr,@($sr) */
2623   {
2624     { 1, 1, 1, 1 },
2625     -1, "ldub-2", "ldub",
2626     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
2627     { 16, 16, 0xf0f0 }, 0x2090,
2628     0,
2629     (PTR) 0,
2630     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2631   },
2632 /* ldub $dr,@($sr,$slo16) */
2633   {
2634     { 1, 1, 1, 1 },
2635     -1, "ldub-d2", "ldub",
2636     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
2637     { 32, 32, 0xf0f00000 }, 0xa0900000,
2638     0,
2639     (PTR) 0,
2640     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2641   },
2642 /* lduh $dr,@($sr) */
2643   {
2644     { 1, 1, 1, 1 },
2645     -1, "lduh-2", "lduh",
2646     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
2647     { 16, 16, 0xf0f0 }, 0x20b0,
2648     0,
2649     (PTR) 0,
2650     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2651   },
2652 /* lduh $dr,@($sr,$slo16) */
2653   {
2654     { 1, 1, 1, 1 },
2655     -1, "lduh-d2", "lduh",
2656     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
2657     { 32, 32, 0xf0f00000 }, 0xa0b00000,
2658     0,
2659     (PTR) 0,
2660     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2661   },
2662 /* pop $dr */
2663   {
2664     { 1, 1, 1, 1 },
2665     -1, "pop", "pop",
2666     { { MNEM, ' ', OP (DR), 0 } },
2667     { 16, 16, 0xf0ff }, 0x20ef,
2668     0,
2669     (PTR) 0,
2670     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2671   },
2672 /* ldi $dr,$simm8 */
2673   {
2674     { 1, 1, 1, 1 },
2675     -1, "ldi8a", "ldi",
2676     { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
2677     { 16, 16, 0xf000 }, 0x6000,
2678     0,
2679     (PTR) 0,
2680     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
2681   },
2682 /* ldi $dr,$hash$slo16 */
2683   {
2684     { 1, 1, 1, 1 },
2685     -1, "ldi16a", "ldi",
2686     { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
2687     { 32, 32, 0xf0ff0000 }, 0x90f00000,
2688     0,
2689     (PTR) 0,
2690     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2691   },
2692 /* rac $accd */
2693   {
2694     { 1, 1, 1, 1 },
2695     -1, "rac-d", "rac",
2696     { { MNEM, ' ', OP (ACCD), 0 } },
2697     { 16, 16, 0xf3ff }, 0x5090,
2698     0,
2699     (PTR) 0,
2700     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2701   },
2702 /* rac $accd,$accs */
2703   {
2704     { 1, 1, 1, 1 },
2705     -1, "rac-ds", "rac",
2706     { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
2707     { 16, 16, 0xf3f3 }, 0x5090,
2708     0,
2709     (PTR) 0,
2710     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2711   },
2712 /* rach $accd */
2713   {
2714     { 1, 1, 1, 1 },
2715     -1, "rach-d", "rach",
2716     { { MNEM, ' ', OP (ACCD), 0 } },
2717     { 16, 16, 0xf3ff }, 0x5080,
2718     0,
2719     (PTR) 0,
2720     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2721   },
2722 /* rach $accd,$accs */
2723   {
2724     { 1, 1, 1, 1 },
2725     -1, "rach-ds", "rach",
2726     { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
2727     { 16, 16, 0xf3f3 }, 0x5080,
2728     0,
2729     (PTR) 0,
2730     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2731   },
2732 /* st $src1,@($src2) */
2733   {
2734     { 1, 1, 1, 1 },
2735     -1, "st-2", "st",
2736     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
2737     { 16, 16, 0xf0f0 }, 0x2040,
2738     0,
2739     (PTR) 0,
2740     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2741   },
2742 /* st $src1,@($src2,$slo16) */
2743   {
2744     { 1, 1, 1, 1 },
2745     -1, "st-d2", "st",
2746     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
2747     { 32, 32, 0xf0f00000 }, 0xa0400000,
2748     0,
2749     (PTR) 0,
2750     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2751   },
2752 /* stb $src1,@($src2) */
2753   {
2754     { 1, 1, 1, 1 },
2755     -1, "stb-2", "stb",
2756     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
2757     { 16, 16, 0xf0f0 }, 0x2000,
2758     0,
2759     (PTR) 0,
2760     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2761   },
2762 /* stb $src1,@($src2,$slo16) */
2763   {
2764     { 1, 1, 1, 1 },
2765     -1, "stb-d2", "stb",
2766     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
2767     { 32, 32, 0xf0f00000 }, 0xa0000000,
2768     0,
2769     (PTR) 0,
2770     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2771   },
2772 /* sth $src1,@($src2) */
2773   {
2774     { 1, 1, 1, 1 },
2775     -1, "sth-2", "sth",
2776     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
2777     { 16, 16, 0xf0f0 }, 0x2020,
2778     0,
2779     (PTR) 0,
2780     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2781   },
2782 /* sth $src1,@($src2,$slo16) */
2783   {
2784     { 1, 1, 1, 1 },
2785     -1, "sth-d2", "sth",
2786     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
2787     { 32, 32, 0xf0f00000 }, 0xa0200000,
2788     0,
2789     (PTR) 0,
2790     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2791   },
2792 /* push $src1 */
2793   {
2794     { 1, 1, 1, 1 },
2795     -1, "push", "push",
2796     { { MNEM, ' ', OP (SRC1), 0 } },
2797     { 16, 16, 0xf0ff }, 0x207f,
2798     0,
2799     (PTR) 0,
2800     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2801   },
2802 };
2803
2804 #undef A
2805 #undef MNEM
2806 #undef OP
2807
2808 static const CGEN_INSN_TABLE macro_insn_table =
2809 {
2810   & macro_insn_table_entries[0],
2811   sizeof (CGEN_INSN),
2812   (sizeof (macro_insn_table_entries) /
2813    sizeof (macro_insn_table_entries[0])),
2814   NULL
2815 };
2816
2817 static void
2818 init_tables ()
2819 {
2820 }
2821
2822 /* Return non-zero if INSN is to be added to the hash table.
2823    Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file.  */
2824
2825 static int
2826 asm_hash_insn_p (insn)
2827      const CGEN_INSN * insn;
2828 {
2829   return CGEN_ASM_HASH_P (insn);
2830 }
2831
2832 static int
2833 dis_hash_insn_p (insn)
2834      const CGEN_INSN * insn;
2835 {
2836   /* If building the hash table and the NO-DIS attribute is present,
2837      ignore.  */
2838   if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS))
2839     return 0;
2840   return CGEN_DIS_HASH_P (insn);
2841 }
2842
2843 /* The result is the hash value of the insn.
2844    Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file.  */
2845
2846 static unsigned int
2847 asm_hash_insn (mnem)
2848      const char * mnem;
2849 {
2850   return CGEN_ASM_HASH (mnem);
2851 }
2852
2853 static unsigned int
2854 dis_hash_insn (buf, value)
2855      const char * buf;
2856      unsigned long value;
2857 {
2858   return CGEN_DIS_HASH (buf, value);
2859 }
2860
2861 /* Initialize an opcode table and return a descriptor.
2862    It's much like opening a file, and must be the first function called.  */
2863
2864 CGEN_OPCODE_DESC
2865 m32r_cgen_opcode_open (mach, endian)
2866      int mach;
2867      enum cgen_endian endian;
2868 {
2869   CGEN_OPCODE_TABLE * table = (CGEN_OPCODE_TABLE *) xmalloc (sizeof (CGEN_OPCODE_TABLE));
2870   static int init_p;
2871
2872   if (! init_p)
2873     {
2874       init_tables ();
2875       init_p = 1;
2876     }
2877
2878   memset (table, 0, sizeof (*table));
2879
2880   CGEN_OPCODE_MACH (table) = mach;
2881   CGEN_OPCODE_ENDIAN (table) = endian;
2882
2883   CGEN_OPCODE_HW_LIST (table) = & m32r_cgen_hw_entries[0];
2884
2885   CGEN_OPCODE_OPERAND_TABLE (table) = & m32r_cgen_operand_table[0];
2886
2887   * CGEN_OPCODE_INSN_TABLE (table) = insn_table;
2888
2889   * CGEN_OPCODE_MACRO_INSN_TABLE (table) = macro_insn_table;
2890
2891   CGEN_OPCODE_ASM_HASH_P (table) = asm_hash_insn_p;
2892   CGEN_OPCODE_ASM_HASH (table) = asm_hash_insn;
2893   CGEN_OPCODE_ASM_HASH_SIZE (table) = CGEN_ASM_HASH_SIZE;
2894
2895   CGEN_OPCODE_DIS_HASH_P (table) = dis_hash_insn_p;
2896   CGEN_OPCODE_DIS_HASH (table) = dis_hash_insn;
2897   CGEN_OPCODE_DIS_HASH_SIZE (table) = CGEN_DIS_HASH_SIZE;
2898
2899   return (CGEN_OPCODE_DESC) table;
2900 }
2901
2902 /* Close an opcode table.  */
2903
2904 void
2905 m32r_cgen_opcode_close (desc)
2906      CGEN_OPCODE_DESC desc;
2907 {
2908   free (desc);
2909 }
2910
2911 /* Getting values from cgen_fields is handled by a collection of functions.
2912    They are distinguished by the type of the VALUE argument they return.
2913    TODO: floating point, inlining support, remove cases where result type
2914    not appropriate.  */
2915
2916 int
2917 m32r_cgen_get_int_operand (opindex, fields)
2918      int opindex;
2919      const CGEN_FIELDS * fields;
2920 {
2921   int value;
2922
2923   switch (opindex)
2924     {
2925     case M32R_OPERAND_SR :
2926       value = fields->f_r2;
2927       break;
2928     case M32R_OPERAND_DR :
2929       value = fields->f_r1;
2930       break;
2931     case M32R_OPERAND_SRC1 :
2932       value = fields->f_r1;
2933       break;
2934     case M32R_OPERAND_SRC2 :
2935       value = fields->f_r2;
2936       break;
2937     case M32R_OPERAND_SCR :
2938       value = fields->f_r2;
2939       break;
2940     case M32R_OPERAND_DCR :
2941       value = fields->f_r1;
2942       break;
2943     case M32R_OPERAND_SIMM8 :
2944       value = fields->f_simm8;
2945       break;
2946     case M32R_OPERAND_SIMM16 :
2947       value = fields->f_simm16;
2948       break;
2949     case M32R_OPERAND_UIMM4 :
2950       value = fields->f_uimm4;
2951       break;
2952     case M32R_OPERAND_UIMM5 :
2953       value = fields->f_uimm5;
2954       break;
2955     case M32R_OPERAND_UIMM16 :
2956       value = fields->f_uimm16;
2957       break;
2958 /* start-sanitize-m32rx */
2959     case M32R_OPERAND_IMM1 :
2960       value = fields->f_imm1;
2961       break;
2962 /* end-sanitize-m32rx */
2963 /* start-sanitize-m32rx */
2964     case M32R_OPERAND_ACCD :
2965       value = fields->f_accd;
2966       break;
2967 /* end-sanitize-m32rx */
2968 /* start-sanitize-m32rx */
2969     case M32R_OPERAND_ACCS :
2970       value = fields->f_accs;
2971       break;
2972 /* end-sanitize-m32rx */
2973 /* start-sanitize-m32rx */
2974     case M32R_OPERAND_ACC :
2975       value = fields->f_acc;
2976       break;
2977 /* end-sanitize-m32rx */
2978     case M32R_OPERAND_HASH :
2979       value = fields->f_nil;
2980       break;
2981     case M32R_OPERAND_HI16 :
2982       value = fields->f_hi16;
2983       break;
2984     case M32R_OPERAND_SLO16 :
2985       value = fields->f_simm16;
2986       break;
2987     case M32R_OPERAND_ULO16 :
2988       value = fields->f_uimm16;
2989       break;
2990     case M32R_OPERAND_UIMM24 :
2991       value = fields->f_uimm24;
2992       break;
2993     case M32R_OPERAND_DISP8 :
2994       value = fields->f_disp8;
2995       break;
2996     case M32R_OPERAND_DISP16 :
2997       value = fields->f_disp16;
2998       break;
2999     case M32R_OPERAND_DISP24 :
3000       value = fields->f_disp24;
3001       break;
3002
3003     default :
3004       /* xgettext:c-format */
3005       fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
3006                        opindex);
3007       abort ();
3008   }
3009
3010   return value;
3011 }
3012
3013 bfd_vma
3014 m32r_cgen_get_vma_operand (opindex, fields)
3015      int opindex;
3016      const CGEN_FIELDS * fields;
3017 {
3018   bfd_vma value;
3019
3020   switch (opindex)
3021     {
3022     case M32R_OPERAND_SR :
3023       value = fields->f_r2;
3024       break;
3025     case M32R_OPERAND_DR :
3026       value = fields->f_r1;
3027       break;
3028     case M32R_OPERAND_SRC1 :
3029       value = fields->f_r1;
3030       break;
3031     case M32R_OPERAND_SRC2 :
3032       value = fields->f_r2;
3033       break;
3034     case M32R_OPERAND_SCR :
3035       value = fields->f_r2;
3036       break;
3037     case M32R_OPERAND_DCR :
3038       value = fields->f_r1;
3039       break;
3040     case M32R_OPERAND_SIMM8 :
3041       value = fields->f_simm8;
3042       break;
3043     case M32R_OPERAND_SIMM16 :
3044       value = fields->f_simm16;
3045       break;
3046     case M32R_OPERAND_UIMM4 :
3047       value = fields->f_uimm4;
3048       break;
3049     case M32R_OPERAND_UIMM5 :
3050       value = fields->f_uimm5;
3051       break;
3052     case M32R_OPERAND_UIMM16 :
3053       value = fields->f_uimm16;
3054       break;
3055 /* start-sanitize-m32rx */
3056     case M32R_OPERAND_IMM1 :
3057       value = fields->f_imm1;
3058       break;
3059 /* end-sanitize-m32rx */
3060 /* start-sanitize-m32rx */
3061     case M32R_OPERAND_ACCD :
3062       value = fields->f_accd;
3063       break;
3064 /* end-sanitize-m32rx */
3065 /* start-sanitize-m32rx */
3066     case M32R_OPERAND_ACCS :
3067       value = fields->f_accs;
3068       break;
3069 /* end-sanitize-m32rx */
3070 /* start-sanitize-m32rx */
3071     case M32R_OPERAND_ACC :
3072       value = fields->f_acc;
3073       break;
3074 /* end-sanitize-m32rx */
3075     case M32R_OPERAND_HASH :
3076       value = fields->f_nil;
3077       break;
3078     case M32R_OPERAND_HI16 :
3079       value = fields->f_hi16;
3080       break;
3081     case M32R_OPERAND_SLO16 :
3082       value = fields->f_simm16;
3083       break;
3084     case M32R_OPERAND_ULO16 :
3085       value = fields->f_uimm16;
3086       break;
3087     case M32R_OPERAND_UIMM24 :
3088       value = fields->f_uimm24;
3089       break;
3090     case M32R_OPERAND_DISP8 :
3091       value = fields->f_disp8;
3092       break;
3093     case M32R_OPERAND_DISP16 :
3094       value = fields->f_disp16;
3095       break;
3096     case M32R_OPERAND_DISP24 :
3097       value = fields->f_disp24;
3098       break;
3099
3100     default :
3101       /* xgettext:c-format */
3102       fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
3103                        opindex);
3104       abort ();
3105   }
3106
3107   return value;
3108 }
3109
3110 /* Stuffing values in cgen_fields is handled by a collection of functions.
3111    They are distinguished by the type of the VALUE argument they accept.
3112    TODO: floating point, inlining support, remove cases where argument type
3113    not appropriate.  */
3114
3115 void
3116 m32r_cgen_set_int_operand (opindex, fields, value)
3117      int opindex;
3118      CGEN_FIELDS * fields;
3119      int value;
3120 {
3121   switch (opindex)
3122     {
3123     case M32R_OPERAND_SR :
3124       fields->f_r2 = value;
3125       break;
3126     case M32R_OPERAND_DR :
3127       fields->f_r1 = value;
3128       break;
3129     case M32R_OPERAND_SRC1 :
3130       fields->f_r1 = value;
3131       break;
3132     case M32R_OPERAND_SRC2 :
3133       fields->f_r2 = value;
3134       break;
3135     case M32R_OPERAND_SCR :
3136       fields->f_r2 = value;
3137       break;
3138     case M32R_OPERAND_DCR :
3139       fields->f_r1 = value;
3140       break;
3141     case M32R_OPERAND_SIMM8 :
3142       fields->f_simm8 = value;
3143       break;
3144     case M32R_OPERAND_SIMM16 :
3145       fields->f_simm16 = value;
3146       break;
3147     case M32R_OPERAND_UIMM4 :
3148       fields->f_uimm4 = value;
3149       break;
3150     case M32R_OPERAND_UIMM5 :
3151       fields->f_uimm5 = value;
3152       break;
3153     case M32R_OPERAND_UIMM16 :
3154       fields->f_uimm16 = value;
3155       break;
3156 /* start-sanitize-m32rx */
3157     case M32R_OPERAND_IMM1 :
3158       fields->f_imm1 = value;
3159       break;
3160 /* end-sanitize-m32rx */
3161 /* start-sanitize-m32rx */
3162     case M32R_OPERAND_ACCD :
3163       fields->f_accd = value;
3164       break;
3165 /* end-sanitize-m32rx */
3166 /* start-sanitize-m32rx */
3167     case M32R_OPERAND_ACCS :
3168       fields->f_accs = value;
3169       break;
3170 /* end-sanitize-m32rx */
3171 /* start-sanitize-m32rx */
3172     case M32R_OPERAND_ACC :
3173       fields->f_acc = value;
3174       break;
3175 /* end-sanitize-m32rx */
3176     case M32R_OPERAND_HASH :
3177       fields->f_nil = value;
3178       break;
3179     case M32R_OPERAND_HI16 :
3180       fields->f_hi16 = value;
3181       break;
3182     case M32R_OPERAND_SLO16 :
3183       fields->f_simm16 = value;
3184       break;
3185     case M32R_OPERAND_ULO16 :
3186       fields->f_uimm16 = value;
3187       break;
3188     case M32R_OPERAND_UIMM24 :
3189       fields->f_uimm24 = value;
3190       break;
3191     case M32R_OPERAND_DISP8 :
3192       fields->f_disp8 = value;
3193       break;
3194     case M32R_OPERAND_DISP16 :
3195       fields->f_disp16 = value;
3196       break;
3197     case M32R_OPERAND_DISP24 :
3198       fields->f_disp24 = value;
3199       break;
3200
3201     default :
3202       /* xgettext:c-format */
3203       fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
3204                        opindex);
3205       abort ();
3206   }
3207 }
3208
3209 void
3210 m32r_cgen_set_vma_operand (opindex, fields, value)
3211      int opindex;
3212      CGEN_FIELDS * fields;
3213      bfd_vma value;
3214 {
3215   switch (opindex)
3216     {
3217     case M32R_OPERAND_SR :
3218       fields->f_r2 = value;
3219       break;
3220     case M32R_OPERAND_DR :
3221       fields->f_r1 = value;
3222       break;
3223     case M32R_OPERAND_SRC1 :
3224       fields->f_r1 = value;
3225       break;
3226     case M32R_OPERAND_SRC2 :
3227       fields->f_r2 = value;
3228       break;
3229     case M32R_OPERAND_SCR :
3230       fields->f_r2 = value;
3231       break;
3232     case M32R_OPERAND_DCR :
3233       fields->f_r1 = value;
3234       break;
3235     case M32R_OPERAND_SIMM8 :
3236       fields->f_simm8 = value;
3237       break;
3238     case M32R_OPERAND_SIMM16 :
3239       fields->f_simm16 = value;
3240       break;
3241     case M32R_OPERAND_UIMM4 :
3242       fields->f_uimm4 = value;
3243       break;
3244     case M32R_OPERAND_UIMM5 :
3245       fields->f_uimm5 = value;
3246       break;
3247     case M32R_OPERAND_UIMM16 :
3248       fields->f_uimm16 = value;
3249       break;
3250 /* start-sanitize-m32rx */
3251     case M32R_OPERAND_IMM1 :
3252       fields->f_imm1 = value;
3253       break;
3254 /* end-sanitize-m32rx */
3255 /* start-sanitize-m32rx */
3256     case M32R_OPERAND_ACCD :
3257       fields->f_accd = value;
3258       break;
3259 /* end-sanitize-m32rx */
3260 /* start-sanitize-m32rx */
3261     case M32R_OPERAND_ACCS :
3262       fields->f_accs = value;
3263       break;
3264 /* end-sanitize-m32rx */
3265 /* start-sanitize-m32rx */
3266     case M32R_OPERAND_ACC :
3267       fields->f_acc = value;
3268       break;
3269 /* end-sanitize-m32rx */
3270     case M32R_OPERAND_HASH :
3271       fields->f_nil = value;
3272       break;
3273     case M32R_OPERAND_HI16 :
3274       fields->f_hi16 = value;
3275       break;
3276     case M32R_OPERAND_SLO16 :
3277       fields->f_simm16 = value;
3278       break;
3279     case M32R_OPERAND_ULO16 :
3280       fields->f_uimm16 = value;
3281       break;
3282     case M32R_OPERAND_UIMM24 :
3283       fields->f_uimm24 = value;
3284       break;
3285     case M32R_OPERAND_DISP8 :
3286       fields->f_disp8 = value;
3287       break;
3288     case M32R_OPERAND_DISP16 :
3289       fields->f_disp16 = value;
3290       break;
3291     case M32R_OPERAND_DISP24 :
3292       fields->f_disp24 = value;
3293       break;
3294
3295     default :
3296       /* xgettext:c-format */
3297       fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
3298                        opindex);
3299       abort ();
3300   }
3301 }
3302