1 /* Generic opcode table support for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
4 THIS FILE IS USED TO GENERATE m32r-opc.c.
6 Copyright (C) 1998 Free Software Foundation, Inc.
8 This file is part of the GNU Binutils and GDB, the GNU debugger.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software Foundation, Inc.,
22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
27 #include "libiberty.h"
33 /* The hash functions are recorded here to help keep assembler code out of
34 the disassembler and vice versa. */
36 static int asm_hash_insn_p
PARAMS ((const CGEN_INSN
*));
37 static unsigned int asm_hash_insn
PARAMS ((const char *));
38 static int dis_hash_insn_p
PARAMS ((const CGEN_INSN
*));
39 static unsigned int dis_hash_insn
PARAMS ((const char *, unsigned long));
41 /* Cover function to read and properly byteswap an insn value. */
44 cgen_get_insn_value (od
, buf
, length
)
57 if (CGEN_OPCODE_INSN_ENDIAN (od
) == CGEN_ENDIAN_BIG
)
58 value
= bfd_getb16 (buf
);
60 value
= bfd_getl16 (buf
);
63 if (CGEN_OPCODE_INSN_ENDIAN (od
) == CGEN_ENDIAN_BIG
)
64 value
= bfd_getb32 (buf
);
66 value
= bfd_getl32 (buf
);
75 /* Cover function to store an insn value properly byteswapped. */
78 cgen_put_insn_value (od
, buf
, length
, value
)
90 if (CGEN_OPCODE_INSN_ENDIAN (od
) == CGEN_ENDIAN_BIG
)
91 bfd_putb16 (value
, buf
);
93 bfd_putl16 (value
, buf
);
96 if (CGEN_OPCODE_INSN_ENDIAN (od
) == CGEN_ENDIAN_BIG
)
97 bfd_putb32 (value
, buf
);
99 bfd_putl32 (value
, buf
);
106 /* Look up instruction INSN_VALUE and extract its fields.
107 INSN, if non-null, is the insn table entry.
108 Otherwise INSN_VALUE is examined to compute it.
109 LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
110 0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'.
111 If INSN != NULL, LENGTH must be valid.
112 ALIAS_P is non-zero if alias insns are to be included in the search.
114 The result a pointer to the insn table entry, or NULL if the instruction
115 wasn't recognized. */
118 m32r_cgen_lookup_insn (od
, insn
, insn_value
, length
, fields
, alias_p
)
120 const CGEN_INSN
*insn
;
121 CGEN_INSN_BYTES insn_value
;
126 unsigned char buf
[16];
128 unsigned int base_insn
;
130 CGEN_EXTRACT_INFO
*info
= NULL
;
132 CGEN_EXTRACT_INFO ex_info
;
133 CGEN_EXTRACT_INFO
*info
= &ex_info
;
136 #if ! CGEN_INT_INSN_P
137 ex_info
.dis_info
= NULL
;
138 ex_info
.bytes
= insn_value
;
144 const CGEN_INSN_LIST
*insn_list
;
147 cgen_put_insn_value (od
, buf
, length
, insn_value
);
149 base_insn
= insn_value
; /*???*/
151 base_insn
= cgen_get_insn_value (od
, buf
, length
);
155 /* The instructions are stored in hash lists.
156 Pick the first one and keep trying until we find the right one. */
158 insn_list
= CGEN_DIS_LOOKUP_INSN (od
, bufp
, base_insn
);
159 while (insn_list
!= NULL
)
161 insn
= insn_list
->insn
;
164 || ! CGEN_INSN_ATTR (insn
, CGEN_INSN_ALIAS
))
166 /* Basic bit mask must be correct. */
167 /* ??? May wish to allow target to defer this check until the
169 if ((insn_value
& CGEN_INSN_MASK (insn
)) == CGEN_INSN_VALUE (insn
))
171 /* ??? 0 is passed for `pc' */
172 int elength
= (*CGEN_EXTRACT_FN (insn
)) (od
, insn
, info
,
178 if (length
!= 0 && length
!= elength
)
185 insn_list
= CGEN_DIS_NEXT_INSN (insn_list
);
190 /* Sanity check: can't pass an alias insn if ! alias_p. */
192 && CGEN_INSN_ATTR (insn
, CGEN_INSN_ALIAS
))
194 /* Sanity check: length must be correct. */
195 if (length
!= CGEN_INSN_BITSIZE (insn
))
198 /* ??? 0 is passed for `pc' */
199 length
= (*CGEN_EXTRACT_FN (insn
)) (od
, insn
, info
, insn_value
, fields
,
201 /* Sanity check: must succeed.
202 Could relax this later if it ever proves useful. */
211 /* Fill in the operand instances used by INSN whose operands are FIELDS.
212 INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
216 m32r_cgen_get_insn_operands (od
, insn
, fields
, indices
)
218 const CGEN_INSN
* insn
;
219 const CGEN_FIELDS
* fields
;
222 const CGEN_OPERAND_INSTANCE
*opinst
;
225 for (i
= 0, opinst
= CGEN_INSN_OPERANDS (insn
);
227 && CGEN_OPERAND_INSTANCE_TYPE (opinst
) != CGEN_OPERAND_INSTANCE_END
;
230 const CGEN_OPERAND
*op
= CGEN_OPERAND_INSTANCE_OPERAND (opinst
);
232 indices
[i
] = CGEN_OPERAND_INSTANCE_INDEX (opinst
);
234 indices
[i
] = m32r_cgen_get_int_operand (CGEN_OPERAND_INDEX (op
),
239 /* Cover function to m32r_cgen_get_insn_operands when either INSN or FIELDS
241 The INSN, INSN_VALUE, and LENGTH arguments are passed to
242 m32r_cgen_lookup_insn unchanged.
244 The result is the insn table entry or NULL if the instruction wasn't
248 m32r_cgen_lookup_get_insn_operands (od
, insn
, insn_value
, length
, indices
)
250 const CGEN_INSN
*insn
;
251 CGEN_INSN_BYTES insn_value
;
257 /* Pass non-zero for ALIAS_P only if INSN != NULL.
258 If INSN == NULL, we want a real insn. */
259 insn
= m32r_cgen_lookup_insn (od
, insn
, insn_value
, length
, &fields
,
264 m32r_cgen_get_insn_operands (od
, insn
, &fields
, indices
);
269 static const CGEN_ATTR_ENTRY MACH_attr
[] =
271 { "base", MACH_BASE
},
272 { "m32r", MACH_M32R
},
273 /* start-sanitize-m32rx */
274 { "m32rx", MACH_M32RX
},
275 /* end-sanitize-m32rx */
280 /* start-sanitize-m32rx */
281 static const CGEN_ATTR_ENTRY PIPE_attr
[] =
283 { "NONE", PIPE_NONE
},
290 /* end-sanitize-m32rx */
291 const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table
[] =
293 { "MACH", & MACH_attr
[0] },
294 { "CACHE-ADDR", NULL
},
295 { "FUN-ACCESS", NULL
},
298 { "SIGN-OPT", NULL
},
299 { "UNSIGNED", NULL
},
303 const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table
[] =
305 { "ABS-ADDR", NULL
},
306 { "HASH-PREFIX", NULL
},
307 { "NEGATIVE", NULL
},
308 { "PCREL-ADDR", NULL
},
311 { "SEM-ONLY", NULL
},
312 { "SIGN-OPT", NULL
},
313 { "UNSIGNED", NULL
},
317 const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table
[] =
319 { "MACH", & MACH_attr
[0] },
320 /* start-sanitize-m32rx */
321 { "PIPE", & PIPE_attr
[0] },
322 /* end-sanitize-m32rx */
324 { "COND-CTI", NULL
},
325 { "FILL-SLOT", NULL
},
328 { "RELAXABLE", NULL
},
329 { "SKIP-CTI", NULL
},
331 { "UNCOND-CTI", NULL
},
336 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_gr_entries
[] =
359 CGEN_KEYWORD m32r_cgen_opval_h_gr
=
361 & m32r_cgen_opval_h_gr_entries
[0],
365 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_cr_entries
[] =
392 CGEN_KEYWORD m32r_cgen_opval_h_cr
=
394 & m32r_cgen_opval_h_cr_entries
[0],
398 /* start-sanitize-m32rx */
399 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries
[] =
405 CGEN_KEYWORD m32r_cgen_opval_h_accums
=
407 & m32r_cgen_opval_h_accums_entries
[0],
411 /* end-sanitize-m32rx */
413 /* The hardware table. */
415 #define HW_ENT(n) m32r_cgen_hw_entries[n]
416 static const CGEN_HW_ENTRY m32r_cgen_hw_entries
[] =
418 { HW_H_PC
, & HW_ENT (HW_H_PC
+ 1), "h-pc", CGEN_ASM_KEYWORD
, (PTR
) 0, { CGEN_HW_NBOOL_ATTRS
, 0|(1<<CGEN_HW_PROFILE
)|(1<<CGEN_HW_PC
), { (1<<MACH_BASE
) } } },
419 { HW_H_MEMORY
, & HW_ENT (HW_H_MEMORY
+ 1), "h-memory", CGEN_ASM_KEYWORD
, (PTR
) 0, { CGEN_HW_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } } },
420 { HW_H_SINT
, & HW_ENT (HW_H_SINT
+ 1), "h-sint", CGEN_ASM_KEYWORD
, (PTR
) 0, { CGEN_HW_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } } },
421 { HW_H_UINT
, & HW_ENT (HW_H_UINT
+ 1), "h-uint", CGEN_ASM_KEYWORD
, (PTR
) 0, { CGEN_HW_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } } },
422 { HW_H_ADDR
, & HW_ENT (HW_H_ADDR
+ 1), "h-addr", CGEN_ASM_KEYWORD
, (PTR
) 0, { CGEN_HW_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } } },
423 { HW_H_IADDR
, & HW_ENT (HW_H_IADDR
+ 1), "h-iaddr", CGEN_ASM_KEYWORD
, (PTR
) 0, { CGEN_HW_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } } },
424 { HW_H_HI16
, & HW_ENT (HW_H_HI16
+ 1), "h-hi16", CGEN_ASM_KEYWORD
, (PTR
) 0, { CGEN_HW_NBOOL_ATTRS
, 0|(1<<CGEN_HW_SIGN_OPT
)|(1<<CGEN_HW_UNSIGNED
), { (1<<MACH_BASE
) } } },
425 { HW_H_SLO16
, & HW_ENT (HW_H_SLO16
+ 1), "h-slo16", CGEN_ASM_KEYWORD
, (PTR
) 0, { CGEN_HW_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } } },
426 { HW_H_ULO16
, & HW_ENT (HW_H_ULO16
+ 1), "h-ulo16", CGEN_ASM_KEYWORD
, (PTR
) 0, { CGEN_HW_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } } },
427 { HW_H_GR
, & HW_ENT (HW_H_GR
+ 1), "h-gr", CGEN_ASM_KEYWORD
, (PTR
) & m32r_cgen_opval_h_gr
, { CGEN_HW_NBOOL_ATTRS
, 0|(1<<CGEN_HW_CACHE_ADDR
)|(1<<CGEN_HW_PROFILE
), { (1<<MACH_BASE
) } } },
428 { HW_H_CR
, & HW_ENT (HW_H_CR
+ 1), "h-cr", CGEN_ASM_KEYWORD
, (PTR
) & m32r_cgen_opval_h_cr
, { CGEN_HW_NBOOL_ATTRS
, 0|(1<<CGEN_HW_FUN_ACCESS
), { (1<<MACH_BASE
) } } },
429 { HW_H_ACCUM
, & HW_ENT (HW_H_ACCUM
+ 1), "h-accum", CGEN_ASM_KEYWORD
, (PTR
) 0, { CGEN_HW_NBOOL_ATTRS
, 0|(1<<CGEN_HW_FUN_ACCESS
), { (1<<MACH_BASE
) } } },
430 /* start-sanitize-m32rx */
431 { HW_H_ACCUMS
, & HW_ENT (HW_H_ACCUMS
+ 1), "h-accums", CGEN_ASM_KEYWORD
, (PTR
) & m32r_cgen_opval_h_accums
, { CGEN_HW_NBOOL_ATTRS
, 0|(1<<CGEN_HW_FUN_ACCESS
), { (1<<MACH_M32RX
) } } },
432 /* end-sanitize-m32rx */
433 { HW_H_COND
, & HW_ENT (HW_H_COND
+ 1), "h-cond", CGEN_ASM_KEYWORD
, (PTR
) 0, { CGEN_HW_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } } },
434 { HW_H_PSW
, & HW_ENT (HW_H_PSW
+ 1), "h-psw", CGEN_ASM_KEYWORD
, (PTR
) 0, { CGEN_HW_NBOOL_ATTRS
, 0|(1<<CGEN_HW_FUN_ACCESS
), { (1<<MACH_BASE
) } } },
435 { HW_H_BPSW
, & HW_ENT (HW_H_BPSW
+ 1), "h-bpsw", CGEN_ASM_KEYWORD
, (PTR
) 0, { CGEN_HW_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } } },
436 { HW_H_BBPSW
, & HW_ENT (HW_H_BBPSW
+ 1), "h-bbpsw", CGEN_ASM_KEYWORD
, (PTR
) 0, { CGEN_HW_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } } },
437 { HW_H_LOCK
, & HW_ENT (HW_H_LOCK
+ 1), "h-lock", CGEN_ASM_KEYWORD
, (PTR
) 0, { CGEN_HW_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
) } } },
441 /* The operand table. */
443 #define OPERAND(op) CONCAT2 (M32R_OPERAND_,op)
444 #define OP_ENT(op) m32r_cgen_operand_table[OPERAND (op)]
446 const CGEN_OPERAND m32r_cgen_operand_table
[MAX_OPERANDS
] =
448 /* pc: program counter */
449 { "pc", & HW_ENT (HW_H_PC
), 0, 0,
450 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY
), { 0 } } },
451 /* sr: source register */
452 { "sr", & HW_ENT (HW_H_GR
), 12, 4,
453 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
454 /* dr: destination register */
455 { "dr", & HW_ENT (HW_H_GR
), 4, 4,
456 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
457 /* src1: source register 1 */
458 { "src1", & HW_ENT (HW_H_GR
), 4, 4,
459 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
460 /* src2: source register 2 */
461 { "src2", & HW_ENT (HW_H_GR
), 12, 4,
462 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
463 /* scr: source control register */
464 { "scr", & HW_ENT (HW_H_CR
), 12, 4,
465 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
466 /* dcr: destination control register */
467 { "dcr", & HW_ENT (HW_H_CR
), 4, 4,
468 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
469 /* simm8: 8 bit signed immediate */
470 { "simm8", & HW_ENT (HW_H_SINT
), 8, 8,
471 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX
), { 0 } } },
472 /* simm16: 16 bit signed immediate */
473 { "simm16", & HW_ENT (HW_H_SINT
), 16, 16,
474 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX
), { 0 } } },
475 /* uimm4: 4 bit trap number */
476 { "uimm4", & HW_ENT (HW_H_UINT
), 12, 4,
477 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX
)|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
478 /* uimm5: 5 bit shift count */
479 { "uimm5", & HW_ENT (HW_H_UINT
), 11, 5,
480 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX
)|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
481 /* uimm16: 16 bit unsigned immediate */
482 { "uimm16", & HW_ENT (HW_H_UINT
), 16, 16,
483 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX
)|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
484 /* start-sanitize-m32rx */
485 /* imm1: 1 bit immediate */
486 { "imm1", & HW_ENT (HW_H_UINT
), 15, 1,
487 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX
)|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
488 /* end-sanitize-m32rx */
489 /* start-sanitize-m32rx */
490 /* accd: accumulator destination register */
491 { "accd", & HW_ENT (HW_H_ACCUMS
), 4, 2,
492 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
493 /* end-sanitize-m32rx */
494 /* start-sanitize-m32rx */
495 /* accs: accumulator source register */
496 { "accs", & HW_ENT (HW_H_ACCUMS
), 12, 2,
497 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
498 /* end-sanitize-m32rx */
499 /* start-sanitize-m32rx */
500 /* acc: accumulator reg (d) */
501 { "acc", & HW_ENT (HW_H_ACCUMS
), 8, 1,
502 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
503 /* end-sanitize-m32rx */
505 { "hash", & HW_ENT (HW_H_SINT
), 0, 0,
507 /* hi16: high 16 bit immediate, sign optional */
508 { "hi16", & HW_ENT (HW_H_HI16
), 16, 16,
509 { 0, 0|(1<<CGEN_OPERAND_SIGN_OPT
)|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
510 /* slo16: 16 bit signed immediate, for low() */
511 { "slo16", & HW_ENT (HW_H_SLO16
), 16, 16,
513 /* ulo16: 16 bit unsigned immediate, for low() */
514 { "ulo16", & HW_ENT (HW_H_ULO16
), 16, 16,
515 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
516 /* uimm24: 24 bit address */
517 { "uimm24", & HW_ENT (HW_H_ADDR
), 8, 24,
518 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX
)|(1<<CGEN_OPERAND_RELOC
)|(1<<CGEN_OPERAND_ABS_ADDR
)|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
519 /* disp8: 8 bit displacement */
520 { "disp8", & HW_ENT (HW_H_IADDR
), 8, 8,
521 { 0, 0|(1<<CGEN_OPERAND_RELAX
)|(1<<CGEN_OPERAND_RELOC
)|(1<<CGEN_OPERAND_PCREL_ADDR
), { 0 } } },
522 /* disp16: 16 bit displacement */
523 { "disp16", & HW_ENT (HW_H_IADDR
), 16, 16,
524 { 0, 0|(1<<CGEN_OPERAND_RELOC
)|(1<<CGEN_OPERAND_PCREL_ADDR
), { 0 } } },
525 /* disp24: 24 bit displacement */
526 { "disp24", & HW_ENT (HW_H_IADDR
), 8, 24,
527 { 0, 0|(1<<CGEN_OPERAND_RELAX
)|(1<<CGEN_OPERAND_RELOC
)|(1<<CGEN_OPERAND_PCREL_ADDR
), { 0 } } },
528 /* condbit: condition bit */
529 { "condbit", & HW_ENT (HW_H_COND
), 0, 0,
530 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY
), { 0 } } },
531 /* accum: accumulator */
532 { "accum", & HW_ENT (HW_H_ACCUM
), 0, 0,
533 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY
), { 0 } } },
536 /* Operand references. */
538 #define INPUT CGEN_OPERAND_INSTANCE_INPUT
539 #define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
541 static const CGEN_OPERAND_INSTANCE fmt_add_ops
[] = {
542 { INPUT
, "dr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
543 { INPUT
, "sr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
544 { OUTPUT
, "dr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
548 static const CGEN_OPERAND_INSTANCE fmt_add3_ops
[] = {
549 { INPUT
, "sr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
550 { INPUT
, "slo16", & HW_ENT (HW_H_SLO16
), CGEN_MODE_HI
, & OP_ENT (SLO16
), 0 },
551 { OUTPUT
, "dr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
555 static const CGEN_OPERAND_INSTANCE fmt_and3_ops
[] = {
556 { INPUT
, "sr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
557 { INPUT
, "uimm16", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (UIMM16
), 0 },
558 { OUTPUT
, "dr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
562 static const CGEN_OPERAND_INSTANCE fmt_or3_ops
[] = {
563 { INPUT
, "sr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
564 { INPUT
, "ulo16", & HW_ENT (HW_H_ULO16
), CGEN_MODE_UHI
, & OP_ENT (ULO16
), 0 },
565 { OUTPUT
, "dr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
569 static const CGEN_OPERAND_INSTANCE fmt_addi_ops
[] = {
570 { INPUT
, "dr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
571 { INPUT
, "simm8", & HW_ENT (HW_H_SINT
), CGEN_MODE_SI
, & OP_ENT (SIMM8
), 0 },
572 { OUTPUT
, "dr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
576 static const CGEN_OPERAND_INSTANCE fmt_addv_ops
[] = {
577 { INPUT
, "dr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
578 { INPUT
, "sr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
579 { OUTPUT
, "dr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
580 { OUTPUT
, "condbit", & HW_ENT (HW_H_COND
), CGEN_MODE_BI
, 0, 0 },
584 static const CGEN_OPERAND_INSTANCE fmt_addv3_ops
[] = {
585 { INPUT
, "sr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
586 { INPUT
, "simm16", & HW_ENT (HW_H_SINT
), CGEN_MODE_SI
, & OP_ENT (SIMM16
), 0 },
587 { OUTPUT
, "dr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
588 { OUTPUT
, "condbit", & HW_ENT (HW_H_COND
), CGEN_MODE_BI
, 0, 0 },
592 static const CGEN_OPERAND_INSTANCE fmt_addx_ops
[] = {
593 { INPUT
, "dr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
594 { INPUT
, "sr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
595 { INPUT
, "condbit", & HW_ENT (HW_H_COND
), CGEN_MODE_BI
, 0, 0 },
596 { OUTPUT
, "dr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
597 { OUTPUT
, "condbit", & HW_ENT (HW_H_COND
), CGEN_MODE_BI
, 0, 0 },
601 static const CGEN_OPERAND_INSTANCE fmt_bc8_ops
[] = {
602 { INPUT
, "condbit", & HW_ENT (HW_H_COND
), CGEN_MODE_BI
, 0, 0 },
603 { INPUT
, "disp8", & HW_ENT (HW_H_IADDR
), CGEN_MODE_USI
, & OP_ENT (DISP8
), 0 },
604 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
608 static const CGEN_OPERAND_INSTANCE fmt_bc24_ops
[] = {
609 { INPUT
, "condbit", & HW_ENT (HW_H_COND
), CGEN_MODE_BI
, 0, 0 },
610 { INPUT
, "disp24", & HW_ENT (HW_H_IADDR
), CGEN_MODE_USI
, & OP_ENT (DISP24
), 0 },
611 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
615 static const CGEN_OPERAND_INSTANCE fmt_beq_ops
[] = {
616 { INPUT
, "src1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0 },
617 { INPUT
, "src2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0 },
618 { INPUT
, "disp16", & HW_ENT (HW_H_IADDR
), CGEN_MODE_USI
, & OP_ENT (DISP16
), 0 },
619 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
623 static const CGEN_OPERAND_INSTANCE fmt_beqz_ops
[] = {
624 { INPUT
, "src2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0 },
625 { INPUT
, "disp16", & HW_ENT (HW_H_IADDR
), CGEN_MODE_USI
, & OP_ENT (DISP16
), 0 },
626 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
630 static const CGEN_OPERAND_INSTANCE fmt_bl8_ops
[] = {
631 { INPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
632 { INPUT
, "disp8", & HW_ENT (HW_H_IADDR
), CGEN_MODE_USI
, & OP_ENT (DISP8
), 0 },
633 { OUTPUT
, "h_gr_14", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 14 },
634 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
638 static const CGEN_OPERAND_INSTANCE fmt_bl24_ops
[] = {
639 { INPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
640 { INPUT
, "disp24", & HW_ENT (HW_H_IADDR
), CGEN_MODE_USI
, & OP_ENT (DISP24
), 0 },
641 { OUTPUT
, "h_gr_14", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 14 },
642 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
646 /* start-sanitize-m32rx */
647 static const CGEN_OPERAND_INSTANCE fmt_bcl8_ops
[] = {
648 { INPUT
, "condbit", & HW_ENT (HW_H_COND
), CGEN_MODE_BI
, 0, 0 },
649 { INPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
650 { INPUT
, "disp8", & HW_ENT (HW_H_IADDR
), CGEN_MODE_USI
, & OP_ENT (DISP8
), 0 },
651 { OUTPUT
, "h_gr_14", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 14 },
652 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
656 /* end-sanitize-m32rx */
657 /* start-sanitize-m32rx */
658 static const CGEN_OPERAND_INSTANCE fmt_bcl24_ops
[] = {
659 { INPUT
, "condbit", & HW_ENT (HW_H_COND
), CGEN_MODE_BI
, 0, 0 },
660 { INPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
661 { INPUT
, "disp24", & HW_ENT (HW_H_IADDR
), CGEN_MODE_USI
, & OP_ENT (DISP24
), 0 },
662 { OUTPUT
, "h_gr_14", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 14 },
663 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
667 /* end-sanitize-m32rx */
668 static const CGEN_OPERAND_INSTANCE fmt_bra8_ops
[] = {
669 { INPUT
, "disp8", & HW_ENT (HW_H_IADDR
), CGEN_MODE_USI
, & OP_ENT (DISP8
), 0 },
670 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
674 static const CGEN_OPERAND_INSTANCE fmt_bra24_ops
[] = {
675 { INPUT
, "disp24", & HW_ENT (HW_H_IADDR
), CGEN_MODE_USI
, & OP_ENT (DISP24
), 0 },
676 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
680 static const CGEN_OPERAND_INSTANCE fmt_cmp_ops
[] = {
681 { INPUT
, "src1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0 },
682 { INPUT
, "src2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0 },
683 { OUTPUT
, "condbit", & HW_ENT (HW_H_COND
), CGEN_MODE_BI
, 0, 0 },
687 static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops
[] = {
688 { INPUT
, "src2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0 },
689 { INPUT
, "simm16", & HW_ENT (HW_H_SINT
), CGEN_MODE_SI
, & OP_ENT (SIMM16
), 0 },
690 { OUTPUT
, "condbit", & HW_ENT (HW_H_COND
), CGEN_MODE_BI
, 0, 0 },
694 /* start-sanitize-m32rx */
695 static const CGEN_OPERAND_INSTANCE fmt_cmpz_ops
[] = {
696 { INPUT
, "src2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0 },
697 { OUTPUT
, "condbit", & HW_ENT (HW_H_COND
), CGEN_MODE_BI
, 0, 0 },
701 /* end-sanitize-m32rx */
702 static const CGEN_OPERAND_INSTANCE fmt_div_ops
[] = {
703 { INPUT
, "sr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
704 { INPUT
, "dr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
705 { OUTPUT
, "dr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
709 /* start-sanitize-m32rx */
710 static const CGEN_OPERAND_INSTANCE fmt_jc_ops
[] = {
711 { INPUT
, "condbit", & HW_ENT (HW_H_COND
), CGEN_MODE_BI
, 0, 0 },
712 { INPUT
, "sr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
713 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
717 /* end-sanitize-m32rx */
718 static const CGEN_OPERAND_INSTANCE fmt_jl_ops
[] = {
719 { INPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
720 { INPUT
, "sr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
721 { OUTPUT
, "h_gr_14", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 14 },
722 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
726 static const CGEN_OPERAND_INSTANCE fmt_jmp_ops
[] = {
727 { INPUT
, "sr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
728 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
732 static const CGEN_OPERAND_INSTANCE fmt_ld_ops
[] = {
733 { INPUT
, "sr", & HW_ENT (HW_H_GR
), CGEN_MODE_USI
, & OP_ENT (SR
), 0 },
734 { INPUT
, "h_memory_sr", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0 },
735 { OUTPUT
, "dr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
739 static const CGEN_OPERAND_INSTANCE fmt_ld_d_ops
[] = {
740 { INPUT
, "sr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
741 { INPUT
, "slo16", & HW_ENT (HW_H_SLO16
), CGEN_MODE_HI
, & OP_ENT (SLO16
), 0 },
742 { INPUT
, "h_memory_add__VM_sr_slo16", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0 },
743 { OUTPUT
, "dr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
747 static const CGEN_OPERAND_INSTANCE fmt_ldb_ops
[] = {
748 { INPUT
, "sr", & HW_ENT (HW_H_GR
), CGEN_MODE_USI
, & OP_ENT (SR
), 0 },
749 { INPUT
, "h_memory_sr", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0 },
750 { OUTPUT
, "dr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
754 static const CGEN_OPERAND_INSTANCE fmt_ldb_d_ops
[] = {
755 { INPUT
, "sr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
756 { INPUT
, "slo16", & HW_ENT (HW_H_SLO16
), CGEN_MODE_HI
, & OP_ENT (SLO16
), 0 },
757 { INPUT
, "h_memory_add__VM_sr_slo16", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0 },
758 { OUTPUT
, "dr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
762 static const CGEN_OPERAND_INSTANCE fmt_ldh_ops
[] = {
763 { INPUT
, "sr", & HW_ENT (HW_H_GR
), CGEN_MODE_USI
, & OP_ENT (SR
), 0 },
764 { INPUT
, "h_memory_sr", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_HI
, 0, 0 },
765 { OUTPUT
, "dr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
769 static const CGEN_OPERAND_INSTANCE fmt_ldh_d_ops
[] = {
770 { INPUT
, "sr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
771 { INPUT
, "slo16", & HW_ENT (HW_H_SLO16
), CGEN_MODE_HI
, & OP_ENT (SLO16
), 0 },
772 { INPUT
, "h_memory_add__VM_sr_slo16", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_HI
, 0, 0 },
773 { OUTPUT
, "dr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
777 static const CGEN_OPERAND_INSTANCE fmt_ld_plus_ops
[] = {
778 { INPUT
, "sr", & HW_ENT (HW_H_GR
), CGEN_MODE_USI
, & OP_ENT (SR
), 0 },
779 { INPUT
, "h_memory_sr", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0 },
780 { OUTPUT
, "dr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
781 { OUTPUT
, "sr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
785 static const CGEN_OPERAND_INSTANCE fmt_ld24_ops
[] = {
786 { INPUT
, "uimm24", & HW_ENT (HW_H_ADDR
), CGEN_MODE_USI
, & OP_ENT (UIMM24
), 0 },
787 { OUTPUT
, "dr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
791 static const CGEN_OPERAND_INSTANCE fmt_ldi8_ops
[] = {
792 { INPUT
, "simm8", & HW_ENT (HW_H_SINT
), CGEN_MODE_SI
, & OP_ENT (SIMM8
), 0 },
793 { OUTPUT
, "dr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
797 static const CGEN_OPERAND_INSTANCE fmt_ldi16_ops
[] = {
798 { INPUT
, "slo16", & HW_ENT (HW_H_SLO16
), CGEN_MODE_HI
, & OP_ENT (SLO16
), 0 },
799 { OUTPUT
, "dr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
803 static const CGEN_OPERAND_INSTANCE fmt_lock_ops
[] = {
804 { INPUT
, "sr", & HW_ENT (HW_H_GR
), CGEN_MODE_USI
, & OP_ENT (SR
), 0 },
805 { INPUT
, "h_memory_sr", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0 },
806 { OUTPUT
, "h_lock_0", & HW_ENT (HW_H_LOCK
), CGEN_MODE_BI
, 0, 0 },
807 { OUTPUT
, "dr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
811 static const CGEN_OPERAND_INSTANCE fmt_machi_ops
[] = {
812 { INPUT
, "accum", & HW_ENT (HW_H_ACCUM
), CGEN_MODE_DI
, 0, 0 },
813 { INPUT
, "src1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0 },
814 { INPUT
, "src2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0 },
815 { OUTPUT
, "accum", & HW_ENT (HW_H_ACCUM
), CGEN_MODE_DI
, 0, 0 },
819 /* start-sanitize-m32rx */
820 static const CGEN_OPERAND_INSTANCE fmt_machi_a_ops
[] = {
821 { INPUT
, "acc", & HW_ENT (HW_H_ACCUMS
), CGEN_MODE_DI
, & OP_ENT (ACC
), 0 },
822 { INPUT
, "src1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0 },
823 { INPUT
, "src2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0 },
824 { OUTPUT
, "acc", & HW_ENT (HW_H_ACCUMS
), CGEN_MODE_DI
, & OP_ENT (ACC
), 0 },
828 /* end-sanitize-m32rx */
829 static const CGEN_OPERAND_INSTANCE fmt_mulhi_ops
[] = {
830 { INPUT
, "src1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0 },
831 { INPUT
, "src2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0 },
832 { OUTPUT
, "accum", & HW_ENT (HW_H_ACCUM
), CGEN_MODE_DI
, 0, 0 },
836 /* start-sanitize-m32rx */
837 static const CGEN_OPERAND_INSTANCE fmt_mulhi_a_ops
[] = {
838 { INPUT
, "src1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0 },
839 { INPUT
, "src2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0 },
840 { OUTPUT
, "acc", & HW_ENT (HW_H_ACCUMS
), CGEN_MODE_DI
, & OP_ENT (ACC
), 0 },
844 /* end-sanitize-m32rx */
845 static const CGEN_OPERAND_INSTANCE fmt_mv_ops
[] = {
846 { INPUT
, "sr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
847 { OUTPUT
, "dr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
851 static const CGEN_OPERAND_INSTANCE fmt_mvfachi_ops
[] = {
852 { INPUT
, "accum", & HW_ENT (HW_H_ACCUM
), CGEN_MODE_DI
, 0, 0 },
853 { OUTPUT
, "dr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
857 /* start-sanitize-m32rx */
858 static const CGEN_OPERAND_INSTANCE fmt_mvfachi_a_ops
[] = {
859 { INPUT
, "accs", & HW_ENT (HW_H_ACCUMS
), CGEN_MODE_DI
, & OP_ENT (ACCS
), 0 },
860 { OUTPUT
, "dr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
864 /* end-sanitize-m32rx */
865 static const CGEN_OPERAND_INSTANCE fmt_mvfc_ops
[] = {
866 { INPUT
, "scr", & HW_ENT (HW_H_CR
), CGEN_MODE_USI
, & OP_ENT (SCR
), 0 },
867 { OUTPUT
, "dr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
871 static const CGEN_OPERAND_INSTANCE fmt_mvtachi_ops
[] = {
872 { INPUT
, "accum", & HW_ENT (HW_H_ACCUM
), CGEN_MODE_DI
, 0, 0 },
873 { INPUT
, "src1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0 },
874 { OUTPUT
, "accum", & HW_ENT (HW_H_ACCUM
), CGEN_MODE_DI
, 0, 0 },
878 /* start-sanitize-m32rx */
879 static const CGEN_OPERAND_INSTANCE fmt_mvtachi_a_ops
[] = {
880 { INPUT
, "accs", & HW_ENT (HW_H_ACCUMS
), CGEN_MODE_DI
, & OP_ENT (ACCS
), 0 },
881 { INPUT
, "src1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0 },
882 { OUTPUT
, "accs", & HW_ENT (HW_H_ACCUMS
), CGEN_MODE_DI
, & OP_ENT (ACCS
), 0 },
886 /* end-sanitize-m32rx */
887 static const CGEN_OPERAND_INSTANCE fmt_mvtc_ops
[] = {
888 { INPUT
, "sr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
889 { OUTPUT
, "dcr", & HW_ENT (HW_H_CR
), CGEN_MODE_USI
, & OP_ENT (DCR
), 0 },
893 static const CGEN_OPERAND_INSTANCE fmt_rac_ops
[] = {
894 { INPUT
, "accum", & HW_ENT (HW_H_ACCUM
), CGEN_MODE_DI
, 0, 0 },
895 { OUTPUT
, "accum", & HW_ENT (HW_H_ACCUM
), CGEN_MODE_DI
, 0, 0 },
899 /* start-sanitize-m32rx */
900 static const CGEN_OPERAND_INSTANCE fmt_rac_dsi_ops
[] = {
901 { INPUT
, "accs", & HW_ENT (HW_H_ACCUMS
), CGEN_MODE_DI
, & OP_ENT (ACCS
), 0 },
902 { INPUT
, "imm1", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (IMM1
), 0 },
903 { OUTPUT
, "accd", & HW_ENT (HW_H_ACCUMS
), CGEN_MODE_DI
, & OP_ENT (ACCD
), 0 },
907 /* end-sanitize-m32rx */
908 static const CGEN_OPERAND_INSTANCE fmt_rte_ops
[] = {
909 { INPUT
, "h_cr_6", & HW_ENT (HW_H_CR
), CGEN_MODE_USI
, 0, 6 },
910 { INPUT
, "h_cr_14", & HW_ENT (HW_H_CR
), CGEN_MODE_USI
, 0, 14 },
911 { INPUT
, "h_bpsw_0", & HW_ENT (HW_H_BPSW
), CGEN_MODE_UQI
, 0, 0 },
912 { INPUT
, "h_bbpsw_0", & HW_ENT (HW_H_BBPSW
), CGEN_MODE_UQI
, 0, 0 },
913 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
914 { OUTPUT
, "h_cr_6", & HW_ENT (HW_H_CR
), CGEN_MODE_USI
, 0, 6 },
915 { OUTPUT
, "h_psw_0", & HW_ENT (HW_H_PSW
), CGEN_MODE_UQI
, 0, 0 },
916 { OUTPUT
, "h_bpsw_0", & HW_ENT (HW_H_BPSW
), CGEN_MODE_UQI
, 0, 0 },
920 static const CGEN_OPERAND_INSTANCE fmt_seth_ops
[] = {
921 { INPUT
, "hi16", & HW_ENT (HW_H_HI16
), CGEN_MODE_SI
, & OP_ENT (HI16
), 0 },
922 { OUTPUT
, "dr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
926 static const CGEN_OPERAND_INSTANCE fmt_sll3_ops
[] = {
927 { INPUT
, "sr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
928 { INPUT
, "simm16", & HW_ENT (HW_H_SINT
), CGEN_MODE_SI
, & OP_ENT (SIMM16
), 0 },
929 { OUTPUT
, "dr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
933 static const CGEN_OPERAND_INSTANCE fmt_slli_ops
[] = {
934 { INPUT
, "dr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
935 { INPUT
, "uimm5", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (UIMM5
), 0 },
936 { OUTPUT
, "dr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
940 static const CGEN_OPERAND_INSTANCE fmt_st_ops
[] = {
941 { INPUT
, "src2", & HW_ENT (HW_H_GR
), CGEN_MODE_USI
, & OP_ENT (SRC2
), 0 },
942 { INPUT
, "src1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0 },
943 { OUTPUT
, "h_memory_src2", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0 },
947 static const CGEN_OPERAND_INSTANCE fmt_st_d_ops
[] = {
948 { INPUT
, "src2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0 },
949 { INPUT
, "slo16", & HW_ENT (HW_H_SLO16
), CGEN_MODE_HI
, & OP_ENT (SLO16
), 0 },
950 { INPUT
, "src1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0 },
951 { OUTPUT
, "h_memory_add__VM_src2_slo16", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0 },
955 static const CGEN_OPERAND_INSTANCE fmt_stb_ops
[] = {
956 { INPUT
, "src2", & HW_ENT (HW_H_GR
), CGEN_MODE_USI
, & OP_ENT (SRC2
), 0 },
957 { INPUT
, "src1", & HW_ENT (HW_H_GR
), CGEN_MODE_QI
, & OP_ENT (SRC1
), 0 },
958 { OUTPUT
, "h_memory_src2", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0 },
962 static const CGEN_OPERAND_INSTANCE fmt_stb_d_ops
[] = {
963 { INPUT
, "src2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0 },
964 { INPUT
, "slo16", & HW_ENT (HW_H_SLO16
), CGEN_MODE_HI
, & OP_ENT (SLO16
), 0 },
965 { INPUT
, "src1", & HW_ENT (HW_H_GR
), CGEN_MODE_QI
, & OP_ENT (SRC1
), 0 },
966 { OUTPUT
, "h_memory_add__VM_src2_slo16", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0 },
970 static const CGEN_OPERAND_INSTANCE fmt_sth_ops
[] = {
971 { INPUT
, "src2", & HW_ENT (HW_H_GR
), CGEN_MODE_USI
, & OP_ENT (SRC2
), 0 },
972 { INPUT
, "src1", & HW_ENT (HW_H_GR
), CGEN_MODE_HI
, & OP_ENT (SRC1
), 0 },
973 { OUTPUT
, "h_memory_src2", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_HI
, 0, 0 },
977 static const CGEN_OPERAND_INSTANCE fmt_sth_d_ops
[] = {
978 { INPUT
, "src2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0 },
979 { INPUT
, "slo16", & HW_ENT (HW_H_SLO16
), CGEN_MODE_HI
, & OP_ENT (SLO16
), 0 },
980 { INPUT
, "src1", & HW_ENT (HW_H_GR
), CGEN_MODE_HI
, & OP_ENT (SRC1
), 0 },
981 { OUTPUT
, "h_memory_add__VM_src2_slo16", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_HI
, 0, 0 },
985 static const CGEN_OPERAND_INSTANCE fmt_st_plus_ops
[] = {
986 { INPUT
, "src2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0 },
987 { INPUT
, "src1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0 },
988 { OUTPUT
, "h_memory_new_src2", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0 },
989 { OUTPUT
, "src2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0 },
993 static const CGEN_OPERAND_INSTANCE fmt_trap_ops
[] = {
994 { INPUT
, "h_cr_6", & HW_ENT (HW_H_CR
), CGEN_MODE_USI
, 0, 6 },
995 { INPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
996 { INPUT
, "h_bpsw_0", & HW_ENT (HW_H_BPSW
), CGEN_MODE_UQI
, 0, 0 },
997 { INPUT
, "h_psw_0", & HW_ENT (HW_H_PSW
), CGEN_MODE_UQI
, 0, 0 },
998 { INPUT
, "uimm4", & HW_ENT (HW_H_UINT
), CGEN_MODE_SI
, & OP_ENT (UIMM4
), 0 },
999 { OUTPUT
, "h_cr_14", & HW_ENT (HW_H_CR
), CGEN_MODE_USI
, 0, 14 },
1000 { OUTPUT
, "h_cr_6", & HW_ENT (HW_H_CR
), CGEN_MODE_USI
, 0, 6 },
1001 { OUTPUT
, "h_bbpsw_0", & HW_ENT (HW_H_BBPSW
), CGEN_MODE_UQI
, 0, 0 },
1002 { OUTPUT
, "h_bpsw_0", & HW_ENT (HW_H_BPSW
), CGEN_MODE_UQI
, 0, 0 },
1003 { OUTPUT
, "h_psw_0", & HW_ENT (HW_H_PSW
), CGEN_MODE_UQI
, 0, 0 },
1004 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_SI
, 0, 0 },
1008 static const CGEN_OPERAND_INSTANCE fmt_unlock_ops
[] = {
1009 { INPUT
, "h_lock_0", & HW_ENT (HW_H_LOCK
), CGEN_MODE_BI
, 0, 0 },
1010 { INPUT
, "src2", & HW_ENT (HW_H_GR
), CGEN_MODE_USI
, & OP_ENT (SRC2
), 0 },
1011 { INPUT
, "src1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0 },
1012 { OUTPUT
, "h_memory_src2", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0 },
1013 { OUTPUT
, "h_lock_0", & HW_ENT (HW_H_LOCK
), CGEN_MODE_BI
, 0, 0 },
1017 /* start-sanitize-m32rx */
1018 static const CGEN_OPERAND_INSTANCE fmt_satb_ops
[] = {
1019 { INPUT
, "sr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
1020 { OUTPUT
, "dr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
1024 /* end-sanitize-m32rx */
1025 /* start-sanitize-m32rx */
1026 static const CGEN_OPERAND_INSTANCE fmt_sat_ops
[] = {
1027 { INPUT
, "condbit", & HW_ENT (HW_H_COND
), CGEN_MODE_BI
, 0, 0 },
1028 { INPUT
, "sr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
1029 { OUTPUT
, "dr", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
1033 /* end-sanitize-m32rx */
1034 /* start-sanitize-m32rx */
1035 static const CGEN_OPERAND_INSTANCE fmt_sadd_ops
[] = {
1036 { INPUT
, "h_accums_1", & HW_ENT (HW_H_ACCUMS
), CGEN_MODE_DI
, 0, 1 },
1037 { INPUT
, "h_accums_0", & HW_ENT (HW_H_ACCUMS
), CGEN_MODE_DI
, 0, 0 },
1038 { OUTPUT
, "h_accums_0", & HW_ENT (HW_H_ACCUMS
), CGEN_MODE_DI
, 0, 0 },
1042 /* end-sanitize-m32rx */
1043 /* start-sanitize-m32rx */
1044 static const CGEN_OPERAND_INSTANCE fmt_macwu1_ops
[] = {
1045 { INPUT
, "h_accums_1", & HW_ENT (HW_H_ACCUMS
), CGEN_MODE_DI
, 0, 1 },
1046 { INPUT
, "src1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0 },
1047 { INPUT
, "src2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0 },
1048 { OUTPUT
, "h_accums_1", & HW_ENT (HW_H_ACCUMS
), CGEN_MODE_DI
, 0, 1 },
1052 /* end-sanitize-m32rx */
1053 /* start-sanitize-m32rx */
1054 static const CGEN_OPERAND_INSTANCE fmt_mulwu1_ops
[] = {
1055 { INPUT
, "src1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0 },
1056 { INPUT
, "src2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0 },
1057 { OUTPUT
, "h_accums_1", & HW_ENT (HW_H_ACCUMS
), CGEN_MODE_DI
, 0, 1 },
1061 /* end-sanitize-m32rx */
1062 /* start-sanitize-m32rx */
1063 static const CGEN_OPERAND_INSTANCE fmt_sc_ops
[] = {
1064 { INPUT
, "condbit", & HW_ENT (HW_H_COND
), CGEN_MODE_BI
, 0, 0 },
1068 /* end-sanitize-m32rx */
1072 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
1073 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
1074 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
1076 /* The instruction table.
1077 This is currently non-static because the simulator accesses it
1080 const CGEN_INSN m32r_cgen_insn_table_entries
[MAX_INSNS
] =
1082 /* Special null first entry.
1083 A `num' value of zero is thus invalid.
1084 Also, the special `invalid' insn resides here. */
1089 M32R_INSN_ADD
, "add", "add",
1090 { { MNEM
, ' ', OP (DR
), ',', OP (SR
), 0 } },
1091 { 16, 16, 0xf0f0 }, 0xa0,
1092 (PTR
) & fmt_add_ops
[0],
1093 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_OS
} }
1095 /* add3 $dr,$sr,$hash$slo16 */
1098 M32R_INSN_ADD3
, "add3", "add3",
1099 { { MNEM
, ' ', OP (DR
), ',', OP (SR
), ',', OP (HASH
), OP (SLO16
), 0 } },
1100 { 32, 32, 0xf0f00000 }, 0x80a00000,
1101 (PTR
) & fmt_add3_ops
[0],
1102 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_NONE
} }
1107 M32R_INSN_AND
, "and", "and",
1108 { { MNEM
, ' ', OP (DR
), ',', OP (SR
), 0 } },
1109 { 16, 16, 0xf0f0 }, 0xc0,
1110 (PTR
) & fmt_add_ops
[0],
1111 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_OS
} }
1113 /* and3 $dr,$sr,$uimm16 */
1116 M32R_INSN_AND3
, "and3", "and3",
1117 { { MNEM
, ' ', OP (DR
), ',', OP (SR
), ',', OP (UIMM16
), 0 } },
1118 { 32, 32, 0xf0f00000 }, 0x80c00000,
1119 (PTR
) & fmt_and3_ops
[0],
1120 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_NONE
} }
1125 M32R_INSN_OR
, "or", "or",
1126 { { MNEM
, ' ', OP (DR
), ',', OP (SR
), 0 } },
1127 { 16, 16, 0xf0f0 }, 0xe0,
1128 (PTR
) & fmt_add_ops
[0],
1129 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_OS
} }
1131 /* or3 $dr,$sr,$hash$ulo16 */
1134 M32R_INSN_OR3
, "or3", "or3",
1135 { { MNEM
, ' ', OP (DR
), ',', OP (SR
), ',', OP (HASH
), OP (ULO16
), 0 } },
1136 { 32, 32, 0xf0f00000 }, 0x80e00000,
1137 (PTR
) & fmt_or3_ops
[0],
1138 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_NONE
} }
1143 M32R_INSN_XOR
, "xor", "xor",
1144 { { MNEM
, ' ', OP (DR
), ',', OP (SR
), 0 } },
1145 { 16, 16, 0xf0f0 }, 0xd0,
1146 (PTR
) & fmt_add_ops
[0],
1147 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_OS
} }
1149 /* xor3 $dr,$sr,$uimm16 */
1152 M32R_INSN_XOR3
, "xor3", "xor3",
1153 { { MNEM
, ' ', OP (DR
), ',', OP (SR
), ',', OP (UIMM16
), 0 } },
1154 { 32, 32, 0xf0f00000 }, 0x80d00000,
1155 (PTR
) & fmt_and3_ops
[0],
1156 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_NONE
} }
1158 /* addi $dr,$simm8 */
1161 M32R_INSN_ADDI
, "addi", "addi",
1162 { { MNEM
, ' ', OP (DR
), ',', OP (SIMM8
), 0 } },
1163 { 16, 16, 0xf000 }, 0x4000,
1164 (PTR
) & fmt_addi_ops
[0],
1165 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_OS
} }
1170 M32R_INSN_ADDV
, "addv", "addv",
1171 { { MNEM
, ' ', OP (DR
), ',', OP (SR
), 0 } },
1172 { 16, 16, 0xf0f0 }, 0x80,
1173 (PTR
) & fmt_addv_ops
[0],
1174 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_OS
} }
1176 /* addv3 $dr,$sr,$simm16 */
1179 M32R_INSN_ADDV3
, "addv3", "addv3",
1180 { { MNEM
, ' ', OP (DR
), ',', OP (SR
), ',', OP (SIMM16
), 0 } },
1181 { 32, 32, 0xf0f00000 }, 0x80800000,
1182 (PTR
) & fmt_addv3_ops
[0],
1183 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_NONE
} }
1188 M32R_INSN_ADDX
, "addx", "addx",
1189 { { MNEM
, ' ', OP (DR
), ',', OP (SR
), 0 } },
1190 { 16, 16, 0xf0f0 }, 0x90,
1191 (PTR
) & fmt_addx_ops
[0],
1192 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_OS
} }
1197 M32R_INSN_BC8
, "bc8", "bc.s",
1198 { { MNEM
, ' ', OP (DISP8
), 0 } },
1199 { 16, 16, 0xff00 }, 0x7c00,
1200 (PTR
) & fmt_bc8_ops
[0],
1201 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
), PIPE_O
} }
1206 M32R_INSN_BC24
, "bc24", "bc.l",
1207 { { MNEM
, ' ', OP (DISP24
), 0 } },
1208 { 32, 32, 0xff000000 }, 0xfc000000,
1209 (PTR
) & fmt_bc24_ops
[0],
1210 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
), PIPE_NONE
} }
1212 /* beq $src1,$src2,$disp16 */
1215 M32R_INSN_BEQ
, "beq", "beq",
1216 { { MNEM
, ' ', OP (SRC1
), ',', OP (SRC2
), ',', OP (DISP16
), 0 } },
1217 { 32, 32, 0xf0f00000 }, 0xb0000000,
1218 (PTR
) & fmt_beq_ops
[0],
1219 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
), PIPE_NONE
} }
1221 /* beqz $src2,$disp16 */
1224 M32R_INSN_BEQZ
, "beqz", "beqz",
1225 { { MNEM
, ' ', OP (SRC2
), ',', OP (DISP16
), 0 } },
1226 { 32, 32, 0xfff00000 }, 0xb0800000,
1227 (PTR
) & fmt_beqz_ops
[0],
1228 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
), PIPE_NONE
} }
1230 /* bgez $src2,$disp16 */
1233 M32R_INSN_BGEZ
, "bgez", "bgez",
1234 { { MNEM
, ' ', OP (SRC2
), ',', OP (DISP16
), 0 } },
1235 { 32, 32, 0xfff00000 }, 0xb0b00000,
1236 (PTR
) & fmt_beqz_ops
[0],
1237 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
), PIPE_NONE
} }
1239 /* bgtz $src2,$disp16 */
1242 M32R_INSN_BGTZ
, "bgtz", "bgtz",
1243 { { MNEM
, ' ', OP (SRC2
), ',', OP (DISP16
), 0 } },
1244 { 32, 32, 0xfff00000 }, 0xb0d00000,
1245 (PTR
) & fmt_beqz_ops
[0],
1246 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
), PIPE_NONE
} }
1248 /* blez $src2,$disp16 */
1251 M32R_INSN_BLEZ
, "blez", "blez",
1252 { { MNEM
, ' ', OP (SRC2
), ',', OP (DISP16
), 0 } },
1253 { 32, 32, 0xfff00000 }, 0xb0c00000,
1254 (PTR
) & fmt_beqz_ops
[0],
1255 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
), PIPE_NONE
} }
1257 /* bltz $src2,$disp16 */
1260 M32R_INSN_BLTZ
, "bltz", "bltz",
1261 { { MNEM
, ' ', OP (SRC2
), ',', OP (DISP16
), 0 } },
1262 { 32, 32, 0xfff00000 }, 0xb0a00000,
1263 (PTR
) & fmt_beqz_ops
[0],
1264 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
), PIPE_NONE
} }
1266 /* bnez $src2,$disp16 */
1269 M32R_INSN_BNEZ
, "bnez", "bnez",
1270 { { MNEM
, ' ', OP (SRC2
), ',', OP (DISP16
), 0 } },
1271 { 32, 32, 0xfff00000 }, 0xb0900000,
1272 (PTR
) & fmt_beqz_ops
[0],
1273 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
), PIPE_NONE
} }
1278 M32R_INSN_BL8
, "bl8", "bl.s",
1279 { { MNEM
, ' ', OP (DISP8
), 0 } },
1280 { 16, 16, 0xff00 }, 0x7e00,
1281 (PTR
) & fmt_bl8_ops
[0],
1282 { CGEN_INSN_NBOOL_ATTRS
, 0|A(FILL_SLOT
)|A(UNCOND_CTI
), { (1<<MACH_BASE
), PIPE_O
} }
1287 M32R_INSN_BL24
, "bl24", "bl.l",
1288 { { MNEM
, ' ', OP (DISP24
), 0 } },
1289 { 32, 32, 0xff000000 }, 0xfe000000,
1290 (PTR
) & fmt_bl24_ops
[0],
1291 { CGEN_INSN_NBOOL_ATTRS
, 0|A(UNCOND_CTI
), { (1<<MACH_BASE
), PIPE_NONE
} }
1293 /* start-sanitize-m32rx */
1297 M32R_INSN_BCL8
, "bcl8", "bcl.s",
1298 { { MNEM
, ' ', OP (DISP8
), 0 } },
1299 { 16, 16, 0xff00 }, 0x7800,
1300 (PTR
) & fmt_bcl8_ops
[0],
1301 { CGEN_INSN_NBOOL_ATTRS
, 0|A(FILL_SLOT
)|A(COND_CTI
), { (1<<MACH_M32RX
), PIPE_O
} }
1303 /* end-sanitize-m32rx */
1304 /* start-sanitize-m32rx */
1308 M32R_INSN_BCL24
, "bcl24", "bcl.l",
1309 { { MNEM
, ' ', OP (DISP24
), 0 } },
1310 { 32, 32, 0xff000000 }, 0xf8000000,
1311 (PTR
) & fmt_bcl24_ops
[0],
1312 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_M32RX
), PIPE_NONE
} }
1314 /* end-sanitize-m32rx */
1318 M32R_INSN_BNC8
, "bnc8", "bnc.s",
1319 { { MNEM
, ' ', OP (DISP8
), 0 } },
1320 { 16, 16, 0xff00 }, 0x7d00,
1321 (PTR
) & fmt_bc8_ops
[0],
1322 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
), PIPE_O
} }
1327 M32R_INSN_BNC24
, "bnc24", "bnc.l",
1328 { { MNEM
, ' ', OP (DISP24
), 0 } },
1329 { 32, 32, 0xff000000 }, 0xfd000000,
1330 (PTR
) & fmt_bc24_ops
[0],
1331 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
), PIPE_NONE
} }
1333 /* bne $src1,$src2,$disp16 */
1336 M32R_INSN_BNE
, "bne", "bne",
1337 { { MNEM
, ' ', OP (SRC1
), ',', OP (SRC2
), ',', OP (DISP16
), 0 } },
1338 { 32, 32, 0xf0f00000 }, 0xb0100000,
1339 (PTR
) & fmt_beq_ops
[0],
1340 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_BASE
), PIPE_NONE
} }
1345 M32R_INSN_BRA8
, "bra8", "bra.s",
1346 { { MNEM
, ' ', OP (DISP8
), 0 } },
1347 { 16, 16, 0xff00 }, 0x7f00,
1348 (PTR
) & fmt_bra8_ops
[0],
1349 { CGEN_INSN_NBOOL_ATTRS
, 0|A(FILL_SLOT
)|A(UNCOND_CTI
), { (1<<MACH_BASE
), PIPE_O
} }
1354 M32R_INSN_BRA24
, "bra24", "bra.l",
1355 { { MNEM
, ' ', OP (DISP24
), 0 } },
1356 { 32, 32, 0xff000000 }, 0xff000000,
1357 (PTR
) & fmt_bra24_ops
[0],
1358 { CGEN_INSN_NBOOL_ATTRS
, 0|A(UNCOND_CTI
), { (1<<MACH_BASE
), PIPE_NONE
} }
1360 /* start-sanitize-m32rx */
1364 M32R_INSN_BNCL8
, "bncl8", "bncl.s",
1365 { { MNEM
, ' ', OP (DISP8
), 0 } },
1366 { 16, 16, 0xff00 }, 0x7900,
1367 (PTR
) & fmt_bcl8_ops
[0],
1368 { CGEN_INSN_NBOOL_ATTRS
, 0|A(FILL_SLOT
)|A(COND_CTI
), { (1<<MACH_M32RX
), PIPE_O
} }
1370 /* end-sanitize-m32rx */
1371 /* start-sanitize-m32rx */
1372 /* bncl.l $disp24 */
1375 M32R_INSN_BNCL24
, "bncl24", "bncl.l",
1376 { { MNEM
, ' ', OP (DISP24
), 0 } },
1377 { 32, 32, 0xff000000 }, 0xf9000000,
1378 (PTR
) & fmt_bcl24_ops
[0],
1379 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_M32RX
), PIPE_NONE
} }
1381 /* end-sanitize-m32rx */
1382 /* cmp $src1,$src2 */
1385 M32R_INSN_CMP
, "cmp", "cmp",
1386 { { MNEM
, ' ', OP (SRC1
), ',', OP (SRC2
), 0 } },
1387 { 16, 16, 0xf0f0 }, 0x40,
1388 (PTR
) & fmt_cmp_ops
[0],
1389 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_OS
} }
1391 /* cmpi $src2,$simm16 */
1394 M32R_INSN_CMPI
, "cmpi", "cmpi",
1395 { { MNEM
, ' ', OP (SRC2
), ',', OP (SIMM16
), 0 } },
1396 { 32, 32, 0xfff00000 }, 0x80400000,
1397 (PTR
) & fmt_cmpi_ops
[0],
1398 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_NONE
} }
1400 /* cmpu $src1,$src2 */
1403 M32R_INSN_CMPU
, "cmpu", "cmpu",
1404 { { MNEM
, ' ', OP (SRC1
), ',', OP (SRC2
), 0 } },
1405 { 16, 16, 0xf0f0 }, 0x50,
1406 (PTR
) & fmt_cmp_ops
[0],
1407 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_OS
} }
1409 /* cmpui $src2,$simm16 */
1412 M32R_INSN_CMPUI
, "cmpui", "cmpui",
1413 { { MNEM
, ' ', OP (SRC2
), ',', OP (SIMM16
), 0 } },
1414 { 32, 32, 0xfff00000 }, 0x80500000,
1415 (PTR
) & fmt_cmpi_ops
[0],
1416 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_NONE
} }
1418 /* start-sanitize-m32rx */
1419 /* cmpeq $src1,$src2 */
1422 M32R_INSN_CMPEQ
, "cmpeq", "cmpeq",
1423 { { MNEM
, ' ', OP (SRC1
), ',', OP (SRC2
), 0 } },
1424 { 16, 16, 0xf0f0 }, 0x60,
1425 (PTR
) & fmt_cmp_ops
[0],
1426 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_OS
} }
1428 /* end-sanitize-m32rx */
1429 /* start-sanitize-m32rx */
1433 M32R_INSN_CMPZ
, "cmpz", "cmpz",
1434 { { MNEM
, ' ', OP (SRC2
), 0 } },
1435 { 16, 16, 0xfff0 }, 0x70,
1436 (PTR
) & fmt_cmpz_ops
[0],
1437 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_OS
} }
1439 /* end-sanitize-m32rx */
1443 M32R_INSN_DIV
, "div", "div",
1444 { { MNEM
, ' ', OP (DR
), ',', OP (SR
), 0 } },
1445 { 32, 32, 0xf0f0ffff }, 0x90000000,
1446 (PTR
) & fmt_div_ops
[0],
1447 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_NONE
} }
1452 M32R_INSN_DIVU
, "divu", "divu",
1453 { { MNEM
, ' ', OP (DR
), ',', OP (SR
), 0 } },
1454 { 32, 32, 0xf0f0ffff }, 0x90100000,
1455 (PTR
) & fmt_div_ops
[0],
1456 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_NONE
} }
1461 M32R_INSN_REM
, "rem", "rem",
1462 { { MNEM
, ' ', OP (DR
), ',', OP (SR
), 0 } },
1463 { 32, 32, 0xf0f0ffff }, 0x90200000,
1464 (PTR
) & fmt_div_ops
[0],
1465 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_NONE
} }
1470 M32R_INSN_REMU
, "remu", "remu",
1471 { { MNEM
, ' ', OP (DR
), ',', OP (SR
), 0 } },
1472 { 32, 32, 0xf0f0ffff }, 0x90300000,
1473 (PTR
) & fmt_div_ops
[0],
1474 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_NONE
} }
1476 /* start-sanitize-m32rx */
1480 M32R_INSN_DIVH
, "divh", "divh",
1481 { { MNEM
, ' ', OP (DR
), ',', OP (SR
), 0 } },
1482 { 32, 32, 0xf0f0ffff }, 0x90000010,
1483 (PTR
) & fmt_div_ops
[0],
1484 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_NONE
} }
1486 /* end-sanitize-m32rx */
1487 /* start-sanitize-m32rx */
1491 M32R_INSN_JC
, "jc", "jc",
1492 { { MNEM
, ' ', OP (SR
), 0 } },
1493 { 16, 16, 0xfff0 }, 0x1cc0,
1494 (PTR
) & fmt_jc_ops
[0],
1495 { CGEN_INSN_NBOOL_ATTRS
, 0|A(SPECIAL
)|A(COND_CTI
), { (1<<MACH_M32RX
), PIPE_O
} }
1497 /* end-sanitize-m32rx */
1498 /* start-sanitize-m32rx */
1502 M32R_INSN_JNC
, "jnc", "jnc",
1503 { { MNEM
, ' ', OP (SR
), 0 } },
1504 { 16, 16, 0xfff0 }, 0x1dc0,
1505 (PTR
) & fmt_jc_ops
[0],
1506 { CGEN_INSN_NBOOL_ATTRS
, 0|A(SPECIAL
)|A(COND_CTI
), { (1<<MACH_M32RX
), PIPE_O
} }
1508 /* end-sanitize-m32rx */
1512 M32R_INSN_JL
, "jl", "jl",
1513 { { MNEM
, ' ', OP (SR
), 0 } },
1514 { 16, 16, 0xfff0 }, 0x1ec0,
1515 (PTR
) & fmt_jl_ops
[0],
1516 { CGEN_INSN_NBOOL_ATTRS
, 0|A(FILL_SLOT
)|A(UNCOND_CTI
), { (1<<MACH_BASE
), PIPE_O
} }
1521 M32R_INSN_JMP
, "jmp", "jmp",
1522 { { MNEM
, ' ', OP (SR
), 0 } },
1523 { 16, 16, 0xfff0 }, 0x1fc0,
1524 (PTR
) & fmt_jmp_ops
[0],
1525 { CGEN_INSN_NBOOL_ATTRS
, 0|A(UNCOND_CTI
), { (1<<MACH_BASE
), PIPE_O
} }
1530 M32R_INSN_LD
, "ld", "ld",
1531 { { MNEM
, ' ', OP (DR
), ',', '@', OP (SR
), 0 } },
1532 { 16, 16, 0xf0f0 }, 0x20c0,
1533 (PTR
) & fmt_ld_ops
[0],
1534 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_O
} }
1536 /* ld $dr,@($slo16,$sr) */
1539 M32R_INSN_LD_D
, "ld-d", "ld",
1540 { { MNEM
, ' ', OP (DR
), ',', '@', '(', OP (SLO16
), ',', OP (SR
), ')', 0 } },
1541 { 32, 32, 0xf0f00000 }, 0xa0c00000,
1542 (PTR
) & fmt_ld_d_ops
[0],
1543 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_NONE
} }
1548 M32R_INSN_LDB
, "ldb", "ldb",
1549 { { MNEM
, ' ', OP (DR
), ',', '@', OP (SR
), 0 } },
1550 { 16, 16, 0xf0f0 }, 0x2080,
1551 (PTR
) & fmt_ldb_ops
[0],
1552 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_O
} }
1554 /* ldb $dr,@($slo16,$sr) */
1557 M32R_INSN_LDB_D
, "ldb-d", "ldb",
1558 { { MNEM
, ' ', OP (DR
), ',', '@', '(', OP (SLO16
), ',', OP (SR
), ')', 0 } },
1559 { 32, 32, 0xf0f00000 }, 0xa0800000,
1560 (PTR
) & fmt_ldb_d_ops
[0],
1561 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_NONE
} }
1566 M32R_INSN_LDH
, "ldh", "ldh",
1567 { { MNEM
, ' ', OP (DR
), ',', '@', OP (SR
), 0 } },
1568 { 16, 16, 0xf0f0 }, 0x20a0,
1569 (PTR
) & fmt_ldh_ops
[0],
1570 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_O
} }
1572 /* ldh $dr,@($slo16,$sr) */
1575 M32R_INSN_LDH_D
, "ldh-d", "ldh",
1576 { { MNEM
, ' ', OP (DR
), ',', '@', '(', OP (SLO16
), ',', OP (SR
), ')', 0 } },
1577 { 32, 32, 0xf0f00000 }, 0xa0a00000,
1578 (PTR
) & fmt_ldh_d_ops
[0],
1579 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_NONE
} }
1584 M32R_INSN_LDUB
, "ldub", "ldub",
1585 { { MNEM
, ' ', OP (DR
), ',', '@', OP (SR
), 0 } },
1586 { 16, 16, 0xf0f0 }, 0x2090,
1587 (PTR
) & fmt_ldb_ops
[0],
1588 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_O
} }
1590 /* ldub $dr,@($slo16,$sr) */
1593 M32R_INSN_LDUB_D
, "ldub-d", "ldub",
1594 { { MNEM
, ' ', OP (DR
), ',', '@', '(', OP (SLO16
), ',', OP (SR
), ')', 0 } },
1595 { 32, 32, 0xf0f00000 }, 0xa0900000,
1596 (PTR
) & fmt_ldb_d_ops
[0],
1597 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_NONE
} }
1602 M32R_INSN_LDUH
, "lduh", "lduh",
1603 { { MNEM
, ' ', OP (DR
), ',', '@', OP (SR
), 0 } },
1604 { 16, 16, 0xf0f0 }, 0x20b0,
1605 (PTR
) & fmt_ldh_ops
[0],
1606 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_O
} }
1608 /* lduh $dr,@($slo16,$sr) */
1611 M32R_INSN_LDUH_D
, "lduh-d", "lduh",
1612 { { MNEM
, ' ', OP (DR
), ',', '@', '(', OP (SLO16
), ',', OP (SR
), ')', 0 } },
1613 { 32, 32, 0xf0f00000 }, 0xa0b00000,
1614 (PTR
) & fmt_ldh_d_ops
[0],
1615 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_NONE
} }
1620 M32R_INSN_LD_PLUS
, "ld-plus", "ld",
1621 { { MNEM
, ' ', OP (DR
), ',', '@', OP (SR
), '+', 0 } },
1622 { 16, 16, 0xf0f0 }, 0x20e0,
1623 (PTR
) & fmt_ld_plus_ops
[0],
1624 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_O
} }
1626 /* ld24 $dr,$uimm24 */
1629 M32R_INSN_LD24
, "ld24", "ld24",
1630 { { MNEM
, ' ', OP (DR
), ',', OP (UIMM24
), 0 } },
1631 { 32, 32, 0xf0000000 }, 0xe0000000,
1632 (PTR
) & fmt_ld24_ops
[0],
1633 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_NONE
} }
1635 /* ldi8 $dr,$simm8 */
1638 M32R_INSN_LDI8
, "ldi8", "ldi8",
1639 { { MNEM
, ' ', OP (DR
), ',', OP (SIMM8
), 0 } },
1640 { 16, 16, 0xf000 }, 0x6000,
1641 (PTR
) & fmt_ldi8_ops
[0],
1642 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_OS
} }
1644 /* ldi16 $dr,$hash$slo16 */
1647 M32R_INSN_LDI16
, "ldi16", "ldi16",
1648 { { MNEM
, ' ', OP (DR
), ',', OP (HASH
), OP (SLO16
), 0 } },
1649 { 32, 32, 0xf0ff0000 }, 0x90f00000,
1650 (PTR
) & fmt_ldi16_ops
[0],
1651 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_NONE
} }
1656 M32R_INSN_LOCK
, "lock", "lock",
1657 { { MNEM
, ' ', OP (DR
), ',', '@', OP (SR
), 0 } },
1658 { 16, 16, 0xf0f0 }, 0x20d0,
1659 (PTR
) & fmt_lock_ops
[0],
1660 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_O
} }
1662 /* machi $src1,$src2 */
1665 M32R_INSN_MACHI
, "machi", "machi",
1666 { { MNEM
, ' ', OP (SRC1
), ',', OP (SRC2
), 0 } },
1667 { 16, 16, 0xf0f0 }, 0x3040,
1668 (PTR
) & fmt_machi_ops
[0],
1669 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_S
} }
1671 /* start-sanitize-m32rx */
1672 /* machi $src1,$src2,$acc */
1675 M32R_INSN_MACHI_A
, "machi-a", "machi",
1676 { { MNEM
, ' ', OP (SRC1
), ',', OP (SRC2
), ',', OP (ACC
), 0 } },
1677 { 16, 16, 0xf070 }, 0x3040,
1678 (PTR
) & fmt_machi_a_ops
[0],
1679 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_S
} }
1681 /* end-sanitize-m32rx */
1682 /* maclo $src1,$src2 */
1685 M32R_INSN_MACLO
, "maclo", "maclo",
1686 { { MNEM
, ' ', OP (SRC1
), ',', OP (SRC2
), 0 } },
1687 { 16, 16, 0xf0f0 }, 0x3050,
1688 (PTR
) & fmt_machi_ops
[0],
1689 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_S
} }
1691 /* start-sanitize-m32rx */
1692 /* maclo $src1,$src2,$acc */
1695 M32R_INSN_MACLO_A
, "maclo-a", "maclo",
1696 { { MNEM
, ' ', OP (SRC1
), ',', OP (SRC2
), ',', OP (ACC
), 0 } },
1697 { 16, 16, 0xf070 }, 0x3050,
1698 (PTR
) & fmt_machi_a_ops
[0],
1699 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_S
} }
1701 /* end-sanitize-m32rx */
1702 /* macwhi $src1,$src2 */
1705 M32R_INSN_MACWHI
, "macwhi", "macwhi",
1706 { { MNEM
, ' ', OP (SRC1
), ',', OP (SRC2
), 0 } },
1707 { 16, 16, 0xf0f0 }, 0x3060,
1708 (PTR
) & fmt_machi_ops
[0],
1709 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_S
} }
1711 /* start-sanitize-m32rx */
1712 /* macwhi $src1,$src2,$acc */
1715 M32R_INSN_MACWHI_A
, "macwhi-a", "macwhi",
1716 { { MNEM
, ' ', OP (SRC1
), ',', OP (SRC2
), ',', OP (ACC
), 0 } },
1717 { 16, 16, 0xf070 }, 0x3060,
1718 (PTR
) & fmt_machi_a_ops
[0],
1719 { CGEN_INSN_NBOOL_ATTRS
, 0|A(SPECIAL
), { (1<<MACH_M32RX
), PIPE_S
} }
1721 /* end-sanitize-m32rx */
1722 /* macwlo $src1,$src2 */
1725 M32R_INSN_MACWLO
, "macwlo", "macwlo",
1726 { { MNEM
, ' ', OP (SRC1
), ',', OP (SRC2
), 0 } },
1727 { 16, 16, 0xf0f0 }, 0x3070,
1728 (PTR
) & fmt_machi_ops
[0],
1729 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_S
} }
1731 /* start-sanitize-m32rx */
1732 /* macwlo $src1,$src2,$acc */
1735 M32R_INSN_MACWLO_A
, "macwlo-a", "macwlo",
1736 { { MNEM
, ' ', OP (SRC1
), ',', OP (SRC2
), ',', OP (ACC
), 0 } },
1737 { 16, 16, 0xf070 }, 0x3070,
1738 (PTR
) & fmt_machi_a_ops
[0],
1739 { CGEN_INSN_NBOOL_ATTRS
, 0|A(SPECIAL
), { (1<<MACH_M32RX
), PIPE_S
} }
1741 /* end-sanitize-m32rx */
1745 M32R_INSN_MUL
, "mul", "mul",
1746 { { MNEM
, ' ', OP (DR
), ',', OP (SR
), 0 } },
1747 { 16, 16, 0xf0f0 }, 0x1060,
1748 (PTR
) & fmt_add_ops
[0],
1749 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_S
} }
1751 /* mulhi $src1,$src2 */
1754 M32R_INSN_MULHI
, "mulhi", "mulhi",
1755 { { MNEM
, ' ', OP (SRC1
), ',', OP (SRC2
), 0 } },
1756 { 16, 16, 0xf0f0 }, 0x3000,
1757 (PTR
) & fmt_mulhi_ops
[0],
1758 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_S
} }
1760 /* start-sanitize-m32rx */
1761 /* mulhi $src1,$src2,$acc */
1764 M32R_INSN_MULHI_A
, "mulhi-a", "mulhi",
1765 { { MNEM
, ' ', OP (SRC1
), ',', OP (SRC2
), ',', OP (ACC
), 0 } },
1766 { 16, 16, 0xf070 }, 0x3000,
1767 (PTR
) & fmt_mulhi_a_ops
[0],
1768 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_S
} }
1770 /* end-sanitize-m32rx */
1771 /* mullo $src1,$src2 */
1774 M32R_INSN_MULLO
, "mullo", "mullo",
1775 { { MNEM
, ' ', OP (SRC1
), ',', OP (SRC2
), 0 } },
1776 { 16, 16, 0xf0f0 }, 0x3010,
1777 (PTR
) & fmt_mulhi_ops
[0],
1778 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_S
} }
1780 /* start-sanitize-m32rx */
1781 /* mullo $src1,$src2,$acc */
1784 M32R_INSN_MULLO_A
, "mullo-a", "mullo",
1785 { { MNEM
, ' ', OP (SRC1
), ',', OP (SRC2
), ',', OP (ACC
), 0 } },
1786 { 16, 16, 0xf070 }, 0x3010,
1787 (PTR
) & fmt_mulhi_a_ops
[0],
1788 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_S
} }
1790 /* end-sanitize-m32rx */
1791 /* mulwhi $src1,$src2 */
1794 M32R_INSN_MULWHI
, "mulwhi", "mulwhi",
1795 { { MNEM
, ' ', OP (SRC1
), ',', OP (SRC2
), 0 } },
1796 { 16, 16, 0xf0f0 }, 0x3020,
1797 (PTR
) & fmt_mulhi_ops
[0],
1798 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_S
} }
1800 /* start-sanitize-m32rx */
1801 /* mulwhi $src1,$src2,$acc */
1804 M32R_INSN_MULWHI_A
, "mulwhi-a", "mulwhi",
1805 { { MNEM
, ' ', OP (SRC1
), ',', OP (SRC2
), ',', OP (ACC
), 0 } },
1806 { 16, 16, 0xf070 }, 0x3020,
1807 (PTR
) & fmt_mulhi_a_ops
[0],
1808 { CGEN_INSN_NBOOL_ATTRS
, 0|A(SPECIAL
), { (1<<MACH_M32RX
), PIPE_S
} }
1810 /* end-sanitize-m32rx */
1811 /* mulwlo $src1,$src2 */
1814 M32R_INSN_MULWLO
, "mulwlo", "mulwlo",
1815 { { MNEM
, ' ', OP (SRC1
), ',', OP (SRC2
), 0 } },
1816 { 16, 16, 0xf0f0 }, 0x3030,
1817 (PTR
) & fmt_mulhi_ops
[0],
1818 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_S
} }
1820 /* start-sanitize-m32rx */
1821 /* mulwlo $src1,$src2,$acc */
1824 M32R_INSN_MULWLO_A
, "mulwlo-a", "mulwlo",
1825 { { MNEM
, ' ', OP (SRC1
), ',', OP (SRC2
), ',', OP (ACC
), 0 } },
1826 { 16, 16, 0xf070 }, 0x3030,
1827 (PTR
) & fmt_mulhi_a_ops
[0],
1828 { CGEN_INSN_NBOOL_ATTRS
, 0|A(SPECIAL
), { (1<<MACH_M32RX
), PIPE_S
} }
1830 /* end-sanitize-m32rx */
1834 M32R_INSN_MV
, "mv", "mv",
1835 { { MNEM
, ' ', OP (DR
), ',', OP (SR
), 0 } },
1836 { 16, 16, 0xf0f0 }, 0x1080,
1837 (PTR
) & fmt_mv_ops
[0],
1838 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_OS
} }
1843 M32R_INSN_MVFACHI
, "mvfachi", "mvfachi",
1844 { { MNEM
, ' ', OP (DR
), 0 } },
1845 { 16, 16, 0xf0ff }, 0x50f0,
1846 (PTR
) & fmt_mvfachi_ops
[0],
1847 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_S
} }
1849 /* start-sanitize-m32rx */
1850 /* mvfachi $dr,$accs */
1853 M32R_INSN_MVFACHI_A
, "mvfachi-a", "mvfachi",
1854 { { MNEM
, ' ', OP (DR
), ',', OP (ACCS
), 0 } },
1855 { 16, 16, 0xf0f3 }, 0x50f0,
1856 (PTR
) & fmt_mvfachi_a_ops
[0],
1857 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_S
} }
1859 /* end-sanitize-m32rx */
1863 M32R_INSN_MVFACLO
, "mvfaclo", "mvfaclo",
1864 { { MNEM
, ' ', OP (DR
), 0 } },
1865 { 16, 16, 0xf0ff }, 0x50f1,
1866 (PTR
) & fmt_mvfachi_ops
[0],
1867 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_S
} }
1869 /* start-sanitize-m32rx */
1870 /* mvfaclo $dr,$accs */
1873 M32R_INSN_MVFACLO_A
, "mvfaclo-a", "mvfaclo",
1874 { { MNEM
, ' ', OP (DR
), ',', OP (ACCS
), 0 } },
1875 { 16, 16, 0xf0f3 }, 0x50f1,
1876 (PTR
) & fmt_mvfachi_a_ops
[0],
1877 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_S
} }
1879 /* end-sanitize-m32rx */
1883 M32R_INSN_MVFACMI
, "mvfacmi", "mvfacmi",
1884 { { MNEM
, ' ', OP (DR
), 0 } },
1885 { 16, 16, 0xf0ff }, 0x50f2,
1886 (PTR
) & fmt_mvfachi_ops
[0],
1887 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_S
} }
1889 /* start-sanitize-m32rx */
1890 /* mvfacmi $dr,$accs */
1893 M32R_INSN_MVFACMI_A
, "mvfacmi-a", "mvfacmi",
1894 { { MNEM
, ' ', OP (DR
), ',', OP (ACCS
), 0 } },
1895 { 16, 16, 0xf0f3 }, 0x50f2,
1896 (PTR
) & fmt_mvfachi_a_ops
[0],
1897 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_S
} }
1899 /* end-sanitize-m32rx */
1903 M32R_INSN_MVFC
, "mvfc", "mvfc",
1904 { { MNEM
, ' ', OP (DR
), ',', OP (SCR
), 0 } },
1905 { 16, 16, 0xf0f0 }, 0x1090,
1906 (PTR
) & fmt_mvfc_ops
[0],
1907 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_O
} }
1912 M32R_INSN_MVTACHI
, "mvtachi", "mvtachi",
1913 { { MNEM
, ' ', OP (SRC1
), 0 } },
1914 { 16, 16, 0xf0ff }, 0x5070,
1915 (PTR
) & fmt_mvtachi_ops
[0],
1916 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_S
} }
1918 /* start-sanitize-m32rx */
1919 /* mvtachi $src1,$accs */
1922 M32R_INSN_MVTACHI_A
, "mvtachi-a", "mvtachi",
1923 { { MNEM
, ' ', OP (SRC1
), ',', OP (ACCS
), 0 } },
1924 { 16, 16, 0xf0f3 }, 0x5070,
1925 (PTR
) & fmt_mvtachi_a_ops
[0],
1926 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_S
} }
1928 /* end-sanitize-m32rx */
1932 M32R_INSN_MVTACLO
, "mvtaclo", "mvtaclo",
1933 { { MNEM
, ' ', OP (SRC1
), 0 } },
1934 { 16, 16, 0xf0ff }, 0x5071,
1935 (PTR
) & fmt_mvtachi_ops
[0],
1936 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_S
} }
1938 /* start-sanitize-m32rx */
1939 /* mvtaclo $src1,$accs */
1942 M32R_INSN_MVTACLO_A
, "mvtaclo-a", "mvtaclo",
1943 { { MNEM
, ' ', OP (SRC1
), ',', OP (ACCS
), 0 } },
1944 { 16, 16, 0xf0f3 }, 0x5071,
1945 (PTR
) & fmt_mvtachi_a_ops
[0],
1946 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_S
} }
1948 /* end-sanitize-m32rx */
1952 M32R_INSN_MVTC
, "mvtc", "mvtc",
1953 { { MNEM
, ' ', OP (SR
), ',', OP (DCR
), 0 } },
1954 { 16, 16, 0xf0f0 }, 0x10a0,
1955 (PTR
) & fmt_mvtc_ops
[0],
1956 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_O
} }
1961 M32R_INSN_NEG
, "neg", "neg",
1962 { { MNEM
, ' ', OP (DR
), ',', OP (SR
), 0 } },
1963 { 16, 16, 0xf0f0 }, 0x30,
1964 (PTR
) & fmt_mv_ops
[0],
1965 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_OS
} }
1970 M32R_INSN_NOP
, "nop", "nop",
1972 { 16, 16, 0xffff }, 0x7000,
1974 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_OS
} }
1979 M32R_INSN_NOT
, "not", "not",
1980 { { MNEM
, ' ', OP (DR
), ',', OP (SR
), 0 } },
1981 { 16, 16, 0xf0f0 }, 0xb0,
1982 (PTR
) & fmt_mv_ops
[0],
1983 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_OS
} }
1988 M32R_INSN_RAC
, "rac", "rac",
1990 { 16, 16, 0xffff }, 0x5090,
1991 (PTR
) & fmt_rac_ops
[0],
1992 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_S
} }
1994 /* start-sanitize-m32rx */
1995 /* rac $accd,$accs,$imm1 */
1998 M32R_INSN_RAC_DSI
, "rac-dsi", "rac",
1999 { { MNEM
, ' ', OP (ACCD
), ',', OP (ACCS
), ',', OP (IMM1
), 0 } },
2000 { 16, 16, 0xf3f2 }, 0x5090,
2001 (PTR
) & fmt_rac_dsi_ops
[0],
2002 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_S
} }
2004 /* end-sanitize-m32rx */
2008 M32R_INSN_RACH
, "rach", "rach",
2010 { 16, 16, 0xffff }, 0x5080,
2011 (PTR
) & fmt_rac_ops
[0],
2012 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_S
} }
2014 /* start-sanitize-m32rx */
2015 /* rach $accd,$accs,$imm1 */
2018 M32R_INSN_RACH_DSI
, "rach-dsi", "rach",
2019 { { MNEM
, ' ', OP (ACCD
), ',', OP (ACCS
), ',', OP (IMM1
), 0 } },
2020 { 16, 16, 0xf3f2 }, 0x5080,
2021 (PTR
) & fmt_rac_dsi_ops
[0],
2022 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_S
} }
2024 /* end-sanitize-m32rx */
2028 M32R_INSN_RTE
, "rte", "rte",
2030 { 16, 16, 0xffff }, 0x10d6,
2031 (PTR
) & fmt_rte_ops
[0],
2032 { CGEN_INSN_NBOOL_ATTRS
, 0|A(UNCOND_CTI
), { (1<<MACH_BASE
), PIPE_O
} }
2034 /* seth $dr,$hash$hi16 */
2037 M32R_INSN_SETH
, "seth", "seth",
2038 { { MNEM
, ' ', OP (DR
), ',', OP (HASH
), OP (HI16
), 0 } },
2039 { 32, 32, 0xf0ff0000 }, 0xd0c00000,
2040 (PTR
) & fmt_seth_ops
[0],
2041 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_NONE
} }
2046 M32R_INSN_SLL
, "sll", "sll",
2047 { { MNEM
, ' ', OP (DR
), ',', OP (SR
), 0 } },
2048 { 16, 16, 0xf0f0 }, 0x1040,
2049 (PTR
) & fmt_add_ops
[0],
2050 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_O
} }
2052 /* sll3 $dr,$sr,$simm16 */
2055 M32R_INSN_SLL3
, "sll3", "sll3",
2056 { { MNEM
, ' ', OP (DR
), ',', OP (SR
), ',', OP (SIMM16
), 0 } },
2057 { 32, 32, 0xf0f00000 }, 0x90c00000,
2058 (PTR
) & fmt_sll3_ops
[0],
2059 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_NONE
} }
2061 /* slli $dr,$uimm5 */
2064 M32R_INSN_SLLI
, "slli", "slli",
2065 { { MNEM
, ' ', OP (DR
), ',', OP (UIMM5
), 0 } },
2066 { 16, 16, 0xf0e0 }, 0x5040,
2067 (PTR
) & fmt_slli_ops
[0],
2068 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_O
} }
2073 M32R_INSN_SRA
, "sra", "sra",
2074 { { MNEM
, ' ', OP (DR
), ',', OP (SR
), 0 } },
2075 { 16, 16, 0xf0f0 }, 0x1020,
2076 (PTR
) & fmt_add_ops
[0],
2077 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_O
} }
2079 /* sra3 $dr,$sr,$simm16 */
2082 M32R_INSN_SRA3
, "sra3", "sra3",
2083 { { MNEM
, ' ', OP (DR
), ',', OP (SR
), ',', OP (SIMM16
), 0 } },
2084 { 32, 32, 0xf0f00000 }, 0x90a00000,
2085 (PTR
) & fmt_sll3_ops
[0],
2086 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_NONE
} }
2088 /* srai $dr,$uimm5 */
2091 M32R_INSN_SRAI
, "srai", "srai",
2092 { { MNEM
, ' ', OP (DR
), ',', OP (UIMM5
), 0 } },
2093 { 16, 16, 0xf0e0 }, 0x5020,
2094 (PTR
) & fmt_slli_ops
[0],
2095 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_O
} }
2100 M32R_INSN_SRL
, "srl", "srl",
2101 { { MNEM
, ' ', OP (DR
), ',', OP (SR
), 0 } },
2102 { 16, 16, 0xf0f0 }, 0x1000,
2103 (PTR
) & fmt_add_ops
[0],
2104 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_O
} }
2106 /* srl3 $dr,$sr,$simm16 */
2109 M32R_INSN_SRL3
, "srl3", "srl3",
2110 { { MNEM
, ' ', OP (DR
), ',', OP (SR
), ',', OP (SIMM16
), 0 } },
2111 { 32, 32, 0xf0f00000 }, 0x90800000,
2112 (PTR
) & fmt_sll3_ops
[0],
2113 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_NONE
} }
2115 /* srli $dr,$uimm5 */
2118 M32R_INSN_SRLI
, "srli", "srli",
2119 { { MNEM
, ' ', OP (DR
), ',', OP (UIMM5
), 0 } },
2120 { 16, 16, 0xf0e0 }, 0x5000,
2121 (PTR
) & fmt_slli_ops
[0],
2122 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_O
} }
2124 /* st $src1,@$src2 */
2127 M32R_INSN_ST
, "st", "st",
2128 { { MNEM
, ' ', OP (SRC1
), ',', '@', OP (SRC2
), 0 } },
2129 { 16, 16, 0xf0f0 }, 0x2040,
2130 (PTR
) & fmt_st_ops
[0],
2131 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_O
} }
2133 /* st $src1,@($slo16,$src2) */
2136 M32R_INSN_ST_D
, "st-d", "st",
2137 { { MNEM
, ' ', OP (SRC1
), ',', '@', '(', OP (SLO16
), ',', OP (SRC2
), ')', 0 } },
2138 { 32, 32, 0xf0f00000 }, 0xa0400000,
2139 (PTR
) & fmt_st_d_ops
[0],
2140 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_NONE
} }
2142 /* stb $src1,@$src2 */
2145 M32R_INSN_STB
, "stb", "stb",
2146 { { MNEM
, ' ', OP (SRC1
), ',', '@', OP (SRC2
), 0 } },
2147 { 16, 16, 0xf0f0 }, 0x2000,
2148 (PTR
) & fmt_stb_ops
[0],
2149 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_O
} }
2151 /* stb $src1,@($slo16,$src2) */
2154 M32R_INSN_STB_D
, "stb-d", "stb",
2155 { { MNEM
, ' ', OP (SRC1
), ',', '@', '(', OP (SLO16
), ',', OP (SRC2
), ')', 0 } },
2156 { 32, 32, 0xf0f00000 }, 0xa0000000,
2157 (PTR
) & fmt_stb_d_ops
[0],
2158 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_NONE
} }
2160 /* sth $src1,@$src2 */
2163 M32R_INSN_STH
, "sth", "sth",
2164 { { MNEM
, ' ', OP (SRC1
), ',', '@', OP (SRC2
), 0 } },
2165 { 16, 16, 0xf0f0 }, 0x2020,
2166 (PTR
) & fmt_sth_ops
[0],
2167 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_O
} }
2169 /* sth $src1,@($slo16,$src2) */
2172 M32R_INSN_STH_D
, "sth-d", "sth",
2173 { { MNEM
, ' ', OP (SRC1
), ',', '@', '(', OP (SLO16
), ',', OP (SRC2
), ')', 0 } },
2174 { 32, 32, 0xf0f00000 }, 0xa0200000,
2175 (PTR
) & fmt_sth_d_ops
[0],
2176 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_NONE
} }
2178 /* st $src1,@+$src2 */
2181 M32R_INSN_ST_PLUS
, "st-plus", "st",
2182 { { MNEM
, ' ', OP (SRC1
), ',', '@', '+', OP (SRC2
), 0 } },
2183 { 16, 16, 0xf0f0 }, 0x2060,
2184 (PTR
) & fmt_st_plus_ops
[0],
2185 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_O
} }
2187 /* st $src1,@-$src2 */
2190 M32R_INSN_ST_MINUS
, "st-minus", "st",
2191 { { MNEM
, ' ', OP (SRC1
), ',', '@', '-', OP (SRC2
), 0 } },
2192 { 16, 16, 0xf0f0 }, 0x2070,
2193 (PTR
) & fmt_st_plus_ops
[0],
2194 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_O
} }
2199 M32R_INSN_SUB
, "sub", "sub",
2200 { { MNEM
, ' ', OP (DR
), ',', OP (SR
), 0 } },
2201 { 16, 16, 0xf0f0 }, 0x20,
2202 (PTR
) & fmt_add_ops
[0],
2203 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_OS
} }
2208 M32R_INSN_SUBV
, "subv", "subv",
2209 { { MNEM
, ' ', OP (DR
), ',', OP (SR
), 0 } },
2210 { 16, 16, 0xf0f0 }, 0x0,
2211 (PTR
) & fmt_addv_ops
[0],
2212 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_OS
} }
2217 M32R_INSN_SUBX
, "subx", "subx",
2218 { { MNEM
, ' ', OP (DR
), ',', OP (SR
), 0 } },
2219 { 16, 16, 0xf0f0 }, 0x10,
2220 (PTR
) & fmt_addx_ops
[0],
2221 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_OS
} }
2226 M32R_INSN_TRAP
, "trap", "trap",
2227 { { MNEM
, ' ', OP (UIMM4
), 0 } },
2228 { 16, 16, 0xfff0 }, 0x10f0,
2229 (PTR
) & fmt_trap_ops
[0],
2230 { CGEN_INSN_NBOOL_ATTRS
, 0|A(FILL_SLOT
)|A(UNCOND_CTI
), { (1<<MACH_BASE
), PIPE_O
} }
2232 /* unlock $src1,@$src2 */
2235 M32R_INSN_UNLOCK
, "unlock", "unlock",
2236 { { MNEM
, ' ', OP (SRC1
), ',', '@', OP (SRC2
), 0 } },
2237 { 16, 16, 0xf0f0 }, 0x2050,
2238 (PTR
) & fmt_unlock_ops
[0],
2239 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_BASE
), PIPE_O
} }
2241 /* start-sanitize-m32rx */
2245 M32R_INSN_SATB
, "satb", "satb",
2246 { { MNEM
, ' ', OP (DR
), ',', OP (SR
), 0 } },
2247 { 32, 32, 0xf0f0ffff }, 0x80600300,
2248 (PTR
) & fmt_satb_ops
[0],
2249 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_NONE
} }
2251 /* end-sanitize-m32rx */
2252 /* start-sanitize-m32rx */
2256 M32R_INSN_SATH
, "sath", "sath",
2257 { { MNEM
, ' ', OP (DR
), ',', OP (SR
), 0 } },
2258 { 32, 32, 0xf0f0ffff }, 0x80600200,
2259 (PTR
) & fmt_satb_ops
[0],
2260 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_NONE
} }
2262 /* end-sanitize-m32rx */
2263 /* start-sanitize-m32rx */
2267 M32R_INSN_SAT
, "sat", "sat",
2268 { { MNEM
, ' ', OP (DR
), ',', OP (SR
), 0 } },
2269 { 32, 32, 0xf0f0ffff }, 0x80600000,
2270 (PTR
) & fmt_sat_ops
[0],
2271 { CGEN_INSN_NBOOL_ATTRS
, 0|A(SPECIAL
), { (1<<MACH_M32RX
), PIPE_NONE
} }
2273 /* end-sanitize-m32rx */
2274 /* start-sanitize-m32rx */
2278 M32R_INSN_PCMPBZ
, "pcmpbz", "pcmpbz",
2279 { { MNEM
, ' ', OP (SRC2
), 0 } },
2280 { 16, 16, 0xfff0 }, 0x370,
2281 (PTR
) & fmt_cmpz_ops
[0],
2282 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_OS
} }
2284 /* end-sanitize-m32rx */
2285 /* start-sanitize-m32rx */
2289 M32R_INSN_SADD
, "sadd", "sadd",
2291 { 16, 16, 0xffff }, 0x50e4,
2292 (PTR
) & fmt_sadd_ops
[0],
2293 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_S
} }
2295 /* end-sanitize-m32rx */
2296 /* start-sanitize-m32rx */
2297 /* macwu1 $src1,$src2 */
2300 M32R_INSN_MACWU1
, "macwu1", "macwu1",
2301 { { MNEM
, ' ', OP (SRC1
), ',', OP (SRC2
), 0 } },
2302 { 16, 16, 0xf0f0 }, 0x50b0,
2303 (PTR
) & fmt_macwu1_ops
[0],
2304 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_S
} }
2306 /* end-sanitize-m32rx */
2307 /* start-sanitize-m32rx */
2308 /* msblo $src1,$src2 */
2311 M32R_INSN_MSBLO
, "msblo", "msblo",
2312 { { MNEM
, ' ', OP (SRC1
), ',', OP (SRC2
), 0 } },
2313 { 16, 16, 0xf0f0 }, 0x50d0,
2314 (PTR
) & fmt_machi_ops
[0],
2315 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_S
} }
2317 /* end-sanitize-m32rx */
2318 /* start-sanitize-m32rx */
2319 /* mulwu1 $src1,$src2 */
2322 M32R_INSN_MULWU1
, "mulwu1", "mulwu1",
2323 { { MNEM
, ' ', OP (SRC1
), ',', OP (SRC2
), 0 } },
2324 { 16, 16, 0xf0f0 }, 0x50a0,
2325 (PTR
) & fmt_mulwu1_ops
[0],
2326 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_S
} }
2328 /* end-sanitize-m32rx */
2329 /* start-sanitize-m32rx */
2330 /* maclh1 $src1,$src2 */
2333 M32R_INSN_MACLH1
, "maclh1", "maclh1",
2334 { { MNEM
, ' ', OP (SRC1
), ',', OP (SRC2
), 0 } },
2335 { 16, 16, 0xf0f0 }, 0x50c0,
2336 (PTR
) & fmt_macwu1_ops
[0],
2337 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_S
} }
2339 /* end-sanitize-m32rx */
2340 /* start-sanitize-m32rx */
2344 M32R_INSN_SC
, "sc", "sc",
2346 { 16, 16, 0xffff }, 0x7401,
2347 (PTR
) & fmt_sc_ops
[0],
2348 { CGEN_INSN_NBOOL_ATTRS
, 0|A(SPECIAL
)|A(SKIP_CTI
), { (1<<MACH_M32RX
), PIPE_O
} }
2350 /* end-sanitize-m32rx */
2351 /* start-sanitize-m32rx */
2355 M32R_INSN_SNC
, "snc", "snc",
2357 { 16, 16, 0xffff }, 0x7501,
2358 (PTR
) & fmt_sc_ops
[0],
2359 { CGEN_INSN_NBOOL_ATTRS
, 0|A(SPECIAL
)|A(SKIP_CTI
), { (1<<MACH_M32RX
), PIPE_O
} }
2361 /* end-sanitize-m32rx */
2368 static const CGEN_INSN_TABLE insn_table
=
2370 & m32r_cgen_insn_table_entries
[0],
2376 /* Each non-simple macro entry points to an array of expansion possibilities. */
2378 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
2379 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
2380 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
2382 /* The macro instruction table. */
2384 static const CGEN_INSN macro_insn_table_entries
[] =
2390 { { MNEM
, ' ', OP (DISP8
), 0 } },
2391 { 16, 16, 0xff00 }, 0x7c00,
2393 { CGEN_INSN_NBOOL_ATTRS
, 0|A(RELAXABLE
)|A(COND_CTI
)|A(ALIAS
), { (1<<MACH_BASE
), PIPE_O
} }
2399 { { MNEM
, ' ', OP (DISP24
), 0 } },
2400 { 32, 32, 0xff000000 }, 0xfc000000,
2402 { CGEN_INSN_NBOOL_ATTRS
, 0|A(RELAX
)|A(COND_CTI
)|A(ALIAS
), { (1<<MACH_BASE
), PIPE_NONE
} }
2408 { { MNEM
, ' ', OP (DISP8
), 0 } },
2409 { 16, 16, 0xff00 }, 0x7e00,
2411 { CGEN_INSN_NBOOL_ATTRS
, 0|A(RELAXABLE
)|A(FILL_SLOT
)|A(UNCOND_CTI
)|A(ALIAS
), { (1<<MACH_BASE
), PIPE_O
} }
2417 { { MNEM
, ' ', OP (DISP24
), 0 } },
2418 { 32, 32, 0xff000000 }, 0xfe000000,
2420 { CGEN_INSN_NBOOL_ATTRS
, 0|A(RELAX
)|A(UNCOND_CTI
)|A(ALIAS
), { (1<<MACH_BASE
), PIPE_NONE
} }
2426 { { MNEM
, ' ', OP (DISP8
), 0 } },
2427 { 16, 16, 0xff00 }, 0x7800,
2429 { CGEN_INSN_NBOOL_ATTRS
, 0|A(RELAXABLE
)|A(FILL_SLOT
)|A(COND_CTI
)|A(ALIAS
), { (1<<MACH_M32RX
), PIPE_O
} }
2434 -1, "bcl24r", "bcl",
2435 { { MNEM
, ' ', OP (DISP24
), 0 } },
2436 { 32, 32, 0xff000000 }, 0xf8000000,
2438 { CGEN_INSN_NBOOL_ATTRS
, 0|A(RELAX
)|A(COND_CTI
)|A(ALIAS
), { (1<<MACH_M32RX
), PIPE_NONE
} }
2444 { { MNEM
, ' ', OP (DISP8
), 0 } },
2445 { 16, 16, 0xff00 }, 0x7d00,
2447 { CGEN_INSN_NBOOL_ATTRS
, 0|A(RELAXABLE
)|A(COND_CTI
)|A(ALIAS
), { (1<<MACH_BASE
), PIPE_O
} }
2452 -1, "bnc24r", "bnc",
2453 { { MNEM
, ' ', OP (DISP24
), 0 } },
2454 { 32, 32, 0xff000000 }, 0xfd000000,
2456 { CGEN_INSN_NBOOL_ATTRS
, 0|A(RELAX
)|A(COND_CTI
)|A(ALIAS
), { (1<<MACH_BASE
), PIPE_NONE
} }
2462 { { MNEM
, ' ', OP (DISP8
), 0 } },
2463 { 16, 16, 0xff00 }, 0x7f00,
2465 { CGEN_INSN_NBOOL_ATTRS
, 0|A(RELAXABLE
)|A(FILL_SLOT
)|A(UNCOND_CTI
)|A(ALIAS
), { (1<<MACH_BASE
), PIPE_O
} }
2470 -1, "bra24r", "bra",
2471 { { MNEM
, ' ', OP (DISP24
), 0 } },
2472 { 32, 32, 0xff000000 }, 0xff000000,
2474 { CGEN_INSN_NBOOL_ATTRS
, 0|A(RELAX
)|A(UNCOND_CTI
)|A(ALIAS
), { (1<<MACH_BASE
), PIPE_NONE
} }
2479 -1, "bncl8r", "bncl",
2480 { { MNEM
, ' ', OP (DISP8
), 0 } },
2481 { 16, 16, 0xff00 }, 0x7900,
2483 { CGEN_INSN_NBOOL_ATTRS
, 0|A(RELAXABLE
)|A(FILL_SLOT
)|A(COND_CTI
)|A(ALIAS
), { (1<<MACH_M32RX
), PIPE_O
} }
2488 -1, "bncl24r", "bncl",
2489 { { MNEM
, ' ', OP (DISP24
), 0 } },
2490 { 32, 32, 0xff000000 }, 0xf9000000,
2492 { CGEN_INSN_NBOOL_ATTRS
, 0|A(RELAX
)|A(COND_CTI
)|A(ALIAS
), { (1<<MACH_M32RX
), PIPE_NONE
} }
2498 { { MNEM
, ' ', OP (DR
), ',', '@', '(', OP (SR
), ')', 0 } },
2499 { 16, 16, 0xf0f0 }, 0x20c0,
2501 { CGEN_INSN_NBOOL_ATTRS
, 0|A(NO_DIS
)|A(ALIAS
), { (1<<MACH_BASE
), PIPE_O
} }
2503 /* ld $dr,@($sr,$slo16) */
2507 { { MNEM
, ' ', OP (DR
), ',', '@', '(', OP (SR
), ',', OP (SLO16
), ')', 0 } },
2508 { 32, 32, 0xf0f00000 }, 0xa0c00000,
2510 { CGEN_INSN_NBOOL_ATTRS
, 0|A(NO_DIS
)|A(ALIAS
), { (1<<MACH_BASE
), PIPE_NONE
} }
2512 /* ldb $dr,@($sr) */
2516 { { MNEM
, ' ', OP (DR
), ',', '@', '(', OP (SR
), ')', 0 } },
2517 { 16, 16, 0xf0f0 }, 0x2080,
2519 { CGEN_INSN_NBOOL_ATTRS
, 0|A(NO_DIS
)|A(ALIAS
), { (1<<MACH_BASE
), PIPE_O
} }
2521 /* ldb $dr,@($sr,$slo16) */
2524 -1, "ldb-d2", "ldb",
2525 { { MNEM
, ' ', OP (DR
), ',', '@', '(', OP (SR
), ',', OP (SLO16
), ')', 0 } },
2526 { 32, 32, 0xf0f00000 }, 0xa0800000,
2528 { CGEN_INSN_NBOOL_ATTRS
, 0|A(NO_DIS
)|A(ALIAS
), { (1<<MACH_BASE
), PIPE_NONE
} }
2530 /* ldh $dr,@($sr) */
2534 { { MNEM
, ' ', OP (DR
), ',', '@', '(', OP (SR
), ')', 0 } },
2535 { 16, 16, 0xf0f0 }, 0x20a0,
2537 { CGEN_INSN_NBOOL_ATTRS
, 0|A(NO_DIS
)|A(ALIAS
), { (1<<MACH_BASE
), PIPE_O
} }
2539 /* ldh $dr,@($sr,$slo16) */
2542 -1, "ldh-d2", "ldh",
2543 { { MNEM
, ' ', OP (DR
), ',', '@', '(', OP (SR
), ',', OP (SLO16
), ')', 0 } },
2544 { 32, 32, 0xf0f00000 }, 0xa0a00000,
2546 { CGEN_INSN_NBOOL_ATTRS
, 0|A(NO_DIS
)|A(ALIAS
), { (1<<MACH_BASE
), PIPE_NONE
} }
2548 /* ldub $dr,@($sr) */
2551 -1, "ldub-2", "ldub",
2552 { { MNEM
, ' ', OP (DR
), ',', '@', '(', OP (SR
), ')', 0 } },
2553 { 16, 16, 0xf0f0 }, 0x2090,
2555 { CGEN_INSN_NBOOL_ATTRS
, 0|A(NO_DIS
)|A(ALIAS
), { (1<<MACH_BASE
), PIPE_O
} }
2557 /* ldub $dr,@($sr,$slo16) */
2560 -1, "ldub-d2", "ldub",
2561 { { MNEM
, ' ', OP (DR
), ',', '@', '(', OP (SR
), ',', OP (SLO16
), ')', 0 } },
2562 { 32, 32, 0xf0f00000 }, 0xa0900000,
2564 { CGEN_INSN_NBOOL_ATTRS
, 0|A(NO_DIS
)|A(ALIAS
), { (1<<MACH_BASE
), PIPE_NONE
} }
2566 /* lduh $dr,@($sr) */
2569 -1, "lduh-2", "lduh",
2570 { { MNEM
, ' ', OP (DR
), ',', '@', '(', OP (SR
), ')', 0 } },
2571 { 16, 16, 0xf0f0 }, 0x20b0,
2573 { CGEN_INSN_NBOOL_ATTRS
, 0|A(NO_DIS
)|A(ALIAS
), { (1<<MACH_BASE
), PIPE_O
} }
2575 /* lduh $dr,@($sr,$slo16) */
2578 -1, "lduh-d2", "lduh",
2579 { { MNEM
, ' ', OP (DR
), ',', '@', '(', OP (SR
), ',', OP (SLO16
), ')', 0 } },
2580 { 32, 32, 0xf0f00000 }, 0xa0b00000,
2582 { CGEN_INSN_NBOOL_ATTRS
, 0|A(NO_DIS
)|A(ALIAS
), { (1<<MACH_BASE
), PIPE_NONE
} }
2588 { { MNEM
, ' ', OP (DR
), 0 } },
2589 { 16, 16, 0xf0ff }, 0x20ef,
2591 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_BASE
), PIPE_NONE
} }
2593 /* ldi $dr,$simm8 */
2597 { { MNEM
, ' ', OP (DR
), ',', OP (SIMM8
), 0 } },
2598 { 16, 16, 0xf000 }, 0x6000,
2600 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_BASE
), PIPE_OS
} }
2602 /* ldi $dr,$hash$slo16 */
2605 -1, "ldi16a", "ldi",
2606 { { MNEM
, ' ', OP (DR
), ',', OP (HASH
), OP (SLO16
), 0 } },
2607 { 32, 32, 0xf0ff0000 }, 0x90f00000,
2609 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_BASE
), PIPE_NONE
} }
2615 { { MNEM
, ' ', OP (ACCD
), 0 } },
2616 { 16, 16, 0xf3ff }, 0x5090,
2618 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32RX
), PIPE_S
} }
2620 /* rac $accd,$accs */
2623 -1, "rac-ds", "rac",
2624 { { MNEM
, ' ', OP (ACCD
), ',', OP (ACCS
), 0 } },
2625 { 16, 16, 0xf3f3 }, 0x5090,
2627 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32RX
), PIPE_S
} }
2632 -1, "rach-d", "rach",
2633 { { MNEM
, ' ', OP (ACCD
), 0 } },
2634 { 16, 16, 0xf3ff }, 0x5080,
2636 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32RX
), PIPE_S
} }
2638 /* rach $accd,$accs */
2641 -1, "rach-ds", "rach",
2642 { { MNEM
, ' ', OP (ACCD
), ',', OP (ACCS
), 0 } },
2643 { 16, 16, 0xf3f3 }, 0x5080,
2645 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32RX
), PIPE_S
} }
2647 /* st $src1,@($src2) */
2651 { { MNEM
, ' ', OP (SRC1
), ',', '@', '(', OP (SRC2
), ')', 0 } },
2652 { 16, 16, 0xf0f0 }, 0x2040,
2654 { CGEN_INSN_NBOOL_ATTRS
, 0|A(NO_DIS
)|A(ALIAS
), { (1<<MACH_BASE
), PIPE_O
} }
2656 /* st $src1,@($src2,$slo16) */
2660 { { MNEM
, ' ', OP (SRC1
), ',', '@', '(', OP (SRC2
), ',', OP (SLO16
), ')', 0 } },
2661 { 32, 32, 0xf0f00000 }, 0xa0400000,
2663 { CGEN_INSN_NBOOL_ATTRS
, 0|A(NO_DIS
)|A(ALIAS
), { (1<<MACH_BASE
), PIPE_NONE
} }
2665 /* stb $src1,@($src2) */
2669 { { MNEM
, ' ', OP (SRC1
), ',', '@', '(', OP (SRC2
), ')', 0 } },
2670 { 16, 16, 0xf0f0 }, 0x2000,
2672 { CGEN_INSN_NBOOL_ATTRS
, 0|A(NO_DIS
)|A(ALIAS
), { (1<<MACH_BASE
), PIPE_O
} }
2674 /* stb $src1,@($src2,$slo16) */
2677 -1, "stb-d2", "stb",
2678 { { MNEM
, ' ', OP (SRC1
), ',', '@', '(', OP (SRC2
), ',', OP (SLO16
), ')', 0 } },
2679 { 32, 32, 0xf0f00000 }, 0xa0000000,
2681 { CGEN_INSN_NBOOL_ATTRS
, 0|A(NO_DIS
)|A(ALIAS
), { (1<<MACH_BASE
), PIPE_NONE
} }
2683 /* sth $src1,@($src2) */
2687 { { MNEM
, ' ', OP (SRC1
), ',', '@', '(', OP (SRC2
), ')', 0 } },
2688 { 16, 16, 0xf0f0 }, 0x2020,
2690 { CGEN_INSN_NBOOL_ATTRS
, 0|A(NO_DIS
)|A(ALIAS
), { (1<<MACH_BASE
), PIPE_O
} }
2692 /* sth $src1,@($src2,$slo16) */
2695 -1, "sth-d2", "sth",
2696 { { MNEM
, ' ', OP (SRC1
), ',', '@', '(', OP (SRC2
), ',', OP (SLO16
), ')', 0 } },
2697 { 32, 32, 0xf0f00000 }, 0xa0200000,
2699 { CGEN_INSN_NBOOL_ATTRS
, 0|A(NO_DIS
)|A(ALIAS
), { (1<<MACH_BASE
), PIPE_NONE
} }
2705 { { MNEM
, ' ', OP (SRC1
), 0 } },
2706 { 16, 16, 0xf0ff }, 0x207f,
2708 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_BASE
), PIPE_NONE
} }
2716 static const CGEN_INSN_TABLE macro_insn_table
=
2718 & macro_insn_table_entries
[0],
2720 (sizeof (macro_insn_table_entries
) /
2721 sizeof (macro_insn_table_entries
[0])),
2730 /* Return non-zero if INSN is to be added to the hash table.
2731 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
2734 asm_hash_insn_p (insn
)
2735 const CGEN_INSN
* insn
;
2737 return CGEN_ASM_HASH_P (insn
);
2741 dis_hash_insn_p (insn
)
2742 const CGEN_INSN
* insn
;
2744 /* If building the hash table and the NO-DIS attribute is present,
2746 if (CGEN_INSN_ATTR (insn
, CGEN_INSN_NO_DIS
))
2748 return CGEN_DIS_HASH_P (insn
);
2751 /* The result is the hash value of the insn.
2752 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
2755 asm_hash_insn (mnem
)
2758 return CGEN_ASM_HASH (mnem
);
2761 /* BUF is a pointer to the insn's bytes in target order.
2762 VALUE is an integer of the first CGEN_BASE_INSN_BITSIZE bits,
2766 dis_hash_insn (buf
, value
)
2768 unsigned long value
;
2770 return CGEN_DIS_HASH (buf
, value
);
2773 /* Initialize an opcode table and return a descriptor.
2774 It's much like opening a file, and must be the first function called. */
2777 m32r_cgen_opcode_open (mach
, endian
)
2779 enum cgen_endian endian
;
2781 CGEN_OPCODE_TABLE
* table
= (CGEN_OPCODE_TABLE
*) xmalloc (sizeof (CGEN_OPCODE_TABLE
));
2790 memset (table
, 0, sizeof (*table
));
2792 CGEN_OPCODE_MACH (table
) = mach
;
2793 CGEN_OPCODE_ENDIAN (table
) = endian
;
2794 /* FIXME: for the sparc case we can determine insn-endianness statically.
2795 The worry here is where both data and insn endian can be independently
2796 chosen, in which case this function will need another argument.
2797 Actually, will want to allow for more arguments in the future anyway. */
2798 CGEN_OPCODE_INSN_ENDIAN (table
) = endian
;
2800 CGEN_OPCODE_HW_LIST (table
) = & m32r_cgen_hw_entries
[0];
2802 CGEN_OPCODE_OPERAND_TABLE (table
) = & m32r_cgen_operand_table
[0];
2804 * CGEN_OPCODE_INSN_TABLE (table
) = insn_table
;
2806 * CGEN_OPCODE_MACRO_INSN_TABLE (table
) = macro_insn_table
;
2808 CGEN_OPCODE_ASM_HASH_P (table
) = asm_hash_insn_p
;
2809 CGEN_OPCODE_ASM_HASH (table
) = asm_hash_insn
;
2810 CGEN_OPCODE_ASM_HASH_SIZE (table
) = CGEN_ASM_HASH_SIZE
;
2812 CGEN_OPCODE_DIS_HASH_P (table
) = dis_hash_insn_p
;
2813 CGEN_OPCODE_DIS_HASH (table
) = dis_hash_insn
;
2814 CGEN_OPCODE_DIS_HASH_SIZE (table
) = CGEN_DIS_HASH_SIZE
;
2816 return (CGEN_OPCODE_DESC
) table
;
2819 /* Close an opcode table. */
2822 m32r_cgen_opcode_close (desc
)
2823 CGEN_OPCODE_DESC desc
;
2828 /* Getting values from cgen_fields is handled by a collection of functions.
2829 They are distinguished by the type of the VALUE argument they return.
2830 TODO: floating point, inlining support, remove cases where result type
2834 m32r_cgen_get_int_operand (opindex
, fields
)
2836 const CGEN_FIELDS
* fields
;
2842 case M32R_OPERAND_SR
:
2843 value
= fields
->f_r2
;
2845 case M32R_OPERAND_DR
:
2846 value
= fields
->f_r1
;
2848 case M32R_OPERAND_SRC1
:
2849 value
= fields
->f_r1
;
2851 case M32R_OPERAND_SRC2
:
2852 value
= fields
->f_r2
;
2854 case M32R_OPERAND_SCR
:
2855 value
= fields
->f_r2
;
2857 case M32R_OPERAND_DCR
:
2858 value
= fields
->f_r1
;
2860 case M32R_OPERAND_SIMM8
:
2861 value
= fields
->f_simm8
;
2863 case M32R_OPERAND_SIMM16
:
2864 value
= fields
->f_simm16
;
2866 case M32R_OPERAND_UIMM4
:
2867 value
= fields
->f_uimm4
;
2869 case M32R_OPERAND_UIMM5
:
2870 value
= fields
->f_uimm5
;
2872 case M32R_OPERAND_UIMM16
:
2873 value
= fields
->f_uimm16
;
2875 /* start-sanitize-m32rx */
2876 case M32R_OPERAND_IMM1
:
2877 value
= fields
->f_imm1
;
2879 /* end-sanitize-m32rx */
2880 /* start-sanitize-m32rx */
2881 case M32R_OPERAND_ACCD
:
2882 value
= fields
->f_accd
;
2884 /* end-sanitize-m32rx */
2885 /* start-sanitize-m32rx */
2886 case M32R_OPERAND_ACCS
:
2887 value
= fields
->f_accs
;
2889 /* end-sanitize-m32rx */
2890 /* start-sanitize-m32rx */
2891 case M32R_OPERAND_ACC
:
2892 value
= fields
->f_acc
;
2894 /* end-sanitize-m32rx */
2895 case M32R_OPERAND_HASH
:
2896 value
= fields
->f_nil
;
2898 case M32R_OPERAND_HI16
:
2899 value
= fields
->f_hi16
;
2901 case M32R_OPERAND_SLO16
:
2902 value
= fields
->f_simm16
;
2904 case M32R_OPERAND_ULO16
:
2905 value
= fields
->f_uimm16
;
2907 case M32R_OPERAND_UIMM24
:
2908 value
= fields
->f_uimm24
;
2910 case M32R_OPERAND_DISP8
:
2911 value
= fields
->f_disp8
;
2913 case M32R_OPERAND_DISP16
:
2914 value
= fields
->f_disp16
;
2916 case M32R_OPERAND_DISP24
:
2917 value
= fields
->f_disp24
;
2921 /* xgettext:c-format */
2922 fprintf (stderr
, _("Unrecognized field %d while getting int operand.\n"),
2931 m32r_cgen_get_vma_operand (opindex
, fields
)
2933 const CGEN_FIELDS
* fields
;
2939 case M32R_OPERAND_SR
:
2940 value
= fields
->f_r2
;
2942 case M32R_OPERAND_DR
:
2943 value
= fields
->f_r1
;
2945 case M32R_OPERAND_SRC1
:
2946 value
= fields
->f_r1
;
2948 case M32R_OPERAND_SRC2
:
2949 value
= fields
->f_r2
;
2951 case M32R_OPERAND_SCR
:
2952 value
= fields
->f_r2
;
2954 case M32R_OPERAND_DCR
:
2955 value
= fields
->f_r1
;
2957 case M32R_OPERAND_SIMM8
:
2958 value
= fields
->f_simm8
;
2960 case M32R_OPERAND_SIMM16
:
2961 value
= fields
->f_simm16
;
2963 case M32R_OPERAND_UIMM4
:
2964 value
= fields
->f_uimm4
;
2966 case M32R_OPERAND_UIMM5
:
2967 value
= fields
->f_uimm5
;
2969 case M32R_OPERAND_UIMM16
:
2970 value
= fields
->f_uimm16
;
2972 /* start-sanitize-m32rx */
2973 case M32R_OPERAND_IMM1
:
2974 value
= fields
->f_imm1
;
2976 /* end-sanitize-m32rx */
2977 /* start-sanitize-m32rx */
2978 case M32R_OPERAND_ACCD
:
2979 value
= fields
->f_accd
;
2981 /* end-sanitize-m32rx */
2982 /* start-sanitize-m32rx */
2983 case M32R_OPERAND_ACCS
:
2984 value
= fields
->f_accs
;
2986 /* end-sanitize-m32rx */
2987 /* start-sanitize-m32rx */
2988 case M32R_OPERAND_ACC
:
2989 value
= fields
->f_acc
;
2991 /* end-sanitize-m32rx */
2992 case M32R_OPERAND_HASH
:
2993 value
= fields
->f_nil
;
2995 case M32R_OPERAND_HI16
:
2996 value
= fields
->f_hi16
;
2998 case M32R_OPERAND_SLO16
:
2999 value
= fields
->f_simm16
;
3001 case M32R_OPERAND_ULO16
:
3002 value
= fields
->f_uimm16
;
3004 case M32R_OPERAND_UIMM24
:
3005 value
= fields
->f_uimm24
;
3007 case M32R_OPERAND_DISP8
:
3008 value
= fields
->f_disp8
;
3010 case M32R_OPERAND_DISP16
:
3011 value
= fields
->f_disp16
;
3013 case M32R_OPERAND_DISP24
:
3014 value
= fields
->f_disp24
;
3018 /* xgettext:c-format */
3019 fprintf (stderr
, _("Unrecognized field %d while getting vma operand.\n"),
3027 /* Stuffing values in cgen_fields is handled by a collection of functions.
3028 They are distinguished by the type of the VALUE argument they accept.
3029 TODO: floating point, inlining support, remove cases where argument type
3033 m32r_cgen_set_int_operand (opindex
, fields
, value
)
3035 CGEN_FIELDS
* fields
;
3040 case M32R_OPERAND_SR
:
3041 fields
->f_r2
= value
;
3043 case M32R_OPERAND_DR
:
3044 fields
->f_r1
= value
;
3046 case M32R_OPERAND_SRC1
:
3047 fields
->f_r1
= value
;
3049 case M32R_OPERAND_SRC2
:
3050 fields
->f_r2
= value
;
3052 case M32R_OPERAND_SCR
:
3053 fields
->f_r2
= value
;
3055 case M32R_OPERAND_DCR
:
3056 fields
->f_r1
= value
;
3058 case M32R_OPERAND_SIMM8
:
3059 fields
->f_simm8
= value
;
3061 case M32R_OPERAND_SIMM16
:
3062 fields
->f_simm16
= value
;
3064 case M32R_OPERAND_UIMM4
:
3065 fields
->f_uimm4
= value
;
3067 case M32R_OPERAND_UIMM5
:
3068 fields
->f_uimm5
= value
;
3070 case M32R_OPERAND_UIMM16
:
3071 fields
->f_uimm16
= value
;
3073 /* start-sanitize-m32rx */
3074 case M32R_OPERAND_IMM1
:
3075 fields
->f_imm1
= value
;
3077 /* end-sanitize-m32rx */
3078 /* start-sanitize-m32rx */
3079 case M32R_OPERAND_ACCD
:
3080 fields
->f_accd
= value
;
3082 /* end-sanitize-m32rx */
3083 /* start-sanitize-m32rx */
3084 case M32R_OPERAND_ACCS
:
3085 fields
->f_accs
= value
;
3087 /* end-sanitize-m32rx */
3088 /* start-sanitize-m32rx */
3089 case M32R_OPERAND_ACC
:
3090 fields
->f_acc
= value
;
3092 /* end-sanitize-m32rx */
3093 case M32R_OPERAND_HASH
:
3094 fields
->f_nil
= value
;
3096 case M32R_OPERAND_HI16
:
3097 fields
->f_hi16
= value
;
3099 case M32R_OPERAND_SLO16
:
3100 fields
->f_simm16
= value
;
3102 case M32R_OPERAND_ULO16
:
3103 fields
->f_uimm16
= value
;
3105 case M32R_OPERAND_UIMM24
:
3106 fields
->f_uimm24
= value
;
3108 case M32R_OPERAND_DISP8
:
3109 fields
->f_disp8
= value
;
3111 case M32R_OPERAND_DISP16
:
3112 fields
->f_disp16
= value
;
3114 case M32R_OPERAND_DISP24
:
3115 fields
->f_disp24
= value
;
3119 /* xgettext:c-format */
3120 fprintf (stderr
, _("Unrecognized field %d while setting int operand.\n"),
3127 m32r_cgen_set_vma_operand (opindex
, fields
, value
)
3129 CGEN_FIELDS
* fields
;
3134 case M32R_OPERAND_SR
:
3135 fields
->f_r2
= value
;
3137 case M32R_OPERAND_DR
:
3138 fields
->f_r1
= value
;
3140 case M32R_OPERAND_SRC1
:
3141 fields
->f_r1
= value
;
3143 case M32R_OPERAND_SRC2
:
3144 fields
->f_r2
= value
;
3146 case M32R_OPERAND_SCR
:
3147 fields
->f_r2
= value
;
3149 case M32R_OPERAND_DCR
:
3150 fields
->f_r1
= value
;
3152 case M32R_OPERAND_SIMM8
:
3153 fields
->f_simm8
= value
;
3155 case M32R_OPERAND_SIMM16
:
3156 fields
->f_simm16
= value
;
3158 case M32R_OPERAND_UIMM4
:
3159 fields
->f_uimm4
= value
;
3161 case M32R_OPERAND_UIMM5
:
3162 fields
->f_uimm5
= value
;
3164 case M32R_OPERAND_UIMM16
:
3165 fields
->f_uimm16
= value
;
3167 /* start-sanitize-m32rx */
3168 case M32R_OPERAND_IMM1
:
3169 fields
->f_imm1
= value
;
3171 /* end-sanitize-m32rx */
3172 /* start-sanitize-m32rx */
3173 case M32R_OPERAND_ACCD
:
3174 fields
->f_accd
= value
;
3176 /* end-sanitize-m32rx */
3177 /* start-sanitize-m32rx */
3178 case M32R_OPERAND_ACCS
:
3179 fields
->f_accs
= value
;
3181 /* end-sanitize-m32rx */
3182 /* start-sanitize-m32rx */
3183 case M32R_OPERAND_ACC
:
3184 fields
->f_acc
= value
;
3186 /* end-sanitize-m32rx */
3187 case M32R_OPERAND_HASH
:
3188 fields
->f_nil
= value
;
3190 case M32R_OPERAND_HI16
:
3191 fields
->f_hi16
= value
;
3193 case M32R_OPERAND_SLO16
:
3194 fields
->f_simm16
= value
;
3196 case M32R_OPERAND_ULO16
:
3197 fields
->f_uimm16
= value
;
3199 case M32R_OPERAND_UIMM24
:
3200 fields
->f_uimm24
= value
;
3202 case M32R_OPERAND_DISP8
:
3203 fields
->f_disp8
= value
;
3205 case M32R_OPERAND_DISP16
:
3206 fields
->f_disp16
= value
;
3208 case M32R_OPERAND_DISP24
:
3209 fields
->f_disp24
= value
;
3213 /* xgettext:c-format */
3214 fprintf (stderr
, _("Unrecognized field %d while setting vma operand.\n"),