opcodes/m32r-opc.c

   1 /* Generic opcode table support for targets using CGEN. -*- C -*-
   2    CGEN: Cpu tools GENerator
   3
   4 THIS FILE IS USED TO GENERATE m32r-opc.c.
   5
   6 Copyright (C) 1998 Free Software Foundation, Inc.
   7
   8 This file is part of the GNU Binutils and GDB, the GNU debugger.
   9
  10 This program is free software; you can redistribute it and/or modify
  11 it under the terms of the GNU General Public License as published by
  12 the Free Software Foundation; either version 2, or (at your option)
  13 any later version.
  14
  15 This program is distributed in the hope that it will be useful,
  16 but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 GNU General Public License for more details.
  19
  20 You should have received a copy of the GNU General Public License
  21 along with this program; if not, write to the Free Software Foundation, Inc.,
  22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  23
  24 #include "sysdep.h"
  25 #include <stdio.h>
  26 #include "ansidecl.h"
  27 #include "libiberty.h"
  28 #include "bfd.h"
  29 #include "symcat.h"
  30 #include "m32r-opc.h"
  31 #include "opintl.h"
  32
  33 /* Look up instruction INSN_VALUE and extract its fields.
  34    INSN, if non-null, is the insn table entry.
  35    Otherwise INSN_VALUE is examined to compute it.
  36    LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
  37    0 is only valid if `insn == NULL && ! defined (CGEN_INT_INSN)'.
  38    If INSN != NULL, LENGTH must be valid.
  39    ALIAS_P is non-zero if alias insns are to be included in the search.
  40
  41    The result a pointer to the insn table entry, or NULL if the instruction
  42    wasn't recognized.  */
  43
  44 const CGEN_INSN *
  45 m32r_cgen_lookup_insn (insn, insn_value, length, fields, alias_p)
  46      const CGEN_INSN *insn;
  47      cgen_insn_t insn_value;
  48      int length;
  49      CGEN_FIELDS *fields;
  50      int alias_p;
  51 {
  52   char buf[16];
  53
  54   if (!insn)
  55     {
  56       const CGEN_INSN_LIST *insn_list;
  57
  58 #ifdef CGEN_INT_INSN
  59       switch (length)
  60         {
  61         case 8:
  62           buf[0] = insn_value;
  63           break;
  64         case 16:
  65           if (cgen_current_endian == CGEN_ENDIAN_BIG)
  66             bfd_putb16 (insn_value, buf);
  67           else
  68             bfd_putl16 (insn_value, buf);
  69           break;
  70         case 32:
  71           if (cgen_current_endian == CGEN_ENDIAN_BIG)
  72             bfd_putb32 (insn_value, buf);
  73           else
  74             bfd_putl32 (insn_value, buf);
  75           break;
  76         default:
  77           abort ();
  78         }
  79 #else
  80       abort (); /* FIXME: unfinished */
  81 #endif
  82
  83       /* The instructions are stored in hash lists.
  84          Pick the first one and keep trying until we find the right one.  */
  85
  86       insn_list = CGEN_DIS_LOOKUP_INSN (buf, insn_value);
  87       while (insn_list != NULL)
  88         {
  89           insn = insn_list->insn;
  90
  91           if (alias_p
  92               || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
  93             {
  94               /* Basic bit mask must be correct.  */
  95               /* ??? May wish to allow target to defer this check until the
  96                  extract handler.  */
  97               if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
  98                 {
  99                   /* ??? 0 is passed for `pc' */
 100                   int elength = (*CGEN_EXTRACT_FN (insn)) (insn, NULL,
 101                                                            insn_value, fields,
 102                                                            (bfd_vma) 0);
 103                   if (elength > 0)
 104                     {
 105                       /* sanity check */
 106                       if (length != 0 && length != elength)
 107                         abort ();
 108                       return insn;
 109                     }
 110                 }
 111             }
 112
 113           insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 114         }
 115     }
 116   else
 117     {
 118       /* Sanity check: can't pass an alias insn if ! alias_p.  */
 119       if (! alias_p
 120           && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
 121         abort ();
 122       /* Sanity check: length must be correct.  */
 123       if (length != CGEN_INSN_BITSIZE (insn))
 124         abort ();
 125
 126       /* ??? 0 is passed for `pc' */
 127       length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields,
 128                                           (bfd_vma) 0);
 129       /* Sanity check: must succeed.
 130          Could relax this later if it ever proves useful.  */
 131       if (length == 0)
 132         abort ();
 133       return insn;
 134     }
 135
 136   return NULL;
 137 }
 138
 139 /* Fill in the operand instances used by INSN whose operands are FIELDS.
 140    INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
 141    in.  */
 142
 143 void
 144 m32r_cgen_get_insn_operands (insn, fields, indices)
 145      const CGEN_INSN * insn;
 146      const CGEN_FIELDS * fields;
 147      int *indices;
 148 {
 149   const CGEN_OPERAND_INSTANCE *opinst;
 150   int i;
 151
 152   for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
 153        opinst != NULL
 154          && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
 155        ++i, ++opinst)
 156     {
 157       const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
 158       if (op == NULL)
 159         indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
 160       else
 161         indices[i] = m32r_cgen_get_int_operand (CGEN_OPERAND_INDEX (op),
 162                                                   fields);
 163     }
 164 }
 165
 166 /* Cover function to m32r_cgen_get_insn_operands when either INSN or FIELDS
 167    isn't known.
 168    The INSN, INSN_VALUE, and LENGTH arguments are passed to
 169    m32r_cgen_lookup_insn unchanged.
 170
 171    The result is the insn table entry or NULL if the instruction wasn't
 172    recognized.  */
 173
 174 const CGEN_INSN *
 175 m32r_cgen_lookup_get_insn_operands (insn, insn_value, length, indices)
 176      const CGEN_INSN *insn;
 177      cgen_insn_t insn_value;
 178      int length;
 179      int *indices;
 180 {
 181   CGEN_FIELDS fields;
 182
 183   /* Pass non-zero for ALIAS_P only if INSN != NULL.
 184      If INSN == NULL, we want a real insn.  */
 185   insn = m32r_cgen_lookup_insn (insn, insn_value, length, &fields,
 186                                   insn != NULL);
 187   if (! insn)
 188     return NULL;
 189
 190   m32r_cgen_get_insn_operands (insn, &fields, indices);
 191   return insn;
 192 }
 193 /* Attributes.  */
 194
 195 static const CGEN_ATTR_ENTRY MACH_attr[] =
 196 {
 197   { "m32r", MACH_M32R },
 198 /* start-sanitize-m32rx */
 199   { "m32rx", MACH_M32RX },
 200 /* end-sanitize-m32rx */
 201   { "max", MACH_MAX },
 202   { 0, 0 }
 203 };
 204
 205 /* start-sanitize-m32rx */
 206 static const CGEN_ATTR_ENTRY PIPE_attr[] =
 207 {
 208   { "NONE", PIPE_NONE },
 209   { "O", PIPE_O },
 210   { "S", PIPE_S },
 211   { "OS", PIPE_OS },
 212   { 0, 0 }
 213 };
 214
 215 /* end-sanitize-m32rx */
 216 const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
 217 {
 218   { "ABS-ADDR", NULL },
 219   { "FAKE", NULL },
 220   { "HASH-PREFIX", NULL },
 221   { "NEGATIVE", NULL },
 222   { "PCREL-ADDR", NULL },
 223   { "RELAX", NULL },
 224   { "RELOC", NULL },
 225   { "SIGN-OPT", NULL },
 226   { "UNSIGNED", NULL },
 227   { 0, 0 }
 228 };
 229
 230 const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
 231 {
 232   { "MACH", & MACH_attr[0] },
 233 /* start-sanitize-m32rx */
 234   { "PIPE", & PIPE_attr[0] },
 235 /* end-sanitize-m32rx */
 236   { "ALIAS", NULL },
 237   { "COND-CTI", NULL },
 238   { "FILL-SLOT", NULL },
 239   { "NO-DIS", NULL },
 240   { "PARALLEL", NULL },
 241   { "RELAX", NULL },
 242   { "RELAXABLE", NULL },
 243   { "SPECIAL", NULL },
 244   { "UNCOND-CTI", NULL },
 245   { 0, 0 }
 246 };
 247
 248 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_gr_entries[] =
 249 {
 250   { "fp", 13 },
 251   { "lr", 14 },
 252   { "sp", 15 },
 253   { "r0", 0 },
 254   { "r1", 1 },
 255   { "r2", 2 },
 256   { "r3", 3 },
 257   { "r4", 4 },
 258   { "r5", 5 },
 259   { "r6", 6 },
 260   { "r7", 7 },
 261   { "r8", 8 },
 262   { "r9", 9 },
 263   { "r10", 10 },
 264   { "r11", 11 },
 265   { "r12", 12 },
 266   { "r13", 13 },
 267   { "r14", 14 },
 268   { "r15", 15 }
 269 };
 270
 271 CGEN_KEYWORD m32r_cgen_opval_h_gr =
 272 {
 273   & m32r_cgen_opval_h_gr_entries[0],
 274   19
 275 };
 276
 277 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_cr_entries[] =
 278 {
 279   { "psw", 0 },
 280   { "cbr", 1 },
 281   { "spi", 2 },
 282   { "spu", 3 },
 283   { "bpc", 6 },
 284   { "cr0", 0 },
 285   { "cr1", 1 },
 286   { "cr2", 2 },
 287   { "cr3", 3 },
 288   { "cr4", 4 },
 289   { "cr5", 5 },
 290   { "cr6", 6 },
 291   { "cr7", 7 },
 292   { "cr8", 8 },
 293   { "cr9", 9 },
 294   { "cr10", 10 },
 295   { "cr11", 11 },
 296   { "cr12", 12 },
 297   { "cr13", 13 },
 298   { "cr14", 14 },
 299   { "cr15", 15 }
 300 };
 301
 302 CGEN_KEYWORD m32r_cgen_opval_h_cr =
 303 {
 304   & m32r_cgen_opval_h_cr_entries[0],
 305   21
 306 };
 307
 308 /* start-sanitize-m32rx */
 309 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
 310 {
 311   { "a0", 0 },
 312   { "a1", 1 }
 313 };
 314
 315 CGEN_KEYWORD m32r_cgen_opval_h_accums =
 316 {
 317   & m32r_cgen_opval_h_accums_entries[0],
 318   2
 319 };
 320
 321 /* end-sanitize-m32rx */
 322
 323 /* The hardware table.  */
 324
 325 #define HW_ENT(n) m32r_cgen_hw_entries[n]
 326 static const CGEN_HW_ENTRY m32r_cgen_hw_entries[] =
 327 {
 328   { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0 },
 329   { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0 },
 330   { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0 },
 331   { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0 },
 332   { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0 },
 333   { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0 },
 334   { HW_H_HI16, & HW_ENT (HW_H_HI16 + 1), "h-hi16", CGEN_ASM_KEYWORD, (PTR) 0 },
 335   { HW_H_SLO16, & HW_ENT (HW_H_SLO16 + 1), "h-slo16", CGEN_ASM_KEYWORD, (PTR) 0 },
 336   { HW_H_ULO16, & HW_ENT (HW_H_ULO16 + 1), "h-ulo16", CGEN_ASM_KEYWORD, (PTR) 0 },
 337   { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_gr },
 338   { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_cr },
 339   { HW_H_ACCUM, & HW_ENT (HW_H_ACCUM + 1), "h-accum", CGEN_ASM_KEYWORD, (PTR) 0 },
 340 /* start-sanitize-m32rx */
 341   { HW_H_ACCUMS, & HW_ENT (HW_H_ACCUMS + 1), "h-accums", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums },
 342 /* end-sanitize-m32rx */
 343   { HW_H_COND, & HW_ENT (HW_H_COND + 1), "h-cond", CGEN_ASM_KEYWORD, (PTR) 0 },
 344   { HW_H_SM, & HW_ENT (HW_H_SM + 1), "h-sm", CGEN_ASM_KEYWORD, (PTR) 0 },
 345   { HW_H_BSM, & HW_ENT (HW_H_BSM + 1), "h-bsm", CGEN_ASM_KEYWORD, (PTR) 0 },
 346   { HW_H_IE, & HW_ENT (HW_H_IE + 1), "h-ie", CGEN_ASM_KEYWORD, (PTR) 0 },
 347   { HW_H_BIE, & HW_ENT (HW_H_BIE + 1), "h-bie", CGEN_ASM_KEYWORD, (PTR) 0 },
 348   { HW_H_BCOND, & HW_ENT (HW_H_BCOND + 1), "h-bcond", CGEN_ASM_KEYWORD, (PTR) 0 },
 349   { HW_H_BPC, & HW_ENT (HW_H_BPC + 1), "h-bpc", CGEN_ASM_KEYWORD, (PTR) 0 },
 350   { HW_H_LOCK, & HW_ENT (HW_H_LOCK + 1), "h-lock", CGEN_ASM_KEYWORD, (PTR) 0 },
 351   { 0 }
 352 };
 353
 354 /* The operand table.  */
 355
 356 #define OPERAND(op) CONCAT2 (M32R_OPERAND_,op)
 357 #define OP_ENT(op) m32r_cgen_operand_table[OPERAND (op)]
 358
 359 const CGEN_OPERAND m32r_cgen_operand_table[MAX_OPERANDS] =
 360 {
 361 /* pc: program counter */
 362   { "pc", & HW_ENT (HW_H_PC), 0, 0,
 363     { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } }  },
 364 /* sr: source register */
 365   { "sr", & HW_ENT (HW_H_GR), 12, 4,
 366     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 367 /* dr: destination register */
 368   { "dr", & HW_ENT (HW_H_GR), 4, 4,
 369     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 370 /* src1: source register 1 */
 371   { "src1", & HW_ENT (HW_H_GR), 4, 4,
 372     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 373 /* src2: source register 2 */
 374   { "src2", & HW_ENT (HW_H_GR), 12, 4,
 375     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 376 /* scr: source control register */
 377   { "scr", & HW_ENT (HW_H_CR), 12, 4,
 378     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 379 /* dcr: destination control register */
 380   { "dcr", & HW_ENT (HW_H_CR), 4, 4,
 381     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 382 /* simm8: 8 bit signed immediate */
 383   { "simm8", & HW_ENT (HW_H_SINT), 8, 8,
 384     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { 0 } }  },
 385 /* simm16: 16 bit signed immediate */
 386   { "simm16", & HW_ENT (HW_H_SINT), 16, 16,
 387     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { 0 } }  },
 388 /* uimm4: 4 bit trap number */
 389   { "uimm4", & HW_ENT (HW_H_UINT), 12, 4,
 390     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 391 /* uimm5: 5 bit shift count */
 392   { "uimm5", & HW_ENT (HW_H_UINT), 11, 5,
 393     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 394 /* uimm16: 16 bit unsigned immediate */
 395   { "uimm16", & HW_ENT (HW_H_UINT), 16, 16,
 396     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 397 /* start-sanitize-m32rx */
 398 /* imm1: 1 bit immediate */
 399   { "imm1", & HW_ENT (HW_H_UINT), 15, 1,
 400     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 401 /* end-sanitize-m32rx */
 402 /* start-sanitize-m32rx */
 403 /* accd: accumulator destination register */
 404   { "accd", & HW_ENT (HW_H_ACCUMS), 4, 2,
 405     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 406 /* end-sanitize-m32rx */
 407 /* start-sanitize-m32rx */
 408 /* accs: accumulator source register */
 409   { "accs", & HW_ENT (HW_H_ACCUMS), 12, 2,
 410     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 411 /* end-sanitize-m32rx */
 412 /* start-sanitize-m32rx */
 413 /* acc: accumulator reg (d) */
 414   { "acc", & HW_ENT (HW_H_ACCUMS), 8, 1,
 415     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 416 /* end-sanitize-m32rx */
 417 /* hash: # prefix */
 418   { "hash", & HW_ENT (HW_H_SINT), 0, 0,
 419     { 0, 0, { 0 } }  },
 420 /* hi16: high 16 bit immediate, sign optional */
 421   { "hi16", & HW_ENT (HW_H_HI16), 16, 16,
 422     { 0, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 423 /* slo16: 16 bit signed immediate, for low() */
 424   { "slo16", & HW_ENT (HW_H_SLO16), 16, 16,
 425     { 0, 0, { 0 } }  },
 426 /* ulo16: 16 bit unsigned immediate, for low() */
 427   { "ulo16", & HW_ENT (HW_H_ULO16), 16, 16,
 428     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 429 /* uimm24: 24 bit address */
 430   { "uimm24", & HW_ENT (HW_H_ADDR), 8, 24,
 431     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 432 /* disp8: 8 bit displacement */
 433   { "disp8", & HW_ENT (HW_H_IADDR), 8, 8,
 434     { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
 435 /* disp16: 16 bit displacement */
 436   { "disp16", & HW_ENT (HW_H_IADDR), 16, 16,
 437     { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
 438 /* disp24: 24 bit displacement */
 439   { "disp24", & HW_ENT (HW_H_IADDR), 8, 24,
 440     { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
 441 /* condbit: condition bit */
 442   { "condbit", & HW_ENT (HW_H_COND), 0, 0,
 443     { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } }  },
 444 /* accum: accumulator */
 445   { "accum", & HW_ENT (HW_H_ACCUM), 0, 0,
 446     { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } }  },
 447 };
 448
 449 /* Operand references.  */
 450
 451 #define INPUT CGEN_OPERAND_INSTANCE_INPUT
 452 #define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
 453
 454 static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = {
 455   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 456   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 457   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 458   { 0 }
 459 };
 460
 461 static const CGEN_OPERAND_INSTANCE fmt_add3_ops[] = {
 462   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 463   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 464   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 465   { 0 }
 466 };
 467
 468 static const CGEN_OPERAND_INSTANCE fmt_and3_ops[] = {
 469   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 470   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0 },
 471   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 472   { 0 }
 473 };
 474
 475 static const CGEN_OPERAND_INSTANCE fmt_or3_ops[] = {
 476   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 477   { INPUT, & HW_ENT (HW_H_ULO16), CGEN_MODE_UHI, & OP_ENT (ULO16), 0 },
 478   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 479   { 0 }
 480 };
 481
 482 static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = {
 483   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 484   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
 485   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 486   { 0 }
 487 };
 488
 489 static const CGEN_OPERAND_INSTANCE fmt_addv_ops[] = {
 490   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 491   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 492   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 493   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 494   { 0 }
 495 };
 496
 497 static const CGEN_OPERAND_INSTANCE fmt_addv3_ops[] = {
 498   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 499   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
 500   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 501   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 502   { 0 }
 503 };
 504
 505 static const CGEN_OPERAND_INSTANCE fmt_addx_ops[] = {
 506   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 507   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 508   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 509   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 510   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 511   { 0 }
 512 };
 513
 514 static const CGEN_OPERAND_INSTANCE fmt_bc8_ops[] = {
 515   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 516   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
 517   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 518   { 0 }
 519 };
 520
 521 static const CGEN_OPERAND_INSTANCE fmt_bc24_ops[] = {
 522   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 523   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
 524   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 525   { 0 }
 526 };
 527
 528 static const CGEN_OPERAND_INSTANCE fmt_beq_ops[] = {
 529   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 530   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 531   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0 },
 532   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 533   { 0 }
 534 };
 535
 536 static const CGEN_OPERAND_INSTANCE fmt_beqz_ops[] = {
 537   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 538   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0 },
 539   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 540   { 0 }
 541 };
 542
 543 static const CGEN_OPERAND_INSTANCE fmt_bl8_ops[] = {
 544   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 545   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
 546   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 547   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 548   { 0 }
 549 };
 550
 551 static const CGEN_OPERAND_INSTANCE fmt_bl24_ops[] = {
 552   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 553   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
 554   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 555   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 556   { 0 }
 557 };
 558
 559 /* start-sanitize-m32rx */
 560 static const CGEN_OPERAND_INSTANCE fmt_bcl8_ops[] = {
 561   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 562   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 563   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
 564   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 565   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 566   { 0 }
 567 };
 568
 569 /* end-sanitize-m32rx */
 570 /* start-sanitize-m32rx */
 571 static const CGEN_OPERAND_INSTANCE fmt_bcl24_ops[] = {
 572   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 573   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 574   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
 575   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 576   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 577   { 0 }
 578 };
 579
 580 /* end-sanitize-m32rx */
 581 static const CGEN_OPERAND_INSTANCE fmt_bra8_ops[] = {
 582   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
 583   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 584   { 0 }
 585 };
 586
 587 static const CGEN_OPERAND_INSTANCE fmt_bra24_ops[] = {
 588   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
 589   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 590   { 0 }
 591 };
 592
 593 static const CGEN_OPERAND_INSTANCE fmt_cmp_ops[] = {
 594   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 595   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 596   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 597   { 0 }
 598 };
 599
 600 static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
 601   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 602   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
 603   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 604   { 0 }
 605 };
 606
 607 /* start-sanitize-m32rx */
 608 static const CGEN_OPERAND_INSTANCE fmt_cmpz_ops[] = {
 609   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 610   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 611   { 0 }
 612 };
 613
 614 /* end-sanitize-m32rx */
 615 static const CGEN_OPERAND_INSTANCE fmt_div_ops[] = {
 616   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 617   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 618   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 619   { 0 }
 620 };
 621
 622 /* start-sanitize-m32rx */
 623 static const CGEN_OPERAND_INSTANCE fmt_jc_ops[] = {
 624   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 625   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 626   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 627   { 0 }
 628 };
 629
 630 /* end-sanitize-m32rx */
 631 static const CGEN_OPERAND_INSTANCE fmt_jl_ops[] = {
 632   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 633   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 634   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 635   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 636   { 0 }
 637 };
 638
 639 static const CGEN_OPERAND_INSTANCE fmt_jmp_ops[] = {
 640   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 641   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 642   { 0 }
 643 };
 644
 645 static const CGEN_OPERAND_INSTANCE fmt_ld_ops[] = {
 646   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 647   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
 648   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 649   { 0 }
 650 };
 651
 652 static const CGEN_OPERAND_INSTANCE fmt_ld_d_ops[] = {
 653   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 654   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 655   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 656   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 657   { 0 }
 658 };
 659
 660 static const CGEN_OPERAND_INSTANCE fmt_ldb_ops[] = {
 661   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 662   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
 663   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 664   { 0 }
 665 };
 666
 667 static const CGEN_OPERAND_INSTANCE fmt_ldb_d_ops[] = {
 668   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 669   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 670   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 671   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 672   { 0 }
 673 };
 674
 675 static const CGEN_OPERAND_INSTANCE fmt_ldh_ops[] = {
 676   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 677   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
 678   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 679   { 0 }
 680 };
 681
 682 static const CGEN_OPERAND_INSTANCE fmt_ldh_d_ops[] = {
 683   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 684   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 685   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 686   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 687   { 0 }
 688 };
 689
 690 static const CGEN_OPERAND_INSTANCE fmt_ld_plus_ops[] = {
 691   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 692   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 693   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 694   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 695   { 0 }
 696 };
 697
 698 static const CGEN_OPERAND_INSTANCE fmt_ld24_ops[] = {
 699   { INPUT, & HW_ENT (HW_H_ADDR), CGEN_MODE_USI, & OP_ENT (UIMM24), 0 },
 700   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 701   { 0 }
 702 };
 703
 704 static const CGEN_OPERAND_INSTANCE fmt_ldi8_ops[] = {
 705   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
 706   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 707   { 0 }
 708 };
 709
 710 static const CGEN_OPERAND_INSTANCE fmt_ldi16_ops[] = {
 711   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 712   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 713   { 0 }
 714 };
 715
 716 static const CGEN_OPERAND_INSTANCE fmt_lock_ops[] = {
 717   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 718   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
 719   { OUTPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
 720   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 721   { 0 }
 722 };
 723
 724 static const CGEN_OPERAND_INSTANCE fmt_machi_ops[] = {
 725   { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 726   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 727   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 728   { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 729   { 0 }
 730 };
 731
 732 /* start-sanitize-m32rx */
 733 static const CGEN_OPERAND_INSTANCE fmt_machi_a_ops[] = {
 734   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
 735   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 736   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 737   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
 738   { 0 }
 739 };
 740
 741 /* end-sanitize-m32rx */
 742 static const CGEN_OPERAND_INSTANCE fmt_mulhi_ops[] = {
 743   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 744   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 745   { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 746   { 0 }
 747 };
 748
 749 /* start-sanitize-m32rx */
 750 static const CGEN_OPERAND_INSTANCE fmt_mulhi_a_ops[] = {
 751   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 752   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 753   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
 754   { 0 }
 755 };
 756
 757 /* end-sanitize-m32rx */
 758 static const CGEN_OPERAND_INSTANCE fmt_mv_ops[] = {
 759   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 760   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 761   { 0 }
 762 };
 763
 764 static const CGEN_OPERAND_INSTANCE fmt_mvfachi_ops[] = {
 765   { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 766   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 767   { 0 }
 768 };
 769
 770 /* start-sanitize-m32rx */
 771 static const CGEN_OPERAND_INSTANCE fmt_mvfachi_a_ops[] = {
 772   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 773   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 774   { 0 }
 775 };
 776
 777 /* end-sanitize-m32rx */
 778 static const CGEN_OPERAND_INSTANCE fmt_mvfc_ops[] = {
 779   { INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (SCR), 0 },
 780   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 781   { 0 }
 782 };
 783
 784 static const CGEN_OPERAND_INSTANCE fmt_mvtachi_ops[] = {
 785   { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 786   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 787   { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 788   { 0 }
 789 };
 790
 791 /* start-sanitize-m32rx */
 792 static const CGEN_OPERAND_INSTANCE fmt_mvtachi_a_ops[] = {
 793   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 794   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 795   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 796   { 0 }
 797 };
 798
 799 /* end-sanitize-m32rx */
 800 static const CGEN_OPERAND_INSTANCE fmt_mvtc_ops[] = {
 801   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 802   { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (DCR), 0 },
 803   { 0 }
 804 };
 805
 806 static const CGEN_OPERAND_INSTANCE fmt_rac_ops[] = {
 807   { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 808   { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 809   { 0 }
 810 };
 811
 812 /* start-sanitize-m32rx */
 813 static const CGEN_OPERAND_INSTANCE fmt_rac_dsi_ops[] = {
 814   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 815   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (IMM1), 0 },
 816   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0 },
 817   { 0 }
 818 };
 819
 820 /* end-sanitize-m32rx */
 821 static const CGEN_OPERAND_INSTANCE fmt_rte_ops[] = {
 822   { INPUT, & HW_ENT (HW_H_BSM), CGEN_MODE_UBI, 0, 0 },
 823   { INPUT, & HW_ENT (HW_H_BIE), CGEN_MODE_UBI, 0, 0 },
 824   { INPUT, & HW_ENT (HW_H_BCOND), CGEN_MODE_UBI, 0, 0 },
 825   { INPUT, & HW_ENT (HW_H_BPC), CGEN_MODE_SI, 0, 0 },
 826   { OUTPUT, & HW_ENT (HW_H_SM), CGEN_MODE_UBI, 0, 0 },
 827   { OUTPUT, & HW_ENT (HW_H_IE), CGEN_MODE_UBI, 0, 0 },
 828   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 829   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 830   { 0 }
 831 };
 832
 833 static const CGEN_OPERAND_INSTANCE fmt_seth_ops[] = {
 834   { INPUT, & HW_ENT (HW_H_HI16), CGEN_MODE_SI, & OP_ENT (HI16), 0 },
 835   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 836   { 0 }
 837 };
 838
 839 static const CGEN_OPERAND_INSTANCE fmt_sll3_ops[] = {
 840   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 841   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
 842   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 843   { 0 }
 844 };
 845
 846 static const CGEN_OPERAND_INSTANCE fmt_slli_ops[] = {
 847   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 848   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM5), 0 },
 849   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 850   { 0 }
 851 };
 852
 853 static const CGEN_OPERAND_INSTANCE fmt_st_ops[] = {
 854   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
 855   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 856   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 857   { 0 }
 858 };
 859
 860 static const CGEN_OPERAND_INSTANCE fmt_st_d_ops[] = {
 861   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 862   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 863   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 864   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 865   { 0 }
 866 };
 867
 868 static const CGEN_OPERAND_INSTANCE fmt_stb_ops[] = {
 869   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
 870   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (SRC1), 0 },
 871   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 872   { 0 }
 873 };
 874
 875 static const CGEN_OPERAND_INSTANCE fmt_stb_d_ops[] = {
 876   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 877   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 878   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (SRC1), 0 },
 879   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 880   { 0 }
 881 };
 882
 883 static const CGEN_OPERAND_INSTANCE fmt_sth_ops[] = {
 884   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
 885   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (SRC1), 0 },
 886   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 887   { 0 }
 888 };
 889
 890 static const CGEN_OPERAND_INSTANCE fmt_sth_d_ops[] = {
 891   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 892   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 893   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (SRC1), 0 },
 894   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 895   { 0 }
 896 };
 897
 898 static const CGEN_OPERAND_INSTANCE fmt_st_plus_ops[] = {
 899   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 900   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 901   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 902   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 903   { 0 }
 904 };
 905
 906 static const CGEN_OPERAND_INSTANCE fmt_trap_ops[] = {
 907   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 908   { INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 0 },
 909   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (UIMM4), 0 },
 910   { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6 },
 911   { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 0 },
 912   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0 },
 913   { 0 }
 914 };
 915
 916 static const CGEN_OPERAND_INSTANCE fmt_unlock_ops[] = {
 917   { INPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
 918   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
 919   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 920   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 921   { OUTPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
 922   { 0 }
 923 };
 924
 925 /* start-sanitize-m32rx */
 926 static const CGEN_OPERAND_INSTANCE fmt_satb_ops[] = {
 927   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 928   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 929   { 0 }
 930 };
 931
 932 /* end-sanitize-m32rx */
 933 /* start-sanitize-m32rx */
 934 static const CGEN_OPERAND_INSTANCE fmt_sat_ops[] = {
 935   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 936   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 937   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 938   { 0 }
 939 };
 940
 941 /* end-sanitize-m32rx */
 942 /* start-sanitize-m32rx */
 943 static const CGEN_OPERAND_INSTANCE fmt_sadd_ops[] = {
 944   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
 945   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
 946   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
 947   { 0 }
 948 };
 949
 950 /* end-sanitize-m32rx */
 951 /* start-sanitize-m32rx */
 952 static const CGEN_OPERAND_INSTANCE fmt_macwu1_ops[] = {
 953   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
 954   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 955   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 956   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
 957   { 0 }
 958 };
 959
 960 /* end-sanitize-m32rx */
 961 /* start-sanitize-m32rx */
 962 static const CGEN_OPERAND_INSTANCE fmt_mulwu1_ops[] = {
 963   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 964   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 965   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
 966   { 0 }
 967 };
 968
 969 /* end-sanitize-m32rx */
 970 /* start-sanitize-m32rx */
 971 static const CGEN_OPERAND_INSTANCE fmt_sc_ops[] = {
 972   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 973   { 0 }
 974 };
 975
 976 /* end-sanitize-m32rx */
 977 #undef INPUT
 978 #undef OUTPUT
 979
 980 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
 981 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
 982 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
 983
 984 /* The instruction table.
 985    This is currently non-static because the simulator accesses it
 986    directly.  */
 987
 988 const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
 989 {
 990   /* Special null first entry.
 991      A `num' value of zero is thus illegal.
 992      Also, the special `illegal' insn resides here.  */
 993   { { 0 }, 0 },
 994 /* add $dr,$sr */
 995   {
 996     { 1, 1, 1, 1 },
 997     M32R_INSN_ADD, "add", "add",
 998     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
 999     { 16, 16, 0xf0f0 }, 0xa0,
1000     (PTR) & fmt_add_ops[0],
1001     { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
1002   },
1003 /* add3 $dr,$sr,$hash$slo16 */
1004   {
1005     { 1, 1, 1, 1 },
1006     M32R_INSN_ADD3, "add3", "add3",
1007     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (SLO16), 0 } },
1008     { 32, 32, 0xf0f00000 }, 0x80a00000,
1009     (PTR) & fmt_add3_ops[0],
1010     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1011   },
1012 /* and $dr,$sr */
1013   {
1014     { 1, 1, 1, 1 },
1015     M32R_INSN_AND, "and", "and",
1016     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1017     { 16, 16, 0xf0f0 }, 0xc0,
1018     (PTR) & fmt_add_ops[0],
1019     { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
1020   },
1021 /* and3 $dr,$sr,$uimm16 */
1022   {
1023     { 1, 1, 1, 1 },
1024     M32R_INSN_AND3, "and3", "and3",
1025     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
1026     { 32, 32, 0xf0f00000 }, 0x80c00000,
1027     (PTR) & fmt_and3_ops[0],
1028     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1029   },
1030 /* or $dr,$sr */
1031   {
1032     { 1, 1, 1, 1 },
1033     M32R_INSN_OR, "or", "or",
1034     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1035     { 16, 16, 0xf0f0 }, 0xe0,
1036     (PTR) & fmt_add_ops[0],
1037     { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
1038   },
1039 /* or3 $dr,$sr,$hash$ulo16 */
1040   {
1041     { 1, 1, 1, 1 },
1042     M32R_INSN_OR3, "or3", "or3",
1043     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (ULO16), 0 } },
1044     { 32, 32, 0xf0f00000 }, 0x80e00000,
1045     (PTR) & fmt_or3_ops[0],
1046     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1047   },
1048 /* xor $dr,$sr */
1049   {
1050     { 1, 1, 1, 1 },
1051     M32R_INSN_XOR, "xor", "xor",
1052     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1053     { 16, 16, 0xf0f0 }, 0xd0,
1054     (PTR) & fmt_add_ops[0],
1055     { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
1056   },
1057 /* xor3 $dr,$sr,$uimm16 */
1058   {
1059     { 1, 1, 1, 1 },
1060     M32R_INSN_XOR3, "xor3", "xor3",
1061     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
1062     { 32, 32, 0xf0f00000 }, 0x80d00000,
1063     (PTR) & fmt_and3_ops[0],
1064     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1065   },
1066 /* addi $dr,$simm8 */
1067   {
1068     { 1, 1, 1, 1 },
1069     M32R_INSN_ADDI, "addi", "addi",
1070     { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
1071     { 16, 16, 0xf000 }, 0x4000,
1072     (PTR) & fmt_addi_ops[0],
1073     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1074   },
1075 /* addv $dr,$sr */
1076   {
1077     { 1, 1, 1, 1 },
1078     M32R_INSN_ADDV, "addv", "addv",
1079     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1080     { 16, 16, 0xf0f0 }, 0x80,
1081     (PTR) & fmt_addv_ops[0],
1082     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1083   },
1084 /* addv3 $dr,$sr,$simm16 */
1085   {
1086     { 1, 1, 1, 1 },
1087     M32R_INSN_ADDV3, "addv3", "addv3",
1088     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
1089     { 32, 32, 0xf0f00000 }, 0x80800000,
1090     (PTR) & fmt_addv3_ops[0],
1091     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1092   },
1093 /* addx $dr,$sr */
1094   {
1095     { 1, 1, 1, 1 },
1096     M32R_INSN_ADDX, "addx", "addx",
1097     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1098     { 16, 16, 0xf0f0 }, 0x90,
1099     (PTR) & fmt_addx_ops[0],
1100     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1101   },
1102 /* bc.s $disp8 */
1103   {
1104     { 1, 1, 1, 1 },
1105     M32R_INSN_BC8, "bc8", "bc.s",
1106     { { MNEM, ' ', OP (DISP8), 0 } },
1107     { 16, 16, 0xff00 }, 0x7c00,
1108     (PTR) & fmt_bc8_ops[0],
1109     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
1110   },
1111 /* bc.l $disp24 */
1112   {
1113     { 1, 1, 1, 1 },
1114     M32R_INSN_BC24, "bc24", "bc.l",
1115     { { MNEM, ' ', OP (DISP24), 0 } },
1116     { 32, 32, 0xff000000 }, 0xfc000000,
1117     (PTR) & fmt_bc24_ops[0],
1118     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1119   },
1120 /* beq $src1,$src2,$disp16 */
1121   {
1122     { 1, 1, 1, 1 },
1123     M32R_INSN_BEQ, "beq", "beq",
1124     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
1125     { 32, 32, 0xf0f00000 }, 0xb0000000,
1126     (PTR) & fmt_beq_ops[0],
1127     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1128   },
1129 /* beqz $src2,$disp16 */
1130   {
1131     { 1, 1, 1, 1 },
1132     M32R_INSN_BEQZ, "beqz", "beqz",
1133     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
1134     { 32, 32, 0xfff00000 }, 0xb0800000,
1135     (PTR) & fmt_beqz_ops[0],
1136     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1137   },
1138 /* bgez $src2,$disp16 */
1139   {
1140     { 1, 1, 1, 1 },
1141     M32R_INSN_BGEZ, "bgez", "bgez",
1142     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
1143     { 32, 32, 0xfff00000 }, 0xb0b00000,
1144     (PTR) & fmt_beqz_ops[0],
1145     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1146   },
1147 /* bgtz $src2,$disp16 */
1148   {
1149     { 1, 1, 1, 1 },
1150     M32R_INSN_BGTZ, "bgtz", "bgtz",
1151     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
1152     { 32, 32, 0xfff00000 }, 0xb0d00000,
1153     (PTR) & fmt_beqz_ops[0],
1154     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1155   },
1156 /* blez $src2,$disp16 */
1157   {
1158     { 1, 1, 1, 1 },
1159     M32R_INSN_BLEZ, "blez", "blez",
1160     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
1161     { 32, 32, 0xfff00000 }, 0xb0c00000,
1162     (PTR) & fmt_beqz_ops[0],
1163     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1164   },
1165 /* bltz $src2,$disp16 */
1166   {
1167     { 1, 1, 1, 1 },
1168     M32R_INSN_BLTZ, "bltz", "bltz",
1169     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
1170     { 32, 32, 0xfff00000 }, 0xb0a00000,
1171     (PTR) & fmt_beqz_ops[0],
1172     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1173   },
1174 /* bnez $src2,$disp16 */
1175   {
1176     { 1, 1, 1, 1 },
1177     M32R_INSN_BNEZ, "bnez", "bnez",
1178     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
1179     { 32, 32, 0xfff00000 }, 0xb0900000,
1180     (PTR) & fmt_beqz_ops[0],
1181     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1182   },
1183 /* bl.s $disp8 */
1184   {
1185     { 1, 1, 1, 1 },
1186     M32R_INSN_BL8, "bl8", "bl.s",
1187     { { MNEM, ' ', OP (DISP8), 0 } },
1188     { 16, 16, 0xff00 }, 0x7e00,
1189     (PTR) & fmt_bl8_ops[0],
1190     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1191   },
1192 /* bl.l $disp24 */
1193   {
1194     { 1, 1, 1, 1 },
1195     M32R_INSN_BL24, "bl24", "bl.l",
1196     { { MNEM, ' ', OP (DISP24), 0 } },
1197     { 32, 32, 0xff000000 }, 0xfe000000,
1198     (PTR) & fmt_bl24_ops[0],
1199     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1200   },
1201 /* start-sanitize-m32rx */
1202 /* bcl.s $disp8 */
1203   {
1204     { 1, 1, 1, 1 },
1205     M32R_INSN_BCL8, "bcl8", "bcl.s",
1206     { { MNEM, ' ', OP (DISP8), 0 } },
1207     { 16, 16, 0xff00 }, 0x7800,
1208     (PTR) & fmt_bcl8_ops[0],
1209     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1210   },
1211 /* end-sanitize-m32rx */
1212 /* start-sanitize-m32rx */
1213 /* bcl.l $disp24 */
1214   {
1215     { 1, 1, 1, 1 },
1216     M32R_INSN_BCL24, "bcl24", "bcl.l",
1217     { { MNEM, ' ', OP (DISP24), 0 } },
1218     { 32, 32, 0xff000000 }, 0xf8000000,
1219     (PTR) & fmt_bcl24_ops[0],
1220     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1221   },
1222 /* end-sanitize-m32rx */
1223 /* bnc.s $disp8 */
1224   {
1225     { 1, 1, 1, 1 },
1226     M32R_INSN_BNC8, "bnc8", "bnc.s",
1227     { { MNEM, ' ', OP (DISP8), 0 } },
1228     { 16, 16, 0xff00 }, 0x7d00,
1229     (PTR) & fmt_bc8_ops[0],
1230     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
1231   },
1232 /* bnc.l $disp24 */
1233   {
1234     { 1, 1, 1, 1 },
1235     M32R_INSN_BNC24, "bnc24", "bnc.l",
1236     { { MNEM, ' ', OP (DISP24), 0 } },
1237     { 32, 32, 0xff000000 }, 0xfd000000,
1238     (PTR) & fmt_bc24_ops[0],
1239     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1240   },
1241 /* bne $src1,$src2,$disp16 */
1242   {
1243     { 1, 1, 1, 1 },
1244     M32R_INSN_BNE, "bne", "bne",
1245     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
1246     { 32, 32, 0xf0f00000 }, 0xb0100000,
1247     (PTR) & fmt_beq_ops[0],
1248     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1249   },
1250 /* bra.s $disp8 */
1251   {
1252     { 1, 1, 1, 1 },
1253     M32R_INSN_BRA8, "bra8", "bra.s",
1254     { { MNEM, ' ', OP (DISP8), 0 } },
1255     { 16, 16, 0xff00 }, 0x7f00,
1256     (PTR) & fmt_bra8_ops[0],
1257     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1258   },
1259 /* bra.l $disp24 */
1260   {
1261     { 1, 1, 1, 1 },
1262     M32R_INSN_BRA24, "bra24", "bra.l",
1263     { { MNEM, ' ', OP (DISP24), 0 } },
1264     { 32, 32, 0xff000000 }, 0xff000000,
1265     (PTR) & fmt_bra24_ops[0],
1266     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1267   },
1268 /* start-sanitize-m32rx */
1269 /* bncl.s $disp8 */
1270   {
1271     { 1, 1, 1, 1 },
1272     M32R_INSN_BNCL8, "bncl8", "bncl.s",
1273     { { MNEM, ' ', OP (DISP8), 0 } },
1274     { 16, 16, 0xff00 }, 0x7900,
1275     (PTR) & fmt_bcl8_ops[0],
1276     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1277   },
1278 /* end-sanitize-m32rx */
1279 /* start-sanitize-m32rx */
1280 /* bncl.l $disp24 */
1281   {
1282     { 1, 1, 1, 1 },
1283     M32R_INSN_BNCL24, "bncl24", "bncl.l",
1284     { { MNEM, ' ', OP (DISP24), 0 } },
1285     { 32, 32, 0xff000000 }, 0xf9000000,
1286     (PTR) & fmt_bcl24_ops[0],
1287     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1288   },
1289 /* end-sanitize-m32rx */
1290 /* cmp $src1,$src2 */
1291   {
1292     { 1, 1, 1, 1 },
1293     M32R_INSN_CMP, "cmp", "cmp",
1294     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1295     { 16, 16, 0xf0f0 }, 0x40,
1296     (PTR) & fmt_cmp_ops[0],
1297     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1298   },
1299 /* cmpi $src2,$simm16 */
1300   {
1301     { 1, 1, 1, 1 },
1302     M32R_INSN_CMPI, "cmpi", "cmpi",
1303     { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
1304     { 32, 32, 0xfff00000 }, 0x80400000,
1305     (PTR) & fmt_cmpi_ops[0],
1306     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1307   },
1308 /* cmpu $src1,$src2 */
1309   {
1310     { 1, 1, 1, 1 },
1311     M32R_INSN_CMPU, "cmpu", "cmpu",
1312     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1313     { 16, 16, 0xf0f0 }, 0x50,
1314     (PTR) & fmt_cmp_ops[0],
1315     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1316   },
1317 /* cmpui $src2,$simm16 */
1318   {
1319     { 1, 1, 1, 1 },
1320     M32R_INSN_CMPUI, "cmpui", "cmpui",
1321     { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
1322     { 32, 32, 0xfff00000 }, 0x80500000,
1323     (PTR) & fmt_cmpi_ops[0],
1324     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1325   },
1326 /* start-sanitize-m32rx */
1327 /* cmpeq $src1,$src2 */
1328   {
1329     { 1, 1, 1, 1 },
1330     M32R_INSN_CMPEQ, "cmpeq", "cmpeq",
1331     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1332     { 16, 16, 0xf0f0 }, 0x60,
1333     (PTR) & fmt_cmp_ops[0],
1334     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
1335   },
1336 /* end-sanitize-m32rx */
1337 /* start-sanitize-m32rx */
1338 /* cmpz $src2 */
1339   {
1340     { 1, 1, 1, 1 },
1341     M32R_INSN_CMPZ, "cmpz", "cmpz",
1342     { { MNEM, ' ', OP (SRC2), 0 } },
1343     { 16, 16, 0xfff0 }, 0x70,
1344     (PTR) & fmt_cmpz_ops[0],
1345     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
1346   },
1347 /* end-sanitize-m32rx */
1348 /* div $dr,$sr */
1349   {
1350     { 1, 1, 1, 1 },
1351     M32R_INSN_DIV, "div", "div",
1352     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1353     { 32, 32, 0xf0f0ffff }, 0x90000000,
1354     (PTR) & fmt_div_ops[0],
1355     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1356   },
1357 /* divu $dr,$sr */
1358   {
1359     { 1, 1, 1, 1 },
1360     M32R_INSN_DIVU, "divu", "divu",
1361     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1362     { 32, 32, 0xf0f0ffff }, 0x90100000,
1363     (PTR) & fmt_div_ops[0],
1364     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1365   },
1366 /* rem $dr,$sr */
1367   {
1368     { 1, 1, 1, 1 },
1369     M32R_INSN_REM, "rem", "rem",
1370     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1371     { 32, 32, 0xf0f0ffff }, 0x90200000,
1372     (PTR) & fmt_div_ops[0],
1373     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1374   },
1375 /* remu $dr,$sr */
1376   {
1377     { 1, 1, 1, 1 },
1378     M32R_INSN_REMU, "remu", "remu",
1379     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1380     { 32, 32, 0xf0f0ffff }, 0x90300000,
1381     (PTR) & fmt_div_ops[0],
1382     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1383   },
1384 /* start-sanitize-m32rx */
1385 /* divh $dr,$sr */
1386   {
1387     { 1, 1, 1, 1 },
1388     M32R_INSN_DIVH, "divh", "divh",
1389     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1390     { 32, 32, 0xf0f0ffff }, 0x90000010,
1391     (PTR) & fmt_div_ops[0],
1392     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
1393   },
1394 /* end-sanitize-m32rx */
1395 /* start-sanitize-m32rx */
1396 /* jc $sr */
1397   {
1398     { 1, 1, 1, 1 },
1399     M32R_INSN_JC, "jc", "jc",
1400     { { MNEM, ' ', OP (SR), 0 } },
1401     { 16, 16, 0xfff0 }, 0x1cc0,
1402     (PTR) & fmt_jc_ops[0],
1403     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1404   },
1405 /* end-sanitize-m32rx */
1406 /* start-sanitize-m32rx */
1407 /* jnc $sr */
1408   {
1409     { 1, 1, 1, 1 },
1410     M32R_INSN_JNC, "jnc", "jnc",
1411     { { MNEM, ' ', OP (SR), 0 } },
1412     { 16, 16, 0xfff0 }, 0x1dc0,
1413     (PTR) & fmt_jc_ops[0],
1414     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1415   },
1416 /* end-sanitize-m32rx */
1417 /* jl $sr */
1418   {
1419     { 1, 1, 1, 1 },
1420     M32R_INSN_JL, "jl", "jl",
1421     { { MNEM, ' ', OP (SR), 0 } },
1422     { 16, 16, 0xfff0 }, 0x1ec0,
1423     (PTR) & fmt_jl_ops[0],
1424     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1425   },
1426 /* jmp $sr */
1427   {
1428     { 1, 1, 1, 1 },
1429     M32R_INSN_JMP, "jmp", "jmp",
1430     { { MNEM, ' ', OP (SR), 0 } },
1431     { 16, 16, 0xfff0 }, 0x1fc0,
1432     (PTR) & fmt_jmp_ops[0],
1433     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1434   },
1435 /* ld $dr,@$sr */
1436   {
1437     { 1, 1, 1, 1 },
1438     M32R_INSN_LD, "ld", "ld",
1439     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
1440     { 16, 16, 0xf0f0 }, 0x20c0,
1441     (PTR) & fmt_ld_ops[0],
1442     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1443   },
1444 /* ld $dr,@($slo16,$sr) */
1445   {
1446     { 1, 1, 1, 1 },
1447     M32R_INSN_LD_D, "ld-d", "ld",
1448     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
1449     { 32, 32, 0xf0f00000 }, 0xa0c00000,
1450     (PTR) & fmt_ld_d_ops[0],
1451     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1452   },
1453 /* ldb $dr,@$sr */
1454   {
1455     { 1, 1, 1, 1 },
1456     M32R_INSN_LDB, "ldb", "ldb",
1457     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
1458     { 16, 16, 0xf0f0 }, 0x2080,
1459     (PTR) & fmt_ldb_ops[0],
1460     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1461   },
1462 /* ldb $dr,@($slo16,$sr) */
1463   {
1464     { 1, 1, 1, 1 },
1465     M32R_INSN_LDB_D, "ldb-d", "ldb",
1466     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
1467     { 32, 32, 0xf0f00000 }, 0xa0800000,
1468     (PTR) & fmt_ldb_d_ops[0],
1469     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1470   },
1471 /* ldh $dr,@$sr */
1472   {
1473     { 1, 1, 1, 1 },
1474     M32R_INSN_LDH, "ldh", "ldh",
1475     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
1476     { 16, 16, 0xf0f0 }, 0x20a0,
1477     (PTR) & fmt_ldh_ops[0],
1478     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1479   },
1480 /* ldh $dr,@($slo16,$sr) */
1481   {
1482     { 1, 1, 1, 1 },
1483     M32R_INSN_LDH_D, "ldh-d", "ldh",
1484     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
1485     { 32, 32, 0xf0f00000 }, 0xa0a00000,
1486     (PTR) & fmt_ldh_d_ops[0],
1487     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1488   },
1489 /* ldub $dr,@$sr */
1490   {
1491     { 1, 1, 1, 1 },
1492     M32R_INSN_LDUB, "ldub", "ldub",
1493     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
1494     { 16, 16, 0xf0f0 }, 0x2090,
1495     (PTR) & fmt_ldb_ops[0],
1496     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1497   },
1498 /* ldub $dr,@($slo16,$sr) */
1499   {
1500     { 1, 1, 1, 1 },
1501     M32R_INSN_LDUB_D, "ldub-d", "ldub",
1502     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
1503     { 32, 32, 0xf0f00000 }, 0xa0900000,
1504     (PTR) & fmt_ldb_d_ops[0],
1505     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1506   },
1507 /* lduh $dr,@$sr */
1508   {
1509     { 1, 1, 1, 1 },
1510     M32R_INSN_LDUH, "lduh", "lduh",
1511     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
1512     { 16, 16, 0xf0f0 }, 0x20b0,
1513     (PTR) & fmt_ldh_ops[0],
1514     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1515   },
1516 /* lduh $dr,@($slo16,$sr) */
1517   {
1518     { 1, 1, 1, 1 },
1519     M32R_INSN_LDUH_D, "lduh-d", "lduh",
1520     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
1521     { 32, 32, 0xf0f00000 }, 0xa0b00000,
1522     (PTR) & fmt_ldh_d_ops[0],
1523     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1524   },
1525 /* ld $dr,@$sr+ */
1526   {
1527     { 1, 1, 1, 1 },
1528     M32R_INSN_LD_PLUS, "ld-plus", "ld",
1529     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 } },
1530     { 16, 16, 0xf0f0 }, 0x20e0,
1531     (PTR) & fmt_ld_plus_ops[0],
1532     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1533   },
1534 /* ld24 $dr,$uimm24 */
1535   {
1536     { 1, 1, 1, 1 },
1537     M32R_INSN_LD24, "ld24", "ld24",
1538     { { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 } },
1539     { 32, 32, 0xf0000000 }, 0xe0000000,
1540     (PTR) & fmt_ld24_ops[0],
1541     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1542   },
1543 /* ldi8 $dr,$simm8 */
1544   {
1545     { 1, 1, 1, 1 },
1546     M32R_INSN_LDI8, "ldi8", "ldi8",
1547     { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
1548     { 16, 16, 0xf000 }, 0x6000,
1549     (PTR) & fmt_ldi8_ops[0],
1550     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1551   },
1552 /* ldi16 $dr,$hash$slo16 */
1553   {
1554     { 1, 1, 1, 1 },
1555     M32R_INSN_LDI16, "ldi16", "ldi16",
1556     { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
1557     { 32, 32, 0xf0ff0000 }, 0x90f00000,
1558     (PTR) & fmt_ldi16_ops[0],
1559     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1560   },
1561 /* lock $dr,@$sr */
1562   {
1563     { 1, 1, 1, 1 },
1564     M32R_INSN_LOCK, "lock", "lock",
1565     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
1566     { 16, 16, 0xf0f0 }, 0x20d0,
1567     (PTR) & fmt_lock_ops[0],
1568     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1569   },
1570 /* machi $src1,$src2 */
1571   {
1572     { 1, 1, 1, 1 },
1573     M32R_INSN_MACHI, "machi", "machi",
1574     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1575     { 16, 16, 0xf0f0 }, 0x3040,
1576     (PTR) & fmt_machi_ops[0],
1577     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1578   },
1579 /* start-sanitize-m32rx */
1580 /* machi $src1,$src2,$acc */
1581   {
1582     { 1, 1, 1, 1 },
1583     M32R_INSN_MACHI_A, "machi-a", "machi",
1584     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
1585     { 16, 16, 0xf070 }, 0x3040,
1586     (PTR) & fmt_machi_a_ops[0],
1587     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1588   },
1589 /* end-sanitize-m32rx */
1590 /* maclo $src1,$src2 */
1591   {
1592     { 1, 1, 1, 1 },
1593     M32R_INSN_MACLO, "maclo", "maclo",
1594     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1595     { 16, 16, 0xf0f0 }, 0x3050,
1596     (PTR) & fmt_machi_ops[0],
1597     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1598   },
1599 /* start-sanitize-m32rx */
1600 /* maclo $src1,$src2,$acc */
1601   {
1602     { 1, 1, 1, 1 },
1603     M32R_INSN_MACLO_A, "maclo-a", "maclo",
1604     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
1605     { 16, 16, 0xf070 }, 0x3050,
1606     (PTR) & fmt_machi_a_ops[0],
1607     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1608   },
1609 /* end-sanitize-m32rx */
1610 /* macwhi $src1,$src2 */
1611   {
1612     { 1, 1, 1, 1 },
1613     M32R_INSN_MACWHI, "macwhi", "macwhi",
1614     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1615     { 16, 16, 0xf0f0 }, 0x3060,
1616     (PTR) & fmt_machi_ops[0],
1617     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1618   },
1619 /* macwlo $src1,$src2 */
1620   {
1621     { 1, 1, 1, 1 },
1622     M32R_INSN_MACWLO, "macwlo", "macwlo",
1623     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1624     { 16, 16, 0xf0f0 }, 0x3070,
1625     (PTR) & fmt_machi_ops[0],
1626     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1627   },
1628 /* mul $dr,$sr */
1629   {
1630     { 1, 1, 1, 1 },
1631     M32R_INSN_MUL, "mul", "mul",
1632     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1633     { 16, 16, 0xf0f0 }, 0x1060,
1634     (PTR) & fmt_add_ops[0],
1635     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1636   },
1637 /* mulhi $src1,$src2 */
1638   {
1639     { 1, 1, 1, 1 },
1640     M32R_INSN_MULHI, "mulhi", "mulhi",
1641     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1642     { 16, 16, 0xf0f0 }, 0x3000,
1643     (PTR) & fmt_mulhi_ops[0],
1644     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1645   },
1646 /* start-sanitize-m32rx */
1647 /* mulhi $src1,$src2,$acc */
1648   {
1649     { 1, 1, 1, 1 },
1650     M32R_INSN_MULHI_A, "mulhi-a", "mulhi",
1651     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
1652     { 16, 16, 0xf070 }, 0x3000,
1653     (PTR) & fmt_mulhi_a_ops[0],
1654     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1655   },
1656 /* end-sanitize-m32rx */
1657 /* mullo $src1,$src2 */
1658   {
1659     { 1, 1, 1, 1 },
1660     M32R_INSN_MULLO, "mullo", "mullo",
1661     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1662     { 16, 16, 0xf0f0 }, 0x3010,
1663     (PTR) & fmt_mulhi_ops[0],
1664     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1665   },
1666 /* start-sanitize-m32rx */
1667 /* mullo $src1,$src2,$acc */
1668   {
1669     { 1, 1, 1, 1 },
1670     M32R_INSN_MULLO_A, "mullo-a", "mullo",
1671     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
1672     { 16, 16, 0xf070 }, 0x3010,
1673     (PTR) & fmt_mulhi_a_ops[0],
1674     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1675   },
1676 /* end-sanitize-m32rx */
1677 /* mulwhi $src1,$src2 */
1678   {
1679     { 1, 1, 1, 1 },
1680     M32R_INSN_MULWHI, "mulwhi", "mulwhi",
1681     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1682     { 16, 16, 0xf0f0 }, 0x3020,
1683     (PTR) & fmt_mulhi_ops[0],
1684     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1685   },
1686 /* mulwlo $src1,$src2 */
1687   {
1688     { 1, 1, 1, 1 },
1689     M32R_INSN_MULWLO, "mulwlo", "mulwlo",
1690     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
1691     { 16, 16, 0xf0f0 }, 0x3030,
1692     (PTR) & fmt_mulhi_ops[0],
1693     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1694   },
1695 /* mv $dr,$sr */
1696   {
1697     { 1, 1, 1, 1 },
1698     M32R_INSN_MV, "mv", "mv",
1699     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1700     { 16, 16, 0xf0f0 }, 0x1080,
1701     (PTR) & fmt_mv_ops[0],
1702     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1703   },
1704 /* mvfachi $dr */
1705   {
1706     { 1, 1, 1, 1 },
1707     M32R_INSN_MVFACHI, "mvfachi", "mvfachi",
1708     { { MNEM, ' ', OP (DR), 0 } },
1709     { 16, 16, 0xf0ff }, 0x50f0,
1710     (PTR) & fmt_mvfachi_ops[0],
1711     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1712   },
1713 /* start-sanitize-m32rx */
1714 /* mvfachi $dr,$accs */
1715   {
1716     { 1, 1, 1, 1 },
1717     M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi",
1718     { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
1719     { 16, 16, 0xf0f3 }, 0x50f0,
1720     (PTR) & fmt_mvfachi_a_ops[0],
1721     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1722   },
1723 /* end-sanitize-m32rx */
1724 /* mvfaclo $dr */
1725   {
1726     { 1, 1, 1, 1 },
1727     M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo",
1728     { { MNEM, ' ', OP (DR), 0 } },
1729     { 16, 16, 0xf0ff }, 0x50f1,
1730     (PTR) & fmt_mvfachi_ops[0],
1731     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1732   },
1733 /* start-sanitize-m32rx */
1734 /* mvfaclo $dr,$accs */
1735   {
1736     { 1, 1, 1, 1 },
1737     M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo",
1738     { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
1739     { 16, 16, 0xf0f3 }, 0x50f1,
1740     (PTR) & fmt_mvfachi_a_ops[0],
1741     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1742   },
1743 /* end-sanitize-m32rx */
1744 /* mvfacmi $dr */
1745   {
1746     { 1, 1, 1, 1 },
1747     M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi",
1748     { { MNEM, ' ', OP (DR), 0 } },
1749     { 16, 16, 0xf0ff }, 0x50f2,
1750     (PTR) & fmt_mvfachi_ops[0],
1751     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1752   },
1753 /* start-sanitize-m32rx */
1754 /* mvfacmi $dr,$accs */
1755   {
1756     { 1, 1, 1, 1 },
1757     M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi",
1758     { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
1759     { 16, 16, 0xf0f3 }, 0x50f2,
1760     (PTR) & fmt_mvfachi_a_ops[0],
1761     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1762   },
1763 /* end-sanitize-m32rx */
1764 /* mvfc $dr,$scr */
1765   {
1766     { 1, 1, 1, 1 },
1767     M32R_INSN_MVFC, "mvfc", "mvfc",
1768     { { MNEM, ' ', OP (DR), ',', OP (SCR), 0 } },
1769     { 16, 16, 0xf0f0 }, 0x1090,
1770     (PTR) & fmt_mvfc_ops[0],
1771     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1772   },
1773 /* mvtachi $src1 */
1774   {
1775     { 1, 1, 1, 1 },
1776     M32R_INSN_MVTACHI, "mvtachi", "mvtachi",
1777     { { MNEM, ' ', OP (SRC1), 0 } },
1778     { 16, 16, 0xf0ff }, 0x5070,
1779     (PTR) & fmt_mvtachi_ops[0],
1780     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1781   },
1782 /* start-sanitize-m32rx */
1783 /* mvtachi $src1,$accs */
1784   {
1785     { 1, 1, 1, 1 },
1786     M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi",
1787     { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
1788     { 16, 16, 0xf0f3 }, 0x5070,
1789     (PTR) & fmt_mvtachi_a_ops[0],
1790     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1791   },
1792 /* end-sanitize-m32rx */
1793 /* mvtaclo $src1 */
1794   {
1795     { 1, 1, 1, 1 },
1796     M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo",
1797     { { MNEM, ' ', OP (SRC1), 0 } },
1798     { 16, 16, 0xf0ff }, 0x5071,
1799     (PTR) & fmt_mvtachi_ops[0],
1800     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1801   },
1802 /* start-sanitize-m32rx */
1803 /* mvtaclo $src1,$accs */
1804   {
1805     { 1, 1, 1, 1 },
1806     M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo",
1807     { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
1808     { 16, 16, 0xf0f3 }, 0x5071,
1809     (PTR) & fmt_mvtachi_a_ops[0],
1810     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1811   },
1812 /* end-sanitize-m32rx */
1813 /* mvtc $sr,$dcr */
1814   {
1815     { 1, 1, 1, 1 },
1816     M32R_INSN_MVTC, "mvtc", "mvtc",
1817     { { MNEM, ' ', OP (SR), ',', OP (DCR), 0 } },
1818     { 16, 16, 0xf0f0 }, 0x10a0,
1819     (PTR) & fmt_mvtc_ops[0],
1820     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1821   },
1822 /* neg $dr,$sr */
1823   {
1824     { 1, 1, 1, 1 },
1825     M32R_INSN_NEG, "neg", "neg",
1826     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1827     { 16, 16, 0xf0f0 }, 0x30,
1828     (PTR) & fmt_mv_ops[0],
1829     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1830   },
1831 /* nop */
1832   {
1833     { 1, 1, 1, 1 },
1834     M32R_INSN_NOP, "nop", "nop",
1835     { { MNEM, 0 } },
1836     { 16, 16, 0xffff }, 0x7000,
1837     (PTR) 0,
1838     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1839   },
1840 /* not $dr,$sr */
1841   {
1842     { 1, 1, 1, 1 },
1843     M32R_INSN_NOT, "not", "not",
1844     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1845     { 16, 16, 0xf0f0 }, 0xb0,
1846     (PTR) & fmt_mv_ops[0],
1847     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1848   },
1849 /* rac */
1850   {
1851     { 1, 1, 1, 1 },
1852     M32R_INSN_RAC, "rac", "rac",
1853     { { MNEM, 0 } },
1854     { 16, 16, 0xffff }, 0x5090,
1855     (PTR) & fmt_rac_ops[0],
1856     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1857   },
1858 /* start-sanitize-m32rx */
1859 /* rac $accd,$accs,$imm1 */
1860   {
1861     { 1, 1, 1, 1 },
1862     M32R_INSN_RAC_DSI, "rac-dsi", "rac",
1863     { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
1864     { 16, 16, 0xf3f2 }, 0x5090,
1865     (PTR) & fmt_rac_dsi_ops[0],
1866     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1867   },
1868 /* end-sanitize-m32rx */
1869 /* rach */
1870   {
1871     { 1, 1, 1, 1 },
1872     M32R_INSN_RACH, "rach", "rach",
1873     { { MNEM, 0 } },
1874     { 16, 16, 0xffff }, 0x5080,
1875     (PTR) & fmt_rac_ops[0],
1876     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1877   },
1878 /* start-sanitize-m32rx */
1879 /* rach $accd,$accs,$imm1 */
1880   {
1881     { 1, 1, 1, 1 },
1882     M32R_INSN_RACH_DSI, "rach-dsi", "rach",
1883     { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
1884     { 16, 16, 0xf3f2 }, 0x5080,
1885     (PTR) & fmt_rac_dsi_ops[0],
1886     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1887   },
1888 /* end-sanitize-m32rx */
1889 /* rte */
1890   {
1891     { 1, 1, 1, 1 },
1892     M32R_INSN_RTE, "rte", "rte",
1893     { { MNEM, 0 } },
1894     { 16, 16, 0xffff }, 0x10d6,
1895     (PTR) & fmt_rte_ops[0],
1896     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1897   },
1898 /* seth $dr,$hash$hi16 */
1899   {
1900     { 1, 1, 1, 1 },
1901     M32R_INSN_SETH, "seth", "seth",
1902     { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (HI16), 0 } },
1903     { 32, 32, 0xf0ff0000 }, 0xd0c00000,
1904     (PTR) & fmt_seth_ops[0],
1905     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1906   },
1907 /* sll $dr,$sr */
1908   {
1909     { 1, 1, 1, 1 },
1910     M32R_INSN_SLL, "sll", "sll",
1911     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1912     { 16, 16, 0xf0f0 }, 0x1040,
1913     (PTR) & fmt_add_ops[0],
1914     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1915   },
1916 /* sll3 $dr,$sr,$simm16 */
1917   {
1918     { 1, 1, 1, 1 },
1919     M32R_INSN_SLL3, "sll3", "sll3",
1920     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
1921     { 32, 32, 0xf0f00000 }, 0x90c00000,
1922     (PTR) & fmt_sll3_ops[0],
1923     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1924   },
1925 /* slli $dr,$uimm5 */
1926   {
1927     { 1, 1, 1, 1 },
1928     M32R_INSN_SLLI, "slli", "slli",
1929     { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
1930     { 16, 16, 0xf0e0 }, 0x5040,
1931     (PTR) & fmt_slli_ops[0],
1932     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1933   },
1934 /* sra $dr,$sr */
1935   {
1936     { 1, 1, 1, 1 },
1937     M32R_INSN_SRA, "sra", "sra",
1938     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1939     { 16, 16, 0xf0f0 }, 0x1020,
1940     (PTR) & fmt_add_ops[0],
1941     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1942   },
1943 /* sra3 $dr,$sr,$simm16 */
1944   {
1945     { 1, 1, 1, 1 },
1946     M32R_INSN_SRA3, "sra3", "sra3",
1947     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
1948     { 32, 32, 0xf0f00000 }, 0x90a00000,
1949     (PTR) & fmt_sll3_ops[0],
1950     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1951   },
1952 /* srai $dr,$uimm5 */
1953   {
1954     { 1, 1, 1, 1 },
1955     M32R_INSN_SRAI, "srai", "srai",
1956     { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
1957     { 16, 16, 0xf0e0 }, 0x5020,
1958     (PTR) & fmt_slli_ops[0],
1959     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1960   },
1961 /* srl $dr,$sr */
1962   {
1963     { 1, 1, 1, 1 },
1964     M32R_INSN_SRL, "srl", "srl",
1965     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
1966     { 16, 16, 0xf0f0 }, 0x1000,
1967     (PTR) & fmt_add_ops[0],
1968     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1969   },
1970 /* srl3 $dr,$sr,$simm16 */
1971   {
1972     { 1, 1, 1, 1 },
1973     M32R_INSN_SRL3, "srl3", "srl3",
1974     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
1975     { 32, 32, 0xf0f00000 }, 0x90800000,
1976     (PTR) & fmt_sll3_ops[0],
1977     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1978   },
1979 /* srli $dr,$uimm5 */
1980   {
1981     { 1, 1, 1, 1 },
1982     M32R_INSN_SRLI, "srli", "srli",
1983     { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
1984     { 16, 16, 0xf0e0 }, 0x5000,
1985     (PTR) & fmt_slli_ops[0],
1986     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1987   },
1988 /* st $src1,@$src2 */
1989   {
1990     { 1, 1, 1, 1 },
1991     M32R_INSN_ST, "st", "st",
1992     { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
1993     { 16, 16, 0xf0f0 }, 0x2040,
1994     (PTR) & fmt_st_ops[0],
1995     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1996   },
1997 /* st $src1,@($slo16,$src2) */
1998   {
1999     { 1, 1, 1, 1 },
2000     M32R_INSN_ST_D, "st-d", "st",
2001     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
2002     { 32, 32, 0xf0f00000 }, 0xa0400000,
2003     (PTR) & fmt_st_d_ops[0],
2004     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2005   },
2006 /* stb $src1,@$src2 */
2007   {
2008     { 1, 1, 1, 1 },
2009     M32R_INSN_STB, "stb", "stb",
2010     { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
2011     { 16, 16, 0xf0f0 }, 0x2000,
2012     (PTR) & fmt_stb_ops[0],
2013     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2014   },
2015 /* stb $src1,@($slo16,$src2) */
2016   {
2017     { 1, 1, 1, 1 },
2018     M32R_INSN_STB_D, "stb-d", "stb",
2019     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
2020     { 32, 32, 0xf0f00000 }, 0xa0000000,
2021     (PTR) & fmt_stb_d_ops[0],
2022     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2023   },
2024 /* sth $src1,@$src2 */
2025   {
2026     { 1, 1, 1, 1 },
2027     M32R_INSN_STH, "sth", "sth",
2028     { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
2029     { 16, 16, 0xf0f0 }, 0x2020,
2030     (PTR) & fmt_sth_ops[0],
2031     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2032   },
2033 /* sth $src1,@($slo16,$src2) */
2034   {
2035     { 1, 1, 1, 1 },
2036     M32R_INSN_STH_D, "sth-d", "sth",
2037     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
2038     { 32, 32, 0xf0f00000 }, 0xa0200000,
2039     (PTR) & fmt_sth_d_ops[0],
2040     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2041   },
2042 /* st $src1,@+$src2 */
2043   {
2044     { 1, 1, 1, 1 },
2045     M32R_INSN_ST_PLUS, "st-plus", "st",
2046     { { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 } },
2047     { 16, 16, 0xf0f0 }, 0x2060,
2048     (PTR) & fmt_st_plus_ops[0],
2049     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2050   },
2051 /* st $src1,@-$src2 */
2052   {
2053     { 1, 1, 1, 1 },
2054     M32R_INSN_ST_MINUS, "st-minus", "st",
2055     { { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 } },
2056     { 16, 16, 0xf0f0 }, 0x2070,
2057     (PTR) & fmt_st_plus_ops[0],
2058     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2059   },
2060 /* sub $dr,$sr */
2061   {
2062     { 1, 1, 1, 1 },
2063     M32R_INSN_SUB, "sub", "sub",
2064     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
2065     { 16, 16, 0xf0f0 }, 0x20,
2066     (PTR) & fmt_add_ops[0],
2067     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2068   },
2069 /* subv $dr,$sr */
2070   {
2071     { 1, 1, 1, 1 },
2072     M32R_INSN_SUBV, "subv", "subv",
2073     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
2074     { 16, 16, 0xf0f0 }, 0x0,
2075     (PTR) & fmt_addv_ops[0],
2076     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2077   },
2078 /* subx $dr,$sr */
2079   {
2080     { 1, 1, 1, 1 },
2081     M32R_INSN_SUBX, "subx", "subx",
2082     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
2083     { 16, 16, 0xf0f0 }, 0x10,
2084     (PTR) & fmt_addx_ops[0],
2085     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2086   },
2087 /* trap $uimm4 */
2088   {
2089     { 1, 1, 1, 1 },
2090     M32R_INSN_TRAP, "trap", "trap",
2091     { { MNEM, ' ', OP (UIMM4), 0 } },
2092     { 16, 16, 0xfff0 }, 0x10f0,
2093     (PTR) & fmt_trap_ops[0],
2094     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
2095   },
2096 /* unlock $src1,@$src2 */
2097   {
2098     { 1, 1, 1, 1 },
2099     M32R_INSN_UNLOCK, "unlock", "unlock",
2100     { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
2101     { 16, 16, 0xf0f0 }, 0x2050,
2102     (PTR) & fmt_unlock_ops[0],
2103     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2104   },
2105 /* start-sanitize-m32rx */
2106 /* satb $dr,$sr */
2107   {
2108     { 1, 1, 1, 1 },
2109     M32R_INSN_SATB, "satb", "satb",
2110     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
2111     { 32, 32, 0xf0f0ffff }, 0x80600300,
2112     (PTR) & fmt_satb_ops[0],
2113     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
2114   },
2115 /* end-sanitize-m32rx */
2116 /* start-sanitize-m32rx */
2117 /* sath $dr,$sr */
2118   {
2119     { 1, 1, 1, 1 },
2120     M32R_INSN_SATH, "sath", "sath",
2121     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
2122     { 32, 32, 0xf0f0ffff }, 0x80600200,
2123     (PTR) & fmt_satb_ops[0],
2124     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
2125   },
2126 /* end-sanitize-m32rx */
2127 /* start-sanitize-m32rx */
2128 /* sat $dr,$sr */
2129   {
2130     { 1, 1, 1, 1 },
2131     M32R_INSN_SAT, "sat", "sat",
2132     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
2133     { 32, 32, 0xf0f0ffff }, 0x80600000,
2134     (PTR) & fmt_sat_ops[0],
2135     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_NONE } }
2136   },
2137 /* end-sanitize-m32rx */
2138 /* start-sanitize-m32rx */
2139 /* pcmpbz $src2 */
2140   {
2141     { 1, 1, 1, 1 },
2142     M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz",
2143     { { MNEM, ' ', OP (SRC2), 0 } },
2144     { 16, 16, 0xfff0 }, 0x370,
2145     (PTR) & fmt_cmpz_ops[0],
2146     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_OS } }
2147   },
2148 /* end-sanitize-m32rx */
2149 /* start-sanitize-m32rx */
2150 /* sadd */
2151   {
2152     { 1, 1, 1, 1 },
2153     M32R_INSN_SADD, "sadd", "sadd",
2154     { { MNEM, 0 } },
2155     { 16, 16, 0xffff }, 0x50e4,
2156     (PTR) & fmt_sadd_ops[0],
2157     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2158   },
2159 /* end-sanitize-m32rx */
2160 /* start-sanitize-m32rx */
2161 /* macwu1 $src1,$src2 */
2162   {
2163     { 1, 1, 1, 1 },
2164     M32R_INSN_MACWU1, "macwu1", "macwu1",
2165     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
2166     { 16, 16, 0xf0f0 }, 0x50b0,
2167     (PTR) & fmt_macwu1_ops[0],
2168     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2169   },
2170 /* end-sanitize-m32rx */
2171 /* start-sanitize-m32rx */
2172 /* msblo $src1,$src2 */
2173   {
2174     { 1, 1, 1, 1 },
2175     M32R_INSN_MSBLO, "msblo", "msblo",
2176     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
2177     { 16, 16, 0xf0f0 }, 0x50d0,
2178     (PTR) & fmt_machi_ops[0],
2179     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2180   },
2181 /* end-sanitize-m32rx */
2182 /* start-sanitize-m32rx */
2183 /* mulwu1 $src1,$src2 */
2184   {
2185     { 1, 1, 1, 1 },
2186     M32R_INSN_MULWU1, "mulwu1", "mulwu1",
2187     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
2188     { 16, 16, 0xf0f0 }, 0x50a0,
2189     (PTR) & fmt_mulwu1_ops[0],
2190     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2191   },
2192 /* end-sanitize-m32rx */
2193 /* start-sanitize-m32rx */
2194 /* maclh1 $src1,$src2 */
2195   {
2196     { 1, 1, 1, 1 },
2197     M32R_INSN_MACLH1, "maclh1", "maclh1",
2198     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
2199     { 16, 16, 0xf0f0 }, 0x50c0,
2200     (PTR) & fmt_macwu1_ops[0],
2201     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2202   },
2203 /* end-sanitize-m32rx */
2204 /* start-sanitize-m32rx */
2205 /* sc */
2206   {
2207     { 1, 1, 1, 1 },
2208     M32R_INSN_SC, "sc", "sc",
2209     { { MNEM, 0 } },
2210     { 16, 16, 0xffff }, 0x7401,
2211     (PTR) & fmt_sc_ops[0],
2212     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_O } }
2213   },
2214 /* end-sanitize-m32rx */
2215 /* start-sanitize-m32rx */
2216 /* snc */
2217   {
2218     { 1, 1, 1, 1 },
2219     M32R_INSN_SNC, "snc", "snc",
2220     { { MNEM, 0 } },
2221     { 16, 16, 0xffff }, 0x7501,
2222     (PTR) & fmt_sc_ops[0],
2223     { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_O } }
2224   },
2225 /* end-sanitize-m32rx */
2226 };
2227
2228 #undef A
2229 #undef MNEM
2230 #undef OP
2231
2232 static CGEN_INSN_TABLE insn_table =
2233 {
2234   & m32r_cgen_insn_table_entries[0],
2235   sizeof (CGEN_INSN),
2236   MAX_INSNS,
2237   NULL
2238 };
2239
2240 /* Each non-simple macro entry points to an array of expansion possibilities.  */
2241
2242 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
2243 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
2244 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
2245
2246 /* The macro instruction table.  */
2247
2248 static const CGEN_INSN macro_insn_table_entries[] =
2249 {
2250 /* bc $disp8 */
2251   {
2252     { 1, 1, 1, 1 },
2253     -1, "bc8r", "bc",
2254     { { MNEM, ' ', OP (DISP8), 0 } },
2255     { 16, 16, 0xff00 }, 0x7c00,
2256     (PTR) 0,
2257     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2258   },
2259 /* bc $disp24 */
2260   {
2261     { 1, 1, 1, 1 },
2262     -1, "bc24r", "bc",
2263     { { MNEM, ' ', OP (DISP24), 0 } },
2264     { 32, 32, 0xff000000 }, 0xfc000000,
2265     (PTR) 0,
2266     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2267   },
2268 /* bl $disp8 */
2269   {
2270     { 1, 1, 1, 1 },
2271     -1, "bl8r", "bl",
2272     { { MNEM, ' ', OP (DISP8), 0 } },
2273     { 16, 16, 0xff00 }, 0x7e00,
2274     (PTR) 0,
2275     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2276   },
2277 /* bl $disp24 */
2278   {
2279     { 1, 1, 1, 1 },
2280     -1, "bl24r", "bl",
2281     { { MNEM, ' ', OP (DISP24), 0 } },
2282     { 32, 32, 0xff000000 }, 0xfe000000,
2283     (PTR) 0,
2284     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2285   },
2286 /* bcl $disp8 */
2287   {
2288     { 1, 1, 1, 1 },
2289     -1, "bcl8r", "bcl",
2290     { { MNEM, ' ', OP (DISP8), 0 } },
2291     { 16, 16, 0xff00 }, 0x7800,
2292     (PTR) 0,
2293     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
2294   },
2295 /* bcl $disp24 */
2296   {
2297     { 1, 1, 1, 1 },
2298     -1, "bcl24r", "bcl",
2299     { { MNEM, ' ', OP (DISP24), 0 } },
2300     { 32, 32, 0xff000000 }, 0xf8000000,
2301     (PTR) 0,
2302     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
2303   },
2304 /* bnc $disp8 */
2305   {
2306     { 1, 1, 1, 1 },
2307     -1, "bnc8r", "bnc",
2308     { { MNEM, ' ', OP (DISP8), 0 } },
2309     { 16, 16, 0xff00 }, 0x7d00,
2310     (PTR) 0,
2311     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2312   },
2313 /* bnc $disp24 */
2314   {
2315     { 1, 1, 1, 1 },
2316     -1, "bnc24r", "bnc",
2317     { { MNEM, ' ', OP (DISP24), 0 } },
2318     { 32, 32, 0xff000000 }, 0xfd000000,
2319     (PTR) 0,
2320     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2321   },
2322 /* bra $disp8 */
2323   {
2324     { 1, 1, 1, 1 },
2325     -1, "bra8r", "bra",
2326     { { MNEM, ' ', OP (DISP8), 0 } },
2327     { 16, 16, 0xff00 }, 0x7f00,
2328     (PTR) 0,
2329     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2330   },
2331 /* bra $disp24 */
2332   {
2333     { 1, 1, 1, 1 },
2334     -1, "bra24r", "bra",
2335     { { MNEM, ' ', OP (DISP24), 0 } },
2336     { 32, 32, 0xff000000 }, 0xff000000,
2337     (PTR) 0,
2338     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2339   },
2340 /* bncl $disp8 */
2341   {
2342     { 1, 1, 1, 1 },
2343     -1, "bncl8r", "bncl",
2344     { { MNEM, ' ', OP (DISP8), 0 } },
2345     { 16, 16, 0xff00 }, 0x7900,
2346     (PTR) 0,
2347     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
2348   },
2349 /* bncl $disp24 */
2350   {
2351     { 1, 1, 1, 1 },
2352     -1, "bncl24r", "bncl",
2353     { { MNEM, ' ', OP (DISP24), 0 } },
2354     { 32, 32, 0xff000000 }, 0xf9000000,
2355     (PTR) 0,
2356     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
2357   },
2358 /* ld $dr,@($sr) */
2359   {
2360     { 1, 1, 1, 1 },
2361     -1, "ld-2", "ld",
2362     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
2363     { 16, 16, 0xf0f0 }, 0x20c0,
2364     (PTR) 0,
2365     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2366   },
2367 /* ld $dr,@($sr,$slo16) */
2368   {
2369     { 1, 1, 1, 1 },
2370     -1, "ld-d2", "ld",
2371     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
2372     { 32, 32, 0xf0f00000 }, 0xa0c00000,
2373     (PTR) 0,
2374     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2375   },
2376 /* ldb $dr,@($sr) */
2377   {
2378     { 1, 1, 1, 1 },
2379     -1, "ldb-2", "ldb",
2380     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
2381     { 16, 16, 0xf0f0 }, 0x2080,
2382     (PTR) 0,
2383     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2384   },
2385 /* ldb $dr,@($sr,$slo16) */
2386   {
2387     { 1, 1, 1, 1 },
2388     -1, "ldb-d2", "ldb",
2389     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
2390     { 32, 32, 0xf0f00000 }, 0xa0800000,
2391     (PTR) 0,
2392     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2393   },
2394 /* ldh $dr,@($sr) */
2395   {
2396     { 1, 1, 1, 1 },
2397     -1, "ldh-2", "ldh",
2398     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
2399     { 16, 16, 0xf0f0 }, 0x20a0,
2400     (PTR) 0,
2401     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2402   },
2403 /* ldh $dr,@($sr,$slo16) */
2404   {
2405     { 1, 1, 1, 1 },
2406     -1, "ldh-d2", "ldh",
2407     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
2408     { 32, 32, 0xf0f00000 }, 0xa0a00000,
2409     (PTR) 0,
2410     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2411   },
2412 /* ldub $dr,@($sr) */
2413   {
2414     { 1, 1, 1, 1 },
2415     -1, "ldub-2", "ldub",
2416     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
2417     { 16, 16, 0xf0f0 }, 0x2090,
2418     (PTR) 0,
2419     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2420   },
2421 /* ldub $dr,@($sr,$slo16) */
2422   {
2423     { 1, 1, 1, 1 },
2424     -1, "ldub-d2", "ldub",
2425     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
2426     { 32, 32, 0xf0f00000 }, 0xa0900000,
2427     (PTR) 0,
2428     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2429   },
2430 /* lduh $dr,@($sr) */
2431   {
2432     { 1, 1, 1, 1 },
2433     -1, "lduh-2", "lduh",
2434     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
2435     { 16, 16, 0xf0f0 }, 0x20b0,
2436     (PTR) 0,
2437     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2438   },
2439 /* lduh $dr,@($sr,$slo16) */
2440   {
2441     { 1, 1, 1, 1 },
2442     -1, "lduh-d2", "lduh",
2443     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
2444     { 32, 32, 0xf0f00000 }, 0xa0b00000,
2445     (PTR) 0,
2446     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2447   },
2448 /* pop $dr */
2449   {
2450     { 1, 1, 1, 1 },
2451     -1, "pop", "pop",
2452     { { MNEM, ' ', OP (DR), 0 } },
2453     { 16, 16, 0xf0ff }, 0x20ef,
2454     (PTR) 0,
2455     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2456   },
2457 /* ldi $dr,$simm8 */
2458   {
2459     { 1, 1, 1, 1 },
2460     -1, "ldi8a", "ldi",
2461     { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
2462     { 16, 16, 0xf000 }, 0x6000,
2463     (PTR) 0,
2464     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
2465   },
2466 /* ldi $dr,$hash$slo16 */
2467   {
2468     { 1, 1, 1, 1 },
2469     -1, "ldi16a", "ldi",
2470     { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
2471     { 32, 32, 0xf0ff0000 }, 0x90f00000,
2472     (PTR) 0,
2473     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2474   },
2475 /* rac $accd */
2476   {
2477     { 1, 1, 1, 1 },
2478     -1, "rac-d", "rac",
2479     { { MNEM, ' ', OP (ACCD), 0 } },
2480     { 16, 16, 0xf3ff }, 0x5090,
2481     (PTR) 0,
2482     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2483   },
2484 /* rac $accd,$accs */
2485   {
2486     { 1, 1, 1, 1 },
2487     -1, "rac-ds", "rac",
2488     { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
2489     { 16, 16, 0xf3f3 }, 0x5090,
2490     (PTR) 0,
2491     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2492   },
2493 /* rach $accd */
2494   {
2495     { 1, 1, 1, 1 },
2496     -1, "rach-d", "rach",
2497     { { MNEM, ' ', OP (ACCD), 0 } },
2498     { 16, 16, 0xf3ff }, 0x5080,
2499     (PTR) 0,
2500     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2501   },
2502 /* rach $accd,$accs */
2503   {
2504     { 1, 1, 1, 1 },
2505     -1, "rach-ds", "rach",
2506     { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
2507     { 16, 16, 0xf3f3 }, 0x5080,
2508     (PTR) 0,
2509     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2510   },
2511 /* st $src1,@($src2) */
2512   {
2513     { 1, 1, 1, 1 },
2514     -1, "st-2", "st",
2515     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
2516     { 16, 16, 0xf0f0 }, 0x2040,
2517     (PTR) 0,
2518     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2519   },
2520 /* st $src1,@($src2,$slo16) */
2521   {
2522     { 1, 1, 1, 1 },
2523     -1, "st-d2", "st",
2524     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
2525     { 32, 32, 0xf0f00000 }, 0xa0400000,
2526     (PTR) 0,
2527     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2528   },
2529 /* stb $src1,@($src2) */
2530   {
2531     { 1, 1, 1, 1 },
2532     -1, "stb-2", "stb",
2533     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
2534     { 16, 16, 0xf0f0 }, 0x2000,
2535     (PTR) 0,
2536     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2537   },
2538 /* stb $src1,@($src2,$slo16) */
2539   {
2540     { 1, 1, 1, 1 },
2541     -1, "stb-d2", "stb",
2542     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
2543     { 32, 32, 0xf0f00000 }, 0xa0000000,
2544     (PTR) 0,
2545     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2546   },
2547 /* sth $src1,@($src2) */
2548   {
2549     { 1, 1, 1, 1 },
2550     -1, "sth-2", "sth",
2551     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
2552     { 16, 16, 0xf0f0 }, 0x2020,
2553     (PTR) 0,
2554     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2555   },
2556 /* sth $src1,@($src2,$slo16) */
2557   {
2558     { 1, 1, 1, 1 },
2559     -1, "sth-d2", "sth",
2560     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
2561     { 32, 32, 0xf0f00000 }, 0xa0200000,
2562     (PTR) 0,
2563     { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2564   },
2565 /* push $src1 */
2566   {
2567     { 1, 1, 1, 1 },
2568     -1, "push", "push",
2569     { { MNEM, ' ', OP (SRC1), 0 } },
2570     { 16, 16, 0xf0ff }, 0x207f,
2571     (PTR) 0,
2572     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2573   },
2574 };
2575
2576 #undef A
2577 #undef MNEM
2578 #undef OP
2579
2580 static CGEN_INSN_TABLE macro_insn_table =
2581 {
2582   & macro_insn_table_entries[0],
2583   sizeof (CGEN_INSN),
2584   (sizeof (macro_insn_table_entries) /
2585    sizeof (macro_insn_table_entries[0])),
2586   NULL
2587 };
2588
2589 /* The hash functions are recorded here to help keep assembler code out of
2590    the disassembler and vice versa.  */
2591
2592 static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
2593 static unsigned int asm_hash_insn PARAMS ((const char *));
2594 static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
2595 static unsigned int dis_hash_insn PARAMS ((const char *, unsigned long));
2596
2597 /* Return non-zero if INSN is to be added to the hash table.
2598    Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file.  */
2599
2600 static int
2601 asm_hash_insn_p (insn)
2602      const CGEN_INSN * insn;
2603 {
2604   return CGEN_ASM_HASH_P (insn);
2605 }
2606
2607 static int
2608 dis_hash_insn_p (insn)
2609      const CGEN_INSN * insn;
2610 {
2611   /* If building the hash table and the NO-DIS attribute is present,
2612      ignore.  */
2613   if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS))
2614     return 0;
2615   return CGEN_DIS_HASH_P (insn);
2616 }
2617
2618 /* The result is the hash value of the insn.
2619    Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file.  */
2620
2621 static unsigned int
2622 asm_hash_insn (mnem)
2623      const char * mnem;
2624 {
2625   return CGEN_ASM_HASH (mnem);
2626 }
2627
2628 static unsigned int
2629 dis_hash_insn (buf, value)
2630      const char * buf;
2631      unsigned long value;
2632 {
2633   return CGEN_DIS_HASH (buf, value);
2634 }
2635
2636 const CGEN_OPCODE_TABLE m32r_cgen_opcode_table =
2637 {
2638   & m32r_cgen_hw_entries[0],
2639   /*& m32r_cgen_operand_table[0], - FIXME:wip */
2640   & insn_table,
2641   & macro_insn_table,
2642   asm_hash_insn_p, asm_hash_insn, CGEN_ASM_HASH_SIZE,
2643   dis_hash_insn_p, dis_hash_insn, CGEN_DIS_HASH_SIZE
2644 };
2645
2646 void
2647 m32r_cgen_init_tables (mach)
2648     int mach;
2649 {
2650 }
2651
2652 /* Getting values from cgen_fields is handled by a collection of functions.
2653    They are distinguished by the type of the VALUE argument they return.
2654    TODO: floating point, inlining support, remove cases where result type
2655    not appropriate.  */
2656
2657 int
2658 m32r_cgen_get_int_operand (opindex, fields)
2659      int opindex;
2660      const CGEN_FIELDS * fields;
2661 {
2662   int value;
2663
2664   switch (opindex)
2665     {
2666     case M32R_OPERAND_SR :
2667       value = fields->f_r2;
2668       break;
2669     case M32R_OPERAND_DR :
2670       value = fields->f_r1;
2671       break;
2672     case M32R_OPERAND_SRC1 :
2673       value = fields->f_r1;
2674       break;
2675     case M32R_OPERAND_SRC2 :
2676       value = fields->f_r2;
2677       break;
2678     case M32R_OPERAND_SCR :
2679       value = fields->f_r2;
2680       break;
2681     case M32R_OPERAND_DCR :
2682       value = fields->f_r1;
2683       break;
2684     case M32R_OPERAND_SIMM8 :
2685       value = fields->f_simm8;
2686       break;
2687     case M32R_OPERAND_SIMM16 :
2688       value = fields->f_simm16;
2689       break;
2690     case M32R_OPERAND_UIMM4 :
2691       value = fields->f_uimm4;
2692       break;
2693     case M32R_OPERAND_UIMM5 :
2694       value = fields->f_uimm5;
2695       break;
2696     case M32R_OPERAND_UIMM16 :
2697       value = fields->f_uimm16;
2698       break;
2699 /* start-sanitize-m32rx */
2700     case M32R_OPERAND_IMM1 :
2701       value = fields->f_imm1;
2702       break;
2703 /* end-sanitize-m32rx */
2704 /* start-sanitize-m32rx */
2705     case M32R_OPERAND_ACCD :
2706       value = fields->f_accd;
2707       break;
2708 /* end-sanitize-m32rx */
2709 /* start-sanitize-m32rx */
2710     case M32R_OPERAND_ACCS :
2711       value = fields->f_accs;
2712       break;
2713 /* end-sanitize-m32rx */
2714 /* start-sanitize-m32rx */
2715     case M32R_OPERAND_ACC :
2716       value = fields->f_acc;
2717       break;
2718 /* end-sanitize-m32rx */
2719     case M32R_OPERAND_HASH :
2720       value = fields->f_nil;
2721       break;
2722     case M32R_OPERAND_HI16 :
2723       value = fields->f_hi16;
2724       break;
2725     case M32R_OPERAND_SLO16 :
2726       value = fields->f_simm16;
2727       break;
2728     case M32R_OPERAND_ULO16 :
2729       value = fields->f_uimm16;
2730       break;
2731     case M32R_OPERAND_UIMM24 :
2732       value = fields->f_uimm24;
2733       break;
2734     case M32R_OPERAND_DISP8 :
2735       value = fields->f_disp8;
2736       break;
2737     case M32R_OPERAND_DISP16 :
2738       value = fields->f_disp16;
2739       break;
2740     case M32R_OPERAND_DISP24 :
2741       value = fields->f_disp24;
2742       break;
2743
2744     default :
2745       /* xgettext:c-format */
2746       fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
2747                        opindex);
2748       abort ();
2749   }
2750
2751   return value;
2752 }
2753
2754 bfd_vma
2755 m32r_cgen_get_vma_operand (opindex, fields)
2756      int opindex;
2757      const CGEN_FIELDS * fields;
2758 {
2759   bfd_vma value;
2760
2761   switch (opindex)
2762     {
2763     case M32R_OPERAND_SR :
2764       value = fields->f_r2;
2765       break;
2766     case M32R_OPERAND_DR :
2767       value = fields->f_r1;
2768       break;
2769     case M32R_OPERAND_SRC1 :
2770       value = fields->f_r1;
2771       break;
2772     case M32R_OPERAND_SRC2 :
2773       value = fields->f_r2;
2774       break;
2775     case M32R_OPERAND_SCR :
2776       value = fields->f_r2;
2777       break;
2778     case M32R_OPERAND_DCR :
2779       value = fields->f_r1;
2780       break;
2781     case M32R_OPERAND_SIMM8 :
2782       value = fields->f_simm8;
2783       break;
2784     case M32R_OPERAND_SIMM16 :
2785       value = fields->f_simm16;
2786       break;
2787     case M32R_OPERAND_UIMM4 :
2788       value = fields->f_uimm4;
2789       break;
2790     case M32R_OPERAND_UIMM5 :
2791       value = fields->f_uimm5;
2792       break;
2793     case M32R_OPERAND_UIMM16 :
2794       value = fields->f_uimm16;
2795       break;
2796 /* start-sanitize-m32rx */
2797     case M32R_OPERAND_IMM1 :
2798       value = fields->f_imm1;
2799       break;
2800 /* end-sanitize-m32rx */
2801 /* start-sanitize-m32rx */
2802     case M32R_OPERAND_ACCD :
2803       value = fields->f_accd;
2804       break;
2805 /* end-sanitize-m32rx */
2806 /* start-sanitize-m32rx */
2807     case M32R_OPERAND_ACCS :
2808       value = fields->f_accs;
2809       break;
2810 /* end-sanitize-m32rx */
2811 /* start-sanitize-m32rx */
2812     case M32R_OPERAND_ACC :
2813       value = fields->f_acc;
2814       break;
2815 /* end-sanitize-m32rx */
2816     case M32R_OPERAND_HASH :
2817       value = fields->f_nil;
2818       break;
2819     case M32R_OPERAND_HI16 :
2820       value = fields->f_hi16;
2821       break;
2822     case M32R_OPERAND_SLO16 :
2823       value = fields->f_simm16;
2824       break;
2825     case M32R_OPERAND_ULO16 :
2826       value = fields->f_uimm16;
2827       break;
2828     case M32R_OPERAND_UIMM24 :
2829       value = fields->f_uimm24;
2830       break;
2831     case M32R_OPERAND_DISP8 :
2832       value = fields->f_disp8;
2833       break;
2834     case M32R_OPERAND_DISP16 :
2835       value = fields->f_disp16;
2836       break;
2837     case M32R_OPERAND_DISP24 :
2838       value = fields->f_disp24;
2839       break;
2840
2841     default :
2842       /* xgettext:c-format */
2843       fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
2844                        opindex);
2845       abort ();
2846   }
2847
2848   return value;
2849 }
2850
2851 /* Stuffing values in cgen_fields is handled by a collection of functions.
2852    They are distinguished by the type of the VALUE argument they accept.
2853    TODO: floating point, inlining support, remove cases where argument type
2854    not appropriate.  */
2855
2856 void
2857 m32r_cgen_set_int_operand (opindex, fields, value)
2858      int opindex;
2859      CGEN_FIELDS * fields;
2860      int value;
2861 {
2862   switch (opindex)
2863     {
2864     case M32R_OPERAND_SR :
2865       fields->f_r2 = value;
2866       break;
2867     case M32R_OPERAND_DR :
2868       fields->f_r1 = value;
2869       break;
2870     case M32R_OPERAND_SRC1 :
2871       fields->f_r1 = value;
2872       break;
2873     case M32R_OPERAND_SRC2 :
2874       fields->f_r2 = value;
2875       break;
2876     case M32R_OPERAND_SCR :
2877       fields->f_r2 = value;
2878       break;
2879     case M32R_OPERAND_DCR :
2880       fields->f_r1 = value;
2881       break;
2882     case M32R_OPERAND_SIMM8 :
2883       fields->f_simm8 = value;
2884       break;
2885     case M32R_OPERAND_SIMM16 :
2886       fields->f_simm16 = value;
2887       break;
2888     case M32R_OPERAND_UIMM4 :
2889       fields->f_uimm4 = value;
2890       break;
2891     case M32R_OPERAND_UIMM5 :
2892       fields->f_uimm5 = value;
2893       break;
2894     case M32R_OPERAND_UIMM16 :
2895       fields->f_uimm16 = value;
2896       break;
2897 /* start-sanitize-m32rx */
2898     case M32R_OPERAND_IMM1 :
2899       fields->f_imm1 = value;
2900       break;
2901 /* end-sanitize-m32rx */
2902 /* start-sanitize-m32rx */
2903     case M32R_OPERAND_ACCD :
2904       fields->f_accd = value;
2905       break;
2906 /* end-sanitize-m32rx */
2907 /* start-sanitize-m32rx */
2908     case M32R_OPERAND_ACCS :
2909       fields->f_accs = value;
2910       break;
2911 /* end-sanitize-m32rx */
2912 /* start-sanitize-m32rx */
2913     case M32R_OPERAND_ACC :
2914       fields->f_acc = value;
2915       break;
2916 /* end-sanitize-m32rx */
2917     case M32R_OPERAND_HASH :
2918       fields->f_nil = value;
2919       break;
2920     case M32R_OPERAND_HI16 :
2921       fields->f_hi16 = value;
2922       break;
2923     case M32R_OPERAND_SLO16 :
2924       fields->f_simm16 = value;
2925       break;
2926     case M32R_OPERAND_ULO16 :
2927       fields->f_uimm16 = value;
2928       break;
2929     case M32R_OPERAND_UIMM24 :
2930       fields->f_uimm24 = value;
2931       break;
2932     case M32R_OPERAND_DISP8 :
2933       fields->f_disp8 = value;
2934       break;
2935     case M32R_OPERAND_DISP16 :
2936       fields->f_disp16 = value;
2937       break;
2938     case M32R_OPERAND_DISP24 :
2939       fields->f_disp24 = value;
2940       break;
2941
2942     default :
2943       /* xgettext:c-format */
2944       fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
2945                        opindex);
2946       abort ();
2947   }
2948 }
2949
2950 void
2951 m32r_cgen_set_vma_operand (opindex, fields, value)
2952      int opindex;
2953      CGEN_FIELDS * fields;
2954      bfd_vma value;
2955 {
2956   switch (opindex)
2957     {
2958     case M32R_OPERAND_SR :
2959       fields->f_r2 = value;
2960       break;
2961     case M32R_OPERAND_DR :
2962       fields->f_r1 = value;
2963       break;
2964     case M32R_OPERAND_SRC1 :
2965       fields->f_r1 = value;
2966       break;
2967     case M32R_OPERAND_SRC2 :
2968       fields->f_r2 = value;
2969       break;
2970     case M32R_OPERAND_SCR :
2971       fields->f_r2 = value;
2972       break;
2973     case M32R_OPERAND_DCR :
2974       fields->f_r1 = value;
2975       break;
2976     case M32R_OPERAND_SIMM8 :
2977       fields->f_simm8 = value;
2978       break;
2979     case M32R_OPERAND_SIMM16 :
2980       fields->f_simm16 = value;
2981       break;
2982     case M32R_OPERAND_UIMM4 :
2983       fields->f_uimm4 = value;
2984       break;
2985     case M32R_OPERAND_UIMM5 :
2986       fields->f_uimm5 = value;
2987       break;
2988     case M32R_OPERAND_UIMM16 :
2989       fields->f_uimm16 = value;
2990       break;
2991 /* start-sanitize-m32rx */
2992     case M32R_OPERAND_IMM1 :
2993       fields->f_imm1 = value;
2994       break;
2995 /* end-sanitize-m32rx */
2996 /* start-sanitize-m32rx */
2997     case M32R_OPERAND_ACCD :
2998       fields->f_accd = value;
2999       break;
3000 /* end-sanitize-m32rx */
3001 /* start-sanitize-m32rx */
3002     case M32R_OPERAND_ACCS :
3003       fields->f_accs = value;
3004       break;
3005 /* end-sanitize-m32rx */
3006 /* start-sanitize-m32rx */
3007     case M32R_OPERAND_ACC :
3008       fields->f_acc = value;
3009       break;
3010 /* end-sanitize-m32rx */
3011     case M32R_OPERAND_HASH :
3012       fields->f_nil = value;
3013       break;
3014     case M32R_OPERAND_HI16 :
3015       fields->f_hi16 = value;
3016       break;
3017     case M32R_OPERAND_SLO16 :
3018       fields->f_simm16 = value;
3019       break;
3020     case M32R_OPERAND_ULO16 :
3021       fields->f_uimm16 = value;
3022       break;
3023     case M32R_OPERAND_UIMM24 :
3024       fields->f_uimm24 = value;
3025       break;
3026     case M32R_OPERAND_DISP8 :
3027       fields->f_disp8 = value;
3028       break;
3029     case M32R_OPERAND_DISP16 :
3030       fields->f_disp16 = value;
3031       break;
3032     case M32R_OPERAND_DISP24 :
3033       fields->f_disp24 = value;
3034       break;
3035
3036     default :
3037       /* xgettext:c-format */
3038       fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
3039                        opindex);
3040       abort ();
3041   }
3042 }
3043