opcodes/m32r-opc.c

   1 /* CGEN opcode support for m32r.
   2
   3 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   4
   5 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20
  21 */
  22
  23
  24 #include "sysdep.h"
  25 #include <stdio.h>
  26 #include "ansidecl.h"
  27 #include "libiberty.h"
  28 #include "bfd.h"
  29 #include "m32r-opc.h"
  30
  31 /* Attributes.  */
  32
  33 static const CGEN_ATTR_ENTRY MACH_attr[] =
  34 {
  35   { "m32r", MACH_M32R },
  36   { 0, 0 }
  37 };
  38
  39 const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
  40 {
  41   { "ABS-ADDR", NULL },
  42   { "FAKE", NULL },
  43   { "NEGATIVE", NULL },
  44   { "PC", NULL },
  45   { "PCREL-ADDR", NULL },
  46   { "RELAX", NULL },
  47   { "RELOC", NULL },
  48   { "SIGN-OPT", NULL },
  49   { "UNSIGNED", NULL },
  50   { 0, 0 }
  51 };
  52
  53 const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
  54 {
  55   { "ALIAS", NULL },
  56   { "COND-CTI", NULL },
  57   { "FILL-SLOT", NULL },
  58   { "RELAX", NULL },
  59   { "RELAX-BC", NULL },
  60   { "RELAX-BL", NULL },
  61   { "RELAX-BNC", NULL },
  62   { "RELAX-BRA", NULL },
  63   { "RELAXABLE", NULL },
  64   { "UNCOND-CTI", NULL },
  65   { 0, 0 }
  66 };
  67
  68 CGEN_KEYWORD_ENTRY m32r_cgen_opval_mach_entries[] =
  69 {
  70   { "m32r", MACH_M32R }
  71 };
  72
  73 CGEN_KEYWORD m32r_cgen_opval_mach =
  74 {
  75   & m32r_cgen_opval_mach_entries[0],
  76   1
  77 };
  78
  79 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_gr_entries[] =
  80 {
  81   { "fp", 13 },
  82   { "lr", 14 },
  83   { "sp", 15 },
  84   { "r0", 0 },
  85   { "r1", 1 },
  86   { "r2", 2 },
  87   { "r3", 3 },
  88   { "r4", 4 },
  89   { "r5", 5 },
  90   { "r6", 6 },
  91   { "r7", 7 },
  92   { "r8", 8 },
  93   { "r9", 9 },
  94   { "r10", 10 },
  95   { "r11", 11 },
  96   { "r12", 12 },
  97   { "r13", 13 },
  98   { "r14", 14 },
  99   { "r15", 15 }
 100 };
 101
 102 CGEN_KEYWORD m32r_cgen_opval_h_gr =
 103 {
 104   & m32r_cgen_opval_h_gr_entries[0],
 105   19
 106 };
 107
 108 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_cr_entries[] =
 109 {
 110   { "psw", 0 },
 111   { "cbr", 1 },
 112   { "spi", 2 },
 113   { "spu", 3 },
 114   { "bpc", 6 },
 115   { "cr0", 0 },
 116   { "cr1", 1 },
 117   { "cr2", 2 },
 118   { "cr3", 3 },
 119   { "cr4", 4 },
 120   { "cr5", 5 },
 121   { "cr6", 6 }
 122 };
 123
 124 CGEN_KEYWORD m32r_cgen_opval_h_cr =
 125 {
 126   & m32r_cgen_opval_h_cr_entries[0],
 127   12
 128 };
 129
 130
 131 static CGEN_HW_ENTRY m32r_cgen_hw_entries[] =
 132 {
 133   { & m32r_cgen_hw_entries[1], "h-pc", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 134   { & m32r_cgen_hw_entries[2], "h-memory", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 135   { & m32r_cgen_hw_entries[3], "h-sint", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 136   { & m32r_cgen_hw_entries[4], "h-uint", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 137   { & m32r_cgen_hw_entries[5], "h-addr", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 138   { & m32r_cgen_hw_entries[6], "h-iaddr", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 139   { & m32r_cgen_hw_entries[7], "h-hi16", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 140   { & m32r_cgen_hw_entries[8], "h-slo16", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 141   { & m32r_cgen_hw_entries[9], "h-ulo16", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 142   { & m32r_cgen_hw_entries[10], "h-gr", CGEN_ASM_KEYWORD /*FIXME*/, & m32r_cgen_opval_h_gr },
 143   { & m32r_cgen_hw_entries[11], "h-cr", CGEN_ASM_KEYWORD /*FIXME*/, & m32r_cgen_opval_h_cr },
 144   { & m32r_cgen_hw_entries[12], "h-accum", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 145   { & m32r_cgen_hw_entries[13], "h-cond", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 146   { & m32r_cgen_hw_entries[14], "h-sm", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 147   { & m32r_cgen_hw_entries[15], "h-bsm", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 148   { & m32r_cgen_hw_entries[16], "h-ie", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 149   { & m32r_cgen_hw_entries[17], "h-bie", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 150   { & m32r_cgen_hw_entries[18], "h-bcond", CGEN_ASM_KEYWORD /*FIXME*/, 0 },
 151   { NULL, "h-bpc", CGEN_ASM_KEYWORD /*FIXME*/, 0 }
 152 };
 153
 154
 155 const CGEN_OPERAND m32r_cgen_operand_table[CGEN_NUM_OPERANDS] =
 156 {
 157 /* pc: program counter */
 158   { "pc", 0, 0, { 0, 0|(1<<CGEN_OPERAND_FAKE)|(1<<CGEN_OPERAND_PC), { 0 } }  },
 159 /* sr: source register */
 160   { "sr", 12, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 161 /* dr: destination register */
 162   { "dr", 4, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 163 /* src1: source register 1 */
 164   { "src1", 4, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 165 /* src2: source register 2 */
 166   { "src2", 12, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 167 /* scr: source control register */
 168   { "scr", 12, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 169 /* dcr: destination control register */
 170   { "dcr", 4, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 171 /* simm8: 8 bit signed immediate */
 172   { "simm8", 8, 8, { 0, 0, { 0 } }  },
 173 /* simm16: 16 bit signed immediate */
 174   { "simm16", 16, 16, { 0, 0, { 0 } }  },
 175 /* uimm4: 4 bit trap number */
 176   { "uimm4", 12, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 177 /* uimm5: 5 bit shift count */
 178   { "uimm5", 11, 5, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 179 /* uimm16: 16 bit unsigned immediate */
 180   { "uimm16", 16, 16, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 181 /* hi16: high 16 bit immediate, sign optional */
 182   { "hi16", 16, 16, { 0, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 183 /* slo16: 16 bit signed immediate, for low() */
 184   { "slo16", 16, 16, { 0, 0, { 0 } }  },
 185 /* ulo16: 16 bit unsigned immediate, for low() */
 186   { "ulo16", 16, 16, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 187 /* uimm24: 24 bit address */
 188   { "uimm24", 8, 24, { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 189 /* disp8: 8 bit displacement */
 190   { "disp8", 8, 8, { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
 191 /* disp16: 16 bit displacement */
 192   { "disp16", 16, 16, { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
 193 /* disp24: 24 bit displacement */
 194   { "disp24", 8, 24, { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
 195 /* condbit: condition bit */
 196   { "condbit", 0, 0, { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } }  },
 197 /* accum: accumulator */
 198   { "accum", 0, 0, { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } }  },
 199 };
 200
 201 #define OP 1 /* syntax value for mnemonic */
 202
 203 static const CGEN_SYNTAX syntax_table[] =
 204 {
 205 /* <op> $dr,$sr */
 206 /*   0 */  { OP, ' ', 130, ',', 129, 0 },
 207 /* <op> $dr,$sr,$slo16 */
 208 /*   1 */  { OP, ' ', 130, ',', 129, ',', 141, 0 },
 209 /* <op> $dr,$sr,$uimm16 */
 210 /*   2 */  { OP, ' ', 130, ',', 129, ',', 139, 0 },
 211 /* <op> $dr,$sr,$ulo16 */
 212 /*   3 */  { OP, ' ', 130, ',', 129, ',', 142, 0 },
 213 /* <op> $dr,$simm8 */
 214 /*   4 */  { OP, ' ', 130, ',', 135, 0 },
 215 /* <op> $dr,$sr,$simm16 */
 216 /*   5 */  { OP, ' ', 130, ',', 129, ',', 136, 0 },
 217 /* <op> $disp8 */
 218 /*   6 */  { OP, ' ', 144, 0 },
 219 /* <op> $disp24 */
 220 /*   7 */  { OP, ' ', 146, 0 },
 221 /* <op> $src1,$src2,$disp16 */
 222 /*   8 */  { OP, ' ', 131, ',', 132, ',', 145, 0 },
 223 /* <op> $src2,$disp16 */
 224 /*   9 */  { OP, ' ', 132, ',', 145, 0 },
 225 /* <op> $src1,$src2 */
 226 /*  10 */  { OP, ' ', 131, ',', 132, 0 },
 227 /* <op> $src2,$simm16 */
 228 /*  11 */  { OP, ' ', 132, ',', 136, 0 },
 229 /* <op> $src2,$uimm16 */
 230 /*  12 */  { OP, ' ', 132, ',', 139, 0 },
 231 /* <op> $sr */
 232 /*  13 */  { OP, ' ', 129, 0 },
 233 /* <op> $dr,@$sr */
 234 /*  14 */  { OP, ' ', 130, ',', '@', 129, 0 },
 235 /* <op> $dr,@($sr) */
 236 /*  15 */  { OP, ' ', 130, ',', '@', '(', 129, ')', 0 },
 237 /* <op> $dr,@($slo16,$sr) */
 238 /*  16 */  { OP, ' ', 130, ',', '@', '(', 141, ',', 129, ')', 0 },
 239 /* <op> $dr,@($sr,$slo16) */
 240 /*  17 */  { OP, ' ', 130, ',', '@', '(', 129, ',', 141, ')', 0 },
 241 /* <op> $dr,@$sr+ */
 242 /*  18 */  { OP, ' ', 130, ',', '@', 129, '+', 0 },
 243 /* <op> $dr,$uimm24 */
 244 /*  19 */  { OP, ' ', 130, ',', 143, 0 },
 245 /* <op> $dr,$slo16 */
 246 /*  20 */  { OP, ' ', 130, ',', 141, 0 },
 247 /* <op> $dr */
 248 /*  21 */  { OP, ' ', 130, 0 },
 249 /* <op> $dr,$scr */
 250 /*  22 */  { OP, ' ', 130, ',', 133, 0 },
 251 /* <op> $src1 */
 252 /*  23 */  { OP, ' ', 131, 0 },
 253 /* <op> $sr,$dcr */
 254 /*  24 */  { OP, ' ', 129, ',', 134, 0 },
 255 /* <op> */
 256 /*  25 */  { OP, 0 },
 257 /* <op> $dr,$hi16 */
 258 /*  26 */  { OP, ' ', 130, ',', 140, 0 },
 259 /* <op> $dr,$uimm5 */
 260 /*  27 */  { OP, ' ', 130, ',', 138, 0 },
 261 /* <op> $src1,@$src2 */
 262 /*  28 */  { OP, ' ', 131, ',', '@', 132, 0 },
 263 /* <op> $src1,@($src2) */
 264 /*  29 */  { OP, ' ', 131, ',', '@', '(', 132, ')', 0 },
 265 /* <op> $src1,@($slo16,$src2) */
 266 /*  30 */  { OP, ' ', 131, ',', '@', '(', 141, ',', 132, ')', 0 },
 267 /* <op> $src1,@($src2,$slo16) */
 268 /*  31 */  { OP, ' ', 131, ',', '@', '(', 132, ',', 141, ')', 0 },
 269 /* <op> $src1,@+$src2 */
 270 /*  32 */  { OP, ' ', 131, ',', '@', '+', 132, 0 },
 271 /* <op> $src1,@-$src2 */
 272 /*  33 */  { OP, ' ', 131, ',', '@', '-', 132, 0 },
 273 /* <op> $uimm4 */
 274 /*  34 */  { OP, ' ', 137, 0 },
 275 };
 276
 277 #undef OP
 278
 279 static const CGEN_FORMAT format_table[] =
 280 {
 281 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr. */
 282 /*   0 */  { 16, 16, 0xf0f0 },
 283 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.slo16. */
 284 /*   1 */  { 32, 32, 0xf0f00000 },
 285 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-uimm16.uimm16. */
 286 /*   2 */  { 32, 32, 0xf0f00000 },
 287 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-uimm16.ulo16. */
 288 /*   3 */  { 32, 32, 0xf0f00000 },
 289 /* f-op1.number.f-r1.dr.f-simm8.simm8. */
 290 /*   4 */  { 16, 16, 0xf000 },
 291 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.simm16. */
 292 /*   5 */  { 32, 32, 0xf0f00000 },
 293 /* f-op1.number.f-r1.number.f-disp8.disp8. */
 294 /*   6 */  { 16, 16, 0xff00 },
 295 /* f-op1.number.f-r1.number.f-disp24.disp24. */
 296 /*   7 */  { 32, 32, 0xff000000 },
 297 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2.f-disp16.disp16. */
 298 /*   8 */  { 32, 32, 0xf0f00000 },
 299 /* f-op1.number.f-r1.number.f-op2.number.f-r2.src2.f-disp16.disp16. */
 300 /*   9 */  { 32, 32, 0xfff00000 },
 301 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2. */
 302 /*  10 */  { 16, 16, 0xf0f0 },
 303 /* f-op1.number.f-r1.number.f-op2.number.f-r2.src2.f-simm16.simm16. */
 304 /*  11 */  { 32, 32, 0xfff00000 },
 305 /* f-op1.number.f-r1.number.f-op2.number.f-r2.src2.f-uimm16.uimm16. */
 306 /*  12 */  { 32, 32, 0xfff00000 },
 307 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.sr.f-simm16.number. */
 308 /*  13 */  { 32, 32, 0xf0f0ffff },
 309 /* f-op1.number.f-r1.number.f-op2.number.f-r2.sr. */
 310 /*  14 */  { 16, 16, 0xfff0 },
 311 /* f-op1.number.f-r1.dr.f-uimm24.uimm24. */
 312 /*  15 */  { 32, 32, 0xf0000000 },
 313 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.number.f-simm16.slo16. */
 314 /*  16 */  { 32, 32, 0xf0ff0000 },
 315 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.number. */
 316 /*  17 */  { 16, 16, 0xf0ff },
 317 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.scr. */
 318 /*  18 */  { 16, 16, 0xf0f0 },
 319 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.number. */
 320 /*  19 */  { 16, 16, 0xf0ff },
 321 /* f-op1.number.f-r1.dcr.f-op2.number.f-r2.sr. */
 322 /*  20 */  { 16, 16, 0xf0f0 },
 323 /* f-op1.number.f-r1.number.f-op2.number.f-r2.number. */
 324 /*  21 */  { 16, 16, 0xffff },
 325 /* f-op1.number.f-r1.dr.f-op2.number.f-r2.number.f-hi16.hi16. */
 326 /*  22 */  { 32, 32, 0xf0ff0000 },
 327 /* f-op1.number.f-r1.dr.f-shift-op2.number.f-uimm5.uimm5. */
 328 /*  23 */  { 16, 16, 0xf0e0 },
 329 /* f-op1.number.f-r1.src1.f-op2.number.f-r2.src2.f-simm16.slo16. */
 330 /*  24 */  { 32, 32, 0xf0f00000 },
 331 /* f-op1.number.f-r1.number.f-op2.number.f-uimm4.uimm4. */
 332 /*  25 */  { 16, 16, 0xfff0 },
 333 };
 334
 335 #define A(a) (1 << CGEN_CAT3 (CGEN_INSN,_,a))
 336 #define SYN(n) (& syntax_table[n])
 337 #define FMT(n) (& format_table[n])
 338
 339 const CGEN_INSN m32r_cgen_insn_table_entries[CGEN_NUM_INSNS] =
 340 {
 341   /* null first entry, end of all hash chains */
 342   { { 0 }, 0 },
 343 /* add $dr,$sr */
 344   {
 345     { 1, 1, 1, 1 },
 346     "add", "add", SYN (0), FMT (0), 0xa0,
 347     { 0, 0, { 0 } }
 348   },
 349 /* add3 $dr,$sr,$slo16 */
 350   {
 351     { 1, 1, 1, 1 },
 352     "add3", "add3", SYN (1), FMT (1), 0x80a00000,
 353     { 0, 0, { 0 } }
 354   },
 355 /* and $dr,$sr */
 356   {
 357     { 1, 1, 1, 1 },
 358     "and", "and", SYN (0), FMT (0), 0xc0,
 359     { 0, 0, { 0 } }
 360   },
 361 /* and3 $dr,$sr,$uimm16 */
 362   {
 363     { 1, 1, 1, 1 },
 364     "and3", "and3", SYN (2), FMT (2), 0x80c00000,
 365     { 0, 0, { 0 } }
 366   },
 367 /* or $dr,$sr */
 368   {
 369     { 1, 1, 1, 1 },
 370     "or", "or", SYN (0), FMT (0), 0xe0,
 371     { 0, 0, { 0 } }
 372   },
 373 /* or3 $dr,$sr,$ulo16 */
 374   {
 375     { 1, 1, 1, 1 },
 376     "or3", "or3", SYN (3), FMT (3), 0x80e00000,
 377     { 0, 0, { 0 } }
 378   },
 379 /* xor $dr,$sr */
 380   {
 381     { 1, 1, 1, 1 },
 382     "xor", "xor", SYN (0), FMT (0), 0xd0,
 383     { 0, 0, { 0 } }
 384   },
 385 /* xor3 $dr,$sr,$uimm16 */
 386   {
 387     { 1, 1, 1, 1 },
 388     "xor3", "xor3", SYN (2), FMT (2), 0x80d00000,
 389     { 0, 0, { 0 } }
 390   },
 391 /* addi $dr,$simm8 */
 392   {
 393     { 1, 1, 1, 1 },
 394     "addi", "addi", SYN (4), FMT (4), 0x4000,
 395     { 0, 0, { 0 } }
 396   },
 397 /* addv $dr,$sr */
 398   {
 399     { 1, 1, 1, 1 },
 400     "addv", "addv", SYN (0), FMT (0), 0x80,
 401     { 0, 0, { 0 } }
 402   },
 403 /* addv3 $dr,$sr,$simm16 */
 404   {
 405     { 1, 1, 1, 1 },
 406     "addv3", "addv3", SYN (5), FMT (5), 0x80800000,
 407     { 0, 0, { 0 } }
 408   },
 409 /* addx $dr,$sr */
 410   {
 411     { 1, 1, 1, 1 },
 412     "addx", "addx", SYN (0), FMT (0), 0x90,
 413     { 0, 0, { 0 } }
 414   },
 415 /* bc $disp8 */
 416   {
 417     { 1, 1, 1, 1 },
 418     "bc8", "bc", SYN (6), FMT (6), 0x7c00,
 419     { 0, 0|A(RELAX_BC)|A(RELAXABLE)|A(COND_CTI), { 0 } }
 420   },
 421 /* bc.s $disp8 */
 422   {
 423     { 1, 1, 1, 1 },
 424     "bc8.s", "bc.s", SYN (6), FMT (6), 0x7c00,
 425     { 0, 0|A(ALIAS)|A(COND_CTI), { 0 } }
 426   },
 427 /* bc $disp24 */
 428   {
 429     { 1, 1, 1, 1 },
 430     "bc24", "bc", SYN (7), FMT (7), 0xfc000000,
 431     { 0, 0|A(RELAX_BC)|A(RELAX)|A(COND_CTI), { 0 } }
 432   },
 433 /* bc.l $disp24 */
 434   {
 435     { 1, 1, 1, 1 },
 436     "bc24.l", "bc.l", SYN (7), FMT (7), 0xfc000000,
 437     { 0, 0|A(ALIAS)|A(COND_CTI), { 0 } }
 438   },
 439 /* beq $src1,$src2,$disp16 */
 440   {
 441     { 1, 1, 1, 1 },
 442     "beq", "beq", SYN (8), FMT (8), 0xb0000000,
 443     { 0, 0|A(COND_CTI), { 0 } }
 444   },
 445 /* beqz $src2,$disp16 */
 446   {
 447     { 1, 1, 1, 1 },
 448     "beqz", "beqz", SYN (9), FMT (9), 0xb0800000,
 449     { 0, 0|A(COND_CTI), { 0 } }
 450   },
 451 /* bgez $src2,$disp16 */
 452   {
 453     { 1, 1, 1, 1 },
 454     "bgez", "bgez", SYN (9), FMT (9), 0xb0b00000,
 455     { 0, 0|A(COND_CTI), { 0 } }
 456   },
 457 /* bgtz $src2,$disp16 */
 458   {
 459     { 1, 1, 1, 1 },
 460     "bgtz", "bgtz", SYN (9), FMT (9), 0xb0d00000,
 461     { 0, 0|A(COND_CTI), { 0 } }
 462   },
 463 /* blez $src2,$disp16 */
 464   {
 465     { 1, 1, 1, 1 },
 466     "blez", "blez", SYN (9), FMT (9), 0xb0c00000,
 467     { 0, 0|A(COND_CTI), { 0 } }
 468   },
 469 /* bltz $src2,$disp16 */
 470   {
 471     { 1, 1, 1, 1 },
 472     "bltz", "bltz", SYN (9), FMT (9), 0xb0a00000,
 473     { 0, 0|A(COND_CTI), { 0 } }
 474   },
 475 /* bnez $src2,$disp16 */
 476   {
 477     { 1, 1, 1, 1 },
 478     "bnez", "bnez", SYN (9), FMT (9), 0xb0900000,
 479     { 0, 0|A(COND_CTI), { 0 } }
 480   },
 481 /* bl $disp8 */
 482   {
 483     { 1, 1, 1, 1 },
 484     "bl8", "bl", SYN (6), FMT (6), 0x7e00,
 485     { 0, 0|A(FILL_SLOT)|A(RELAX_BL)|A(RELAXABLE)|A(UNCOND_CTI), { 0 } }
 486   },
 487 /* bl.s $disp8 */
 488   {
 489     { 1, 1, 1, 1 },
 490     "bl8.s", "bl.s", SYN (6), FMT (6), 0x7e00,
 491     { 0, 0|A(FILL_SLOT)|A(ALIAS)|A(UNCOND_CTI), { 0 } }
 492   },
 493 /* bl $disp24 */
 494   {
 495     { 1, 1, 1, 1 },
 496     "bl24", "bl", SYN (7), FMT (7), 0xfe000000,
 497     { 0, 0|A(RELAX_BL)|A(RELAX)|A(UNCOND_CTI), { 0 } }
 498   },
 499 /* bl.l $disp24 */
 500   {
 501     { 1, 1, 1, 1 },
 502     "bl24.l", "bl.l", SYN (7), FMT (7), 0xfe000000,
 503     { 0, 0|A(ALIAS)|A(UNCOND_CTI), { 0 } }
 504   },
 505 /* bnc $disp8 */
 506   {
 507     { 1, 1, 1, 1 },
 508     "bnc8", "bnc", SYN (6), FMT (6), 0x7d00,
 509     { 0, 0|A(RELAX_BNC)|A(RELAXABLE)|A(COND_CTI), { 0 } }
 510   },
 511 /* bnc.s $disp8 */
 512   {
 513     { 1, 1, 1, 1 },
 514     "bnc8.s", "bnc.s", SYN (6), FMT (6), 0x7d00,
 515     { 0, 0|A(ALIAS)|A(COND_CTI), { 0 } }
 516   },
 517 /* bnc $disp24 */
 518   {
 519     { 1, 1, 1, 1 },
 520     "bnc24", "bnc", SYN (7), FMT (7), 0xfd000000,
 521     { 0, 0|A(RELAX_BNC)|A(RELAX)|A(COND_CTI), { 0 } }
 522   },
 523 /* bnc.l $disp24 */
 524   {
 525     { 1, 1, 1, 1 },
 526     "bnc24.l", "bnc.l", SYN (7), FMT (7), 0xfd000000,
 527     { 0, 0|A(ALIAS)|A(COND_CTI), { 0 } }
 528   },
 529 /* bne $src1,$src2,$disp16 */
 530   {
 531     { 1, 1, 1, 1 },
 532     "bne", "bne", SYN (8), FMT (8), 0xb0100000,
 533     { 0, 0|A(COND_CTI), { 0 } }
 534   },
 535 /* bra $disp8 */
 536   {
 537     { 1, 1, 1, 1 },
 538     "bra8", "bra", SYN (6), FMT (6), 0x7f00,
 539     { 0, 0|A(RELAX_BRA)|A(RELAXABLE)|A(UNCOND_CTI), { 0 } }
 540   },
 541 /* bra.s $disp8 */
 542   {
 543     { 1, 1, 1, 1 },
 544     "bra8.s", "bra.s", SYN (6), FMT (6), 0x7f00,
 545     { 0, 0|A(ALIAS)|A(UNCOND_CTI), { 0 } }
 546   },
 547 /* bra $disp24 */
 548   {
 549     { 1, 1, 1, 1 },
 550     "bra24", "bra", SYN (7), FMT (7), 0xff000000,
 551     { 0, 0|A(RELAX_BRA)|A(RELAX)|A(UNCOND_CTI), { 0 } }
 552   },
 553 /* bra.l $disp24 */
 554   {
 555     { 1, 1, 1, 1 },
 556     "bra24.l", "bra.l", SYN (7), FMT (7), 0xff000000,
 557     { 0, 0|A(ALIAS)|A(UNCOND_CTI), { 0 } }
 558   },
 559 /* cmp $src1,$src2 */
 560   {
 561     { 1, 1, 1, 1 },
 562     "cmp", "cmp", SYN (10), FMT (10), 0x40,
 563     { 0, 0, { 0 } }
 564   },
 565 /* cmpi $src2,$simm16 */
 566   {
 567     { 1, 1, 1, 1 },
 568     "cmpi", "cmpi", SYN (11), FMT (11), 0x80400000,
 569     { 0, 0, { 0 } }
 570   },
 571 /* cmpu $src1,$src2 */
 572   {
 573     { 1, 1, 1, 1 },
 574     "cmpu", "cmpu", SYN (10), FMT (10), 0x50,
 575     { 0, 0, { 0 } }
 576   },
 577 /* cmpui $src2,$uimm16 */
 578   {
 579     { 1, 1, 1, 1 },
 580     "cmpui", "cmpui", SYN (12), FMT (12), 0x80500000,
 581     { 0, 0, { 0 } }
 582   },
 583 /* div $dr,$sr */
 584   {
 585     { 1, 1, 1, 1 },
 586     "div", "div", SYN (0), FMT (13), 0x90000000,
 587     { 0, 0, { 0 } }
 588   },
 589 /* divu $dr,$sr */
 590   {
 591     { 1, 1, 1, 1 },
 592     "divu", "divu", SYN (0), FMT (13), 0x90100000,
 593     { 0, 0, { 0 } }
 594   },
 595 /* rem $dr,$sr */
 596   {
 597     { 1, 1, 1, 1 },
 598     "rem", "rem", SYN (0), FMT (13), 0x90200000,
 599     { 0, 0, { 0 } }
 600   },
 601 /* remu $dr,$sr */
 602   {
 603     { 1, 1, 1, 1 },
 604     "remu", "remu", SYN (0), FMT (13), 0x90300000,
 605     { 0, 0, { 0 } }
 606   },
 607 /* jl $sr */
 608   {
 609     { 1, 1, 1, 1 },
 610     "jl", "jl", SYN (13), FMT (14), 0x1ec0,
 611     { 0, 0|A(FILL_SLOT)|A(UNCOND_CTI), { 0 } }
 612   },
 613 /* jmp $sr */
 614   {
 615     { 1, 1, 1, 1 },
 616     "jmp", "jmp", SYN (13), FMT (14), 0x1fc0,
 617     { 0, 0|A(UNCOND_CTI), { 0 } }
 618   },
 619 /* ld $dr,@$sr */
 620   {
 621     { 1, 1, 1, 1 },
 622     "ld", "ld", SYN (14), FMT (0), 0x20c0,
 623     { 0, 0, { 0 } }
 624   },
 625 /* ld $dr,@($sr) */
 626   {
 627     { 1, 1, 1, 1 },
 628     "ld-2", "ld", SYN (15), FMT (0), 0x20c0,
 629     { 0, 0|A(ALIAS), { 0 } }
 630   },
 631 /* ld $dr,@($slo16,$sr) */
 632   {
 633     { 1, 1, 1, 1 },
 634     "ld-d", "ld", SYN (16), FMT (1), 0xa0c00000,
 635     { 0, 0, { 0 } }
 636   },
 637 /* ld $dr,@($sr,$slo16) */
 638   {
 639     { 1, 1, 1, 1 },
 640     "ld-d2", "ld", SYN (17), FMT (1), 0xa0c00000,
 641     { 0, 0|A(ALIAS), { 0 } }
 642   },
 643 /* ldb $dr,@$sr */
 644   {
 645     { 1, 1, 1, 1 },
 646     "ldb", "ldb", SYN (14), FMT (0), 0x2080,
 647     { 0, 0, { 0 } }
 648   },
 649 /* ldb $dr,@($sr) */
 650   {
 651     { 1, 1, 1, 1 },
 652     "ldb-2", "ldb", SYN (15), FMT (0), 0x2080,
 653     { 0, 0|A(ALIAS), { 0 } }
 654   },
 655 /* ldb $dr,@($slo16,$sr) */
 656   {
 657     { 1, 1, 1, 1 },
 658     "ldb-d", "ldb", SYN (16), FMT (1), 0xa0800000,
 659     { 0, 0, { 0 } }
 660   },
 661 /* ldb $dr,@($sr,$slo16) */
 662   {
 663     { 1, 1, 1, 1 },
 664     "ldb-d2", "ldb", SYN (17), FMT (1), 0xa0800000,
 665     { 0, 0|A(ALIAS), { 0 } }
 666   },
 667 /* ldh $dr,@$sr */
 668   {
 669     { 1, 1, 1, 1 },
 670     "ldh", "ldh", SYN (14), FMT (0), 0x20a0,
 671     { 0, 0, { 0 } }
 672   },
 673 /* ldh $dr,@($sr) */
 674   {
 675     { 1, 1, 1, 1 },
 676     "ldh-2", "ldh", SYN (15), FMT (0), 0x20a0,
 677     { 0, 0|A(ALIAS), { 0 } }
 678   },
 679 /* ldh $dr,@($slo16,$sr) */
 680   {
 681     { 1, 1, 1, 1 },
 682     "ldh-d", "ldh", SYN (16), FMT (1), 0xa0a00000,
 683     { 0, 0, { 0 } }
 684   },
 685 /* ldh $dr,@($sr,$slo16) */
 686   {
 687     { 1, 1, 1, 1 },
 688     "ldh-d2", "ldh", SYN (17), FMT (1), 0xa0a00000,
 689     { 0, 0|A(ALIAS), { 0 } }
 690   },
 691 /* ldub $dr,@$sr */
 692   {
 693     { 1, 1, 1, 1 },
 694     "ldub", "ldub", SYN (14), FMT (0), 0x2090,
 695     { 0, 0, { 0 } }
 696   },
 697 /* ldub $dr,@($sr) */
 698   {
 699     { 1, 1, 1, 1 },
 700     "ldub-2", "ldub", SYN (15), FMT (0), 0x2090,
 701     { 0, 0|A(ALIAS), { 0 } }
 702   },
 703 /* ldub $dr,@($slo16,$sr) */
 704   {
 705     { 1, 1, 1, 1 },
 706     "ldub-d", "ldub", SYN (16), FMT (1), 0xa0900000,
 707     { 0, 0, { 0 } }
 708   },
 709 /* ldub $dr,@($sr,$slo16) */
 710   {
 711     { 1, 1, 1, 1 },
 712     "ldub-d2", "ldub", SYN (17), FMT (1), 0xa0900000,
 713     { 0, 0|A(ALIAS), { 0 } }
 714   },
 715 /* lduh $dr,@$sr */
 716   {
 717     { 1, 1, 1, 1 },
 718     "lduh", "lduh", SYN (14), FMT (0), 0x20b0,
 719     { 0, 0, { 0 } }
 720   },
 721 /* lduh $dr,@($sr) */
 722   {
 723     { 1, 1, 1, 1 },
 724     "lduh-2", "lduh", SYN (15), FMT (0), 0x20b0,
 725     { 0, 0|A(ALIAS), { 0 } }
 726   },
 727 /* lduh $dr,@($slo16,$sr) */
 728   {
 729     { 1, 1, 1, 1 },
 730     "lduh-d", "lduh", SYN (16), FMT (1), 0xa0b00000,
 731     { 0, 0, { 0 } }
 732   },
 733 /* lduh $dr,@($sr,$slo16) */
 734   {
 735     { 1, 1, 1, 1 },
 736     "lduh-d2", "lduh", SYN (17), FMT (1), 0xa0b00000,
 737     { 0, 0|A(ALIAS), { 0 } }
 738   },
 739 /* ld $dr,@$sr+ */
 740   {
 741     { 1, 1, 1, 1 },
 742     "ld-plus", "ld", SYN (18), FMT (0), 0x20e0,
 743     { 0, 0, { 0 } }
 744   },
 745 /* ld24 $dr,$uimm24 */
 746   {
 747     { 1, 1, 1, 1 },
 748     "ld24", "ld24", SYN (19), FMT (15), 0xe0000000,
 749     { 0, 0, { 0 } }
 750   },
 751 /* ldi $dr,$simm8 */
 752   {
 753     { 1, 1, 1, 1 },
 754     "ldi8", "ldi", SYN (4), FMT (4), 0x6000,
 755     { 0, 0, { 0 } }
 756   },
 757 /* ldi8 $dr,$simm8 */
 758   {
 759     { 1, 1, 1, 1 },
 760     "ldi8a", "ldi8", SYN (4), FMT (4), 0x6000,
 761     { 0, 0|A(ALIAS), { 0 } }
 762   },
 763 /* ldi $dr,$slo16 */
 764   {
 765     { 1, 1, 1, 1 },
 766     "ldi16", "ldi", SYN (20), FMT (16), 0x90f00000,
 767     { 0, 0, { 0 } }
 768   },
 769 /* ldi16 $dr,$slo16 */
 770   {
 771     { 1, 1, 1, 1 },
 772     "ldi16a", "ldi16", SYN (20), FMT (16), 0x90f00000,
 773     { 0, 0|A(ALIAS), { 0 } }
 774   },
 775 /* lock $dr,@$sr */
 776   {
 777     { 1, 1, 1, 1 },
 778     "lock", "lock", SYN (14), FMT (0), 0x20d0,
 779     { 0, 0, { 0 } }
 780   },
 781 /* machi $src1,$src2 */
 782   {
 783     { 1, 1, 1, 1 },
 784     "machi", "machi", SYN (10), FMT (10), 0x3040,
 785     { 0, 0, { 0 } }
 786   },
 787 /* maclo $src1,$src2 */
 788   {
 789     { 1, 1, 1, 1 },
 790     "maclo", "maclo", SYN (10), FMT (10), 0x3050,
 791     { 0, 0, { 0 } }
 792   },
 793 /* macwhi $src1,$src2 */
 794   {
 795     { 1, 1, 1, 1 },
 796     "macwhi", "macwhi", SYN (10), FMT (10), 0x3060,
 797     { 0, 0, { 0 } }
 798   },
 799 /* macwlo $src1,$src2 */
 800   {
 801     { 1, 1, 1, 1 },
 802     "macwlo", "macwlo", SYN (10), FMT (10), 0x3070,
 803     { 0, 0, { 0 } }
 804   },
 805 /* mul $dr,$sr */
 806   {
 807     { 1, 1, 1, 1 },
 808     "mul", "mul", SYN (0), FMT (0), 0x1060,
 809     { 0, 0, { 0 } }
 810   },
 811 /* mulhi $src1,$src2 */
 812   {
 813     { 1, 1, 1, 1 },
 814     "mulhi", "mulhi", SYN (10), FMT (10), 0x3000,
 815     { 0, 0, { 0 } }
 816   },
 817 /* mullo $src1,$src2 */
 818   {
 819     { 1, 1, 1, 1 },
 820     "mullo", "mullo", SYN (10), FMT (10), 0x3010,
 821     { 0, 0, { 0 } }
 822   },
 823 /* mulwhi $src1,$src2 */
 824   {
 825     { 1, 1, 1, 1 },
 826     "mulwhi", "mulwhi", SYN (10), FMT (10), 0x3020,
 827     { 0, 0, { 0 } }
 828   },
 829 /* mulwlo $src1,$src2 */
 830   {
 831     { 1, 1, 1, 1 },
 832     "mulwlo", "mulwlo", SYN (10), FMT (10), 0x3030,
 833     { 0, 0, { 0 } }
 834   },
 835 /* mv $dr,$sr */
 836   {
 837     { 1, 1, 1, 1 },
 838     "mv", "mv", SYN (0), FMT (0), 0x1080,
 839     { 0, 0, { 0 } }
 840   },
 841 /* mvfachi $dr */
 842   {
 843     { 1, 1, 1, 1 },
 844     "mvfachi", "mvfachi", SYN (21), FMT (17), 0x50f0,
 845     { 0, 0, { 0 } }
 846   },
 847 /* mvfaclo $dr */
 848   {
 849     { 1, 1, 1, 1 },
 850     "mvfaclo", "mvfaclo", SYN (21), FMT (17), 0x50f1,
 851     { 0, 0, { 0 } }
 852   },
 853 /* mvfacmi $dr */
 854   {
 855     { 1, 1, 1, 1 },
 856     "mvfacmi", "mvfacmi", SYN (21), FMT (17), 0x50f2,
 857     { 0, 0, { 0 } }
 858   },
 859 /* mvfc $dr,$scr */
 860   {
 861     { 1, 1, 1, 1 },
 862     "mvfc", "mvfc", SYN (22), FMT (18), 0x1090,
 863     { 0, 0, { 0 } }
 864   },
 865 /* mvtachi $src1 */
 866   {
 867     { 1, 1, 1, 1 },
 868     "mvtachi", "mvtachi", SYN (23), FMT (19), 0x5070,
 869     { 0, 0, { 0 } }
 870   },
 871 /* mvtaclo $src1 */
 872   {
 873     { 1, 1, 1, 1 },
 874     "mvtaclo", "mvtaclo", SYN (23), FMT (19), 0x5071,
 875     { 0, 0, { 0 } }
 876   },
 877 /* mvtc $sr,$dcr */
 878   {
 879     { 1, 1, 1, 1 },
 880     "mvtc", "mvtc", SYN (24), FMT (20), 0x10a0,
 881     { 0, 0, { 0 } }
 882   },
 883 /* neg $dr,$sr */
 884   {
 885     { 1, 1, 1, 1 },
 886     "neg", "neg", SYN (0), FMT (0), 0x30,
 887     { 0, 0, { 0 } }
 888   },
 889 /* nop */
 890   {
 891     { 1, 1, 1, 1 },
 892     "nop", "nop", SYN (25), FMT (21), 0x7000,
 893     { 0, 0, { 0 } }
 894   },
 895 /* not $dr,$sr */
 896   {
 897     { 1, 1, 1, 1 },
 898     "not", "not", SYN (0), FMT (0), 0xb0,
 899     { 0, 0, { 0 } }
 900   },
 901 /* rac */
 902   {
 903     { 1, 1, 1, 1 },
 904     "rac", "rac", SYN (25), FMT (21), 0x5090,
 905     { 0, 0, { 0 } }
 906   },
 907 /* rach */
 908   {
 909     { 1, 1, 1, 1 },
 910     "rach", "rach", SYN (25), FMT (21), 0x5080,
 911     { 0, 0, { 0 } }
 912   },
 913 /* rte */
 914   {
 915     { 1, 1, 1, 1 },
 916     "rte", "rte", SYN (25), FMT (21), 0x10d6,
 917     { 0, 0|A(UNCOND_CTI), { 0 } }
 918   },
 919 /* seth $dr,$hi16 */
 920   {
 921     { 1, 1, 1, 1 },
 922     "seth", "seth", SYN (26), FMT (22), 0xd0c00000,
 923     { 0, 0, { 0 } }
 924   },
 925 /* sll $dr,$sr */
 926   {
 927     { 1, 1, 1, 1 },
 928     "sll", "sll", SYN (0), FMT (0), 0x1040,
 929     { 0, 0, { 0 } }
 930   },
 931 /* sll3 $dr,$sr,$simm16 */
 932   {
 933     { 1, 1, 1, 1 },
 934     "sll3", "sll3", SYN (5), FMT (5), 0x90c00000,
 935     { 0, 0, { 0 } }
 936   },
 937 /* slli $dr,$uimm5 */
 938   {
 939     { 1, 1, 1, 1 },
 940     "slli", "slli", SYN (27), FMT (23), 0x5040,
 941     { 0, 0, { 0 } }
 942   },
 943 /* sra $dr,$sr */
 944   {
 945     { 1, 1, 1, 1 },
 946     "sra", "sra", SYN (0), FMT (0), 0x1020,
 947     { 0, 0, { 0 } }
 948   },
 949 /* sra3 $dr,$sr,$simm16 */
 950   {
 951     { 1, 1, 1, 1 },
 952     "sra3", "sra3", SYN (5), FMT (5), 0x90a00000,
 953     { 0, 0, { 0 } }
 954   },
 955 /* srai $dr,$uimm5 */
 956   {
 957     { 1, 1, 1, 1 },
 958     "srai", "srai", SYN (27), FMT (23), 0x5020,
 959     { 0, 0, { 0 } }
 960   },
 961 /* srl $dr,$sr */
 962   {
 963     { 1, 1, 1, 1 },
 964     "srl", "srl", SYN (0), FMT (0), 0x1000,
 965     { 0, 0, { 0 } }
 966   },
 967 /* srl3 $dr,$sr,$simm16 */
 968   {
 969     { 1, 1, 1, 1 },
 970     "srl3", "srl3", SYN (5), FMT (5), 0x90800000,
 971     { 0, 0, { 0 } }
 972   },
 973 /* srli $dr,$uimm5 */
 974   {
 975     { 1, 1, 1, 1 },
 976     "srli", "srli", SYN (27), FMT (23), 0x5000,
 977     { 0, 0, { 0 } }
 978   },
 979 /* st $src1,@$src2 */
 980   {
 981     { 1, 1, 1, 1 },
 982     "st", "st", SYN (28), FMT (10), 0x2040,
 983     { 0, 0, { 0 } }
 984   },
 985 /* st $src1,@($src2) */
 986   {
 987     { 1, 1, 1, 1 },
 988     "st-2", "st", SYN (29), FMT (10), 0x2040,
 989     { 0, 0|A(ALIAS), { 0 } }
 990   },
 991 /* st $src1,@($slo16,$src2) */
 992   {
 993     { 1, 1, 1, 1 },
 994     "st-d", "st", SYN (30), FMT (24), 0xa0400000,
 995     { 0, 0, { 0 } }
 996   },
 997 /* st $src1,@($src2,$slo16) */
 998   {
 999     { 1, 1, 1, 1 },
1000     "st-d2", "st", SYN (31), FMT (24), 0xa0400000,
1001     { 0, 0|A(ALIAS), { 0 } }
1002   },
1003 /* stb $src1,@$src2 */
1004   {
1005     { 1, 1, 1, 1 },
1006     "stb", "stb", SYN (28), FMT (10), 0x2000,
1007     { 0, 0, { 0 } }
1008   },
1009 /* stb $src1,@($src2) */
1010   {
1011     { 1, 1, 1, 1 },
1012     "stb-2", "stb", SYN (29), FMT (10), 0x2000,
1013     { 0, 0|A(ALIAS), { 0 } }
1014   },
1015 /* stb $src1,@($slo16,$src2) */
1016   {
1017     { 1, 1, 1, 1 },
1018     "stb-d", "stb", SYN (30), FMT (24), 0xa0000000,
1019     { 0, 0, { 0 } }
1020   },
1021 /* stb $src1,@($src2,$slo16) */
1022   {
1023     { 1, 1, 1, 1 },
1024     "stb-d2", "stb", SYN (31), FMT (24), 0xa0000000,
1025     { 0, 0|A(ALIAS), { 0 } }
1026   },
1027 /* sth $src1,@$src2 */
1028   {
1029     { 1, 1, 1, 1 },
1030     "sth", "sth", SYN (28), FMT (10), 0x2020,
1031     { 0, 0, { 0 } }
1032   },
1033 /* sth $src1,@($src2) */
1034   {
1035     { 1, 1, 1, 1 },
1036     "sth-2", "sth", SYN (29), FMT (10), 0x2020,
1037     { 0, 0|A(ALIAS), { 0 } }
1038   },
1039 /* sth $src1,@($slo16,$src2) */
1040   {
1041     { 1, 1, 1, 1 },
1042     "sth-d", "sth", SYN (30), FMT (24), 0xa0200000,
1043     { 0, 0, { 0 } }
1044   },
1045 /* sth $src1,@($src2,$slo16) */
1046   {
1047     { 1, 1, 1, 1 },
1048     "sth-d2", "sth", SYN (31), FMT (24), 0xa0200000,
1049     { 0, 0|A(ALIAS), { 0 } }
1050   },
1051 /* st $src1,@+$src2 */
1052   {
1053     { 1, 1, 1, 1 },
1054     "st-plus", "st", SYN (32), FMT (10), 0x2060,
1055     { 0, 0, { 0 } }
1056   },
1057 /* st $src1,@-$src2 */
1058   {
1059     { 1, 1, 1, 1 },
1060     "st-minus", "st", SYN (33), FMT (10), 0x2070,
1061     { 0, 0, { 0 } }
1062   },
1063 /* sub $dr,$sr */
1064   {
1065     { 1, 1, 1, 1 },
1066     "sub", "sub", SYN (0), FMT (0), 0x20,
1067     { 0, 0, { 0 } }
1068   },
1069 /* subv $dr,$sr */
1070   {
1071     { 1, 1, 1, 1 },
1072     "subv", "subv", SYN (0), FMT (0), 0x0,
1073     { 0, 0, { 0 } }
1074   },
1075 /* subx $dr,$sr */
1076   {
1077     { 1, 1, 1, 1 },
1078     "subx", "subx", SYN (0), FMT (0), 0x10,
1079     { 0, 0, { 0 } }
1080   },
1081 /* trap $uimm4 */
1082   {
1083     { 1, 1, 1, 1 },
1084     "trap", "trap", SYN (34), FMT (25), 0x10f0,
1085     { 0, 0|A(FILL_SLOT)|A(UNCOND_CTI), { 0 } }
1086   },
1087 /* unlock $src1,@$src2 */
1088   {
1089     { 1, 1, 1, 1 },
1090     "unlock", "unlock", SYN (28), FMT (10), 0x2050,
1091     { 0, 0, { 0 } }
1092   },
1093 /* push $src1 */
1094   {
1095     { 1, 1, 1, 1 },
1096     "push", "push", SYN (23), FMT (19), 0x207f,
1097     { 0, 0|A(ALIAS), { 0 } }
1098   },
1099 /* pop $dr */
1100   {
1101     { 1, 1, 1, 1 },
1102     "pop", "pop", SYN (21), FMT (17), 0x20ef,
1103     { 0, 0|A(ALIAS), { 0 } }
1104   },
1105 };
1106
1107 #undef A
1108 #undef SYN
1109 #undef FMT
1110
1111 CGEN_INSN_TABLE m32r_cgen_insn_table =
1112 {
1113   & m32r_cgen_insn_table_entries[0],
1114   sizeof (CGEN_INSN),
1115   CGEN_NUM_INSNS,
1116   NULL,
1117   m32r_cgen_asm_hash_insn, CGEN_ASM_HASH_SIZE,
1118   m32r_cgen_dis_hash_insn, CGEN_DIS_HASH_SIZE
1119 };
1120
1121 /* The hash functions are recorded here to help keep assembler code out of
1122    the disassembler and vice versa.  */
1123
1124 unsigned int
1125 m32r_cgen_asm_hash_insn (insn)
1126      const char * insn;
1127 {
1128   return CGEN_ASM_HASH (insn);
1129 }
1130
1131 unsigned int
1132 m32r_cgen_dis_hash_insn (buf, value)
1133      const char * buf;
1134      unsigned long value;
1135 {
1136   return CGEN_DIS_HASH (buf, value);
1137 }
1138
1139 CGEN_OPCODE_DATA m32r_cgen_opcode_data =
1140 {
1141   & m32r_cgen_hw_entries[0],
1142   & m32r_cgen_insn_table,
1143 };
1144
1145 void
1146 m32r_cgen_init_tables (mach)
1147     int mach;
1148 {
1149 }
1150
1151 /* Main entry point for stuffing values in cgen_fields.  */
1152
1153 CGEN_INLINE void
1154 m32r_cgen_set_operand (opindex, valuep, fields)
1155      int opindex;
1156      const long * valuep;
1157      CGEN_FIELDS * fields;
1158 {
1159   switch (opindex)
1160     {
1161     case M32R_OPERAND_SR :
1162       fields->f_r2 = * valuep;
1163       break;
1164     case M32R_OPERAND_DR :
1165       fields->f_r1 = * valuep;
1166       break;
1167     case M32R_OPERAND_SRC1 :
1168       fields->f_r1 = * valuep;
1169       break;
1170     case M32R_OPERAND_SRC2 :
1171       fields->f_r2 = * valuep;
1172       break;
1173     case M32R_OPERAND_SCR :
1174       fields->f_r2 = * valuep;
1175       break;
1176     case M32R_OPERAND_DCR :
1177       fields->f_r1 = * valuep;
1178       break;
1179     case M32R_OPERAND_SIMM8 :
1180       fields->f_simm8 = * valuep;
1181       break;
1182     case M32R_OPERAND_SIMM16 :
1183       fields->f_simm16 = * valuep;
1184       break;
1185     case M32R_OPERAND_UIMM4 :
1186       fields->f_uimm4 = * valuep;
1187       break;
1188     case M32R_OPERAND_UIMM5 :
1189       fields->f_uimm5 = * valuep;
1190       break;
1191     case M32R_OPERAND_UIMM16 :
1192       fields->f_uimm16 = * valuep;
1193       break;
1194     case M32R_OPERAND_HI16 :
1195       fields->f_hi16 = * valuep;
1196       break;
1197     case M32R_OPERAND_SLO16 :
1198       fields->f_simm16 = * valuep;
1199       break;
1200     case M32R_OPERAND_ULO16 :
1201       fields->f_uimm16 = * valuep;
1202       break;
1203     case M32R_OPERAND_UIMM24 :
1204       fields->f_uimm24 = * valuep;
1205       break;
1206     case M32R_OPERAND_DISP8 :
1207       fields->f_disp8 = * valuep;
1208       break;
1209     case M32R_OPERAND_DISP16 :
1210       fields->f_disp16 = * valuep;
1211       break;
1212     case M32R_OPERAND_DISP24 :
1213       fields->f_disp24 = * valuep;
1214       break;
1215
1216     default :
1217       fprintf (stderr, "Unrecognized field %d while setting operand.\n",
1218                        opindex);
1219       abort ();
1220   }
1221 }
1222
1223 /* Main entry point for getting values from cgen_fields.  */
1224
1225 CGEN_INLINE long
1226 m32r_cgen_get_operand (opindex, fields)
1227      int opindex;
1228      const CGEN_FIELDS * fields;
1229 {
1230   long value;
1231
1232   switch (opindex)
1233     {
1234     case M32R_OPERAND_SR :
1235       value = fields->f_r2;
1236       break;
1237     case M32R_OPERAND_DR :
1238       value = fields->f_r1;
1239       break;
1240     case M32R_OPERAND_SRC1 :
1241       value = fields->f_r1;
1242       break;
1243     case M32R_OPERAND_SRC2 :
1244       value = fields->f_r2;
1245       break;
1246     case M32R_OPERAND_SCR :
1247       value = fields->f_r2;
1248       break;
1249     case M32R_OPERAND_DCR :
1250       value = fields->f_r1;
1251       break;
1252     case M32R_OPERAND_SIMM8 :
1253       value = fields->f_simm8;
1254       break;
1255     case M32R_OPERAND_SIMM16 :
1256       value = fields->f_simm16;
1257       break;
1258     case M32R_OPERAND_UIMM4 :
1259       value = fields->f_uimm4;
1260       break;
1261     case M32R_OPERAND_UIMM5 :
1262       value = fields->f_uimm5;
1263       break;
1264     case M32R_OPERAND_UIMM16 :
1265       value = fields->f_uimm16;
1266       break;
1267     case M32R_OPERAND_HI16 :
1268       value = fields->f_hi16;
1269       break;
1270     case M32R_OPERAND_SLO16 :
1271       value = fields->f_simm16;
1272       break;
1273     case M32R_OPERAND_ULO16 :
1274       value = fields->f_uimm16;
1275       break;
1276     case M32R_OPERAND_UIMM24 :
1277       value = fields->f_uimm24;
1278       break;
1279     case M32R_OPERAND_DISP8 :
1280       value = fields->f_disp8;
1281       break;
1282     case M32R_OPERAND_DISP16 :
1283       value = fields->f_disp16;
1284       break;
1285     case M32R_OPERAND_DISP24 :
1286       value = fields->f_disp24;
1287       break;
1288
1289     default :
1290       fprintf (stderr, "Unrecognized field %d while getting operand.\n",
1291                        opindex);
1292       abort ();
1293   }
1294
1295   return value;
1296 }
1297