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* mips-dis.c (_print_insn_mips) : Handle bfd_mach_mips4320.
[deliverable/binutils-gdb.git] / opcodes / m32r-opc.c
1 /* Generic opcode table support for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
3
4 This file is used to generate m32r-opc.c.
5
6 Copyright (C) 1998 Free Software Foundation, Inc.
7
8 This file is part of the GNU Binutils and GDB, the GNU debugger.
9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
23
24 #include "sysdep.h"
25 #include <stdio.h>
26 #include "ansidecl.h"
27 #include "libiberty.h"
28 #include "bfd.h"
29 #include "symcat.h"
30 #include "m32r-opc.h"
31
32 /* Look up instruction INSN_VALUE and extract its fields.
33 If non-null INSN is the insn table entry.
34 Otherwise INSN_VALUE is examined to compute it.
35 LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
36 ALIAS_P is non-zero if alias insns are to be included in the search.
37 The result a pointer to the insn table entry, or NULL if the instruction
38 wasn't recognized. */
39
40 const CGEN_INSN *
41 m32r_cgen_lookup_insn (insn, insn_value, length, fields, alias_p)
42 const CGEN_INSN *insn;
43 cgen_insn_t insn_value;
44 int length;
45 CGEN_FIELDS *fields;
46 {
47 char buf[16];
48
49 if (!insn)
50 {
51 const CGEN_INSN_LIST *insn_list;
52
53 #ifdef CGEN_INT_INSN
54 switch (length)
55 {
56 case 8:
57 buf[0] = insn_value;
58 break;
59 case 16:
60 if (cgen_current_endian == CGEN_ENDIAN_BIG)
61 bfd_putb16 (insn_value, buf);
62 else
63 bfd_putl16 (insn_value, buf);
64 break;
65 case 32:
66 if (cgen_current_endian == CGEN_ENDIAN_BIG)
67 bfd_putb32 (insn_value, buf);
68 else
69 bfd_putl32 (insn_value, buf);
70 break;
71 default:
72 abort ();
73 }
74 #else
75 abort (); /* FIXME: unfinished */
76 #endif
77
78 /* The instructions are stored in hash lists.
79 Pick the first one and keep trying until we find the right one. */
80
81 insn_list = CGEN_DIS_LOOKUP_INSN (buf, insn_value);
82 while (insn_list != NULL)
83 {
84 insn = insn_list->insn;
85
86 if (alias_p
87 || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
88 {
89 /* Basic bit mask must be correct. */
90 /* ??? May wish to allow target to defer this check until the
91 extract handler. */
92 if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
93 {
94 length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields);
95 if (length > 0)
96 return insn;
97 }
98 }
99
100 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
101 }
102 }
103 else
104 {
105 /* Sanity check: can't pass an alias insn if ! alias_p. */
106 if (! alias_p
107 && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
108 abort ();
109
110 length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields);
111 if (length > 0)
112 return insn;
113 }
114
115 return NULL;
116 }
117
118 /* Fill in the operand instances used by insn INSN_VALUE.
119 If non-null INS is the insn table entry.
120 Otherwise INSN_VALUE is examined to compute it.
121 LENGTH is the number of bits in INSN_VALUE if known, otherwise 0.
122 INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
123 in.
124 The result a pointer to the insn table entry, or NULL if the instruction
125 wasn't recognized. */
126
127 const CGEN_INSN *
128 m32r_cgen_get_insn_operands (insn, insn_value, length, indices)
129 const CGEN_INSN *insn;
130 cgen_insn_t insn_value;
131 int length;
132 int *indices;
133 {
134 CGEN_FIELDS fields;
135 const CGEN_OPERAND_INSTANCE *opinst;
136 int i;
137
138 /* FIXME: ALIAS insns are in transition from being record in the insn table
139 to being recorded separately as macros. They don't have semantic code
140 so they can't be used here. Thus we currently always ignore the INSN
141 argument. */
142 insn = m32r_cgen_lookup_insn (NULL, insn_value, length, &fields, 0);
143 if (! insn)
144 return NULL;
145
146 for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
147 opinst != NULL
148 && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
149 ++i, ++opinst)
150 {
151 const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
152 if (op == NULL)
153 indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
154 else
155 indices[i] = m32r_cgen_get_operand (CGEN_OPERAND_INDEX (op), &fields);
156 }
157
158 return insn;
159 }
160 /* Attributes. */
161
162 static const CGEN_ATTR_ENTRY MACH_attr[] =
163 {
164 { "m32r", MACH_M32R },
165 /* start-sanitize-m32rx */
166 { "m32rx", MACH_M32RX },
167 /* end-sanitize-m32rx */
168 { "max", MACH_MAX },
169 { 0, 0 }
170 };
171
172 /* start-sanitize-m32rx */
173 static const CGEN_ATTR_ENTRY PIPE_attr[] =
174 {
175 { "NONE", PIPE_NONE },
176 { "O", PIPE_O },
177 { "S", PIPE_S },
178 { "OS", PIPE_OS },
179 { 0, 0 }
180 };
181
182 /* end-sanitize-m32rx */
183 const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
184 {
185 { "ABS-ADDR", NULL },
186 { "FAKE", NULL },
187 { "NEGATIVE", NULL },
188 { "PC", NULL },
189 { "PCREL-ADDR", NULL },
190 { "RELAX", NULL },
191 { "RELOC", NULL },
192 { "SIGN-OPT", NULL },
193 { "UNSIGNED", NULL },
194 { 0, 0 }
195 };
196
197 const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
198 {
199 { "MACH", & MACH_attr[0] },
200 /* start-sanitize-m32rx */
201 { "PIPE", & PIPE_attr[0] },
202 /* end-sanitize-m32rx */
203 { "ALIAS", NULL },
204 { "COND-CTI", NULL },
205 { "FILL-SLOT", NULL },
206 { "PARALLEL", NULL },
207 { "RELAX", NULL },
208 { "RELAXABLE", NULL },
209 { "UNCOND-CTI", NULL },
210 { 0, 0 }
211 };
212
213 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_gr_entries[] =
214 {
215 { "fp", 13 },
216 { "lr", 14 },
217 { "sp", 15 },
218 { "r0", 0 },
219 { "r1", 1 },
220 { "r2", 2 },
221 { "r3", 3 },
222 { "r4", 4 },
223 { "r5", 5 },
224 { "r6", 6 },
225 { "r7", 7 },
226 { "r8", 8 },
227 { "r9", 9 },
228 { "r10", 10 },
229 { "r11", 11 },
230 { "r12", 12 },
231 { "r13", 13 },
232 { "r14", 14 },
233 { "r15", 15 }
234 };
235
236 CGEN_KEYWORD m32r_cgen_opval_h_gr =
237 {
238 & m32r_cgen_opval_h_gr_entries[0],
239 19
240 };
241
242 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_cr_entries[] =
243 {
244 { "psw", 0 },
245 { "cbr", 1 },
246 { "spi", 2 },
247 { "spu", 3 },
248 { "bpc", 6 },
249 { "cr0", 0 },
250 { "cr1", 1 },
251 { "cr2", 2 },
252 { "cr3", 3 },
253 { "cr4", 4 },
254 { "cr5", 5 },
255 { "cr6", 6 }
256 };
257
258 CGEN_KEYWORD m32r_cgen_opval_h_cr =
259 {
260 & m32r_cgen_opval_h_cr_entries[0],
261 12
262 };
263
264 /* start-sanitize-m32rx */
265 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
266 {
267 { "a0", 0 },
268 { "a1", 1 }
269 };
270
271 CGEN_KEYWORD m32r_cgen_opval_h_accums =
272 {
273 & m32r_cgen_opval_h_accums_entries[0],
274 2
275 };
276
277 /* end-sanitize-m32rx */
278
279 /* The hardware table. */
280
281 #define HW_ENT(n) m32r_cgen_hw_entries[n]
282 static const CGEN_HW_ENTRY m32r_cgen_hw_entries[] =
283 {
284 { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0 },
285 { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0 },
286 { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0 },
287 { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0 },
288 { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0 },
289 { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0 },
290 { HW_H_HI16, & HW_ENT (HW_H_HI16 + 1), "h-hi16", CGEN_ASM_KEYWORD, (PTR) 0 },
291 { HW_H_SLO16, & HW_ENT (HW_H_SLO16 + 1), "h-slo16", CGEN_ASM_KEYWORD, (PTR) 0 },
292 { HW_H_ULO16, & HW_ENT (HW_H_ULO16 + 1), "h-ulo16", CGEN_ASM_KEYWORD, (PTR) 0 },
293 { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_gr },
294 { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_cr },
295 { HW_H_ACCUM, & HW_ENT (HW_H_ACCUM + 1), "h-accum", CGEN_ASM_KEYWORD, (PTR) 0 },
296 /* start-sanitize-m32rx */
297 { HW_H_ACCUMS, & HW_ENT (HW_H_ACCUMS + 1), "h-accums", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums },
298 /* end-sanitize-m32rx */
299 /* start-sanitize-m32rx */
300 { HW_H_ABORT, & HW_ENT (HW_H_ABORT + 1), "h-abort", CGEN_ASM_KEYWORD, (PTR) 0 },
301 /* end-sanitize-m32rx */
302 { HW_H_COND, & HW_ENT (HW_H_COND + 1), "h-cond", CGEN_ASM_KEYWORD, (PTR) 0 },
303 { HW_H_SM, & HW_ENT (HW_H_SM + 1), "h-sm", CGEN_ASM_KEYWORD, (PTR) 0 },
304 { HW_H_BSM, & HW_ENT (HW_H_BSM + 1), "h-bsm", CGEN_ASM_KEYWORD, (PTR) 0 },
305 { HW_H_IE, & HW_ENT (HW_H_IE + 1), "h-ie", CGEN_ASM_KEYWORD, (PTR) 0 },
306 { HW_H_BIE, & HW_ENT (HW_H_BIE + 1), "h-bie", CGEN_ASM_KEYWORD, (PTR) 0 },
307 { HW_H_BCOND, & HW_ENT (HW_H_BCOND + 1), "h-bcond", CGEN_ASM_KEYWORD, (PTR) 0 },
308 { HW_H_BPC, & HW_ENT (HW_H_BPC + 1), "h-bpc", CGEN_ASM_KEYWORD, (PTR) 0 },
309 { HW_H_LOCK, & HW_ENT (HW_H_LOCK + 1), "h-lock", CGEN_ASM_KEYWORD, (PTR) 0 },
310 { 0 }
311 };
312
313 /* The operand table. */
314
315 #define OPERAND(op) CONCAT2 (M32R_OPERAND_,op)
316 #define OP_ENT(op) m32r_cgen_operand_table[OPERAND (op)]
317
318 const CGEN_OPERAND m32r_cgen_operand_table[MAX_OPERANDS] =
319 {
320 /* pc: program counter */
321 { "pc", & HW_ENT (HW_H_PC), 0, 0,
322 { 0, 0|(1<<CGEN_OPERAND_FAKE)|(1<<CGEN_OPERAND_PC), { 0 } } },
323 /* sr: source register */
324 { "sr", & HW_ENT (HW_H_GR), 12, 4,
325 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
326 /* dr: destination register */
327 { "dr", & HW_ENT (HW_H_GR), 4, 4,
328 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
329 /* src1: source register 1 */
330 { "src1", & HW_ENT (HW_H_GR), 4, 4,
331 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
332 /* src2: source register 2 */
333 { "src2", & HW_ENT (HW_H_GR), 12, 4,
334 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
335 /* scr: source control register */
336 { "scr", & HW_ENT (HW_H_CR), 12, 4,
337 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
338 /* dcr: destination control register */
339 { "dcr", & HW_ENT (HW_H_CR), 4, 4,
340 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
341 /* simm8: 8 bit signed immediate */
342 { "simm8", & HW_ENT (HW_H_SINT), 8, 8,
343 { 0, 0, { 0 } } },
344 /* simm16: 16 bit signed immediate */
345 { "simm16", & HW_ENT (HW_H_SINT), 16, 16,
346 { 0, 0, { 0 } } },
347 /* uimm4: 4 bit trap number */
348 { "uimm4", & HW_ENT (HW_H_UINT), 12, 4,
349 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
350 /* uimm5: 5 bit shift count */
351 { "uimm5", & HW_ENT (HW_H_UINT), 11, 5,
352 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
353 /* uimm16: 16 bit unsigned immediate */
354 { "uimm16", & HW_ENT (HW_H_UINT), 16, 16,
355 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
356 /* start-sanitize-m32rx */
357 /* imm1: 1 bit immediate */
358 { "imm1", & HW_ENT (HW_H_UINT), 15, 1,
359 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
360 /* end-sanitize-m32rx */
361 /* start-sanitize-m32rx */
362 /* accd: accumulator destination register */
363 { "accd", & HW_ENT (HW_H_ACCUMS), 4, 2,
364 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
365 /* end-sanitize-m32rx */
366 /* start-sanitize-m32rx */
367 /* accs: accumulator source register */
368 { "accs", & HW_ENT (HW_H_ACCUMS), 12, 2,
369 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
370 /* end-sanitize-m32rx */
371 /* start-sanitize-m32rx */
372 /* acc: accumulator reg (d) */
373 { "acc", & HW_ENT (HW_H_ACCUMS), 8, 1,
374 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
375 /* end-sanitize-m32rx */
376 /* hi16: high 16 bit immediate, sign optional */
377 { "hi16", & HW_ENT (HW_H_HI16), 16, 16,
378 { 0, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
379 /* slo16: 16 bit signed immediate, for low() */
380 { "slo16", & HW_ENT (HW_H_SLO16), 16, 16,
381 { 0, 0, { 0 } } },
382 /* ulo16: 16 bit unsigned immediate, for low() */
383 { "ulo16", & HW_ENT (HW_H_ULO16), 16, 16,
384 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
385 /* uimm24: 24 bit address */
386 { "uimm24", & HW_ENT (HW_H_ADDR), 8, 24,
387 { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
388 /* disp8: 8 bit displacement */
389 { "disp8", & HW_ENT (HW_H_IADDR), 8, 8,
390 { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
391 /* disp16: 16 bit displacement */
392 { "disp16", & HW_ENT (HW_H_IADDR), 16, 16,
393 { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
394 /* disp24: 24 bit displacement */
395 { "disp24", & HW_ENT (HW_H_IADDR), 8, 24,
396 { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
397 /* condbit: condition bit */
398 { "condbit", & HW_ENT (HW_H_COND), 0, 0,
399 { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
400 /* accum: accumulator */
401 { "accum", & HW_ENT (HW_H_ACCUM), 0, 0,
402 { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
403 };
404
405 /* Operand references. */
406
407 #define INPUT CGEN_OPERAND_INSTANCE_INPUT
408 #define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
409
410 static const CGEN_OPERAND_INSTANCE fmt_0_add_ops[] = {
411 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
412 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
413 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
414 { 0 }
415 };
416
417 static const CGEN_OPERAND_INSTANCE fmt_1_add3_ops[] = {
418 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
419 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
420 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
421 { 0 }
422 };
423
424 static const CGEN_OPERAND_INSTANCE fmt_2_and3_ops[] = {
425 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
426 { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0 },
427 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
428 { 0 }
429 };
430
431 static const CGEN_OPERAND_INSTANCE fmt_3_or3_ops[] = {
432 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
433 { INPUT, & HW_ENT (HW_H_ULO16), CGEN_MODE_UHI, & OP_ENT (ULO16), 0 },
434 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
435 { 0 }
436 };
437
438 static const CGEN_OPERAND_INSTANCE fmt_4_addi_ops[] = {
439 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
440 { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
441 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
442 { 0 }
443 };
444
445 static const CGEN_OPERAND_INSTANCE fmt_5_addv_ops[] = {
446 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
447 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
448 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
449 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
450 { 0 }
451 };
452
453 static const CGEN_OPERAND_INSTANCE fmt_6_addv3_ops[] = {
454 { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
455 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
456 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
457 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
458 { 0 }
459 };
460
461 static const CGEN_OPERAND_INSTANCE fmt_7_addx_ops[] = {
462 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
463 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
464 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
465 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
466 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
467 { 0 }
468 };
469
470 static const CGEN_OPERAND_INSTANCE fmt_8_bc8_ops[] = {
471 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
472 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
473 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
474 { 0 }
475 };
476
477 static const CGEN_OPERAND_INSTANCE fmt_10_bc24_ops[] = {
478 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
479 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
480 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
481 { 0 }
482 };
483
484 static const CGEN_OPERAND_INSTANCE fmt_12_beq_ops[] = {
485 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP16), 0 },
486 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
487 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
488 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
489 { 0 }
490 };
491
492 static const CGEN_OPERAND_INSTANCE fmt_13_beqz_ops[] = {
493 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP16), 0 },
494 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
495 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
496 { 0 }
497 };
498
499 static const CGEN_OPERAND_INSTANCE fmt_14_bl8_ops[] = {
500 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
501 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
502 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
503 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
504 { 0 }
505 };
506
507 static const CGEN_OPERAND_INSTANCE fmt_15_bl24_ops[] = {
508 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
509 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
510 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
511 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
512 { 0 }
513 };
514
515 static const CGEN_OPERAND_INSTANCE fmt_16_bcl8_ops[] = {
516 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
517 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
518 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
519 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
520 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
521 { 0 }
522 };
523
524 static const CGEN_OPERAND_INSTANCE fmt_17_bcl24_ops[] = {
525 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
526 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
527 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
528 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
529 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
530 { 0 }
531 };
532
533 static const CGEN_OPERAND_INSTANCE fmt_18_bra8_ops[] = {
534 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
535 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
536 { 0 }
537 };
538
539 static const CGEN_OPERAND_INSTANCE fmt_19_bra24_ops[] = {
540 { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
541 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
542 { 0 }
543 };
544
545 static const CGEN_OPERAND_INSTANCE fmt_20_cmp_ops[] = {
546 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
547 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
548 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
549 { 0 }
550 };
551
552 static const CGEN_OPERAND_INSTANCE fmt_21_cmpi_ops[] = {
553 { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
554 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
555 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
556 { 0 }
557 };
558
559 static const CGEN_OPERAND_INSTANCE fmt_22_cmpui_ops[] = {
560 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
561 { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0 },
562 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
563 { 0 }
564 };
565
566 static const CGEN_OPERAND_INSTANCE fmt_23_cmpz_ops[] = {
567 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
568 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
569 { 0 }
570 };
571
572 static const CGEN_OPERAND_INSTANCE fmt_24_div_ops[] = {
573 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
574 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
575 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
576 { 0 }
577 };
578
579 static const CGEN_OPERAND_INSTANCE fmt_25_jc_ops[] = {
580 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
581 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
582 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
583 { 0 }
584 };
585
586 static const CGEN_OPERAND_INSTANCE fmt_26_jl_ops[] = {
587 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
588 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
589 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
590 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
591 { 0 }
592 };
593
594 static const CGEN_OPERAND_INSTANCE fmt_27_jmp_ops[] = {
595 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
596 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
597 { 0 }
598 };
599
600 static const CGEN_OPERAND_INSTANCE fmt_28_ld_ops[] = {
601 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
602 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
603 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
604 { 0 }
605 };
606
607 static const CGEN_OPERAND_INSTANCE fmt_30_ld_d_ops[] = {
608 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
609 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
610 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
611 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
612 { 0 }
613 };
614
615 static const CGEN_OPERAND_INSTANCE fmt_32_ldb_ops[] = {
616 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
617 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
618 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
619 { 0 }
620 };
621
622 static const CGEN_OPERAND_INSTANCE fmt_33_ldb_d_ops[] = {
623 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
624 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
625 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
626 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
627 { 0 }
628 };
629
630 static const CGEN_OPERAND_INSTANCE fmt_34_ldh_ops[] = {
631 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
632 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
633 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
634 { 0 }
635 };
636
637 static const CGEN_OPERAND_INSTANCE fmt_35_ldh_d_ops[] = {
638 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
639 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
640 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
641 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
642 { 0 }
643 };
644
645 static const CGEN_OPERAND_INSTANCE fmt_36_ld_plus_ops[] = {
646 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
647 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
648 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
649 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
650 { 0 }
651 };
652
653 static const CGEN_OPERAND_INSTANCE fmt_37_ld24_ops[] = {
654 { INPUT, & HW_ENT (HW_H_ADDR), CGEN_MODE_VM, & OP_ENT (UIMM24), 0 },
655 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
656 { 0 }
657 };
658
659 static const CGEN_OPERAND_INSTANCE fmt_38_ldi8_ops[] = {
660 { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
661 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
662 { 0 }
663 };
664
665 static const CGEN_OPERAND_INSTANCE fmt_39_ldi16_ops[] = {
666 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
667 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
668 { 0 }
669 };
670
671 static const CGEN_OPERAND_INSTANCE fmt_40_lock_ops[] = {
672 { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
673 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
674 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
675 { OUTPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
676 { 0 }
677 };
678
679 static const CGEN_OPERAND_INSTANCE fmt_41_machi_ops[] = {
680 { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
681 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
682 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
683 { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
684 { 0 }
685 };
686
687 static const CGEN_OPERAND_INSTANCE fmt_42_machi_a_ops[] = {
688 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
689 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
690 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
691 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
692 { 0 }
693 };
694
695 static const CGEN_OPERAND_INSTANCE fmt_43_mulhi_ops[] = {
696 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
697 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
698 { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
699 { 0 }
700 };
701
702 static const CGEN_OPERAND_INSTANCE fmt_44_mulhi_a_ops[] = {
703 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
704 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
705 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
706 { 0 }
707 };
708
709 static const CGEN_OPERAND_INSTANCE fmt_45_mv_ops[] = {
710 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
711 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
712 { 0 }
713 };
714
715 static const CGEN_OPERAND_INSTANCE fmt_46_mvfachi_ops[] = {
716 { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
717 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
718 { 0 }
719 };
720
721 static const CGEN_OPERAND_INSTANCE fmt_47_mvfachi_a_ops[] = {
722 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
723 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
724 { 0 }
725 };
726
727 static const CGEN_OPERAND_INSTANCE fmt_48_mvfc_ops[] = {
728 { INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (SCR), 0 },
729 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
730 { 0 }
731 };
732
733 static const CGEN_OPERAND_INSTANCE fmt_49_mvtachi_ops[] = {
734 { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
735 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
736 { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
737 { 0 }
738 };
739
740 static const CGEN_OPERAND_INSTANCE fmt_50_mvtachi_a_ops[] = {
741 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
742 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
743 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
744 { 0 }
745 };
746
747 static const CGEN_OPERAND_INSTANCE fmt_51_mvtc_ops[] = {
748 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
749 { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (DCR), 0 },
750 { 0 }
751 };
752
753 static const CGEN_OPERAND_INSTANCE fmt_53_rac_ops[] = {
754 { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
755 { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
756 { 0 }
757 };
758
759 static const CGEN_OPERAND_INSTANCE fmt_56_rac_dsi_ops[] = {
760 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
761 { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (IMM1), 0 },
762 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0 },
763 { 0 }
764 };
765
766 static const CGEN_OPERAND_INSTANCE fmt_57_rte_ops[] = {
767 { INPUT, & HW_ENT (HW_H_BCOND), CGEN_MODE_VM, 0, 0 },
768 { INPUT, & HW_ENT (HW_H_BIE), CGEN_MODE_VM, 0, 0 },
769 { INPUT, & HW_ENT (HW_H_BPC), CGEN_MODE_VM, 0, 0 },
770 { INPUT, & HW_ENT (HW_H_BSM), CGEN_MODE_VM, 0, 0 },
771 { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
772 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
773 { OUTPUT, & HW_ENT (HW_H_IE), CGEN_MODE_VM, 0, 0 },
774 { OUTPUT, & HW_ENT (HW_H_SM), CGEN_MODE_VM, 0, 0 },
775 { 0 }
776 };
777
778 static const CGEN_OPERAND_INSTANCE fmt_58_seth_ops[] = {
779 { INPUT, & HW_ENT (HW_H_HI16), CGEN_MODE_UHI, & OP_ENT (HI16), 0 },
780 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
781 { 0 }
782 };
783
784 static const CGEN_OPERAND_INSTANCE fmt_59_sll3_ops[] = {
785 { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
786 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
787 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
788 { 0 }
789 };
790
791 static const CGEN_OPERAND_INSTANCE fmt_60_slli_ops[] = {
792 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
793 { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM5), 0 },
794 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
795 { 0 }
796 };
797
798 static const CGEN_OPERAND_INSTANCE fmt_61_st_ops[] = {
799 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
800 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
801 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
802 { 0 }
803 };
804
805 static const CGEN_OPERAND_INSTANCE fmt_63_st_d_ops[] = {
806 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
807 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
808 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
809 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
810 { 0 }
811 };
812
813 static const CGEN_OPERAND_INSTANCE fmt_65_stb_ops[] = {
814 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
815 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
816 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
817 { 0 }
818 };
819
820 static const CGEN_OPERAND_INSTANCE fmt_66_stb_d_ops[] = {
821 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
822 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
823 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
824 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
825 { 0 }
826 };
827
828 static const CGEN_OPERAND_INSTANCE fmt_67_sth_ops[] = {
829 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
830 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
831 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
832 { 0 }
833 };
834
835 static const CGEN_OPERAND_INSTANCE fmt_68_sth_d_ops[] = {
836 { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
837 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
838 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
839 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
840 { 0 }
841 };
842
843 static const CGEN_OPERAND_INSTANCE fmt_69_st_plus_ops[] = {
844 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
845 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
846 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
847 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
848 { 0 }
849 };
850
851 static const CGEN_OPERAND_INSTANCE fmt_70_trap_ops[] = {
852 { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
853 { INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_SI, 0, 0 },
854 { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM4), 0 },
855 { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
856 { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_SI, 0, 0 },
857 { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_SI, 0, 6 },
858 { 0 }
859 };
860
861 static const CGEN_OPERAND_INSTANCE fmt_72_unlock_ops[] = {
862 { INPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
863 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
864 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
865 { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
866 { OUTPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
867 { 0 }
868 };
869
870 static const CGEN_OPERAND_INSTANCE fmt_75_satb_ops[] = {
871 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
872 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
873 { 0 }
874 };
875
876 static const CGEN_OPERAND_INSTANCE fmt_76_sat_ops[] = {
877 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
878 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
879 { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
880 { 0 }
881 };
882
883 static const CGEN_OPERAND_INSTANCE fmt_77_sadd_ops[] = {
884 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
885 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
886 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
887 { 0 }
888 };
889
890 static const CGEN_OPERAND_INSTANCE fmt_78_macwu1_ops[] = {
891 { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
892 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
893 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
894 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
895 { 0 }
896 };
897
898 static const CGEN_OPERAND_INSTANCE fmt_79_mulwu1_ops[] = {
899 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
900 { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
901 { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
902 { 0 }
903 };
904
905 static const CGEN_OPERAND_INSTANCE fmt_80_sc_ops[] = {
906 { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
907 { 0 }
908 };
909
910 #undef INPUT
911 #undef OUTPUT
912
913 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
914 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
915 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
916
917 /* The instruction table. */
918
919 const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
920 {
921 /* null first entry, end of all hash chains */
922 { { 0 }, 0 },
923 /* add $dr,$sr */
924 {
925 { 1, 1, 1, 1 },
926 "add", "add",
927 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
928 { 16, 16, 0xf0f0 }, 0xa0,
929 & fmt_0_add_ops[0],
930 { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
931 },
932 /* add3 $dr,$sr,#$slo16 */
933 {
934 { 1, 1, 1, 1 },
935 "add3", "add3",
936 { MNEM, ' ', OP (DR), ',', OP (SR), ',', '#', OP (SLO16), 0 },
937 { 32, 32, 0xf0f00000 }, 0x80a00000,
938 & fmt_1_add3_ops[0],
939 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
940 },
941 /* add3 $dr,$sr,$slo16 */
942 {
943 { 1, 1, 1, 1 },
944 "add3.a", "add3",
945 { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SLO16), 0 },
946 { 32, 32, 0xf0f00000 }, 0x80a00000,
947 & fmt_1_add3_ops[0],
948 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
949 },
950 /* and $dr,$sr */
951 {
952 { 1, 1, 1, 1 },
953 "and", "and",
954 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
955 { 16, 16, 0xf0f0 }, 0xc0,
956 & fmt_0_add_ops[0],
957 { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
958 },
959 /* and3 $dr,$sr,#$uimm16 */
960 {
961 { 1, 1, 1, 1 },
962 "and3", "and3",
963 { MNEM, ' ', OP (DR), ',', OP (SR), ',', '#', OP (UIMM16), 0 },
964 { 32, 32, 0xf0f00000 }, 0x80c00000,
965 & fmt_2_and3_ops[0],
966 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
967 },
968 /* and3 $dr,$sr,$uimm16 */
969 {
970 { 1, 1, 1, 1 },
971 "and3.a", "and3",
972 { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 },
973 { 32, 32, 0xf0f00000 }, 0x80c00000,
974 & fmt_2_and3_ops[0],
975 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
976 },
977 /* or $dr,$sr */
978 {
979 { 1, 1, 1, 1 },
980 "or", "or",
981 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
982 { 16, 16, 0xf0f0 }, 0xe0,
983 & fmt_0_add_ops[0],
984 { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
985 },
986 /* or3 $dr,$sr,#$ulo16 */
987 {
988 { 1, 1, 1, 1 },
989 "or3", "or3",
990 { MNEM, ' ', OP (DR), ',', OP (SR), ',', '#', OP (ULO16), 0 },
991 { 32, 32, 0xf0f00000 }, 0x80e00000,
992 & fmt_3_or3_ops[0],
993 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
994 },
995 /* or3 $dr,$sr,$ulo16 */
996 {
997 { 1, 1, 1, 1 },
998 "or3.a", "or3",
999 { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (ULO16), 0 },
1000 { 32, 32, 0xf0f00000 }, 0x80e00000,
1001 & fmt_3_or3_ops[0],
1002 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1003 },
1004 /* xor $dr,$sr */
1005 {
1006 { 1, 1, 1, 1 },
1007 "xor", "xor",
1008 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1009 { 16, 16, 0xf0f0 }, 0xd0,
1010 & fmt_0_add_ops[0],
1011 { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
1012 },
1013 /* xor3 $dr,$sr,#$uimm16 */
1014 {
1015 { 1, 1, 1, 1 },
1016 "xor3", "xor3",
1017 { MNEM, ' ', OP (DR), ',', OP (SR), ',', '#', OP (UIMM16), 0 },
1018 { 32, 32, 0xf0f00000 }, 0x80d00000,
1019 & fmt_2_and3_ops[0],
1020 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1021 },
1022 /* xor3 $dr,$sr,$uimm16 */
1023 {
1024 { 1, 1, 1, 1 },
1025 "xor3.a", "xor3",
1026 { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 },
1027 { 32, 32, 0xf0f00000 }, 0x80d00000,
1028 & fmt_2_and3_ops[0],
1029 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1030 },
1031 /* addi $dr,#$simm8 */
1032 {
1033 { 1, 1, 1, 1 },
1034 "addi", "addi",
1035 { MNEM, ' ', OP (DR), ',', '#', OP (SIMM8), 0 },
1036 { 16, 16, 0xf000 }, 0x4000,
1037 & fmt_4_addi_ops[0],
1038 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1039 },
1040 /* addi $dr,$simm8 */
1041 {
1042 { 1, 1, 1, 1 },
1043 "addi.a", "addi",
1044 { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 },
1045 { 16, 16, 0xf000 }, 0x4000,
1046 & fmt_4_addi_ops[0],
1047 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
1048 },
1049 /* addv $dr,$sr */
1050 {
1051 { 1, 1, 1, 1 },
1052 "addv", "addv",
1053 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1054 { 16, 16, 0xf0f0 }, 0x80,
1055 & fmt_5_addv_ops[0],
1056 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1057 },
1058 /* addv3 $dr,$sr,#$simm16 */
1059 {
1060 { 1, 1, 1, 1 },
1061 "addv3", "addv3",
1062 { MNEM, ' ', OP (DR), ',', OP (SR), ',', '#', OP (SIMM16), 0 },
1063 { 32, 32, 0xf0f00000 }, 0x80800000,
1064 & fmt_6_addv3_ops[0],
1065 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1066 },
1067 /* addv3 $dr,$sr,$simm16 */
1068 {
1069 { 1, 1, 1, 1 },
1070 "addv3.a", "addv3",
1071 { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
1072 { 32, 32, 0xf0f00000 }, 0x80800000,
1073 & fmt_6_addv3_ops[0],
1074 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1075 },
1076 /* addx $dr,$sr */
1077 {
1078 { 1, 1, 1, 1 },
1079 "addx", "addx",
1080 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1081 { 16, 16, 0xf0f0 }, 0x90,
1082 & fmt_7_addx_ops[0],
1083 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1084 },
1085 /* bc $disp8 */
1086 {
1087 { 1, 1, 1, 1 },
1088 "bc8", "bc",
1089 { MNEM, ' ', OP (DISP8), 0 },
1090 { 16, 16, 0xff00 }, 0x7c00,
1091 & fmt_8_bc8_ops[0],
1092 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
1093 },
1094 /* bc.s $disp8 */
1095 {
1096 { 1, 1, 1, 1 },
1097 "bc8.s", "bc.s",
1098 { MNEM, ' ', OP (DISP8), 0 },
1099 { 16, 16, 0xff00 }, 0x7c00,
1100 0,
1101 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
1102 },
1103 /* bc $disp24 */
1104 {
1105 { 1, 1, 1, 1 },
1106 "bc24", "bc",
1107 { MNEM, ' ', OP (DISP24), 0 },
1108 { 32, 32, 0xff000000 }, 0xfc000000,
1109 & fmt_10_bc24_ops[0],
1110 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1111 },
1112 /* bc.l $disp24 */
1113 {
1114 { 1, 1, 1, 1 },
1115 "bc24.l", "bc.l",
1116 { MNEM, ' ', OP (DISP24), 0 },
1117 { 32, 32, 0xff000000 }, 0xfc000000,
1118 0,
1119 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1120 },
1121 /* beq $src1,$src2,$disp16 */
1122 {
1123 { 1, 1, 1, 1 },
1124 "beq", "beq",
1125 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 },
1126 { 32, 32, 0xf0f00000 }, 0xb0000000,
1127 & fmt_12_beq_ops[0],
1128 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1129 },
1130 /* beqz $src2,$disp16 */
1131 {
1132 { 1, 1, 1, 1 },
1133 "beqz", "beqz",
1134 { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1135 { 32, 32, 0xfff00000 }, 0xb0800000,
1136 & fmt_13_beqz_ops[0],
1137 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1138 },
1139 /* bgez $src2,$disp16 */
1140 {
1141 { 1, 1, 1, 1 },
1142 "bgez", "bgez",
1143 { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1144 { 32, 32, 0xfff00000 }, 0xb0b00000,
1145 & fmt_13_beqz_ops[0],
1146 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1147 },
1148 /* bgtz $src2,$disp16 */
1149 {
1150 { 1, 1, 1, 1 },
1151 "bgtz", "bgtz",
1152 { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1153 { 32, 32, 0xfff00000 }, 0xb0d00000,
1154 & fmt_13_beqz_ops[0],
1155 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1156 },
1157 /* blez $src2,$disp16 */
1158 {
1159 { 1, 1, 1, 1 },
1160 "blez", "blez",
1161 { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1162 { 32, 32, 0xfff00000 }, 0xb0c00000,
1163 & fmt_13_beqz_ops[0],
1164 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1165 },
1166 /* bltz $src2,$disp16 */
1167 {
1168 { 1, 1, 1, 1 },
1169 "bltz", "bltz",
1170 { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1171 { 32, 32, 0xfff00000 }, 0xb0a00000,
1172 & fmt_13_beqz_ops[0],
1173 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1174 },
1175 /* bnez $src2,$disp16 */
1176 {
1177 { 1, 1, 1, 1 },
1178 "bnez", "bnez",
1179 { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1180 { 32, 32, 0xfff00000 }, 0xb0900000,
1181 & fmt_13_beqz_ops[0],
1182 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1183 },
1184 /* bl $disp8 */
1185 {
1186 { 1, 1, 1, 1 },
1187 "bl8", "bl",
1188 { MNEM, ' ', OP (DISP8), 0 },
1189 { 16, 16, 0xff00 }, 0x7e00,
1190 & fmt_14_bl8_ops[0],
1191 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1192 },
1193 /* bl.s $disp8 */
1194 {
1195 { 1, 1, 1, 1 },
1196 "bl8.s", "bl.s",
1197 { MNEM, ' ', OP (DISP8), 0 },
1198 { 16, 16, 0xff00 }, 0x7e00,
1199 0,
1200 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1201 },
1202 /* bl $disp24 */
1203 {
1204 { 1, 1, 1, 1 },
1205 "bl24", "bl",
1206 { MNEM, ' ', OP (DISP24), 0 },
1207 { 32, 32, 0xff000000 }, 0xfe000000,
1208 & fmt_15_bl24_ops[0],
1209 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1210 },
1211 /* bl.l $disp24 */
1212 {
1213 { 1, 1, 1, 1 },
1214 "bl24.l", "bl.l",
1215 { MNEM, ' ', OP (DISP24), 0 },
1216 { 32, 32, 0xff000000 }, 0xfe000000,
1217 0,
1218 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1219 },
1220 /* start-sanitize-m32rx */
1221 /* bcl $disp8 */
1222 {
1223 { 1, 1, 1, 1 },
1224 "bcl8", "bcl",
1225 { MNEM, ' ', OP (DISP8), 0 },
1226 { 16, 16, 0xff00 }, 0x7800,
1227 & fmt_16_bcl8_ops[0],
1228 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1229 },
1230 /* end-sanitize-m32rx */
1231 /* start-sanitize-m32rx */
1232 /* bcl.s $disp8 */
1233 {
1234 { 1, 1, 1, 1 },
1235 "bcl8.s", "bcl.s",
1236 { MNEM, ' ', OP (DISP8), 0 },
1237 { 16, 16, 0xff00 }, 0x7800,
1238 0,
1239 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1240 },
1241 /* end-sanitize-m32rx */
1242 /* start-sanitize-m32rx */
1243 /* bcl $disp24 */
1244 {
1245 { 1, 1, 1, 1 },
1246 "bcl24", "bcl",
1247 { MNEM, ' ', OP (DISP24), 0 },
1248 { 32, 32, 0xff000000 }, 0xf8000000,
1249 & fmt_17_bcl24_ops[0],
1250 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1251 },
1252 /* end-sanitize-m32rx */
1253 /* start-sanitize-m32rx */
1254 /* bcl.l $disp24 */
1255 {
1256 { 1, 1, 1, 1 },
1257 "bcl24.l", "bcl.l",
1258 { MNEM, ' ', OP (DISP24), 0 },
1259 { 32, 32, 0xff000000 }, 0xf8000000,
1260 0,
1261 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1262 },
1263 /* end-sanitize-m32rx */
1264 /* bnc $disp8 */
1265 {
1266 { 1, 1, 1, 1 },
1267 "bnc8", "bnc",
1268 { MNEM, ' ', OP (DISP8), 0 },
1269 { 16, 16, 0xff00 }, 0x7d00,
1270 & fmt_8_bc8_ops[0],
1271 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
1272 },
1273 /* bnc.s $disp8 */
1274 {
1275 { 1, 1, 1, 1 },
1276 "bnc8.s", "bnc.s",
1277 { MNEM, ' ', OP (DISP8), 0 },
1278 { 16, 16, 0xff00 }, 0x7d00,
1279 0,
1280 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
1281 },
1282 /* bnc $disp24 */
1283 {
1284 { 1, 1, 1, 1 },
1285 "bnc24", "bnc",
1286 { MNEM, ' ', OP (DISP24), 0 },
1287 { 32, 32, 0xff000000 }, 0xfd000000,
1288 & fmt_10_bc24_ops[0],
1289 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1290 },
1291 /* bnc.l $disp24 */
1292 {
1293 { 1, 1, 1, 1 },
1294 "bnc24.l", "bnc.l",
1295 { MNEM, ' ', OP (DISP24), 0 },
1296 { 32, 32, 0xff000000 }, 0xfd000000,
1297 0,
1298 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1299 },
1300 /* bne $src1,$src2,$disp16 */
1301 {
1302 { 1, 1, 1, 1 },
1303 "bne", "bne",
1304 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 },
1305 { 32, 32, 0xf0f00000 }, 0xb0100000,
1306 & fmt_12_beq_ops[0],
1307 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1308 },
1309 /* bra $disp8 */
1310 {
1311 { 1, 1, 1, 1 },
1312 "bra8", "bra",
1313 { MNEM, ' ', OP (DISP8), 0 },
1314 { 16, 16, 0xff00 }, 0x7f00,
1315 & fmt_18_bra8_ops[0],
1316 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1317 },
1318 /* bra.s $disp8 */
1319 {
1320 { 1, 1, 1, 1 },
1321 "bra8.s", "bra.s",
1322 { MNEM, ' ', OP (DISP8), 0 },
1323 { 16, 16, 0xff00 }, 0x7f00,
1324 0,
1325 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1326 },
1327 /* bra $disp24 */
1328 {
1329 { 1, 1, 1, 1 },
1330 "bra24", "bra",
1331 { MNEM, ' ', OP (DISP24), 0 },
1332 { 32, 32, 0xff000000 }, 0xff000000,
1333 & fmt_19_bra24_ops[0],
1334 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1335 },
1336 /* bra.l $disp24 */
1337 {
1338 { 1, 1, 1, 1 },
1339 "bra24.l", "bra.l",
1340 { MNEM, ' ', OP (DISP24), 0 },
1341 { 32, 32, 0xff000000 }, 0xff000000,
1342 0,
1343 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1344 },
1345 /* start-sanitize-m32rx */
1346 /* bncl $disp8 */
1347 {
1348 { 1, 1, 1, 1 },
1349 "bncl8", "bncl",
1350 { MNEM, ' ', OP (DISP8), 0 },
1351 { 16, 16, 0xff00 }, 0x7900,
1352 & fmt_16_bcl8_ops[0],
1353 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1354 },
1355 /* end-sanitize-m32rx */
1356 /* start-sanitize-m32rx */
1357 /* bncl.s $disp8 */
1358 {
1359 { 1, 1, 1, 1 },
1360 "bncl8.s", "bncl.s",
1361 { MNEM, ' ', OP (DISP8), 0 },
1362 { 16, 16, 0xff00 }, 0x7900,
1363 0,
1364 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1365 },
1366 /* end-sanitize-m32rx */
1367 /* start-sanitize-m32rx */
1368 /* bncl $disp24 */
1369 {
1370 { 1, 1, 1, 1 },
1371 "bncl24", "bncl",
1372 { MNEM, ' ', OP (DISP24), 0 },
1373 { 32, 32, 0xff000000 }, 0xf9000000,
1374 & fmt_17_bcl24_ops[0],
1375 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1376 },
1377 /* end-sanitize-m32rx */
1378 /* start-sanitize-m32rx */
1379 /* bncl.l $disp24 */
1380 {
1381 { 1, 1, 1, 1 },
1382 "bncl24.l", "bncl.l",
1383 { MNEM, ' ', OP (DISP24), 0 },
1384 { 32, 32, 0xff000000 }, 0xf9000000,
1385 0,
1386 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1387 },
1388 /* end-sanitize-m32rx */
1389 /* cmp $src1,$src2 */
1390 {
1391 { 1, 1, 1, 1 },
1392 "cmp", "cmp",
1393 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1394 { 16, 16, 0xf0f0 }, 0x40,
1395 & fmt_20_cmp_ops[0],
1396 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1397 },
1398 /* cmpi $src2,#$simm16 */
1399 {
1400 { 1, 1, 1, 1 },
1401 "cmpi", "cmpi",
1402 { MNEM, ' ', OP (SRC2), ',', '#', OP (SIMM16), 0 },
1403 { 32, 32, 0xfff00000 }, 0x80400000,
1404 & fmt_21_cmpi_ops[0],
1405 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1406 },
1407 /* cmpi $src2,$simm16 */
1408 {
1409 { 1, 1, 1, 1 },
1410 "cmpi.a", "cmpi",
1411 { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 },
1412 { 32, 32, 0xfff00000 }, 0x80400000,
1413 & fmt_21_cmpi_ops[0],
1414 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1415 },
1416 /* cmpu $src1,$src2 */
1417 {
1418 { 1, 1, 1, 1 },
1419 "cmpu", "cmpu",
1420 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1421 { 16, 16, 0xf0f0 }, 0x50,
1422 & fmt_20_cmp_ops[0],
1423 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1424 },
1425 /* cmpui $src2,#$uimm16 */
1426 {
1427 { 1, 1, 1, 1 },
1428 "cmpui", "cmpui",
1429 { MNEM, ' ', OP (SRC2), ',', '#', OP (UIMM16), 0 },
1430 { 32, 32, 0xfff00000 }, 0x80500000,
1431 & fmt_22_cmpui_ops[0],
1432 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1433 },
1434 /* cmpui $src2,$uimm16 */
1435 {
1436 { 1, 1, 1, 1 },
1437 "cmpui.a", "cmpui",
1438 { MNEM, ' ', OP (SRC2), ',', OP (UIMM16), 0 },
1439 { 32, 32, 0xfff00000 }, 0x80500000,
1440 & fmt_22_cmpui_ops[0],
1441 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1442 },
1443 /* start-sanitize-m32rx */
1444 /* cmpeq $src1,$src2 */
1445 {
1446 { 1, 1, 1, 1 },
1447 "cmpeq", "cmpeq",
1448 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1449 { 16, 16, 0xf0f0 }, 0x60,
1450 & fmt_20_cmp_ops[0],
1451 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
1452 },
1453 /* end-sanitize-m32rx */
1454 /* start-sanitize-m32rx */
1455 /* cmpz $src2 */
1456 {
1457 { 1, 1, 1, 1 },
1458 "cmpz", "cmpz",
1459 { MNEM, ' ', OP (SRC2), 0 },
1460 { 16, 16, 0xfff0 }, 0x70,
1461 & fmt_23_cmpz_ops[0],
1462 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
1463 },
1464 /* end-sanitize-m32rx */
1465 /* div $dr,$sr */
1466 {
1467 { 1, 1, 1, 1 },
1468 "div", "div",
1469 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1470 { 32, 32, 0xf0f0ffff }, 0x90000000,
1471 & fmt_24_div_ops[0],
1472 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1473 },
1474 /* divu $dr,$sr */
1475 {
1476 { 1, 1, 1, 1 },
1477 "divu", "divu",
1478 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1479 { 32, 32, 0xf0f0ffff }, 0x90100000,
1480 & fmt_24_div_ops[0],
1481 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1482 },
1483 /* rem $dr,$sr */
1484 {
1485 { 1, 1, 1, 1 },
1486 "rem", "rem",
1487 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1488 { 32, 32, 0xf0f0ffff }, 0x90200000,
1489 & fmt_24_div_ops[0],
1490 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1491 },
1492 /* remu $dr,$sr */
1493 {
1494 { 1, 1, 1, 1 },
1495 "remu", "remu",
1496 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1497 { 32, 32, 0xf0f0ffff }, 0x90300000,
1498 & fmt_24_div_ops[0],
1499 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1500 },
1501 /* start-sanitize-m32rx */
1502 /* divh $dr,$sr */
1503 {
1504 { 1, 1, 1, 1 },
1505 "divh", "divh",
1506 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1507 { 32, 32, 0xf0f0ffff }, 0x90000010,
1508 & fmt_24_div_ops[0],
1509 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
1510 },
1511 /* end-sanitize-m32rx */
1512 /* start-sanitize-m32rx */
1513 /* jc $sr */
1514 {
1515 { 1, 1, 1, 1 },
1516 "jc", "jc",
1517 { MNEM, ' ', OP (SR), 0 },
1518 { 16, 16, 0xfff0 }, 0x1cc0,
1519 & fmt_25_jc_ops[0],
1520 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1521 },
1522 /* end-sanitize-m32rx */
1523 /* start-sanitize-m32rx */
1524 /* jnc $sr */
1525 {
1526 { 1, 1, 1, 1 },
1527 "jnc", "jnc",
1528 { MNEM, ' ', OP (SR), 0 },
1529 { 16, 16, 0xfff0 }, 0x1dc0,
1530 & fmt_25_jc_ops[0],
1531 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1532 },
1533 /* end-sanitize-m32rx */
1534 /* jl $sr */
1535 {
1536 { 1, 1, 1, 1 },
1537 "jl", "jl",
1538 { MNEM, ' ', OP (SR), 0 },
1539 { 16, 16, 0xfff0 }, 0x1ec0,
1540 & fmt_26_jl_ops[0],
1541 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1542 },
1543 /* jmp $sr */
1544 {
1545 { 1, 1, 1, 1 },
1546 "jmp", "jmp",
1547 { MNEM, ' ', OP (SR), 0 },
1548 { 16, 16, 0xfff0 }, 0x1fc0,
1549 & fmt_27_jmp_ops[0],
1550 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1551 },
1552 /* ld $dr,@$sr */
1553 {
1554 { 1, 1, 1, 1 },
1555 "ld", "ld",
1556 { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1557 { 16, 16, 0xf0f0 }, 0x20c0,
1558 & fmt_28_ld_ops[0],
1559 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1560 },
1561 /* ld $dr,@($sr) */
1562 {
1563 { 1, 1, 1, 1 },
1564 "ld-2", "ld",
1565 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
1566 { 16, 16, 0xf0f0 }, 0x20c0,
1567 0,
1568 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1569 },
1570 /* ld $dr,@($slo16,$sr) */
1571 {
1572 { 1, 1, 1, 1 },
1573 "ld-d", "ld",
1574 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1575 { 32, 32, 0xf0f00000 }, 0xa0c00000,
1576 & fmt_30_ld_d_ops[0],
1577 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1578 },
1579 /* ld $dr,@($sr,$slo16) */
1580 {
1581 { 1, 1, 1, 1 },
1582 "ld-d2", "ld",
1583 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
1584 { 32, 32, 0xf0f00000 }, 0xa0c00000,
1585 0,
1586 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1587 },
1588 /* ldb $dr,@$sr */
1589 {
1590 { 1, 1, 1, 1 },
1591 "ldb", "ldb",
1592 { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1593 { 16, 16, 0xf0f0 }, 0x2080,
1594 & fmt_32_ldb_ops[0],
1595 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1596 },
1597 /* ldb $dr,@($sr) */
1598 {
1599 { 1, 1, 1, 1 },
1600 "ldb-2", "ldb",
1601 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
1602 { 16, 16, 0xf0f0 }, 0x2080,
1603 0,
1604 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1605 },
1606 /* ldb $dr,@($slo16,$sr) */
1607 {
1608 { 1, 1, 1, 1 },
1609 "ldb-d", "ldb",
1610 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1611 { 32, 32, 0xf0f00000 }, 0xa0800000,
1612 & fmt_33_ldb_d_ops[0],
1613 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1614 },
1615 /* ldb $dr,@($sr,$slo16) */
1616 {
1617 { 1, 1, 1, 1 },
1618 "ldb-d2", "ldb",
1619 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
1620 { 32, 32, 0xf0f00000 }, 0xa0800000,
1621 0,
1622 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1623 },
1624 /* ldh $dr,@$sr */
1625 {
1626 { 1, 1, 1, 1 },
1627 "ldh", "ldh",
1628 { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1629 { 16, 16, 0xf0f0 }, 0x20a0,
1630 & fmt_34_ldh_ops[0],
1631 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1632 },
1633 /* ldh $dr,@($sr) */
1634 {
1635 { 1, 1, 1, 1 },
1636 "ldh-2", "ldh",
1637 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
1638 { 16, 16, 0xf0f0 }, 0x20a0,
1639 0,
1640 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1641 },
1642 /* ldh $dr,@($slo16,$sr) */
1643 {
1644 { 1, 1, 1, 1 },
1645 "ldh-d", "ldh",
1646 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1647 { 32, 32, 0xf0f00000 }, 0xa0a00000,
1648 & fmt_35_ldh_d_ops[0],
1649 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1650 },
1651 /* ldh $dr,@($sr,$slo16) */
1652 {
1653 { 1, 1, 1, 1 },
1654 "ldh-d2", "ldh",
1655 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
1656 { 32, 32, 0xf0f00000 }, 0xa0a00000,
1657 0,
1658 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1659 },
1660 /* ldub $dr,@$sr */
1661 {
1662 { 1, 1, 1, 1 },
1663 "ldub", "ldub",
1664 { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1665 { 16, 16, 0xf0f0 }, 0x2090,
1666 & fmt_32_ldb_ops[0],
1667 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1668 },
1669 /* ldub $dr,@($sr) */
1670 {
1671 { 1, 1, 1, 1 },
1672 "ldub-2", "ldub",
1673 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
1674 { 16, 16, 0xf0f0 }, 0x2090,
1675 0,
1676 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1677 },
1678 /* ldub $dr,@($slo16,$sr) */
1679 {
1680 { 1, 1, 1, 1 },
1681 "ldub-d", "ldub",
1682 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1683 { 32, 32, 0xf0f00000 }, 0xa0900000,
1684 & fmt_33_ldb_d_ops[0],
1685 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1686 },
1687 /* ldub $dr,@($sr,$slo16) */
1688 {
1689 { 1, 1, 1, 1 },
1690 "ldub-d2", "ldub",
1691 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
1692 { 32, 32, 0xf0f00000 }, 0xa0900000,
1693 0,
1694 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1695 },
1696 /* lduh $dr,@$sr */
1697 {
1698 { 1, 1, 1, 1 },
1699 "lduh", "lduh",
1700 { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1701 { 16, 16, 0xf0f0 }, 0x20b0,
1702 & fmt_34_ldh_ops[0],
1703 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1704 },
1705 /* lduh $dr,@($sr) */
1706 {
1707 { 1, 1, 1, 1 },
1708 "lduh-2", "lduh",
1709 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
1710 { 16, 16, 0xf0f0 }, 0x20b0,
1711 0,
1712 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1713 },
1714 /* lduh $dr,@($slo16,$sr) */
1715 {
1716 { 1, 1, 1, 1 },
1717 "lduh-d", "lduh",
1718 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1719 { 32, 32, 0xf0f00000 }, 0xa0b00000,
1720 & fmt_35_ldh_d_ops[0],
1721 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1722 },
1723 /* lduh $dr,@($sr,$slo16) */
1724 {
1725 { 1, 1, 1, 1 },
1726 "lduh-d2", "lduh",
1727 { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
1728 { 32, 32, 0xf0f00000 }, 0xa0b00000,
1729 0,
1730 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1731 },
1732 /* ld $dr,@$sr+ */
1733 {
1734 { 1, 1, 1, 1 },
1735 "ld-plus", "ld",
1736 { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 },
1737 { 16, 16, 0xf0f0 }, 0x20e0,
1738 & fmt_36_ld_plus_ops[0],
1739 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1740 },
1741 /* ld24 $dr,#$uimm24 */
1742 {
1743 { 1, 1, 1, 1 },
1744 "ld24", "ld24",
1745 { MNEM, ' ', OP (DR), ',', '#', OP (UIMM24), 0 },
1746 { 32, 32, 0xf0000000 }, 0xe0000000,
1747 & fmt_37_ld24_ops[0],
1748 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1749 },
1750 /* ld24 $dr,$uimm24 */
1751 {
1752 { 1, 1, 1, 1 },
1753 "ld24.a", "ld24",
1754 { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 },
1755 { 32, 32, 0xf0000000 }, 0xe0000000,
1756 & fmt_37_ld24_ops[0],
1757 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1758 },
1759 /* ldi $dr,#$simm8 */
1760 {
1761 { 1, 1, 1, 1 },
1762 "ldi8", "ldi",
1763 { MNEM, ' ', OP (DR), ',', '#', OP (SIMM8), 0 },
1764 { 16, 16, 0xf000 }, 0x6000,
1765 & fmt_38_ldi8_ops[0],
1766 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1767 },
1768 /* ldi $dr,$simm8 */
1769 {
1770 { 1, 1, 1, 1 },
1771 "ldi8.a", "ldi",
1772 { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 },
1773 { 16, 16, 0xf000 }, 0x6000,
1774 & fmt_38_ldi8_ops[0],
1775 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
1776 },
1777 /* ldi8 $dr,#$simm8 */
1778 {
1779 { 1, 1, 1, 1 },
1780 "ldi8a", "ldi8",
1781 { MNEM, ' ', OP (DR), ',', '#', OP (SIMM8), 0 },
1782 { 16, 16, 0xf000 }, 0x6000,
1783 & fmt_38_ldi8_ops[0],
1784 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
1785 },
1786 /* ldi8 $dr,$simm8 */
1787 {
1788 { 1, 1, 1, 1 },
1789 "ldi8a.a", "ldi8",
1790 { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 },
1791 { 16, 16, 0xf000 }, 0x6000,
1792 & fmt_38_ldi8_ops[0],
1793 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
1794 },
1795 /* ldi $dr,$slo16 */
1796 {
1797 { 1, 1, 1, 1 },
1798 "ldi16", "ldi",
1799 { MNEM, ' ', OP (DR), ',', OP (SLO16), 0 },
1800 { 32, 32, 0xf0ff0000 }, 0x90f00000,
1801 & fmt_39_ldi16_ops[0],
1802 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1803 },
1804 /* ldi16 $dr,$slo16 */
1805 {
1806 { 1, 1, 1, 1 },
1807 "ldi16a", "ldi16",
1808 { MNEM, ' ', OP (DR), ',', OP (SLO16), 0 },
1809 { 32, 32, 0xf0ff0000 }, 0x90f00000,
1810 & fmt_39_ldi16_ops[0],
1811 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1812 },
1813 /* lock $dr,@$sr */
1814 {
1815 { 1, 1, 1, 1 },
1816 "lock", "lock",
1817 { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1818 { 16, 16, 0xf0f0 }, 0x20d0,
1819 & fmt_40_lock_ops[0],
1820 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1821 },
1822 /* machi $src1,$src2 */
1823 {
1824 { 1, 1, 1, 1 },
1825 "machi", "machi",
1826 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1827 { 16, 16, 0xf0f0 }, 0x3040,
1828 & fmt_41_machi_ops[0],
1829 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1830 },
1831 /* start-sanitize-m32rx */
1832 /* machi $src1,$src2,$acc */
1833 {
1834 { 1, 1, 1, 1 },
1835 "machi-a", "machi",
1836 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
1837 { 16, 16, 0xf070 }, 0x3040,
1838 & fmt_42_machi_a_ops[0],
1839 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1840 },
1841 /* end-sanitize-m32rx */
1842 /* maclo $src1,$src2 */
1843 {
1844 { 1, 1, 1, 1 },
1845 "maclo", "maclo",
1846 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1847 { 16, 16, 0xf0f0 }, 0x3050,
1848 & fmt_41_machi_ops[0],
1849 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1850 },
1851 /* start-sanitize-m32rx */
1852 /* maclo $src1,$src2,$acc */
1853 {
1854 { 1, 1, 1, 1 },
1855 "maclo-a", "maclo",
1856 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
1857 { 16, 16, 0xf070 }, 0x3050,
1858 & fmt_42_machi_a_ops[0],
1859 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1860 },
1861 /* end-sanitize-m32rx */
1862 /* macwhi $src1,$src2 */
1863 {
1864 { 1, 1, 1, 1 },
1865 "macwhi", "macwhi",
1866 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1867 { 16, 16, 0xf0f0 }, 0x3060,
1868 & fmt_41_machi_ops[0],
1869 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1870 },
1871 /* macwlo $src1,$src2 */
1872 {
1873 { 1, 1, 1, 1 },
1874 "macwlo", "macwlo",
1875 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1876 { 16, 16, 0xf0f0 }, 0x3070,
1877 & fmt_41_machi_ops[0],
1878 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1879 },
1880 /* mul $dr,$sr */
1881 {
1882 { 1, 1, 1, 1 },
1883 "mul", "mul",
1884 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1885 { 16, 16, 0xf0f0 }, 0x1060,
1886 & fmt_0_add_ops[0],
1887 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1888 },
1889 /* mulhi $src1,$src2 */
1890 {
1891 { 1, 1, 1, 1 },
1892 "mulhi", "mulhi",
1893 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1894 { 16, 16, 0xf0f0 }, 0x3000,
1895 & fmt_43_mulhi_ops[0],
1896 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1897 },
1898 /* start-sanitize-m32rx */
1899 /* mulhi $src1,$src2,$acc */
1900 {
1901 { 1, 1, 1, 1 },
1902 "mulhi-a", "mulhi",
1903 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
1904 { 16, 16, 0xf070 }, 0x3000,
1905 & fmt_44_mulhi_a_ops[0],
1906 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1907 },
1908 /* end-sanitize-m32rx */
1909 /* mullo $src1,$src2 */
1910 {
1911 { 1, 1, 1, 1 },
1912 "mullo", "mullo",
1913 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1914 { 16, 16, 0xf0f0 }, 0x3010,
1915 & fmt_43_mulhi_ops[0],
1916 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1917 },
1918 /* start-sanitize-m32rx */
1919 /* mullo $src1,$src2,$acc */
1920 {
1921 { 1, 1, 1, 1 },
1922 "mullo-a", "mullo",
1923 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
1924 { 16, 16, 0xf070 }, 0x3010,
1925 & fmt_44_mulhi_a_ops[0],
1926 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1927 },
1928 /* end-sanitize-m32rx */
1929 /* mulwhi $src1,$src2 */
1930 {
1931 { 1, 1, 1, 1 },
1932 "mulwhi", "mulwhi",
1933 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1934 { 16, 16, 0xf0f0 }, 0x3020,
1935 & fmt_43_mulhi_ops[0],
1936 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1937 },
1938 /* mulwlo $src1,$src2 */
1939 {
1940 { 1, 1, 1, 1 },
1941 "mulwlo", "mulwlo",
1942 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1943 { 16, 16, 0xf0f0 }, 0x3030,
1944 & fmt_43_mulhi_ops[0],
1945 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1946 },
1947 /* mv $dr,$sr */
1948 {
1949 { 1, 1, 1, 1 },
1950 "mv", "mv",
1951 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1952 { 16, 16, 0xf0f0 }, 0x1080,
1953 & fmt_45_mv_ops[0],
1954 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1955 },
1956 /* mvfachi $dr */
1957 {
1958 { 1, 1, 1, 1 },
1959 "mvfachi", "mvfachi",
1960 { MNEM, ' ', OP (DR), 0 },
1961 { 16, 16, 0xf0ff }, 0x50f0,
1962 & fmt_46_mvfachi_ops[0],
1963 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1964 },
1965 /* start-sanitize-m32rx */
1966 /* mvfachi $dr,$accs */
1967 {
1968 { 1, 1, 1, 1 },
1969 "mvfachi-a", "mvfachi",
1970 { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 },
1971 { 16, 16, 0xf0f3 }, 0x50f0,
1972 & fmt_47_mvfachi_a_ops[0],
1973 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1974 },
1975 /* end-sanitize-m32rx */
1976 /* mvfaclo $dr */
1977 {
1978 { 1, 1, 1, 1 },
1979 "mvfaclo", "mvfaclo",
1980 { MNEM, ' ', OP (DR), 0 },
1981 { 16, 16, 0xf0ff }, 0x50f1,
1982 & fmt_46_mvfachi_ops[0],
1983 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1984 },
1985 /* start-sanitize-m32rx */
1986 /* mvfaclo $dr,$accs */
1987 {
1988 { 1, 1, 1, 1 },
1989 "mvfaclo-a", "mvfaclo",
1990 { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 },
1991 { 16, 16, 0xf0f3 }, 0x50f1,
1992 & fmt_47_mvfachi_a_ops[0],
1993 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1994 },
1995 /* end-sanitize-m32rx */
1996 /* mvfacmi $dr */
1997 {
1998 { 1, 1, 1, 1 },
1999 "mvfacmi", "mvfacmi",
2000 { MNEM, ' ', OP (DR), 0 },
2001 { 16, 16, 0xf0ff }, 0x50f2,
2002 & fmt_46_mvfachi_ops[0],
2003 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
2004 },
2005 /* start-sanitize-m32rx */
2006 /* mvfacmi $dr,$accs */
2007 {
2008 { 1, 1, 1, 1 },
2009 "mvfacmi-a", "mvfacmi",
2010 { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 },
2011 { 16, 16, 0xf0f3 }, 0x50f2,
2012 & fmt_47_mvfachi_a_ops[0],
2013 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2014 },
2015 /* end-sanitize-m32rx */
2016 /* mvfc $dr,$scr */
2017 {
2018 { 1, 1, 1, 1 },
2019 "mvfc", "mvfc",
2020 { MNEM, ' ', OP (DR), ',', OP (SCR), 0 },
2021 { 16, 16, 0xf0f0 }, 0x1090,
2022 & fmt_48_mvfc_ops[0],
2023 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2024 },
2025 /* mvtachi $src1 */
2026 {
2027 { 1, 1, 1, 1 },
2028 "mvtachi", "mvtachi",
2029 { MNEM, ' ', OP (SRC1), 0 },
2030 { 16, 16, 0xf0ff }, 0x5070,
2031 & fmt_49_mvtachi_ops[0],
2032 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
2033 },
2034 /* start-sanitize-m32rx */
2035 /* mvtachi $src1,$accs */
2036 {
2037 { 1, 1, 1, 1 },
2038 "mvtachi-a", "mvtachi",
2039 { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 },
2040 { 16, 16, 0xf0f3 }, 0x5070,
2041 & fmt_50_mvtachi_a_ops[0],
2042 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2043 },
2044 /* end-sanitize-m32rx */
2045 /* mvtaclo $src1 */
2046 {
2047 { 1, 1, 1, 1 },
2048 "mvtaclo", "mvtaclo",
2049 { MNEM, ' ', OP (SRC1), 0 },
2050 { 16, 16, 0xf0ff }, 0x5071,
2051 & fmt_49_mvtachi_ops[0],
2052 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
2053 },
2054 /* start-sanitize-m32rx */
2055 /* mvtaclo $src1,$accs */
2056 {
2057 { 1, 1, 1, 1 },
2058 "mvtaclo-a", "mvtaclo",
2059 { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 },
2060 { 16, 16, 0xf0f3 }, 0x5071,
2061 & fmt_50_mvtachi_a_ops[0],
2062 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2063 },
2064 /* end-sanitize-m32rx */
2065 /* mvtc $sr,$dcr */
2066 {
2067 { 1, 1, 1, 1 },
2068 "mvtc", "mvtc",
2069 { MNEM, ' ', OP (SR), ',', OP (DCR), 0 },
2070 { 16, 16, 0xf0f0 }, 0x10a0,
2071 & fmt_51_mvtc_ops[0],
2072 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2073 },
2074 /* neg $dr,$sr */
2075 {
2076 { 1, 1, 1, 1 },
2077 "neg", "neg",
2078 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2079 { 16, 16, 0xf0f0 }, 0x30,
2080 & fmt_45_mv_ops[0],
2081 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2082 },
2083 /* nop */
2084 {
2085 { 1, 1, 1, 1 },
2086 "nop", "nop",
2087 { MNEM, 0 },
2088 { 16, 16, 0xffff }, 0x7000,
2089 0,
2090 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2091 },
2092 /* not $dr,$sr */
2093 {
2094 { 1, 1, 1, 1 },
2095 "not", "not",
2096 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2097 { 16, 16, 0xf0f0 }, 0xb0,
2098 & fmt_45_mv_ops[0],
2099 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2100 },
2101 /* rac */
2102 {
2103 { 1, 1, 1, 1 },
2104 "rac", "rac",
2105 { MNEM, 0 },
2106 { 16, 16, 0xffff }, 0x5090,
2107 & fmt_53_rac_ops[0],
2108 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
2109 },
2110 /* start-sanitize-m32rx */
2111 /* rac $accd */
2112 {
2113 { 1, 1, 1, 1 },
2114 "rac-d", "rac",
2115 { MNEM, ' ', OP (ACCD), 0 },
2116 { 16, 16, 0xf3ff }, 0x5090,
2117 0,
2118 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2119 },
2120 /* end-sanitize-m32rx */
2121 /* start-sanitize-m32rx */
2122 /* rac $accd,$accs */
2123 {
2124 { 1, 1, 1, 1 },
2125 "rac-ds", "rac",
2126 { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 },
2127 { 16, 16, 0xf3f3 }, 0x5090,
2128 0,
2129 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2130 },
2131 /* end-sanitize-m32rx */
2132 /* start-sanitize-m32rx */
2133 /* rac $accd,$accs,#$imm1 */
2134 {
2135 { 1, 1, 1, 1 },
2136 "rac-dsi", "rac",
2137 { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', '#', OP (IMM1), 0 },
2138 { 16, 16, 0xf3f2 }, 0x5090,
2139 & fmt_56_rac_dsi_ops[0],
2140 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2141 },
2142 /* end-sanitize-m32rx */
2143 /* rach */
2144 {
2145 { 1, 1, 1, 1 },
2146 "rach", "rach",
2147 { MNEM, 0 },
2148 { 16, 16, 0xffff }, 0x5080,
2149 & fmt_53_rac_ops[0],
2150 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
2151 },
2152 /* start-sanitize-m32rx */
2153 /* rach $accd */
2154 {
2155 { 1, 1, 1, 1 },
2156 "rach-d", "rach",
2157 { MNEM, ' ', OP (ACCD), 0 },
2158 { 16, 16, 0xf3ff }, 0x5080,
2159 0,
2160 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2161 },
2162 /* end-sanitize-m32rx */
2163 /* start-sanitize-m32rx */
2164 /* rach $accd,$accs */
2165 {
2166 { 1, 1, 1, 1 },
2167 "rach-ds", "rach",
2168 { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 },
2169 { 16, 16, 0xf3f3 }, 0x5080,
2170 0,
2171 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2172 },
2173 /* end-sanitize-m32rx */
2174 /* start-sanitize-m32rx */
2175 /* rach $accd,$accs,#$imm1 */
2176 {
2177 { 1, 1, 1, 1 },
2178 "rach-dsi", "rach",
2179 { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', '#', OP (IMM1), 0 },
2180 { 16, 16, 0xf3f2 }, 0x5080,
2181 & fmt_56_rac_dsi_ops[0],
2182 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2183 },
2184 /* end-sanitize-m32rx */
2185 /* rte */
2186 {
2187 { 1, 1, 1, 1 },
2188 "rte", "rte",
2189 { MNEM, 0 },
2190 { 16, 16, 0xffff }, 0x10d6,
2191 & fmt_57_rte_ops[0],
2192 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
2193 },
2194 /* seth $dr,#$hi16 */
2195 {
2196 { 1, 1, 1, 1 },
2197 "seth", "seth",
2198 { MNEM, ' ', OP (DR), ',', '#', OP (HI16), 0 },
2199 { 32, 32, 0xf0ff0000 }, 0xd0c00000,
2200 & fmt_58_seth_ops[0],
2201 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2202 },
2203 /* seth $dr,$hi16 */
2204 {
2205 { 1, 1, 1, 1 },
2206 "seth.a", "seth",
2207 { MNEM, ' ', OP (DR), ',', OP (HI16), 0 },
2208 { 32, 32, 0xf0ff0000 }, 0xd0c00000,
2209 & fmt_58_seth_ops[0],
2210 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2211 },
2212 /* sll $dr,$sr */
2213 {
2214 { 1, 1, 1, 1 },
2215 "sll", "sll",
2216 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2217 { 16, 16, 0xf0f0 }, 0x1040,
2218 & fmt_0_add_ops[0],
2219 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2220 },
2221 /* sll3 $dr,$sr,#$simm16 */
2222 {
2223 { 1, 1, 1, 1 },
2224 "sll3", "sll3",
2225 { MNEM, ' ', OP (DR), ',', OP (SR), ',', '#', OP (SIMM16), 0 },
2226 { 32, 32, 0xf0f00000 }, 0x90c00000,
2227 & fmt_59_sll3_ops[0],
2228 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2229 },
2230 /* sll3 $dr,$sr,$simm16 */
2231 {
2232 { 1, 1, 1, 1 },
2233 "sll3.a", "sll3",
2234 { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
2235 { 32, 32, 0xf0f00000 }, 0x90c00000,
2236 & fmt_59_sll3_ops[0],
2237 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2238 },
2239 /* slli $dr,#$uimm5 */
2240 {
2241 { 1, 1, 1, 1 },
2242 "slli", "slli",
2243 { MNEM, ' ', OP (DR), ',', '#', OP (UIMM5), 0 },
2244 { 16, 16, 0xf0e0 }, 0x5040,
2245 & fmt_60_slli_ops[0],
2246 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2247 },
2248 /* slli $dr,$uimm5 */
2249 {
2250 { 1, 1, 1, 1 },
2251 "slli.a", "slli",
2252 { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 },
2253 { 16, 16, 0xf0e0 }, 0x5040,
2254 & fmt_60_slli_ops[0],
2255 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2256 },
2257 /* sra $dr,$sr */
2258 {
2259 { 1, 1, 1, 1 },
2260 "sra", "sra",
2261 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2262 { 16, 16, 0xf0f0 }, 0x1020,
2263 & fmt_0_add_ops[0],
2264 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2265 },
2266 /* sra3 $dr,$sr,#$simm16 */
2267 {
2268 { 1, 1, 1, 1 },
2269 "sra3", "sra3",
2270 { MNEM, ' ', OP (DR), ',', OP (SR), ',', '#', OP (SIMM16), 0 },
2271 { 32, 32, 0xf0f00000 }, 0x90a00000,
2272 & fmt_59_sll3_ops[0],
2273 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2274 },
2275 /* sra3 $dr,$sr,$simm16 */
2276 {
2277 { 1, 1, 1, 1 },
2278 "sra3.a", "sra3",
2279 { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
2280 { 32, 32, 0xf0f00000 }, 0x90a00000,
2281 & fmt_59_sll3_ops[0],
2282 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2283 },
2284 /* srai $dr,#$uimm5 */
2285 {
2286 { 1, 1, 1, 1 },
2287 "srai", "srai",
2288 { MNEM, ' ', OP (DR), ',', '#', OP (UIMM5), 0 },
2289 { 16, 16, 0xf0e0 }, 0x5020,
2290 & fmt_60_slli_ops[0],
2291 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2292 },
2293 /* srai $dr,$uimm5 */
2294 {
2295 { 1, 1, 1, 1 },
2296 "srai.a", "srai",
2297 { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 },
2298 { 16, 16, 0xf0e0 }, 0x5020,
2299 & fmt_60_slli_ops[0],
2300 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2301 },
2302 /* srl $dr,$sr */
2303 {
2304 { 1, 1, 1, 1 },
2305 "srl", "srl",
2306 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2307 { 16, 16, 0xf0f0 }, 0x1000,
2308 & fmt_0_add_ops[0],
2309 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2310 },
2311 /* srl3 $dr,$sr,#$simm16 */
2312 {
2313 { 1, 1, 1, 1 },
2314 "srl3", "srl3",
2315 { MNEM, ' ', OP (DR), ',', OP (SR), ',', '#', OP (SIMM16), 0 },
2316 { 32, 32, 0xf0f00000 }, 0x90800000,
2317 & fmt_59_sll3_ops[0],
2318 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2319 },
2320 /* srl3 $dr,$sr,$simm16 */
2321 {
2322 { 1, 1, 1, 1 },
2323 "srl3.a", "srl3",
2324 { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
2325 { 32, 32, 0xf0f00000 }, 0x90800000,
2326 & fmt_59_sll3_ops[0],
2327 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2328 },
2329 /* srli $dr,#$uimm5 */
2330 {
2331 { 1, 1, 1, 1 },
2332 "srli", "srli",
2333 { MNEM, ' ', OP (DR), ',', '#', OP (UIMM5), 0 },
2334 { 16, 16, 0xf0e0 }, 0x5000,
2335 & fmt_60_slli_ops[0],
2336 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2337 },
2338 /* srli $dr,$uimm5 */
2339 {
2340 { 1, 1, 1, 1 },
2341 "srli.a", "srli",
2342 { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 },
2343 { 16, 16, 0xf0e0 }, 0x5000,
2344 & fmt_60_slli_ops[0],
2345 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2346 },
2347 /* st $src1,@$src2 */
2348 {
2349 { 1, 1, 1, 1 },
2350 "st", "st",
2351 { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
2352 { 16, 16, 0xf0f0 }, 0x2040,
2353 & fmt_61_st_ops[0],
2354 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2355 },
2356 /* st $src1,@($src2) */
2357 {
2358 { 1, 1, 1, 1 },
2359 "st-2", "st",
2360 { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 },
2361 { 16, 16, 0xf0f0 }, 0x2040,
2362 0,
2363 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2364 },
2365 /* st $src1,@($slo16,$src2) */
2366 {
2367 { 1, 1, 1, 1 },
2368 "st-d", "st",
2369 { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 },
2370 { 32, 32, 0xf0f00000 }, 0xa0400000,
2371 & fmt_63_st_d_ops[0],
2372 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2373 },
2374 /* st $src1,@($src2,$slo16) */
2375 {
2376 { 1, 1, 1, 1 },
2377 "st-d2", "st",
2378 { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 },
2379 { 32, 32, 0xf0f00000 }, 0xa0400000,
2380 0,
2381 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2382 },
2383 /* stb $src1,@$src2 */
2384 {
2385 { 1, 1, 1, 1 },
2386 "stb", "stb",
2387 { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
2388 { 16, 16, 0xf0f0 }, 0x2000,
2389 & fmt_65_stb_ops[0],
2390 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2391 },
2392 /* stb $src1,@($src2) */
2393 {
2394 { 1, 1, 1, 1 },
2395 "stb-2", "stb",
2396 { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 },
2397 { 16, 16, 0xf0f0 }, 0x2000,
2398 0,
2399 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2400 },
2401 /* stb $src1,@($slo16,$src2) */
2402 {
2403 { 1, 1, 1, 1 },
2404 "stb-d", "stb",
2405 { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 },
2406 { 32, 32, 0xf0f00000 }, 0xa0000000,
2407 & fmt_66_stb_d_ops[0],
2408 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2409 },
2410 /* stb $src1,@($src2,$slo16) */
2411 {
2412 { 1, 1, 1, 1 },
2413 "stb-d2", "stb",
2414 { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 },
2415 { 32, 32, 0xf0f00000 }, 0xa0000000,
2416 0,
2417 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2418 },
2419 /* sth $src1,@$src2 */
2420 {
2421 { 1, 1, 1, 1 },
2422 "sth", "sth",
2423 { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
2424 { 16, 16, 0xf0f0 }, 0x2020,
2425 & fmt_67_sth_ops[0],
2426 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2427 },
2428 /* sth $src1,@($src2) */
2429 {
2430 { 1, 1, 1, 1 },
2431 "sth-2", "sth",
2432 { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 },
2433 { 16, 16, 0xf0f0 }, 0x2020,
2434 0,
2435 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2436 },
2437 /* sth $src1,@($slo16,$src2) */
2438 {
2439 { 1, 1, 1, 1 },
2440 "sth-d", "sth",
2441 { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 },
2442 { 32, 32, 0xf0f00000 }, 0xa0200000,
2443 & fmt_68_sth_d_ops[0],
2444 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2445 },
2446 /* sth $src1,@($src2,$slo16) */
2447 {
2448 { 1, 1, 1, 1 },
2449 "sth-d2", "sth",
2450 { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 },
2451 { 32, 32, 0xf0f00000 }, 0xa0200000,
2452 0,
2453 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2454 },
2455 /* st $src1,@+$src2 */
2456 {
2457 { 1, 1, 1, 1 },
2458 "st-plus", "st",
2459 { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 },
2460 { 16, 16, 0xf0f0 }, 0x2060,
2461 & fmt_69_st_plus_ops[0],
2462 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2463 },
2464 /* st $src1,@-$src2 */
2465 {
2466 { 1, 1, 1, 1 },
2467 "st-minus", "st",
2468 { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 },
2469 { 16, 16, 0xf0f0 }, 0x2070,
2470 & fmt_69_st_plus_ops[0],
2471 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2472 },
2473 /* sub $dr,$sr */
2474 {
2475 { 1, 1, 1, 1 },
2476 "sub", "sub",
2477 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2478 { 16, 16, 0xf0f0 }, 0x20,
2479 & fmt_0_add_ops[0],
2480 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2481 },
2482 /* subv $dr,$sr */
2483 {
2484 { 1, 1, 1, 1 },
2485 "subv", "subv",
2486 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2487 { 16, 16, 0xf0f0 }, 0x0,
2488 & fmt_5_addv_ops[0],
2489 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2490 },
2491 /* subx $dr,$sr */
2492 {
2493 { 1, 1, 1, 1 },
2494 "subx", "subx",
2495 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2496 { 16, 16, 0xf0f0 }, 0x10,
2497 & fmt_7_addx_ops[0],
2498 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2499 },
2500 /* trap #$uimm4 */
2501 {
2502 { 1, 1, 1, 1 },
2503 "trap", "trap",
2504 { MNEM, ' ', '#', OP (UIMM4), 0 },
2505 { 16, 16, 0xfff0 }, 0x10f0,
2506 & fmt_70_trap_ops[0],
2507 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
2508 },
2509 /* trap $uimm4 */
2510 {
2511 { 1, 1, 1, 1 },
2512 "trap.a", "trap",
2513 { MNEM, ' ', OP (UIMM4), 0 },
2514 { 16, 16, 0xfff0 }, 0x10f0,
2515 0,
2516 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
2517 },
2518 /* unlock $src1,@$src2 */
2519 {
2520 { 1, 1, 1, 1 },
2521 "unlock", "unlock",
2522 { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
2523 { 16, 16, 0xf0f0 }, 0x2050,
2524 & fmt_72_unlock_ops[0],
2525 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2526 },
2527 /* push $src1 */
2528 {
2529 { 1, 1, 1, 1 },
2530 "push", "push",
2531 { MNEM, ' ', OP (SRC1), 0 },
2532 { 16, 16, 0xf0ff }, 0x207f,
2533 0,
2534 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2535 },
2536 /* pop $dr */
2537 {
2538 { 1, 1, 1, 1 },
2539 "pop", "pop",
2540 { MNEM, ' ', OP (DR), 0 },
2541 { 16, 16, 0xf0ff }, 0x20ef,
2542 0,
2543 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2544 },
2545 /* start-sanitize-m32rx */
2546 /* satb $dr,$sr */
2547 {
2548 { 1, 1, 1, 1 },
2549 "satb", "satb",
2550 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2551 { 32, 32, 0xf0f0ffff }, 0x80000100,
2552 & fmt_75_satb_ops[0],
2553 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
2554 },
2555 /* end-sanitize-m32rx */
2556 /* start-sanitize-m32rx */
2557 /* sath $dr,$sr */
2558 {
2559 { 1, 1, 1, 1 },
2560 "sath", "sath",
2561 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2562 { 32, 32, 0xf0f0ffff }, 0x80000200,
2563 & fmt_75_satb_ops[0],
2564 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
2565 },
2566 /* end-sanitize-m32rx */
2567 /* start-sanitize-m32rx */
2568 /* sat $dr,$sr */
2569 {
2570 { 1, 1, 1, 1 },
2571 "sat", "sat",
2572 { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2573 { 32, 32, 0xf0f0ffff }, 0x80000000,
2574 & fmt_76_sat_ops[0],
2575 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
2576 },
2577 /* end-sanitize-m32rx */
2578 /* start-sanitize-m32rx */
2579 /* pcmpbz $src2 */
2580 {
2581 { 1, 1, 1, 1 },
2582 "pcmpbz", "pcmpbz",
2583 { MNEM, ' ', OP (SRC2), 0 },
2584 { 16, 16, 0xfff0 }, 0x370,
2585 & fmt_23_cmpz_ops[0],
2586 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
2587 },
2588 /* end-sanitize-m32rx */
2589 /* start-sanitize-m32rx */
2590 /* sadd */
2591 {
2592 { 1, 1, 1, 1 },
2593 "sadd", "sadd",
2594 { MNEM, 0 },
2595 { 16, 16, 0xffff }, 0x50e4,
2596 & fmt_77_sadd_ops[0],
2597 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2598 },
2599 /* end-sanitize-m32rx */
2600 /* start-sanitize-m32rx */
2601 /* macwu1 $src1,$src2 */
2602 {
2603 { 1, 1, 1, 1 },
2604 "macwu1", "macwu1",
2605 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
2606 { 16, 16, 0xf0f0 }, 0x50b0,
2607 & fmt_78_macwu1_ops[0],
2608 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2609 },
2610 /* end-sanitize-m32rx */
2611 /* start-sanitize-m32rx */
2612 /* msblo $src1,$src2 */
2613 {
2614 { 1, 1, 1, 1 },
2615 "msblo", "msblo",
2616 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
2617 { 16, 16, 0xf0f0 }, 0x50d0,
2618 & fmt_41_machi_ops[0],
2619 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2620 },
2621 /* end-sanitize-m32rx */
2622 /* start-sanitize-m32rx */
2623 /* mulwu1 $src1,$src2 */
2624 {
2625 { 1, 1, 1, 1 },
2626 "mulwu1", "mulwu1",
2627 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
2628 { 16, 16, 0xf0f0 }, 0x50a0,
2629 & fmt_79_mulwu1_ops[0],
2630 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2631 },
2632 /* end-sanitize-m32rx */
2633 /* start-sanitize-m32rx */
2634 /* maclh1 $src1,$src2 */
2635 {
2636 { 1, 1, 1, 1 },
2637 "maclh1", "maclh1",
2638 { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
2639 { 16, 16, 0xf0f0 }, 0x50c0,
2640 & fmt_78_macwu1_ops[0],
2641 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2642 },
2643 /* end-sanitize-m32rx */
2644 /* start-sanitize-m32rx */
2645 /* sc */
2646 {
2647 { 1, 1, 1, 1 },
2648 "sc", "sc",
2649 { MNEM, 0 },
2650 { 16, 16, 0xffff }, 0x7401,
2651 & fmt_80_sc_ops[0],
2652 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_O } }
2653 },
2654 /* end-sanitize-m32rx */
2655 /* start-sanitize-m32rx */
2656 /* snc */
2657 {
2658 { 1, 1, 1, 1 },
2659 "snc", "snc",
2660 { MNEM, 0 },
2661 { 16, 16, 0xffff }, 0x7501,
2662 & fmt_80_sc_ops[0],
2663 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_O } }
2664 },
2665 /* end-sanitize-m32rx */
2666 };
2667
2668 #undef A
2669 #undef MNEM
2670 #undef OP
2671
2672 CGEN_INSN_TABLE m32r_cgen_insn_table =
2673 {
2674 & m32r_cgen_insn_table_entries[0],
2675 sizeof (CGEN_INSN),
2676 MAX_INSNS,
2677 NULL,
2678 m32r_cgen_asm_hash_insn, CGEN_ASM_HASH_SIZE,
2679 m32r_cgen_dis_hash_insn, CGEN_DIS_HASH_SIZE
2680 };
2681
2682 /* The hash functions are recorded here to help keep assembler code out of
2683 the disassembler and vice versa. */
2684
2685 unsigned int
2686 m32r_cgen_asm_hash_insn (insn)
2687 const char * insn;
2688 {
2689 return CGEN_ASM_HASH (insn);
2690 }
2691
2692 unsigned int
2693 m32r_cgen_dis_hash_insn (buf, value)
2694 const char * buf;
2695 unsigned long value;
2696 {
2697 return CGEN_DIS_HASH (buf, value);
2698 }
2699
2700 CGEN_OPCODE_DATA m32r_cgen_opcode_data =
2701 {
2702 & m32r_cgen_hw_entries[0],
2703 & m32r_cgen_insn_table,
2704 };
2705
2706 void
2707 m32r_cgen_init_tables (mach)
2708 int mach;
2709 {
2710 }
2711
2712 /* Main entry point for stuffing values in cgen_fields. */
2713
2714 CGEN_INLINE void
2715 m32r_cgen_set_operand (opindex, valuep, fields)
2716 int opindex;
2717 const long * valuep;
2718 CGEN_FIELDS * fields;
2719 {
2720 switch (opindex)
2721 {
2722 case M32R_OPERAND_SR :
2723 fields->f_r2 = * valuep;
2724 break;
2725 case M32R_OPERAND_DR :
2726 fields->f_r1 = * valuep;
2727 break;
2728 case M32R_OPERAND_SRC1 :
2729 fields->f_r1 = * valuep;
2730 break;
2731 case M32R_OPERAND_SRC2 :
2732 fields->f_r2 = * valuep;
2733 break;
2734 case M32R_OPERAND_SCR :
2735 fields->f_r2 = * valuep;
2736 break;
2737 case M32R_OPERAND_DCR :
2738 fields->f_r1 = * valuep;
2739 break;
2740 case M32R_OPERAND_SIMM8 :
2741 fields->f_simm8 = * valuep;
2742 break;
2743 case M32R_OPERAND_SIMM16 :
2744 fields->f_simm16 = * valuep;
2745 break;
2746 case M32R_OPERAND_UIMM4 :
2747 fields->f_uimm4 = * valuep;
2748 break;
2749 case M32R_OPERAND_UIMM5 :
2750 fields->f_uimm5 = * valuep;
2751 break;
2752 case M32R_OPERAND_UIMM16 :
2753 fields->f_uimm16 = * valuep;
2754 break;
2755 /* start-sanitize-m32rx */
2756 case M32R_OPERAND_IMM1 :
2757 fields->f_imm1 = * valuep;
2758 break;
2759 /* end-sanitize-m32rx */
2760 /* start-sanitize-m32rx */
2761 case M32R_OPERAND_ACCD :
2762 fields->f_accd = * valuep;
2763 break;
2764 /* end-sanitize-m32rx */
2765 /* start-sanitize-m32rx */
2766 case M32R_OPERAND_ACCS :
2767 fields->f_accs = * valuep;
2768 break;
2769 /* end-sanitize-m32rx */
2770 /* start-sanitize-m32rx */
2771 case M32R_OPERAND_ACC :
2772 fields->f_acc = * valuep;
2773 break;
2774 /* end-sanitize-m32rx */
2775 case M32R_OPERAND_HI16 :
2776 fields->f_hi16 = * valuep;
2777 break;
2778 case M32R_OPERAND_SLO16 :
2779 fields->f_simm16 = * valuep;
2780 break;
2781 case M32R_OPERAND_ULO16 :
2782 fields->f_uimm16 = * valuep;
2783 break;
2784 case M32R_OPERAND_UIMM24 :
2785 fields->f_uimm24 = * valuep;
2786 break;
2787 case M32R_OPERAND_DISP8 :
2788 fields->f_disp8 = * valuep;
2789 break;
2790 case M32R_OPERAND_DISP16 :
2791 fields->f_disp16 = * valuep;
2792 break;
2793 case M32R_OPERAND_DISP24 :
2794 fields->f_disp24 = * valuep;
2795 break;
2796
2797 default :
2798 fprintf (stderr, "Unrecognized field %d while setting operand.\n",
2799 opindex);
2800 abort ();
2801 }
2802 }
2803
2804 /* Main entry point for getting values from cgen_fields. */
2805
2806 CGEN_INLINE long
2807 m32r_cgen_get_operand (opindex, fields)
2808 int opindex;
2809 const CGEN_FIELDS * fields;
2810 {
2811 long value;
2812
2813 switch (opindex)
2814 {
2815 case M32R_OPERAND_SR :
2816 value = fields->f_r2;
2817 break;
2818 case M32R_OPERAND_DR :
2819 value = fields->f_r1;
2820 break;
2821 case M32R_OPERAND_SRC1 :
2822 value = fields->f_r1;
2823 break;
2824 case M32R_OPERAND_SRC2 :
2825 value = fields->f_r2;
2826 break;
2827 case M32R_OPERAND_SCR :
2828 value = fields->f_r2;
2829 break;
2830 case M32R_OPERAND_DCR :
2831 value = fields->f_r1;
2832 break;
2833 case M32R_OPERAND_SIMM8 :
2834 value = fields->f_simm8;
2835 break;
2836 case M32R_OPERAND_SIMM16 :
2837 value = fields->f_simm16;
2838 break;
2839 case M32R_OPERAND_UIMM4 :
2840 value = fields->f_uimm4;
2841 break;
2842 case M32R_OPERAND_UIMM5 :
2843 value = fields->f_uimm5;
2844 break;
2845 case M32R_OPERAND_UIMM16 :
2846 value = fields->f_uimm16;
2847 break;
2848 /* start-sanitize-m32rx */
2849 case M32R_OPERAND_IMM1 :
2850 value = fields->f_imm1;
2851 break;
2852 /* end-sanitize-m32rx */
2853 /* start-sanitize-m32rx */
2854 case M32R_OPERAND_ACCD :
2855 value = fields->f_accd;
2856 break;
2857 /* end-sanitize-m32rx */
2858 /* start-sanitize-m32rx */
2859 case M32R_OPERAND_ACCS :
2860 value = fields->f_accs;
2861 break;
2862 /* end-sanitize-m32rx */
2863 /* start-sanitize-m32rx */
2864 case M32R_OPERAND_ACC :
2865 value = fields->f_acc;
2866 break;
2867 /* end-sanitize-m32rx */
2868 case M32R_OPERAND_HI16 :
2869 value = fields->f_hi16;
2870 break;
2871 case M32R_OPERAND_SLO16 :
2872 value = fields->f_simm16;
2873 break;
2874 case M32R_OPERAND_ULO16 :
2875 value = fields->f_uimm16;
2876 break;
2877 case M32R_OPERAND_UIMM24 :
2878 value = fields->f_uimm24;
2879 break;
2880 case M32R_OPERAND_DISP8 :
2881 value = fields->f_disp8;
2882 break;
2883 case M32R_OPERAND_DISP16 :
2884 value = fields->f_disp16;
2885 break;
2886 case M32R_OPERAND_DISP24 :
2887 value = fields->f_disp24;
2888 break;
2889
2890 default :
2891 fprintf (stderr, "Unrecognized field %d while getting operand.\n",
2892 opindex);
2893 abort ();
2894 }
2895
2896 return value;
2897 }
2898
GDB Binutils - Deliverables
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